阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 奥田聪志 古川彰彦 清井明 于 2017-12-06 设计创作，主要内容包括：目的在于提供不增加IGBT等半导体装置的厚度而能够抑制关断时的浪涌电压的技术。半导体装置具备按照从第1半导体层至第4半导体层的顺序层叠的、分别具有第1导电类型的第1至第4半导体层,还具备基极层、发射极层、栅极电极、集电极层以及集电极电极。在第1至第4半导体层中,第2半导体层的第1导电类型的杂质浓度最低,第3半导体层的第1导电类型的杂质浓度高于第4半导体层的第1导电类型的杂质浓度。(Provided is a technique capable of suppressing surge voltage at turn-off without increasing the thickness of a semiconductor device such as an IGBT. The semiconductor device includes 1 st to 4 th semiconductor layers having a 1 st conductivity type, which are stacked in this order from the 1 st to 4 th semiconductor layers, and further includes a base layer, an emitter layer, a gate electrode, a collector layer, and a collector electrode. Among the 1 st to 4 th semiconductor layers, the 1 st conductivity type impurity concentration of the 2 nd semiconductor layer is the lowest, and the 1 st conductivity type impurity concentration of the 3 rd semiconductor layer is higher than the 1 st conductivity type impurity concentration of the 4 th semiconductor layer.)

1. A kind of semiconductor device is provided, in which,

Includes 1 st to 4 th semiconductor layers having 1 st conductivity type and stacked in this order from the 1 st to 4 th semiconductor layers,

The 1 st direction and the 2 nd direction are respectively set as the forward direction and the reverse direction of the lamination,

The semiconductor device further includes:

a base layer which is arranged on a surface side of the 4 th semiconductor layer facing the 1 st direction and has a 2 nd conductivity type;

An emitter layer selectively arranged on a surface of the base layer facing the 1 st direction, and having a 1 st conductivity type;

A gate electrode capable of forming a channel in the base layer;

A collector layer disposed on the 2 nd direction side of the 1 st semiconductor layer and having a 2 nd conductivity type; and

A collector electrode disposed on a surface of the collector layer facing the 2 nd direction,

Wherein an impurity concentration of a 1 st conductivity type of either one of the 2 nd semiconductor layer and the 3 rd semiconductor layer is lower than an impurity concentration of a 1 st conductivity type of each of a semiconductor layer adjacent to the one semiconductor layer in the 1 st direction and a semiconductor layer adjacent to the one semiconductor layer in the 2 nd direction,

The concentration of hydrogen atoms contained in the one semiconductor layer is equal to the concentration of hydrogen atoms contained in each of the semiconductor layer adjacent to the one semiconductor layer in the 1 st direction and the semiconductor layer adjacent to the one semiconductor layer in the 2 nd direction.

2. The semiconductor device according to claim 1,

The one semiconductor layer is the 2 nd semiconductor layer,

Among the 1 st semiconductor layer to the 4 th semiconductor layer, the 2 nd semiconductor layer has the lowest impurity concentration of the 1 st conductivity type,

The impurity concentration of the 1 st conductive type of the 3 rd semiconductor layer is higher than the impurity concentration of the 1 st conductive type of the 4 th semiconductor layer.

3. The semiconductor device according to claim 1,

The one semiconductor layer is the 2 nd semiconductor layer,

Among the 1 st to 4 th semiconductor layers, the 4 th semiconductor layer has the lowest impurity concentration of the 1 st conductivity type.

4. The semiconductor device according to claim 1,

The thickness of the one semiconductor layer is 0.5 to 20 μm.

5. A method for manufacturing the semiconductor device according to claim 2 or 3, comprising:

(a) A step of sequentially forming the 2 nd semiconductor layer to the 4 th semiconductor layer by epitaxial growth on a surface facing the 1 st direction of a semiconductor substrate which is a part of the 1 st semiconductor layer; and

(b) And thinning the semiconductor substrate.

6. A method for manufacturing the semiconductor device according to claim 2 or 3, comprising:

(a) A step of sequentially forming the 3 rd semiconductor layer and the 4 th semiconductor layer by epitaxial growth on a surface of the semiconductor substrate, a part of which is the 2 nd semiconductor layer, facing the 1 st direction;

(b) Thinning the semiconductor substrate; and

(c) And (b) forming the 1 st semiconductor layer on a surface of the semiconductor substrate facing the 2 nd direction after the step (b).

7. The semiconductor device according to claim 1,

Further comprising a 1 st conductivity type 5 th semiconductor layer disposed between the 1 st semiconductor layer and the collector layer,

The one semiconductor layer is the 3 rd semiconductor layer,

Among the 1 st semiconductor layer to the 5 th semiconductor layer, the 3 rd semiconductor layer has the lowest impurity concentration of the 1 st conductive type,

The impurity concentration of the 1 st conductivity type of the 1 st semiconductor layer is lower than the impurity concentration of the 1 st conductivity type of the 2 nd semiconductor layer and the impurity concentration of the 1 st conductivity type of the 5 th semiconductor layer.

8. The semiconductor device according to claim 1,

The one semiconductor layer is the 3 rd semiconductor layer,

among the 1 st semiconductor layer to the 4 th semiconductor layer, the 3 rd semiconductor layer has the lowest impurity concentration of the 1 st conductive type,

The 1 st semiconductor layer has a 1 st conductive type impurity concentration higher than a 1 st conductive type impurity concentration of the 2 nd semiconductor layer.

9. The semiconductor device according to claim 1,

The maximum value of the impurity concentration of the 2 nd conductivity type of the collector layer is 10 times or more the maximum value of the impurity concentration of the 1 st conductivity type of the 1 st semiconductor layer.

10. The semiconductor device according to claim 1,

the maximum value of the impurity concentration of the 1 st conductivity type of the semiconductor layer adjacent to the one semiconductor layer in the 1 st direction is 3 times or more the maximum value of the 1 st conductivity type of the impurity concentration of the one semiconductor layer.

Technical Field

The present invention relates to a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) and a method for manufacturing the same.

Background

Inverters used in various places around the body such as industry, automobiles, electric railways, and the like are controlled by a power module or the like mounted with an IGBT. In order to save energy in the inverter, it is essential to reduce power loss in the IGBT that performs power control. Heretofore, in order to improve the saturation voltage of the IGBT and reduce the switching loss at the same time, thinning of the IGBT chip has been performed. The thickness of the chip and the reverse breakdown voltage have a trade-off relationship, and as a structure for realizing the same at the same time, an FS (Field Stop) type IGBT is used. In FS type IGBT, n on the back of chip^-An n-type buffer layer having a higher impurity concentration than the drift layer is provided below the drift layer. With such a structure, p, in which the depletion layer reaches the back surface of the chip in the off state of the IGBT, is suppressed⁺And a collector type layer.

In addition, in recent years, the IGBT is becoming thinner, and a surge voltage and voltage oscillation at the time of turn-off accompanying this progress become a problem. These problems are caused by the depletion of carriers in the drift layer during the off period and the sharp decrease in current.

In order to solve this problem, for example, as in the technique of patent document 1, it is proposed to reduce the ratio of the depletion layer extension to the voltage by making the n-type buffer layer relatively thick in the thickness direction of the IGBT. Hereinafter, the buffer layer having a wide width in the film thickness direction is referred to as a "deep buffer layer".

Further, patent document 2 proposes an n-type buffer layer and a p-type buffer layer⁺The low impurity concentration layer is provided between the collector layers. According to such a configuration, holes are accumulated in the low impurity concentration layer in the on state, and the holes are supplied to the drift layer in the off state, so that rapid depletion of carriers can be suppressed.

Disclosure of Invention

In order to suppress the surge voltage at the time of turn-off of the IGBT, it is effective to increase the impurity concentration in the deep buffer layer as in the technique of patent document 1. However, when the amount of impurities in the deep buffer layer is increased, the breakdown voltage of the IGBT decreases, and therefore, there is a limit to increase in the thickness of the deep buffer layer and increase in the impurity concentration.

As described above, in the structure in which the thinning of the IGBT is excessively advanced, a sufficient surge voltage suppression effect may not be obtained only by providing a deep buffer layer. In addition, as in the technique of patent document 2, the n-type buffer layer and the p-type buffer layer are formed⁺In the structure in which the low impurity concentration layer is provided between the collector layers, the depletion layer does not extend to the low impurity concentration layer, and therefore, the effect of maintaining the withstand voltage is not obtained. Therefore, the thickness of the IGBT increases by the amount of the low impurity concentration layer, and the conduction loss increases.

The present invention has been made in view of the above-described problems, and an object thereof is to provide a technique capable of suppressing a surge voltage at the time of turn-off without increasing the thickness of a semiconductor device such as an IGBT.

The present invention provides a semiconductor device including 1 st to 4 th semiconductor layers having 1 st conductivity type and stacked in order from 1 st to 4 th semiconductor layers, wherein the forward direction and reverse direction of the stack are defined as 1 st and 2 nd directions, respectively, the semiconductor device further including: a base layer which is arranged on a surface side of the 4 th semiconductor layer facing the 1 st direction and has a 2 nd conductivity type; an emitter layer selectively arranged on a surface of the base layer facing the 1 st direction, and having a 1 st conductivity type; a gate electrode capable of forming a channel in the base layer; a collector layer disposed on the 2 nd direction side of the 1 st semiconductor layer and having a 2 nd conductivity type; and a collector electrode disposed on a surface of the collector layer facing the 2 nd direction, wherein an impurity concentration of the 1 st conductivity type in any one of the 2 nd semiconductor layer and the 3 rd semiconductor layer is lower than impurity concentrations of the 1 st conductivity type in each of a semiconductor layer adjacent to the one semiconductor layer in the 1 st direction and a semiconductor layer adjacent to the one semiconductor layer in the 2 nd direction, and a hydrogen atom concentration included in the one semiconductor layer is equal to a hydrogen atom concentration included in each of the semiconductor layer adjacent to the one semiconductor layer in the 1 st direction and the semiconductor layer adjacent to the one semiconductor layer in the 2 nd direction.

According to the present invention, the impurity concentration of the 1 st conductivity type in any one of the 2 nd semiconductor layer and the 3 rd semiconductor layer is lower than the impurity concentration of the 1 st conductivity type in each of the semiconductor layer adjacent to the one semiconductor layer in the 1 st direction and the semiconductor layer adjacent to the one semiconductor layer in the 2 nd direction. With such a configuration, the surge voltage at the time of turn-off can be suppressed without increasing the thickness of the semiconductor device such as an IGBT.

the objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

drawings

Fig. 1 is a schematic sectional view showing the structure of an associated semiconductor device.

Fig. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to embodiment 1.

Fig. 3 is a diagram showing an impurity concentration profile of the semiconductor device according to embodiment 1.

Fig. 4 is a diagram showing an impurity concentration distribution diagram of a modification of the semiconductor device according to embodiment 1.

Fig. 5 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 2.

Fig. 6 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 2.

Fig. 7 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 2.

Fig. 8 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 2.

Fig. 9 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 2.

Fig. 10 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 3.

Fig. 11 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 3.

Fig. 12 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 3.

Fig. 13 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 3.

Fig. 14 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 3.

fig. 15 is a diagram showing an impurity concentration profile of the semiconductor device according to embodiment 4.

Fig. 16 is a schematic cross-sectional view showing the structure of the semiconductor device according to embodiment 5.

Fig. 17 is a diagram showing an impurity concentration profile of the semiconductor device according to embodiment 5.

Fig. 18 is a schematic cross-sectional view for explaining the manufacturing method according to embodiment 5.

Fig. 19 is a schematic cross-sectional view for explaining a manufacturing method according to a modification of embodiment 5.

Fig. 20 is a schematic cross-sectional view showing the structure of a semiconductor device according to embodiment 6.

Fig. 21 is a diagram showing an impurity concentration profile of the semiconductor device according to embodiment 6.

(symbol description)

3: a gate electrode; 5: n is⁺A type emitter layer; 6: a p-type base layer; 9: p is a radical of⁺A collector type layer; 10: a collector electrode; 11: n is^-A type drift layer; 13: n is⁺A type 1 buffer layer; 14: n is^-A back carrier accumulation layer of type; 15: an n-type 2 nd buffer layer; 16: n is⁺A model silicon substrate; 20: n is^-A model silicon substrate; 23: n is^-Type I1 a back carrier accumulation layer; 24: n is^--Type 2 nd back carrier accumulation layer; 29: n is^--A back carrier accumulation layer.

Detailed Description

In the following description, n and p represent conductivity types of semiconductors. In addition, n^--Represents the impurity concentration ratio n^-Low concentration, n^-indicating that the impurity concentration is lower than n⁺Indicating a higher concentration of impurities than n. Likewise, p^-Indicating a lower concentration of impurity than p, p⁺Indicating a higher concentration of impurities than p.

In the following description, a 1 st direction, which is a forward direction of the lamination of the 1 st semiconductor layer to the 4 th semiconductor layer to be described later, is an upward direction, and a 2 nd direction, which is a reverse direction of the forward direction, is a downward direction. The surface facing upward is referred to as the upper surface, and the surface facing downward is referred to as the lower surface. In the following description, the 1 st conductivity type is n, n^-、n^--、n⁺The 2 nd conductivity type is p, p^-、p⁺But they may also be reversed.

< related semiconductor device >

First, before a semiconductor device according to an embodiment of the present invention is described, a related semiconductor device (hereinafter, referred to as a related semiconductor device) will be described.

Fig. 1 is a schematic sectional view showing the structure of an associated semiconductor device. In the example of fig. 1, the relevant semiconductor device is an FS type IGBT. The semiconductor structure 200 is formed by doping n containing phosphorus at a low concentration^-The silicon substrate is produced by performing FZ (Floating Zone) method or MCZ (magnetic field applied CZ) method.

the related semiconductor device of fig. 1 includes a trench gate electrode 1, an emitter electrode 4, and n⁺Emitter layer 5, p-type base layer 6, n-type carrier accumulation layer 7, interlayer insulating film 8, p⁺Collector layer 9, collector electrode 10, n^-Drift layer 11, n⁺And a buffer layer 12.

A p-type base layer 6 arranged on n^-Upper surface side of type drift layer 11, n⁺The emitter layer 5 is selectively disposed on the upper surface of the p-type base layer 6. The trench gate electrode 1 of fig. 1 has a channel n⁺The upper surface of the emitter layer 5 reaches n^-A gate insulating film 2 disposed on the trench inner wall of drift layer 11, and a gate electrode 3 buried so as to be surrounded by gate insulating film 2. The gate electrode 3 can be formed so that n is n when a gate voltage is applied⁺Type emitter layer 5 and n^-A channel conducting between the drift layers 11.

in the related semiconductor device of FIG. 1, p-type base layer 6 and n are provided^-An n-type carrier accumulation layer 7 is provided between the drift layers 11.

On the trench gate electrode 1 and n⁺An interlayer insulating film 8 is provided on a part of the emitter layer 5. And, in n⁺An emitter electrode 4 is disposed on the remaining part of the emitter type layer 5, on the p-type base layer 6, and on the interlayer insulating film 8.

At n^-N are arranged on the lower surface of the drift layer 11 in this order from above⁺buffer layer 12, p of type⁺A collector type layer 9 and a collector electrode 10. n is⁺The buffer layer 12 is for suppressing the spread from the pn junction surface of the p-type base layer 6 to n at the time of turn-off^-Depletion layer in type drift layer 11 reaches p⁺Punch-through of the type collector layer 9 is provided.

In addition, in the past, n was used to reduce conduction loss^-Thinning of the type drift layer 11 progresses. This thinning can increase the speed of shutdown, but extends to n^-Depletion layer in type drift layer 11 collides with n⁺And a buffer layer 12. Thus, from n^-The electron discharge from the drift layer 11 is suppressed and p is derived⁺The hole supply of the type collector layer 9 is suppressed. As a result, n^-Carriers in drift layer 11 are rapidly depleted, and the collector current is rapidly reduced. In addition, a large surge voltage generated by the rapid change in the collector current may exceed the element breakdown voltage or generate noise oscillating in the voltage waveform.

As a solutionAs a means for solving the above problem, it is known to arrange a deep buffer layer as n^-The drift layer 11 is formed so that the depletion layer is gradually extended to suppress n when turned off^-Means for depleting carriers in drift layer 11. In this means, the effect of suppressing the surge voltage can be increased by increasing the impurity concentration in the deep buffer layer. However, when the impurity concentration is increased, the element withstand voltage is lowered, and therefore the surge voltage may not be sufficiently suppressed.

As a configuration for solving such a problem, n is considered⁺Buffer layer 12 and p⁺The low impurity concentration layer is provided between the collector layers 9. According to this configuration, holes are accumulated in the low impurity concentration layer in the on state, and the holes are supplied to n in the off state^-Since drift layer 11 is formed, rapid depletion of carriers can be suppressed. However, the depletion layer does not extend to the low impurity concentration layer, and therefore the effect of maintaining the withstand voltage is not obtained. Therefore, the thickness of the chip of the related semiconductor device increases by the amount of the low impurity concentration layer, and the conduction loss increases. In contrast, as described below, in the semiconductor device according to the embodiment of the present invention, the surge voltage at the time of off-state can be suppressed without increasing the thickness of the semiconductor device.

< embodiment 1>

Fig. 2 is a schematic cross-sectional view showing the structure of a semiconductor device 100 according to embodiment 1 of the present invention. In the example of fig. 2, the semiconductor device 100 is an FS type IGBT, as in the case of the related semiconductor device. The semiconductor device 100 and n is a constituent element of the related semiconductor device shown in fig. 1⁺The buffer layer 12 being replaced by n⁺Type 1 st buffer layer 13, n^-The structure of the type back carrier accumulation layer 14 and the n-type 2 nd buffer layer 15 is the same. Hereinafter, among the components described in embodiment 1, the same reference numerals are given to the same or similar components as those described above, and different components will be mainly described.

The semiconductor device 100 includes n as a 1 st semiconductor layer⁺Type 1 buffer layer 13, n as 2 nd semiconductor layer^-type back carrier accumulation layer 14 as the 3 rd semiconductorN-type 2 nd buffer layer 15 of bulk layer and n as 4 th semiconductor layer^-and a drift layer 11. These n⁺type 1 st buffer layer 13, n^-Type back carrier accumulation layer 14, n-type 2 nd buffer layer 15, n^-The type drift layers 11 are stacked in this order from bottom to top. In the following description, n may be n⁺Type 1 st buffer layer 13, n^-Type back carrier accumulation layer 14, n-type 2 nd buffer layer 15, n^-The type drift layer 11 is collectively referred to as "4 semiconductor layers".

The semiconductor device 100 includes a trench gate electrode 1, an emitter electrode 4, and n, as in the related semiconductor device⁺Emitter layer 5, p-type base layer 6, n-type carrier accumulation layer 7, interlayer insulating film 8, p⁺Collector type layer 9, collector electrode 10.

A p-type base layer 6 arranged on n^-Upper surface side of type drift layer 11, n⁺The emitter layer 5 is selectively disposed on the upper surface of the p-type base layer 6. The trench gate electrode 1 capable of forming a channel in the p-type base layer 6 is arranged from n⁺The upper surface of the emitter layer 5 reaches n^-The drift layer 11 can be formed such that n is n when a gate voltage is applied to the gate electrode 3⁺Type emitter layer 5 and n^-A channel conducting between the drift layers 11. And, p⁺A collector layer 9 arranged on n⁺A collector electrode 10 is disposed below the 1 st buffer layer 13⁺The lower surface of the type collector layer 9.

in addition, the semiconductor device 100 of FIG. 2 has p-type base layers 6 and n^-The n-type carrier accumulation layer 7 is provided between the drift layers 11, but the n-type carrier accumulation layer 7 is not essential.

Fig. 3 is a graph showing an impurity concentration profile, i.e., a profile of net doping concentration, in the line a-a' of fig. 2.

n^-The n-type impurity concentration of one of the semiconductor layers of the type back carrier accumulation layer 14 and the n-type 2 nd buffer layer 15 is lower than the n-type impurity concentrations of the semiconductor layer adjacent to the one semiconductor layer in the upward direction and the semiconductor layer adjacent to the one semiconductor layer in the downward direction.

For example, the semiconductor layer is n^-Back carrier accumulation layer 14, n of type^-The n-type impurity concentration of the type back carrier accumulation layer 14 is lower than that of the n-type 2 nd buffer layer 15 adjacent to the n-type back carrier accumulation layer in the upper direction and that of the n-type buffer layer 15 adjacent to the n-type back carrier accumulation layer in the lower direction⁺The n-type impurity concentration of each of the type 1 buffer layers 13. And, among the 4 semiconductor layers, n^-The n-type impurity concentration of the type back carrier accumulation layer 14 is the lowest. The n-type buffer layer 2 15 has an n-type impurity concentration higher than n^-The n-type impurity concentration of the drift layer 11.

For example, the one semiconductor layer may be the n-type 2 nd buffer layer 15. In this case, as shown in fig. 4, the n-type impurity concentration of the n-type 2 nd buffer layer 15 is lower than that of the n-type adjacent to the n-type 2 nd buffer layer in the upward direction^-Drift layer 11 and n adjacent to each other in the lower direction^-The n-type impurity concentration of each of the type back carrier accumulation layers 14. In the following, the semiconductor layer is described as n^-The back surface carrier accumulation layer 14.

In embodiment 1, the profile of the net doping concentration of 4 semiconductor layers is a stepwise profile. The stepwise profile is a profile having a portion where the concentration is substantially constant and a portion where the change in concentration is rapid.

In addition, in n^-The concentration of hydrogen atoms contained in the type back carrier accumulation layer 14 is equal to the concentration of hydrogen atoms contained in n of the n-type 2 nd buffer layer 15 adjacent in the up direction and the n + type 1 st buffer layer 13 adjacent in the down direction. Here, the hydrogen atom concentrations of both being equal means that the difference in hydrogen ion concentration between the two regions is equal to or less than the detection limit. In the detection limit, for example, a general definition of 3 times or less of noise is adopted. Here, the standard deviation of the hydrogen concentration in the chip depth direction of the entire 4 semiconductor layers and the standard deviation of the hydrogen concentration in the chip depth direction of each of the 4 semiconductor layers are n^-The standard deviation of the hydrogen ion concentration in the chip depth direction of drift layer 11 is 3 times or less.

n^-The lower limit of the thickness of the back surface carrier trapping layer 14 is effective in carrier trappingThe thickness is determined in the range where the effect does not disappear, and is, for example, approximately 0.5 μm. n is^-The upper limit of the thickness of the type back surface carrier accumulation layer 14 is, for example, 20 μm. However, with respect to n^-The upper limit of the thickness of the back surface carrier storage layer 14 needs to be such that the entire carrier distribution pattern of the n-type layer can be designed to maintain the rated voltage of the semiconductor device 100. In addition, from the viewpoint of surge suppression of the off-voltage, the impurity area density is preferably high in order to stop the extension of the depletion layer. It is preferable to design n within a range satisfying the impurity areal density of the n-type layer thus designed^-Thickness and impurity concentration of the type back surface carrier accumulation layer 14.

Furthermore, to prevent the depletion layer from reaching p at the time of turn-off⁺Punch-through of the type collector layer 9, n⁺The impurity concentration of the type 1 st buffer layer 13 is more preferably high. On the other hand, in n⁺When the concentration of the type 1 st buffer layer 13 is high, p comes from the on state⁺The injection efficiency of holes of the type collector layer 9 is lowered. From p⁺The decrease in the hole injection efficiency of the type collector layer 9 leads to an increase in the on-voltage, p⁺An increase in variation in on-voltage due to variation in concentration of the collector layer 9 and a decrease in reliability of the semiconductor device 100 due to an increase in back surface electric field at the time of off-state. Thus, p⁺Impurity concentration peak and n of type collector layer 9⁺The ratio of the impurity concentration peak of the type 1 st buffer layer 13 needs to be determined appropriately. Specifically, the ratio is preferably 10 or more. By designing the concentration ratio in this manner, it is possible to simultaneously suppress punch-through and maintain hole injection efficiency. As described above, it is necessary to design the concentration profile of the entire n-type layer so as not to exceed the upper limit of the impurity areal density defined by the thickness of the n-type layer and the withstand voltage.

Further, the n-type 2 nd buffer layer 15 has an orientation n^-The effect of trapping holes in the type back surface carrier accumulation layer 14 and the effect of suppressing the expansion of the depletion layer extending from the surface at the time of turn-off. Therefore, the impurity concentration ratio n of the n-type 2 nd buffer layer 15 is required to be higher than that of the n^-The impurity concentration of the type back surface carrier accumulation layer 14 is sufficiently high. Specifically, the n-type 2 nd buffer layer 15 has an impurity peak concentration and n^-The concentration ratio of the impurity peak concentration of the type back surface carrier accumulation layer 14 is preferably 3 or more, and more preferably 10 or more. By designing such an impurity concentration profile, the depletion of holes in the back surface can be suppressed, and the expansion of the depletion layer can be suppressed.

< summary of embodiment 1>

according to the structure of the semiconductor device 100 according to embodiment 1, the slave p is turned on⁺Part of holes injected from the type collector layer 9 is accumulated in n^-The back surface carrier accumulation layer 14. When the semiconductor device is turned off, a depletion layer from an upper pn junction surface such as a pn junction surface of the p-type base layer 6 is n^-And elongation in the drift layer 11. In this case, n is a component of the semiconductor device 100 according to embodiment 1^-The effect of the back surface carrier accumulation layer 14 that a part of the holes are retained is more that the related semiconductor device, and therefore n can be delayed^-Depletion of carriers in the drift layer 11. This can suppress a rapid decrease in collector current during the off period, and can reduce a surge voltage generated due to the rapid decrease in current.

In addition, is provided at n^-The n-type 2 nd buffer layer 15 on the type back surface carrier accumulation layer 14 functions as a deep buffer layer structure that suppresses the extension of the depletion layer, and therefore, the surge voltage can be further reduced. As described above, by setting n^-The type back carrier accumulation layer 14 and the n-type 2 nd buffer layer 15 can improve the surge voltage suppression effect without increasing the thickness of the chip. Thus, a power module capable of suppressing a malfunction generated when an overvoltage is applied to a semiconductor device such as an IGBT and reducing noise can be provided.

< embodiment 2>

Conventionally, several methods have been proposed as a method for forming a deep buffer layer structure. For example, a method is known in which a shallow n-type buffer layer is formed by ion implantation of phosphorus, and then selenium or sulfur having a higher diffusion coefficient than phosphorus is ion implanted to form a buffer layer having a concentration gradient up to a deep portion. However, selenium is in general semiconductorsSince the ion implantation apparatus is not used in the process, a dedicated expensive ion implantation apparatus is required, and there is a fear that other equipment is contaminated when a diffusion furnace or the like is used. Further, since the range of selenium and sulfur in ion implantation is generally about 1 μm, it is difficult to form the layer structure of the semiconductor device 100 according to embodiment 1, that is, the structure including n^-The back surface carrier accumulation layer 14 has a multilayer structure with different concentrations.

In addition, it is known to irradiate protons (H) in multiple stages while varying the acceleration energy and the dose⁺) A method of forming a multilayered semiconductor layer. However, an accelerator such as a cyclotron is required for proton irradiation, and there is a problem that the installation location of the accelerator, that is, the location where the accelerator can be irradiated, is limited. In addition, since crystal defects are generated in the semiconductor region through which protons pass, the leakage current in the off state in the IGBT increases. The impurity concentration profile formed by proton irradiation is gaussian. Therefore, when the region of the 2-step proton irradiation and the 2-step proton irradiation with the 2-step sweep of the gaussian distribution is used as the low impurity concentration layer, it is necessary to sufficiently separate the peaks of the 2-step gaussian distribution from each other so that the low impurity concentration layer is sufficiently reduced in concentration. However, the irradiation of protons from the lower surface (back surface) of the IGBT to a deep position by a high acceleration voltage, which is necessary for realizing this, has a problem of further increasing crystal defects.

therefore, the manufacturing method according to embodiment 2 of the present invention can solve the problem that occurs when manufacturing the semiconductor device 100 according to embodiment 1. Fig. 5 to 9 are sectional views for explaining the semiconductor device in each step of the manufacturing method according to embodiment 2.

First, n shown in FIG. 5 is prepared as⁺N of type semiconductor substrate⁺A model silicon substrate 16. Further, n is⁺A part of the type silicon substrate 16 becomes n in fig. 2 through the following steps⁺Type 1 buffer layer 13.

Next, as shown in FIG. 5, at n⁺N is formed on the upper surface of the type silicon substrate 16^-Type I1 epitaxial growth layer 17, n-type 2 nd epitaxial growth layer 18, n^-Type 3 epitaxial growth layer 19. N as a substrate for epitaxial growth⁺The method for manufacturing the silicon substrate 16 is arbitrary, and for example, FZ method, MCZ method, CZ (Czochralski) method, or the like can be used. The concentration of the substrate and each epitaxially grown layer on the substrate can be controlled by changing the doping concentration of, for example, phosphorus or arsenic. According to the manufacturing method of embodiment 2, the impurity concentration profile can be made the stepped profile described in embodiment 1, unlike the proton irradiation of the related semiconductor device.

The difference between the conventional deep buffer layer structure formed by proton irradiation and the buffer layer structure according to embodiment 2 formed by epitaxial growth and the method for determining the difference between these layer structures will be described below.

It is known that hydrogen donors are generally formed when a single-crystal silicon is irradiated with protons and then subjected to a heat treatment. It is considered that the irradiation defects are bonded to hydrogen atoms with the heat treatment to form hydrogen donors. The irradiation defects decrease the carrier lifetime of the semiconductor device, increase the on-resistance, or increase the leakage current, so it is preferable that the number of crystal defects is as small as possible. Therefore, heat treatment at high temperature is required.

However, generally, the proton irradiation is performed after the structure on the front surface side (upper side in fig. 2) of the semiconductor device is manufactured. In order to prevent damage to the surface structure of the semiconductor device, the temperature of the heat treatment after proton irradiation is limited to, for example, 400 ℃. Therefore, the crystal defects are not sufficiently recovered, and in the buffer layer region, a VO complex defect formed by vacancies (V) and oxygen (O) atoms and a VOH complex defect including hydrogen (H) remain. On the other hand, in the manufacturing method according to embodiment 2, since the epitaxial growth method is used, a deep buffer layer can be formed in a wafer state with defects that reduce the lifetime being suppressed before the surface structure is formed.

In general, after the front surface of the semiconductor device is formed and before proton irradiation, the semiconductor device is ground and thinned from the back surface side. By this thinning, a thickness deviation of 1 μm occursTo the extent of 5 μm. Therefore, when proton irradiation is performed under the same conditions, an error of the same degree as the variation in thickness occurs in the back surface carrier distribution map. The irradiation depth of the protons to the wafer can be controlled by an absorber made of aluminum foil or the like. However, since the production efficiency is extremely lowered when the absorber is replaced in accordance with the grinding error of the wafer, the adjustment of the back surface carrier profile using the absorber is difficult, and the grinding thickness error cannot be reduced in the step of proton irradiation. As a result of the above, in the case where it is intended to form a low impurity concentration layer on the back surface by proton irradiation, the depth as viewed from the surface varies for each semiconductor device. On the other hand, in embodiment 2, n is formed in advance by epitaxial growth^-Back carrier accumulation layer of type 14, n⁺Since the type 1 buffer layer 13 and the n-type 2 buffer layer 15 can be formed by n^-The depth of the impurity concentration layer of the back carrier accumulation layer 14 as viewed from the front surface side is constant. Therefore, variations in manufacturing can be suppressed.

Several methods are considered for determining whether the deep buffer layer is formed by proton irradiation or epitaxial growth. For example, the manufacturing method can be determined by whether or not a peak due to a VO complex defect or a VOH complex defect is detected by a Deep Level Transient Spectrum (DLTS) method. As another method, the manufacturing method can be determined based on whether or not hydrogen atoms of different concentrations remain at the peak positions of the n-type impurity concentration of each buffer layer. For example, in FIG. 2 and FIG. 3, the measurement of n is performed by SIMS (Secondary Ion Mass Spectrometry) method^-The concentration of hydrogen atoms contained in each of the type drift layer 11 and the n-type 2 nd buffer layer 15. Further, if the measured concentrations of the both are equal, it can be judged that the buffer layer is formed by epitaxial growth, and if the measured concentrations of the both are different, it can be judged that the buffer layer is formed by proton irradiation.

N is a magnitude relation of an impurity concentration of n-type of each layer^-The type 1 st epitaxial growth layer 17 has the lowest impurity concentration, and the n-type 2 nd epitaxial growth layer 18 has an impurity concentration higher than n^-Impurity concentration of the type 3 rd epitaxial growth layer 19. Through the above steps, in n⁺N is formed on the upper surface of the type silicon substrate 16 by epitaxial growth^-Type back carrier accumulation layer 14, n-type 2 nd buffer layer 15, n^-And a drift layer 11.

Next, as shown in FIG. 6, at n^-A trench gate electrode 1, an emitter electrode 4, and an n electrode are formed on the upper surface of the drift layer 11⁺A type emitter layer 5, a p-type base layer 6, an n-type carrier accumulation layer 7, and an interlayer insulating film 8.

Then, as shown in FIG. 7, n is added⁺The model silicon substrate 16 is ground from its back side to n⁺The thickness of the silicon substrate 16 is a predetermined thickness. After grinding, n may be set to⁺The type silicon substrate 16 is made to have a higher concentration, and is activated by, for example, laser annealing after ion implantation of phosphorus or the like. Thereby forming n⁺Type 1 buffer layer 13.

Further, as shown in FIG. 8, n is the number of n⁺The lower surface (back surface) of the type 1 st buffer layer 13 is subjected to activation annealing such as ion implantation of boron and laser annealing to form p⁺And a collector layer 9 of the type.

Finally, as shown in FIG. 9, at p⁺Collector electrode 10 is formed on the lower surface of collector type layer 9. Thus, the semiconductor device 100 according to embodiment 1 is completed.

Here, in n⁺When all of the silicon substrate 16 is ground, the strength of a wafer on which semiconductor devices such as IGBTs are formed may be reduced, and the wafer may be broken during production. Therefore, n is preferably such that⁺The thickness of the chip of the semiconductor device is designed so that the upper limit of the grinding error of the silicon substrate 16 is 2 μm or more. According to such a step, the breakage of the wafer can be reduced. In addition, n can be substituted⁺Type silicon substrate 16 is active as n⁺The type 1 st buffer layer 13 can reduce the number of manufacturing steps.

In addition, when a deep buffer layer structure is to be formed by proton irradiation after the surface production process, it is not possible to form n-type impurities in the buffer layer by proton irradiationThe concentration is equal to or less than the concentration of the substrate. Thus, even if one wants to irradiate by protons, n on the back surface⁺N is formed near the type 1 buffer layer 13^-A low concentration layer such as the back surface carrier storage layer 14 cannot be made sufficiently low in concentration. On the other hand, according to embodiment 2, since the concentration of each buffer layer on the back surface can be freely controlled during epitaxial growth, n can be designed so as to be n, for example^-the impurity concentration of the back carrier accumulation layer 14 is lower than n^-And a drift layer 11. As described above, the manufacturing method of embodiment 2 also has the effect of improving the degree of freedom in designing the impurity concentration profile of the back surface.

Furthermore, in the manufacturing method of embodiment 2, n is formed by epitaxial growth^-Back carrier accumulation layer of type 14, n⁺Since the type 1 buffer layer 13 and the n-type 2 buffer layer 15 can be formed by n^-The impurity concentration of each film such as the back carrier accumulation layer 14 is constant in each film, and the design of the impurity concentration is facilitated. In addition, according to the manufacturing method of embodiment 2, n is easily made^-The thickness of the back surface carrier storage layer 14 is relatively thick, for example, 20 μm, and therefore, it is advantageous to increase the hole storage amount and control the hole storage amount.

< summary of embodiment 2>

According to the manufacturing method of embodiment 2, a semiconductor device is manufactured using a silicon substrate having a desired impurity concentration profile formed by epitaxial growth in advance. Thus, n can be included without introducing a special apparatus or a special process^-The multilayer layer structure of the back surface carrier accumulation layer 14 can be easily produced. Further, by using the epitaxial growth method, a stepwise profile or the like can be realized, and a desired difference in concentration between semiconductor layers and a desired thickness of each layer can be realized. In addition, n is prepared by mixing⁺The ground residue of the silicon substrate 16 is used as n⁺The type 1 st buffer layer 13 can reduce the number of epitaxial layers, the ion implantation step, and the laser annealing step, and can improve the strength of the substrate. This can improve the productivity and yield of semiconductor devices such as IGBTs.

In addition, is provided at n^-The n-type 2 nd buffer layer 15 on the type back surface carrier accumulation layer 14 functions as a deep buffer layer structure that suppresses the extension of the depletion layer, and therefore, the surge voltage can be further reduced. As described above, by setting n^-The type back carrier accumulation layer 14 and the n-type 2 nd buffer layer 15 can improve the surge voltage suppression effect without increasing the thickness of the chip. Thus, a power module capable of suppressing a malfunction generated when an overvoltage is applied to a semiconductor device such as an IGBT and reducing noise can be provided.

< embodiment 3>

The manufacturing method according to embodiment 3 of the present invention can solve the problem occurring in manufacturing the semiconductor device 100 according to embodiment 1, as in the manufacturing method according to embodiment 2. Fig. 10 to 14 are sectional views for explaining the semiconductor device in each step of the manufacturing method according to embodiment 3.

First, n shown in FIG. 10 is prepared as^-N of type semiconductor substrate^-A model silicon substrate 20. Further, n is^-A part of the type silicon substrate 20 is n in fig. 2 through the following steps^-The back surface carrier accumulation layer 14.

Then, as shown in FIG. 10, at n^-An n-type 1 st epitaxial growth layer 21 and n are sequentially formed on the upper surface of the type silicon substrate 20^-type 2 epitaxially grown layer 22. According to the manufacturing method of embodiment 3, the impurity concentration profile can be made to be the stepped profile described in embodiment 1. Through the above steps, in n^-An n-type 2 nd buffer layer 15 and an n-type buffer layer 15 are sequentially formed on the upper surface of a type silicon substrate 20 by epitaxial growth^-And a drift layer 11.

next, as shown in FIG. 11, n is formed^-type drift layer 11 trench gate electrode 1, emitter electrode 4, n⁺A type emitter layer 5, a p-type base layer 6, an n-type carrier accumulation layer 7, and an interlayer insulating film 8.

Then, as shown in FIG. 12, n is added^-The type silicon substrate 20 is from its back sideGrinding. Thereby forming n^-The back surface carrier accumulation layer 14. In addition, n after grinding^-The thickness of the type silicon substrate 20 is preferably 3 μm or more.

Then, as shown in FIG. 13, at n^-Lower surface (back surface) of type silicon substrate 20, i.e., n^-The lower surface of the back carrier accumulation layer 14 is subjected to activation annealing such as ion implantation of phosphorus and laser annealing to form n⁺Type 1 buffer layer 13. Then, at n⁺The lower surface of the type 1 st buffer layer 13 is subjected to activation annealing such as ion implantation of boron and laser annealing to form p⁺And a collector layer 9 of the type.

Finally, as shown in FIG. 14, at p⁺Collector electrode 10 is formed on the lower surface of collector type layer 9. Thus, the semiconductor device according to embodiment 1 is completed. N of the thus completed semiconductor device^-The n-type impurity concentration of the type back carrier accumulation layer 14 is lower than n⁺The n-type impurity concentration of the type 1 st buffer layer 13 and the n-type 2 nd buffer layer 15.

< summary of embodiment 3>

N is defined as in embodiment 2 described above⁺The ground residue of the silicon substrate 16 is used as n⁺In the method of the type 1 buffer layer 13, n is generated due to a grinding error⁺The impurity amount in the type 1 st buffer layer 13 greatly varies. Therefore, the characteristics of the semiconductor devices such as IGBTs vary from wafer to wafer. On the other hand, according to the manufacturing method of embodiment 3, n is used^-The type silicon substrate 20 can reduce n⁺The variation in the amount of impurities in the type 1 st buffer layer 13 is directed to the influence of the variation in the grinding thickness. Further, by mixing n^-The ground residue of the silicon substrate 20 is used as n^-The back carrier accumulation layer 14 can reduce the number of epitaxial layers and improve the strength of the substrate. This can improve the productivity and yield of semiconductor devices such as IGBTs.

< embodiment 4>

The semiconductor device 100 according to embodiment 4 of the present invention has the same cross-sectional structure (fig. 2) as the semiconductor device 100 according to embodiment 1, except for the impurity concentration profile. Hereinafter, among the components described in embodiment 4, the same reference numerals are given to the same or similar components as those described above, and different components will be mainly described.

Fig. 15 is a graph showing an impurity concentration profile, i.e., a profile of net doping concentration, in the line a-a' of fig. 2.

In embodiment 1 of fig. 3, n is n among the 4 semiconductor layers^-The n-type impurity concentration of the type back carrier accumulation layer 14 is the lowest. In contrast, in embodiment 4 of fig. 15, n is n among the 4 semiconductor layers described above^-the n-type impurity concentration of the type drift layer 11 is the lowest. And, n^-the n-type impurity concentration of the type back carrier accumulation layer 14 is lower than n⁺The n-type impurity concentration of the n-type 1 st buffer layer 13 and the n-type impurity concentration of the n-type 2 nd buffer layer 15.

< summary of embodiment 4>

According to the above structure, n can be set^-The drift layer 11 is lower than n^-Impurity concentration of the type back surface carrier accumulation layer 14. This can improve the delay of n at the time of shutdown^-The function of the deep buffer layer extending in the depletion layer extending in the back carrier accumulation layer 14, i.e., the function of delaying the extension of the depletion layer. This can suppress the surge voltage.

< embodiment 5>

Fig. 16 is a schematic cross-sectional view showing the structure of a semiconductor device 100 according to embodiment 5 of the present invention. Hereinafter, among the components described in embodiment 5, the same reference numerals are given to the same or similar components as those described above, and different components will be mainly described.

The semiconductor device 100 according to embodiment 1 includes n⁺Type 1 st buffer layer 13, n^-type back carrier accumulation layer 14, n-type 2 nd buffer layer 15, n^-And a drift layer 11. The semiconductor device 100 according to embodiment 5 includes, instead of these components, a componentN of the 1 st semiconductor layer^-Type 1 st back surface carrier accumulation layer 23, n-type 2 nd buffer layer 15 as 2 nd semiconductor layer, n as 3 rd semiconductor layer^--Type 2 nd back surface carrier accumulation layer 24, n as the 4 th semiconductor layer^-drift layer 11, n as the 5 th semiconductor layer⁺Type 1 buffer layer 13.

n^-Type 1 st back surface carrier accumulation layer 23, n type 2 nd buffer layer 15, n^--Type 2 nd back surface carrier accumulation layer 24, n^-The type drift layer 11 is stacked from below to above. n is⁺The type 1 st buffer layer 13 is disposed at n^-Type 1 st back carrier accumulation layer 23 and p⁺Between the collector type layers 9. In the following description, n may be n^-Type 1 st back surface carrier accumulation layer 23, n type 2 nd buffer layer 15, n^--Type 2 nd back surface carrier accumulation layer 24, n^-Drift layer 11, n⁺The type 1 st buffer layer 13 is collectively referred to as "5 semiconductor layers".

Fig. 17 is a graph showing an impurity concentration profile, i.e., a profile of net doping concentration, in the line a-a' of fig. 16.

n-type 2 nd buffer layer 15 and n^--The n-type impurity concentration of any one semiconductor layer of the type 2 nd back surface carrier accumulation layer 24 is lower than the n-type impurity concentrations of the semiconductor layer adjacent to the one semiconductor layer in the up direction and the semiconductor layer adjacent to the one semiconductor layer in the down direction. In embodiment 5, n represents one of the semiconductor layers^--Type 2 nd back surface carrier accumulation layer 24, n^--the n-type impurity concentration of the type 2 nd back surface carrier accumulation layer 24 is lower than that of the n adjacent in the upward direction^-The n-type drift layer 11 and the n-type 2 nd buffer layer 15 adjacent to each other in the lower direction have respective n-type impurity concentrations.

And, among the 5 semiconductor layers, n^--The n-type impurity concentration of the type 2 nd back surface carrier accumulation layer 24 is the lowest. n is^-The n-type impurity concentration of the type 1 st back surface carrier accumulation layer 23 is lower than the n-type impurity concentration of the n-type 2 nd buffer layer 15 and n⁺The n-type impurity concentration of the type 1 st buffer layer 13. In this embodiment 5, the net doping concentration of 5 semiconductor layersthe degree profile is a step profile.

In addition, in n^--The concentration of hydrogen atoms contained in the type 2 nd back surface carrier accumulation layer 24 and n adjacent in the upward direction^-The concentration of hydrogen atoms contained in n in each of the n-type drift layer 11 and the n-type 2 nd buffer layer 15 adjacent to each other in the lower direction is equal. Here, the standard deviation of the hydrogen concentration in the chip depth direction of the entire 5 semiconductor layers and the standard deviation of the hydrogen concentration in the chip depth direction of each of the 5 semiconductor layers are n^-The standard deviation of the hydrogen ion concentration in the chip depth direction of drift layer 11 is 3 times or less.

< production method >

Fig. 18 is a sectional view for explaining a semiconductor device in a first step of the manufacturing method according to embodiment 5.

First, n shown in FIG. 18 is prepared as⁺n of type semiconductor substrate⁺A model silicon substrate 16. Further, n is⁺A part of the type silicon substrate 16 finally becomes n of fig. 16⁺Type 1 buffer layer 13.

Then, as shown in FIG. 18, at n⁺N is formed on the upper surface of the type silicon substrate 16^-Type 1 st epitaxial growth layer 17, n type 2 nd epitaxial growth layer 18, n^--Type 3 epitaxial growth layer 25, n^-Type 4 epitaxially grown layer 26. I.e. at n⁺N is formed on the upper surface of the type silicon substrate 16^-Type 1 st back surface carrier accumulation layer 23, n type 2 nd buffer layer 15, n^--Type 2 nd back surface carrier accumulation layer 24, n^-And a drift layer 11. In the structure of fig. 18, the same steps as those of fig. 6 to 9 described in embodiment 2 are performed. Thus, having n^-Type 1 st back surface carrier accumulation layer 23 and n^--The semiconductor device 100 according to embodiment 5 of the type 2 nd back surface carrier accumulation layer 24, i.e., the 2 nd order back surface carrier accumulation layer is completed.

< summary of embodiment 5>

According to the semiconductor device 100 of embodiment 5 having a plurality of back surface carrier accumulation layers, holes can be efficiently accumulated in the on state. This can further enhance the depletion of carriers at the time of off-state, and can further suppress the surge voltage at the time of off-state.

Although the semiconductor device including the 2-stage back surface carrier storage layer is described in embodiment 5, the semiconductor device including the 3-stage or more back surface carrier storage layer has the same effects as described above.

< modification of embodiment 5>

The manufacturing method described in embodiment 5 is the same as the manufacturing method according to embodiment 2, but is not limited thereto, and may be the same as the manufacturing method according to embodiment 3, for example.

Fig. 19 is a sectional view for explaining a semiconductor device in a first step of the manufacturing method according to embodiment 5.

First, n shown in FIG. 19 is prepared as^-N of type semiconductor substrate^-A model silicon substrate 20. Further, n is^-A part of the type silicon substrate 20 finally becomes n of fig. 16^-Type 1 st back surface carrier accumulation layer 23.

Then, as shown in FIG. 19, at n^-An n-type 1 st epitaxial growth layer 21 and n are sequentially formed on the upper surface of the type silicon substrate 20^--Type 2 epitaxial growth layer 27, n^-Type 3 epitaxially grown layer 28. I.e. at n^-An n-type 2 nd buffer layer 15 and an n-type buffer layer are sequentially formed on the upper surface of a type silicon substrate 20^--Type 2 nd back surface carrier accumulation layer 24, n^-And a drift layer 11. In the structure of fig. 19, the same steps as those in fig. 10 to 14 described in embodiment 3 are performed. Thus, having n^-Type 1 st back surface carrier accumulation layer 23 and n^--The semiconductor device 100 according to embodiment 5 of the type 2 nd back surface carrier accumulation layer 24, i.e., the 2 nd order back surface carrier accumulation layer is completed.

According to the present modification as described above, the number of epitaxial layers can be reduced in one step as compared with the manufacturing method described in embodiment 5, and therefore, the productivity of the semiconductor device is improved. In addition, similar to embodiment 5, the same effects as described above can be obtained by fabricating a semiconductor device including a back surface carrier accumulation layer of 3 levels or more in this modification.

< embodiment 6>

Fig. 20 is a schematic cross-sectional view showing the structure of a semiconductor device 100 according to embodiment 6 of the present invention. Hereinafter, among the components described in embodiment 6, the same reference numerals are given to the same or similar components as those described above, and different components will be mainly described.

The semiconductor device 100 according to embodiment 6 and the structure of embodiment 5 are different from each other in n^-The structure other than the type 1 st back surface carrier accumulation layer 23 is the same. The semiconductor device 100 according to embodiment 6 includes n as the 1 st semiconductor layer⁺A type 1 buffer layer 13, an n-type 2 buffer layer 15 as a 2 nd semiconductor layer, and an n-type 3 rd semiconductor layer^--Type back carrier accumulation layer 29, n as the 4 th semiconductor layer^-And a drift layer 11. In the following description, n may be n⁺Type 1 st buffer layer 13, n-type 2 nd buffer layer 15, n^--Back carrier accumulation layer 29, n of type^-The type drift layer 11 is collectively referred to as "4 semiconductor layers".

fig. 21 is a graph showing an impurity concentration profile, i.e., a profile of net doping concentration, in the line a-a' of fig. 21.

n-type 2 nd buffer layer 15 and n^--The n-type impurity concentration of one semiconductor layer of the type back carrier accumulation layer 29 is lower than the n-type impurity concentrations of the semiconductor layer adjacent to the one semiconductor layer in the upward direction and the semiconductor layer adjacent to the one semiconductor layer in the downward direction. In embodiment 6, n represents one of the semiconductor layers^--Back carrier accumulation layer 29, n of type^--The n-type impurity concentration of the type back carrier accumulation layer 29 is lower than the n adjacent in the upward direction^-The n-type drift layer 11 and the n-type 2 nd buffer layer 15 adjacent to each other in the lower direction have respective n-type impurity concentrations.

And, among the 4 semiconductor layers, n^--The n-type impurity concentration of the type back carrier accumulation layer 29 is the lowest. n is⁺Of type 1 buffer layer 13The n-type impurity concentration is higher than that of the n-type 2 nd buffer layer 15. In embodiment 6, the profile of the net doping concentration of 4 semiconductor layers is a stepwise profile.

In addition, in n^--The concentration of hydrogen atoms contained in the back carrier accumulation layer 29 and n adjacent to each other in the upward direction^-The concentration of hydrogen atoms contained in n in each of the n-type drift layer 11 and the n-type 2 nd buffer layer 15 adjacent to each other in the lower direction is equal. Here, the standard deviation of the hydrogen concentration in the chip depth direction of the entire 4 semiconductor layers and the standard deviation of the hydrogen concentration in the chip depth direction of each of the 4 semiconductor layers are n^-The standard deviation of the hydrogen ion concentration in the chip depth direction of drift layer 11 is 3 times or less.

< summary of embodiment 6>

N in embodiment 6^--Upper and lower semiconductor layers (n-type 2 nd buffer layer 15, n) in contact with the back carrier accumulation layer 29^-Type drift layer 11) has an impurity concentration lower than n in embodiment 1^-upper and lower semiconductor layers (n) in contact with the back carrier storage layer 14 (fig. 2)⁺Type 1 buffer layer 13, n-type 2 buffer layer 15). Therefore, according to embodiment 6, n can be suppressed in the heating step in the manufacturing process of the semiconductor device^--The impurity concentration of the type back carrier accumulation layer 29 increases due to diffusion of impurities from the upper and lower layers. This can suppress the loss of the carrier accumulation effect of the carrier accumulation layer.

< modifications of embodiments 1 to 6>

In embodiments 1 to 6, the material of each of the 4 semiconductor layers or the material of each of the 5 semiconductor layers is described to be silicon. However, the material of these semiconductor layers is not limited to silicon, and wide band gap semiconductors such as gallium nitride, silicon carbide, aluminum nitride, diamond, and gallium oxide may be used. In addition, although the semiconductor device 100 is described using a trench gate type IGBT as an example, similar effects can be obtained even in a planar gate type IGBT. Further, the present invention can also be applied to a reverse-conducting IGBT (RC-IGBT) and the like.

In addition, the present invention can freely combine the embodiments and the modifications or appropriately modify and omit the embodiments and the modifications within the scope of the present invention.

Although the present invention has been described in detail, the above description is illustrative only in all aspects, and the present invention is not limited thereto. It is to be understood that numerous modifications, not illustrated, can be devised without departing from the scope of the invention.