阅读说明：本技术 有源矩阵基板及其制造方法 (Active matrix substrate and method for manufacturing the same ) 是由 木本英伸 于 2019-06-05 设计创作，主要内容包括：本发明涉及一种有源矩阵基板及其制造方法。FFS模式的液晶面板的有源矩阵基板具备：多个栅极线；多个数据线；多个像素电路,其包含开关元件和像素电极；保护绝缘膜,其与这些要素相比形成于上层；以及共用电极,其形成在保护绝缘膜的上层。数据线包含：下层导体部,其与像素电极一起使用氧化铟锡形成；以及上层导体部,其使用钼铌和铝合金形成。下层导体部形成为在开关元件的位置被切断的形状,上层导体部以与下层导体部重叠的方式形成为连续的形状。从而,提供能够防止数据线的断线不良、取向不良的有源矩阵基板。(The present invention relates to an active matrix substrate and a method for manufacturing the same. An active matrix substrate of an FFS mode liquid crystal panel is provided with: a plurality of gate lines; a plurality of data lines; a plurality of pixel circuits including a switching element and a pixel electrode; a protective insulating film formed on an upper layer than these elements; and a common electrode formed on an upper layer of the protective insulating film. The data line includes: a lower conductor portion formed using indium tin oxide together with the pixel electrode; and an upper conductor portion formed using molybdenum niobium and an aluminum alloy. The lower conductor portion is formed in a cut-off shape at the position of the switching element, and the upper conductor portion is formed in a continuous shape so as to overlap the lower conductor portion. Thus, an active matrix substrate capable of preventing disconnection failure and alignment failure of data lines is provided.)

1. An active matrix substrate is characterized by comprising:

a plurality of gate lines;

a plurality of data lines;

a plurality of pixel circuits, each of which includes a switching element and a pixel electrode, disposed corresponding to an intersection of the gate line and the data line;

a protective insulating film formed on an upper layer of the gate line, the data line, the switching element, and the pixel electrode; and

a common electrode formed on the upper layer of the protective insulating film,

the data line includes: a lower conductor portion formed using indium tin oxide together with the pixel electrode; and an upper conductor portion formed using a metal material other than indium tin oxide,

the lower conductor portion is formed in a shape cut at the position of the switching element,

the upper conductor portion is formed in a continuous shape so as to overlap the lower conductor portion.

2. The active matrix substrate according to claim 1,

the lower conductor portion is cut at a position where the gate line is disposed.

3. The active matrix substrate according to claim 1,

the upper conductor portion is formed using molybdenum niobium and an aluminum alloy.

4. The active matrix substrate according to claim 3,

the upper conductor portion has a 3-layer structure including molybdenum niobium, an aluminum alloy, and molybdenum niobium.

5. The active matrix substrate according to claim 1,

the upper conductor portion is formed to have a narrower line width than the lower conductor portion.

6. The active matrix substrate according to claim 1,

the common electrode has a plurality of slits corresponding to the pixel electrodes.

7. A method for manufacturing an active matrix substrate, comprising:

a step of forming a plurality of gate lines and gate electrodes of a plurality of switching elements on a1 st wiring layer;

a step of forming a gate insulating film and a semiconductor film;

a pixel electrode layer forming step of forming a pixel electrode and a lower conductor portion of the plurality of data lines in the pixel electrode layer using indium tin oxide;

a source layer forming step of forming an upper conductor portion of the data line and a conductive electrode of the switching element in a2 nd wiring layer using a metal material other than indium tin oxide, and patterning the semiconductor film;

forming a protective insulating film on the pixel electrode; and

a step of forming a common electrode on the upper layer of the protective insulating film,

in the pixel electrode layer forming step, the lower conductor portion is formed in a shape cut at a position of the switching element,

in the source layer forming step, the upper conductor portion is formed in a continuous shape so as to overlap the lower conductor portion.

8. The method of manufacturing an active matrix substrate according to claim 7,

in the pixel electrode layer forming step, the lower conductor portion is formed in a shape cut at a position where the gate line is arranged.

9. The method of manufacturing an active matrix substrate according to claim 7,

in the source layer forming step, the upper conductor portion and the conductive electrode are formed using molybdenum niobium and an aluminum alloy.

10. The method of manufacturing an active matrix substrate according to claim 9,

in the source layer forming step, the upper conductor portion and the conductive electrode are formed to have a 3-layer structure including molybdenum niobium, an aluminum alloy, and molybdenum niobium.

11. The method of manufacturing an active matrix substrate according to claim 7,

in the above-described pixel electrode layer forming step, etching is performed using ferric chloride or oxalic acid,

in the source layer formation step, etching is performed using an etching solution that does not etch indium tin oxide.

12. The method of manufacturing an active matrix substrate according to claim 11,

in the above-described source layer formation step, etching is performed using phosphoric acid-nitric acid-acetic acid.

13. The method of manufacturing an active matrix substrate according to claim 7,

in the source layer forming step, the upper conductor portion is formed to have a narrower line width than the lower conductor portion.

14. The method of manufacturing an active matrix substrate according to claim 7,

in the step of forming the common electrode, the common electrode is formed to have a plurality of slits corresponding to the pixel electrodes.

Technical Field

The present invention relates to a display device, and more particularly, to an active matrix substrate having a common electrode and a method for manufacturing the same.

Background

Liquid crystal display devices are widely used as thin, lightweight, and low power consumption display devices. A liquid crystal panel included in a liquid crystal display device has a structure in which an active matrix substrate and a counter substrate are bonded to each other, and a liquid crystal layer is provided between 2 substrates. A plurality of gate lines, a plurality of data lines, and a plurality of pixel circuits including Thin Film transistors (hereinafter, referred to as TFTs) and pixel electrodes are formed on an active matrix substrate.

As methods of applying an electric field to a liquid crystal layer of a liquid crystal panel, a vertical electric field method and a horizontal electric field method are known. In the vertical electric field type liquid crystal panel, an electric field in a substantially vertical direction is applied to a liquid crystal layer using a pixel electrode and a common electrode formed on a counter substrate. In a liquid crystal panel of the transverse electric field type, a common electrode is formed on an active matrix substrate together with a pixel electrode, and a substantially transverse electric field is applied to a liquid crystal layer using the pixel electrode and the common electrode. The liquid crystal panel of the lateral electric field type has an advantage of a wider viewing angle than the liquid crystal panel of the vertical electric field type.

As the transverse electric Field system, an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode are known. In the IPS mode liquid crystal panel, the pixel electrodes and the common electrodes are formed in a comb-tooth shape and are arranged so as not to overlap in a plan view. In the FFS mode liquid crystal panel, a slit is formed in either one of the common electrode and the pixel electrode, and the pixel electrode and the common electrode are arranged so as to overlap with each other in a plan view with a protective insulating film interposed therebetween. The FFS mode liquid crystal panel has an advantage of a high aperture ratio compared to the IPS mode liquid crystal panel.

The active matrix substrate of the FFS mode liquid crystal panel is manufactured using 5 or 6 photomasks. International publication No. 2016/21319 discloses a method for manufacturing an active matrix substrate using 6 photomasks. In this document, after a source layer pattern is formed using MoNb (molybdenum niobium) in the 3 rd step, a pixel electrode is formed using IZO (indium zinc oxide) in the 4 th step. The data line of the active matrix substrate manufactured by this method has a 2-layer structure including a lower layer formed of MoNb and an upper layer formed of IZO.

Data lines having a 2-layer structure are also described in Japanese patent laid-open Nos. 4-276723, 11-295760, and 11-326950. Japanese patent application laid-open No. 4-276723 discloses a data line including a lower layer formed of ITO (indium tin oxide) and an upper layer formed using Mo (molybdenum) and having a width larger than that of the lower layer. Japanese patent application laid-open No. 11-295760 describes a data line including a lower layer formed of ITO and an upper layer formed using Al (aluminum) and having a width larger than that of the lower layer at an end of a portion intersecting with a scanning line. Jp 11-326950 a describes a data line formed by etching a transparent conductive layer and a metal layer in the same pattern.

As described in international publication No. 2016/21319, a case where a source layer pattern is formed using MoNb in the 3 rd step and a pixel electrode is formed using IZO in the 4 th step is considered. In this case, phosphoric acid-nitric acid-acetic acid is used as an etching solution in the 3 rd step and the 4 th step. However, if the etching is performed using the same chemical solution in the 4 th step after the etching is performed using phosphoric acid-nitric acid-acetic acid in the 3 rd step, the etching is excessive. Therefore, if the data line has a defective pattern, the data line is likely to be broken.

In the active matrix substrate described in international publication No. 2016/21319, the drain electrode and the source electrode of the TFT have a 2-layer structure, as in the case of the data line. Therefore, the thickness of the film increases at the position where the TFT is formed, and a step is generated between the position where the TFT is formed and the peripheral portion. If rubbing treatment is performed on an active matrix substrate having a level difference, an alignment failure may occur, and a display failure called a stripe may occur.

Disclosure of Invention

Therefore, it is proposed as a technical problem to provide an active matrix substrate capable of preventing disconnection failure and alignment failure of data lines.

(1) An active matrix substrate according to some embodiments of the present invention includes:

a plurality of gate lines;

a plurality of data lines;

a plurality of pixel circuits, each of which includes a switching element and a pixel electrode, disposed corresponding to an intersection of the gate line and the data line;

a protective insulating film formed on an upper layer of the gate line, the data line, the switching element, and the pixel electrode; and

a common electrode formed on the upper layer of the protective insulating film,

the data line includes: a lower conductor portion formed using indium tin oxide together with the pixel electrode; and an upper conductor portion formed using a metal material other than indium tin oxide,

the lower conductor portion is formed in a shape cut at the position of the switching element,

the upper conductor portion is formed in a continuous shape so as to overlap the lower conductor portion.

According to the active matrix substrate, the lower conductor portion of the data line can be prevented from being excessively etched by appropriately selecting the etching liquid for forming the pixel electrode and the like and the etching liquid for forming the source layer pattern. In addition, the data line has a lengthy structure including a lower conductor portion and an upper conductor portion. Therefore, disconnection failure of the data line can be prevented. Further, since the lower conductor portion is not formed at the position of the switching element, the difference in height between the position where the switching element is formed and the peripheral portion can be reduced, and alignment failure and streaking can be prevented when the rubbing treatment is performed.

(2) The active matrix substrate according to some embodiments of the present invention has the configuration (1) described above,

the lower conductor portion is cut at a position where the gate line is disposed.

(3) The active matrix substrate according to some embodiments of the present invention has the configuration (1) described above,

the upper conductor portion is formed using molybdenum niobium and an aluminum alloy.

(4) The active matrix substrate according to some embodiments of the present invention has the configuration (3) described above,

the upper conductor portion has a 3-layer structure including molybdenum niobium, an aluminum alloy, and molybdenum niobium.

(5) The active matrix substrate according to some embodiments of the present invention has the configuration (1) described above,

the upper conductor portion is formed to have a narrower line width than the lower conductor portion.

(6) The active matrix substrate according to some embodiments of the present invention has the configuration (1) described above,

the common electrode has a plurality of slits corresponding to the pixel electrodes.

(7) A method for manufacturing an active matrix substrate according to some embodiments of the present invention includes:

a step of forming a plurality of gate lines and gate electrodes of a plurality of switching elements on a1 st wiring layer;

a step of forming a gate insulating film and a semiconductor film;

a pixel electrode layer forming step of forming a pixel electrode and a lower conductor portion of the plurality of data lines in the pixel electrode layer using indium tin oxide;

a source layer forming step of forming an upper conductor portion of the data line and a conductive electrode of the switching element in a2 nd wiring layer using a metal material other than indium tin oxide, and patterning the semiconductor film;

forming a protective insulating film on the pixel electrode; and

a step of forming a common electrode on the upper layer of the protective insulating film,

in the pixel electrode layer forming step, the lower conductor portion is formed in a shape cut at a position of the switching element,

in the source layer forming step, the upper conductor portion is formed in a continuous shape so as to overlap the lower conductor portion.

According to the method for manufacturing an active matrix substrate, an active matrix substrate having the above-described effects can be manufactured.

(8) The method for manufacturing an active matrix substrate according to some embodiments of the present invention has the configuration (7) described above,

in the pixel electrode layer forming step, the lower conductor portion is formed in a shape cut at a position where the gate line is arranged.

(9) The method for manufacturing an active matrix substrate according to some embodiments of the present invention has the configuration (7) described above,

in the source layer forming step, the upper conductor portion and the conductive electrode are formed using molybdenum niobium and an aluminum alloy.

(10) The method for manufacturing an active matrix substrate according to some embodiments of the present invention has the configuration (9) described above,

in the source layer forming step, the upper conductor portion and the conductive electrode are formed to have a 3-layer structure including molybdenum niobium, an aluminum alloy, and molybdenum niobium.

(11) The method for manufacturing an active matrix substrate according to some embodiments of the present invention has the configuration (7) described above,

in the above-described pixel electrode layer forming step, etching is performed using ferric chloride or oxalic acid,

in the source layer formation step, etching is performed using an etching solution that does not etch indium tin oxide.

(12) The method for manufacturing an active matrix substrate according to some embodiments of the present invention has the configuration (11) described above,

in the above-described source layer formation step, etching is performed using phosphoric acid-nitric acid-acetic acid.

(13) The method for manufacturing an active matrix substrate according to some embodiments of the present invention has the configuration (7) described above,

in the source layer forming step, the upper conductor portion is formed to have a narrower line width than the lower conductor portion.

(14) The method for manufacturing an active matrix substrate according to some embodiments of the present invention has the configuration (7) described above,

in the step of forming the common electrode, the common electrode is formed to have a plurality of slits corresponding to the pixel electrodes.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention with reference to the accompanying drawings.

Drawings

Fig. 1 is a block diagram showing a configuration of a liquid crystal display device including an active matrix substrate according to an embodiment.

Fig. 2 is a plan view of the active matrix substrate shown in fig. 1.

Fig. 3 is a layout view of the active matrix substrate shown in fig. 1.

Fig. 4 is a diagram showing a pattern other than the common electrode of the active matrix substrate shown in fig. 1.

Fig. 5 is a diagram showing a pattern of a common electrode of the active matrix substrate shown in fig. 1.

Fig. 6A is a view illustrating a method of manufacturing the active matrix substrate shown in fig. 1.

Fig. 6B is a continuation of fig. 6A.

Fig. 6C is a continuation of fig. 6B.

Fig. 6D is a continuation of fig. 6C.

Fig. 6E is a continuation of fig. 6D.

Fig. 6F is a continuation of fig. 6E.

Fig. 7 is a schematic view of a data line of the active matrix substrate shown in fig. 1.

Fig. 8 is a diagram showing characteristics of the etching solution used in the manufacturing method of the embodiment.

Fig. 9 is a diagram showing the 3 rd and 4 th steps of the manufacturing method of the comparative example.

Fig. 10 is a diagram showing the 3 rd and 4 th steps of the manufacturing method of the embodiment.

Fig. 11 is a cross-sectional view of a TFT of an active matrix substrate of a comparative example.

Fig. 12 is a cross-sectional view of a TFT of the active matrix substrate shown in fig. 1.

Fig. 13 is a diagram illustrating an example of the defect rate of the active matrix substrate.

Fig. 14 is a view showing the 3 rd and 4 th steps of the manufacturing method of the modification.

Detailed Description

Fig. 1 is a block diagram showing a configuration of a liquid crystal display device including an active matrix substrate according to an embodiment. The liquid crystal display device 1 shown in fig. 1 includes a liquid crystal panel 2, a display control circuit 3, a gate line drive circuit 4, a data line drive circuit 5, and a backlight 6. In the following, m and n are integers of 2 or more, i is an integer of 1 to m or less, and j is an integer of 1 to n or more.

The liquid crystal panel 2 is an FFS mode liquid crystal panel. The liquid crystal panel 2 has a structure in which an active matrix substrate 10 and a counter substrate 40 are bonded to each other, and a liquid crystal layer is provided between the 2 substrates. A black matrix (not shown) or the like is formed on the counter substrate 40. The active matrix substrate 10 is provided with m gate lines G1 to Gm, n data lines S1 to Sn, (m × n) pixel circuits 20, a common electrode 30 (dot pattern portion), and the like. A semiconductor chip functioning as the gate line driving circuit 4 and a semiconductor chip functioning as the data line driving circuit 5 are mounted on the active matrix substrate 10. Fig. 1 is a diagram schematically showing the configuration of the liquid crystal display device 1, and the shapes of elements described in fig. 1 are inaccurate.

Hereinafter, the extending direction of the gate lines (horizontal direction in the drawing) is referred to as a row direction, and the extending direction of the data lines (vertical direction in the drawing) is referred to as a column direction. The gate lines G1 to Gm extend in the row direction and are arranged parallel to each other. The data lines S1 to Sn extend in the column direction and are arranged parallel to each other. The gate lines G1 to Gm and the data lines S1 to Sn intersect at (m × n) locations. The (m × n) pixel circuits 20 are arranged in a two-dimensional shape corresponding to intersections of the gate lines G1 to Gm and the data lines S1 to Sn.

The pixel circuit 20 includes an N-channel TFT21 and a pixel electrode 22. The TFT21 included in the pixel circuit 20 in the i-th row and j-th column has a gate electrode connected to the gate line Gi, a source electrode connected to the data line Sj, and a drain electrode connected to the pixel electrode 22. A protective insulating film (not shown) is formed on the upper layer of the gate lines G1 to Gm, the data lines S1 to Sn, the TFT21, and the pixel electrode 22. The common electrode 30 is formed on the upper layer of the protective insulating film. The pixel electrode 22 and the common electrode 30 face each other with a protective insulating film interposed therebetween. The backlight 6 is disposed on the back surface side of the liquid crystal panel 2, and irradiates the back surface of the liquid crystal panel 2 with light.

The display control circuit 3 outputs a control signal C1 to the gate line driving circuit 4, and outputs a control signal C2 and a data signal D1 to the data line driving circuit 5. The gate line driving circuit 4 drives the gate lines G1 to Gm based on a control signal C1. The data line driving circuit 5 controls the data lines S1 to Sn based on the control signal C2 and the data signal D1. More specifically, the gate line driving circuit 4 selects 1 gate line from the gate lines G1 to Gm in each horizontal period (row period), and applies a high-level voltage to the selected gate line. The data line driving circuit 5 applies n data voltages corresponding to the data signal D1 to the data lines S1 to Sn in each horizontal period. Accordingly, n pixel circuits 20 are selected in the 1 horizontal period, and n data voltages are written to the selected n pixel circuits 20, respectively.

Fig. 2 is a plan view of the active matrix substrate 10. Fig. 2 shows a part of elements formed on the active matrix substrate 10. As shown in fig. 2, the active matrix substrate 10 is divided into an opposing region 11 opposing the opposing substrate 40 and a non-opposing region 12 not opposing the opposing substrate 40. In fig. 2, the non-opposing region 12 is located on the right and lower sides of the opposing region 11. A display region 13 (region indicated by a broken line) in which the pixel circuit 20 is disposed is set in the counter region 11. The portion of the counter area 11 excluding the display area 13 is referred to as a frame area 14.

In the display region 13, (m × n) pixel circuits 20, m gate lines 23, and n data lines 24 are formed. The (m × n) pixel circuits 20 are two-dimensionally arranged in the display region 13. An external terminal 15 for inputting a common electrode signal is provided in the non-opposing region 12. In order to apply the common electrode signal input from the external terminal 15 to the common electrode 30, the frame region 14 is formed with: a1 st common trunk line 16 formed in the same wiring layer as the gate line 23; and a2 nd common trunk line 17 formed in the same wiring layer as the data line 24. In fig. 2, the 1 st common trunk line 16 is formed above, on the left, and on the lower side of the display region 13, and the 2 nd common trunk line 17 is formed on the right side of the display region 13. In addition, in portions a1 and a2 in fig. 2, a via circuit (not shown) is formed to connect the common electrode 30, the 1 st common trunk line 16, and the 2 nd common trunk line 17. In the non-opposing area 12, a mounting area 18 for mounting the gate line driving circuit 4 and a mounting area 19 for mounting the data line driving circuit 5 are set.

The active matrix substrate 10 is formed by sequentially forming a gate electrode layer, a gate insulating film, a1 st semiconductor layer, a2 nd semiconductor layer, a pixel electrode layer, a source electrode layer, a protective insulating film, and a common electrode layer from below on a glass substrate (details will be described later). The gate line 23 and the 1 st common trunk line 16 are formed in the gate layer. The data line 24 and the 2 nd common trunk line 17 are lines having a 2-layer structure formed in the pixel electrode layer and the source layer.

Fig. 3 is a layout diagram of the active matrix substrate 10. Fig. 3 is divided into 2 diagrams for explanation. Fig. 4 is a diagram showing a pattern of the active matrix substrate 10 other than the common electrode 30. Fig. 5 is a diagram showing the pattern of the common electrode 30 of the active matrix substrate 10. In order to facilitate understanding of the drawings, the pattern shown in fig. 4 is illustrated by thin lines and the pattern shown in fig. 5 is illustrated by lines having a normal thickness in fig. 3.

In fig. 3, an area OP indicated by a thin broken line indicates a position of an opening formed in the counter substrate 40. A region SP indicated by a thin broken line indicates a position (not shown) of a post spacer provided between the active matrix substrate 10 and the counter substrate 40. The column spacer is provided to keep the interval between the active matrix substrate 10 and the counter substrate 40 constant.

As shown in fig. 4, the gate line 23 (left lower diagonal portion) is bent halfway and extends in the row direction. The data line 24 (lower right diagonal portion) has a protruding portion in the vicinity of an intersection with the gate line 23 and extends in the column direction. The gate lines 23 and the data lines 24 are formed in different wiring layers. A TFT21 is formed near the intersection of the gate line 23 and the data line 24. In an area separated by the gate line 23 and the data line 24, a pixel electrode 22 is formed. The TFT21 has a gate electrode connected to the gate line 23, a source electrode connected to the data line 24, and a drain electrode connected to the pixel electrode 22. In this way, the liquid crystal panel 2 includes a plurality of pixel circuits 20 arranged corresponding to intersections of the gate lines 23 and the data lines 24.

The common electrode 30 is formed on a further upper layer of a protective insulating film formed on an upper layer (i.e., on a side closer to the liquid crystal layer) than the TFT21, the pixel electrode 22, the gate line 23, and the data line 24. As shown in fig. 5, the common electrode 30 is formed to cover the entire surface of the display region 13 except for the positions of the slits 31 and the cutouts 32. The common electrode 30 has a plurality of slits 31 corresponding to the pixel electrodes 22 so as to generate a lateral electric field applied to the liquid crystal layer together with the pixel electrodes 22. In fig. 5, 4 slits 31 bent near the center are formed corresponding to 1 pixel electrode 22. By forming the curved slit 31 in the common electrode 30, the viewing angle of the liquid crystal panel 2 can be widened. In addition, the common electrode 30 has cutouts 32 formed at the same positions as the TFTs 21. By providing the notch 32 in the common electrode 30, the common electrode 30 formed above the TFT21 can be prevented from affecting the operation of the TFT 21.

Next, a method for manufacturing the active matrix substrate 10 will be described with reference to fig. 6A to 6F. Fig. 6A to 6F show the process of forming the gate line 23, the data line 24, the pixel opening (the portion facing the opening of the counter substrate 40), the TFT21, and the relay circuit, respectively.

(step 1) formation of Gate layer Pattern (FIG. 6A)

Ti (titanium), Al (aluminum), and Ti were sequentially formed on the glass substrate 101 by a sputtering method. Next, the gate layer is patterned by photolithography and etching to form the gate line 23, the gate electrode 111 of the TFT21, the 1 st common trunk line 16, and the like. Here, the patterning by photolithography and etching refers to the following process. First, a photoresist is coated on a substrate. Next, the substrate is exposed to light by covering a photomask having a desired pattern, and a photoresist having the same pattern as that of the photomask remains on the substrate. Next, the substrate is etched using the remaining photoresist as a mask, thereby forming a pattern on the surface of the substrate. Finally, the photoresist is stripped.

(step 2) formation of semiconductor layer (FIG. 6B)

On the substrate shown in fig. 6A, a SiNx (silicon nitride) film 121, an amorphous Si (amorphous silicon) film 122, and a phosphorus-doped n + amorphous Si film 123 as a gate insulating film are successively formed by a CVD (Chemical Vapor Deposition) method. Next, the semiconductor layer is patterned using photolithography and etching, and the semiconductor layer including the amorphous Si film 122 and the n + amorphous Si film 123 is formed into an island shape over the gate electrode 111 of the TFT 21.

(step 3) formation of Pixel electrode (FIG. 6C)

On the substrate shown in fig. 6B, an ITO film as the pixel electrode 22 is formed by a sputtering method. Next, the pixel electrode layer is patterned by photolithography and etching, and the lower conductor portion 131 of the data line 24, the pixel electrode 22, the lower conductor portion 132 of the 2 nd common dry line 17, and the like are formed. In the 3 rd step, the lower conductor portion 131 of the data line 24 is formed in a shape (a perforated shape) cut at the position of the TFT21 without forming an ITO film at the position of the TFT21 (see fig. 7 described later). In the case of forming an ITO film using poly ITO, wet etching is performed using ferric chloride. In the case of forming an ITO film using amorphous ITO, wet etching is performed using oxalic acid.

(step 4) Source layer Pattern formation (FIG. 6D)

On the substrate shown in fig. 6C, MoNb, an Al alloy, and MoNb were formed in this order by a sputtering method. Next, the source layer is patterned by photolithography and etching, and the upper conductor portion 141 of the data line 24, the source electrode 142 and the drain electrode 143 of the TFT21, the upper conductor portion 144 of the 2 nd common trunk line 17, and the like are formed. In the 4 th step, the upper conductor portion 141 of the data line 24 is formed in a continuous shape so as to overlap the lower conductor portion 131 of the data line 24 (see fig. 7 described later). In the 4 th step, a photomask is used in which a photoresist is left at the positions of the pixel electrode layer pattern and the source layer pattern. Therefore, after exposure, the photoresist remains at the position of the pixel electrode layer pattern and at the position of the source layer pattern. With the photoresist as a mask, the metal film of the 3-layer structure is first etched by wet etching, and then the n + amorphous Si film 123 existing at the position of the channel region of the TFT21 is etched by dry etching. Finally, the photoresist is stripped, thereby obtaining the substrate shown in fig. 6D.

On the substrate shown in fig. 6D, the source electrode 142 and the drain electrode 143 are formed with the channel region of the TFT21 interposed therebetween. The lower conductor portion 131 of the data line 24 is present below the upper conductor portion 141 of the data line 24, and the lower conductor portion 132 of the 2 nd common trunk line 17 is present below the upper conductor portion 144 of the 2 nd common trunk line 17. The data line 24 is formed by the upper conductor portion 141 and the lower conductor portion 131, and the 2 nd common trunk line 17 is formed by the upper conductor portion 144 and the lower conductor portion 132. The upper conductor portions 141 and 144 have a 3-layer structure including MoNb, Al alloy, and MoNb.

Fig. 7 is a schematic diagram of the data line 24. In fig. 7, the data line 24 is illustrated as extending in the horizontal direction of the drawing, unlike in other drawings. In fig. 7, reference symbol GL denotes an arrangement position of the gate line 23. In the 3 rd step, the lower conductor portion 131 of the data line 24 is cut at the position of the TFT21 (fig. 7 (a)). More specifically, the lower conductor portion 131 is formed in a shape cut at the gate line arrangement position GL intersecting the data line 24. In fig. 7 (a), a part of the lower conductor portion 131 is formed so as to overlap with the n + amorphous Si film 123 constituting the TFT 21. The lower conductor portion 131 may not overlap the n + amorphous Si film 123. In the 4 th step, the upper conductor portion 141 of the data line 24 is formed in a continuous shape so as to overlap the lower conductor portion 131 of the data line 24 ((b) of fig. 7). The data line 24 has a 2-layer structure including a lower conductor portion 131 and an upper conductor portion 141.

(step 5) formation of protective insulating film (FIG. 6E)

On the substrate shown in fig. 6D, 2 SiNx films 151 and 152 as a protective insulating film were sequentially formed by CVD. The film formation conditions of the lower SiNx film 151 are different from those of the upper SiNx film 152. For example, a thin film having a high film density formed at a high temperature is used as the lower SiNx film 151, and a thick film having a low film density formed at a low temperature is used as the upper SiNx film 152. Next, the 2-layer SiNx films 151 and 152 formed in the 5 th step and the SiNx film 121 formed in the 2 nd step are patterned using photolithography and etching. As shown in fig. 6E (E), at the position where the via circuit is formed, a contact hole 153 penetrating the SiNx films 151 and 152 of the 2 layers and the SiNx film 121, and a contact hole 154 penetrating the SiNx films 151 and 152 of the 2 layers are formed.

(step 6) formation of common electrode (FIG. 6F)

An IZO film as the common electrode 30 is formed on the substrate shown in fig. 6E by sputtering. Next, the common electrode layer is patterned using photolithography and etching, and the common electrode 30 and the transfer electrode 161 are formed. As shown in fig. 6F (c), a common electrode 30 having a slit 31 is formed in the pixel opening. As shown in fig. 6f (e), the via electrode 161 is in direct contact with the 1 st common trunk line 16 at the position of the contact hole 153, and is electrically connected to the upper layer conductor portion 144 of the 2 nd common trunk line 17 at the position of the contact hole 154. The relay electrode 161 is formed integrally with the common electrode 30. Therefore, common electrode 30, 1 st common trunk line 16, and 2 nd common trunk line 17 can be electrically connected using via electrode 161. By performing the 1 st to 6 th steps described above, the active matrix substrate 10 having the cross-sectional structure shown in fig. 6F can be manufactured.

In the manufacturing method of the present embodiment, in the 1 st to 6 th steps, photolithography is performed using different photomasks. The number of photomasks used in the manufacturing method of the present embodiment is 6 in total. Note that Cu (copper), Mo (molybdenum), Al, Ti, or a laminated film of these metals may be used instead of the above-described materials when the gate line 23 is formed in the 1 st step and when the upper conductor portion 141 of the data line 24 is formed in the 4 th step. In addition, when the protective insulating film is formed in the 5 th step, a 1-layer SiNx film may be formed instead of the 2-layer SiNx film. Alternatively, a SiOx (silicon oxide) film, a SiON (silicon oxynitride) film, or a stacked film thereof may be used instead of the SiNx film. In addition, when the common electrode 30 is formed in the 6 th step, ITO may be used instead of IZO.

In the manufacturing method of the present embodiment, the thickness of each film formed on the substrate is appropriately determined depending on the material, function, and the like of the film. The thickness of the film is, for example, about 10nm to 1 μm. An example of the film thickness is shown below. For example, in the step 1, a Ti film having a thickness of 25 to 35nm, an Al film having a thickness of 180 to 220nm, and a Ti film having a thickness of 90 to 110nm are formed in this order. In the step 2, a SiNx film 121 having a thickness of 360 to 450nm, an amorphous Si film 122 having a thickness of 100 to 200nm, and an n + amorphous Si film 123 having a thickness of 30 to 80nm are continuously formed. In the step 3, an ITO film having a thickness of 80 to 100nm is formed. In the step 4, a MoNb film having a thickness of 40 to 60nm, an Al alloy film having a thickness of 120 to 180nm, and a MoNb film having a thickness of 30 to 40nm are formed in this order. In the step 5, a SiNx film 151 with a thickness of 220 to 280nm and a SiNx film 152 with a thickness of 450 to 550nm are formed, and in the step 6, an IZO film with a thickness of 110 to 140nm is formed.

Fig. 8 is a graph showing the characteristics of the etching solutions used in the 3 rd and 4 th steps. In fig. 8, the o-shaped mark indicates that etching is possible, and the x-shaped mark indicates that etching is not possible. As shown in fig. 8, the MoNb and Al alloy used to form the source layer pattern in the 4 th process can be etched by phosphoric acid-nitric acid-acetic acid, but the etching rate is too fast using ferric chloride, so that the line width and taper size cannot be controlled. On the other hand, the ITO used to form the pixel electrode in the 3 rd process can be etched by ferric chloride, but cannot be etched by phosphoric acid-nitric acid-acetic acid. Therefore, in the production method of the present embodiment, ferric chloride is used as the etching solution in the 3 rd step, and phosphoric acid-nitric acid-acetic acid is used as the etching solution in the 4 th step. In the 3 rd step, instead of ferric chloride, another chemical solution (for example, oxalic acid) capable of etching ITO may be used as the etching solution.

Hereinafter, the manufacturing method described in international publication No. 2016/21319 will be referred to as a "manufacturing method of a comparative example", and the active matrix substrate manufactured by the manufacturing method of the comparative example will be referred to as an "active matrix substrate of the comparative example". Fig. 9 is a diagram showing the 3 rd and 4 th steps of the manufacturing method of the comparative example. In the manufacturing method of the comparative example, after the source layer pattern was formed using MoNb in the 3 rd step, the pixel electrode was formed using IZO in the 4 th step. Accordingly, the data line has a 2-layer structure including a lower layer formed of MoNb and an upper layer formed of IZO.

Fig. 10 is a diagram showing the 3 rd and 4 th steps of the manufacturing method of the present embodiment. In the manufacturing method of the present embodiment, after the pixel circuit 20 is formed using ITO in the 3 rd step, the source layer pattern is formed using MoNb/Al alloy/MoNb in the 4 th step. Therefore, the data line 24 has a 2-layer structure including a lower layer (lower conductor portion 131) formed of ITO and an upper layer (upper conductor portion 141) formed of MoNb/Al alloy/MoNb.

Next, the effects of the active matrix substrate 10 and the method for manufacturing the same according to the present embodiment will be described in comparison with a comparative example. In the manufacturing method of the comparative example, when the source layer pattern is formed using MoNb in the 3 rd step and then the pixel electrode is formed using IZO in the 4 th step, phosphoric acid-nitric acid-acetic acid is used as an etching solution for forming the source layer pattern and the pixel electrode (see fig. 8). However, if the etching is performed using the same chemical solution in the 4 th step after the etching is performed using phosphoric acid-nitric acid-acetic acid in the 3 rd step, the etching is excessive. Therefore, if the data line has a defective pattern, the data line is likely to be broken.

In contrast, in the manufacturing method of the present embodiment, after the pixel electrode 22 and the lower conductor portion 131 of the data line 24 are formed using ITO in the 3 rd step, the source layer pattern (the upper conductor portion 141 of the data line 24, etc.) is formed using MoNb/Al alloy/MoNb in the 4 th step. Ferric chloride is used as an etching solution for forming the pixel electrode 22 and the like, and phosphoric acid-nitric acid-acetic acid is used as an etching solution for forming the source layer pattern. The ITO cannot be etched by phosphoric acid-nitric acid-acetic acid, and thus, even if the source layer pattern is etched using phosphoric acid-nitric acid-acetic acid after the lower conductor part 131 of the data line 24 is formed, the lower conductor part 131 of the data line 24 is not excessively etched. The data line 24 has a redundant structure (2-layer structure) including the lower conductor portion 131 and the upper conductor portion 141. Therefore, even when one of the lower conductor portion 131 and the upper conductor portion 141 is cut at an intermediate position, the data line 24 is not broken as long as the other is connected. Therefore, according to the active matrix substrate 10 of the present embodiment, a disconnection defect of the data line can be prevented.

Fig. 11 is a cross-sectional view of a TFT of an active matrix substrate of a comparative example. Fig. 12 is a cross-sectional view of the TFT21 of the active matrix substrate 10 of the present embodiment. In addition, fig. 11 is also denoted by the same reference numerals as fig. 12 in order to facilitate comparison of the two. Generally, the film thickness of the active matrix substrate is maximized at the position where the TFT is formed.

In the active matrix substrate of the comparative example (fig. 11), the drain electrode and the source electrode of the TFT also have a 2-layer structure (2-layer structure including MoNb and IZO) as in the data line. Therefore, the film thickness increases at the position where the TFT is formed, and a step is generated between the position where the TFT is formed and the peripheral portion. In the example shown in FIG. 11, the difference L1 in height between the highest position of the TFT and the common electrode was 1.55 μm. If rubbing treatment is performed on an active matrix substrate having a level difference, an alignment failure may occur, and a display failure called a stripe may occur.

In contrast, in the active matrix substrate 10 (fig. 12), an ITO film is not formed at the positions of the source electrode 142 and the drain electrode 143 of the TFT 21. Therefore, the film thickness at the position where the TFT21 is formed is thinner than that of the active matrix substrate of the comparative example, and the level difference between the position where the TFT21 is formed and the peripheral portion is smaller. In the example shown in fig. 12, the height difference L2 between the highest position of the TFT21 and the common electrode 30 is 1.48 μm. As described above, according to the active matrix substrate 10 of the present embodiment, the difference in height between the position where the TFT21 is formed and the peripheral portion can be reduced, and alignment failure and streaking can be prevented when rubbing treatment is performed.

Fig. 13 is a diagram illustrating an example of the defect rate of the active matrix substrate. Fig. 13 shows the defect rate of the test active matrix substrate. In the active matrix substrate of the comparative example, the generation rate of the source wiring defect was 5.20%, and the generation rate of the stripe defect was 2.20%. In contrast, in the active matrix substrate 10 of the present embodiment, the occurrence rate of the source line defect is 0.60%, and the occurrence rate of the stripe defect is 1.50%. As described above, according to the active matrix substrate 10 of the present embodiment, it is possible to prevent a stripe defect caused by a disconnection defect or an alignment defect of a data line.

In addition, in the manufacturing method of the comparative example, IZO and phosphoric acid-nitric acid-acetic acid were used in forming the pixel electrode, whereas in the manufacturing method of the present embodiment, ITO and ferric chloride were used in forming the pixel electrode 22. ITO is cheaper than IZO, and ferric chloride is cheaper than phosphoric acid-nitric acid-acetic acid. Therefore, the active matrix substrate 10 of the present embodiment can be manufactured at low cost compared to the active matrix substrate of the comparative example.

In fig. 10, the upper conductor portion of the data line has the same line width as the lower conductor portion, but the upper conductor portion may have a line width narrower than the lower conductor portion as shown in fig. 14. When the upper conductor portion and the lower conductor portion are formed to have the same line width, if a pattern shift occurs, the upper conductor portion and the lower conductor portion are shifted in the width direction. Therefore, the distance between the data line 24 and the pixel electrode 22 varies, and the parasitic capacitance between the data line 24 and the pixel electrode 22 varies. When the upper layer conductor portion is formed to have a narrower line width than the lower layer conductor portion, the data line 24 has a convex cross section, and thus the distance between the data line 24 and the pixel electrode 22 is constant. Therefore, the variation in parasitic capacitance generated between the data line 24 and the pixel electrode 22 can be prevented. Further, since the cross section of the data line 24 is convex and tapered, the protective insulating film formed on the data line 24 is less likely to crack.

As described above, the active matrix substrate 10 of the present embodiment includes: a plurality of gate lines 23; a plurality of data lines 24; a plurality of pixel circuits 20, each including a switching element (TFT21) and a pixel electrode 22, disposed corresponding to an intersection of a gate line 23 and a data line 24; protective insulating films (SiNx films 151 and 152) formed on an upper layer than the gate lines 23, the data lines 24, the switching elements, and the pixel electrodes 22; and a common electrode 30 formed on an upper layer of the protective insulating film. The data line 24 includes a lower conductor portion 131 formed using ITO together with the pixel electrode 22, and an upper conductor portion 141 formed using a metal material other than ITO (MoNb/Al alloy/MoNb). The lower conductor portion 131 is formed in a shape cut at the position of the switching element, and the upper conductor portion 141 is formed in a continuous shape so as to overlap the lower conductor portion 131. The lower conductor portion 131 is formed in a cut shape at the position where the gate line 23 is disposed.

According to the active matrix substrate 10 of the present embodiment, the lower conductor portion 131 of the data line 24 can be prevented from being excessively etched by appropriately selecting the etching liquid for forming the pixel electrode 22 and the like and the etching liquid for forming the source layer pattern. The data line 24 has a redundant structure including a lower conductor portion 131 and an upper conductor portion 141. Therefore, disconnection failure of the data line 24 can be prevented. Further, since the lower conductor portion 131 is not formed at the position of the switching element, the difference in height between the position where the switching element is formed and the peripheral portion can be reduced, and alignment failure and streaking can be prevented when performing rubbing treatment.

The upper conductor portion 141 is formed using MoNb and an Al alloy. The upper layer conductor portion 141 is formed to have a 3-layer structure including MoNb, Al alloy, and MoNb. Therefore, the above-described effects can be obtained by using ferric chloride or oxalic acid as an etching solution for forming the pixel electrode 22 and the like, and using phosphoric acid-nitric acid-acetic acid as an etching solution for forming the source layer pattern. Further, by forming the upper layer conductor portion 141 to have a narrower line width than the lower layer conductor portion 131, it is possible to prevent a variation in parasitic capacitance generated between the data line 24 and the pixel electrode 22. The common electrode 30 has a plurality of slits 31 corresponding to the pixel electrodes 22. Therefore, a lateral electric field can be applied to the liquid crystal layer using the common electrode 30 and the pixel electrode 22.

The method for manufacturing the active matrix substrate 10 of the present embodiment includes: a step of forming a plurality of gate lines 23 and a plurality of gate electrodes 111 of switching elements on the 1 st wiring layer (step 1); a step of forming a gate insulating film (SiNx film 121) and a semiconductor film (amorphous Si film 122 and n + amorphous Si film 123) (2 nd step); a pixel electrode layer forming step (step 3) of forming the pixel electrode 22 and the lower conductor portion 131 of the plurality of data lines 24 in the pixel electrode layer using ITO; a source layer forming step (a 4 th step) of forming the upper conductor portion 141 of the data line 24 and the conduction electrodes (the source electrode 142 and the drain electrode 143) of the switching element using a metal material other than ITO in the 2 nd wiring layer, and patterning the semiconductor film; a step of forming a protective insulating film on the upper layer of the pixel electrode 22 (step 5); and a step of forming a common electrode 30 on the upper layer of the protective insulating film (step 6). In the pixel electrode layer forming step, the lower conductor portion 131 is formed in a shape cut at the position of the switching element, and in the source layer forming step, the upper conductor portion 141 is formed in a continuous shape so as to overlap the lower conductor portion 131. In the pixel electrode layer forming step, the lower conductor portion 131 is formed in a shape cut at the position where the gate line 23 is arranged. In the source layer forming step, the upper conductor portion 141 and the via electrode are formed using MoNb and an Al alloy. In the source layer forming step, the upper conductor portion 141 and the conductive electrode are formed to have a 3-layer structure including MoNb, an Al alloy, and MoNb. In the source layer forming step, the upper conductor portion 141 may be formed to have a narrower line width than the lower conductor portion 131. In the step of forming the common electrode 30, the common electrode 30 is formed to have a plurality of slits 31 corresponding to the pixel electrodes 22. Thus, the active matrix substrate 10 having the above-described effects can be manufactured.

In the pixel electrode layer formation step, etching is performed using ferric chloride or oxalic acid, and in the source layer formation step, etching is performed using an etching solution that does not etch indium tin oxide. Therefore, in the source layer formation step, an appropriate etching solution can be selected without etching indium tin oxide. In the source layer formation step, etching is preferably performed using phosphoric acid-nitric acid-acetic acid. Accordingly, the active matrix substrate 10 having the above-described effects can be manufactured at low cost.

Although the active matrix substrate of the liquid crystal panel of the lateral electric field system has been described above, the active matrix substrate of the liquid crystal panel of the vertical electric field system and the active matrix substrate of the organic EL (Electro Luminescence) display device can be configured in the same manner. In addition, an active matrix substrate including a TFT using an oxide semiconductor such as IGZO (indium gallium zinc oxide) can be configured in the same manner.

While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is to be understood that numerous other modifications and variations can be devised without departing from the scope of the invention.