Access method, device and system of shared storage space and storage medium

文档序号：1737213 发布日期：2019-12-20 浏览：6次中文

阅读说明：本技术 共享存储空间的访问方法、装置以及系统和存储介质 (Access method, device and system of shared storage space and storage medium ) 是由不公告发明人于 2019-11-11 设计创作，主要内容包括：本公开涉及一种共享存储空间的访问方法、装置以及系统和存储介质。所述产品包括控制模块,所述控制模块包括：指令缓存单元、指令处理单元和存储队列单元；所述指令缓存单元,用于存储所述人工神经网络运算关联的计算指令；所述指令处理单元,用于对所述计算指令解析得到多个运算指令；所述存储队列单元,用于存储指令队列,该指令队列包括：按该队列的前后顺序待执行的多个运算指令或计算指令。通过以上方法或产品,本公开可以提高存储空间访问效率。(The disclosure relates to a method, a device and a system for accessing a shared storage space and a storage medium. The product includes a control module, the control module including: the device comprises an instruction cache unit, an instruction processing unit and a storage queue unit; the instruction cache unit is used for storing the calculation instruction associated with the artificial neural network operation; the instruction processing unit is used for analyzing the calculation instruction to obtain a plurality of operation instructions; the storage queue unit is configured to store an instruction queue, where the instruction queue includes: and a plurality of operation instructions or calculation instructions to be executed according to the front and back sequence of the queue. By the above method or product, the present disclosure may improve storage access efficiency.)

1. An access method for a shared memory space, the method being applied to a first unit, the first unit being capable of accessing the shared memory space, the first unit being a processor or a core in the processor, the method comprising:

sending a write request to a shared memory, wherein the write request carries an operator and a destination address, so that the shared memory acquires an operand according to the destination address, performs operation on the operand by adopting the operator to obtain an operation result, and writes the operation result into the destination address.

2. The method of claim 1, wherein the write request further carries a read request identifier, wherein the read request identifier is used to indicate that the first unit needs to obtain the operand, and wherein the write request is further used to cause the shared memory to store the operand in a buffer after obtaining the operand.

3. The method of claim 2, further comprising:

receiving a response signal returned by the shared memory in response to the write request, wherein the response signal carries the storage information of the operand in the buffer;

and sending a read request to a shared memory according to the storage information so as to access the cache to obtain the operand.

4. An access method of a shared memory space, which is applied to a shared memory, the method comprising:

receiving a write request, wherein the write request carries an operational character and a destination address;

and obtaining an operand according to the destination address, operating the operand by adopting the operator to obtain an operation result, and writing the operation result into the destination address.

5. The method of claim 4, further comprising:

if the write request also carries a read request identifier, storing the operand in a buffer after the operand is obtained; the read request identifier is used for indicating that an opposite end sending the write request needs to acquire the operand;

and returning a response signal in response to the write request, wherein the response signal carries the storage information of the operand in the buffer.

6. The method of claim 5, further comprising:

receiving a read request, wherein the read request carries storage information of the operand in the buffer;

and acquiring the operand according to the storage information and returning the operand.

7. A system, characterized in that the system comprises: a first unit and a shared memory, and,

the first unit can access a shared storage space, the first unit is a processor or a core in the processor, and the first unit is used for sending a write request to the shared storage, wherein the write request carries an operator and a destination address;

and the shared memory receives the write request, acquires an operand according to the destination address, adopts the operator to operate the operand to obtain an operation result, and writes the operation result into the destination address.

8. The system according to claim 7, wherein the shared memory comprises a control unit, a shared memory space, and an arithmetic unit, the control unit being connected to the shared memory space and the arithmetic unit, respectively.

9. The system of claim 8, wherein the control unit is configured to retrieve the operand from the shared memory space according to the destination address after receiving the write request;

the control unit is used for sending an operation instruction to the operation unit according to the operator and the operand;

the operation unit is used for operating the operand by adopting the operational character according to the operation instruction to obtain an operation result and sending the operation result to the control unit;

the control unit is used for writing the operation result into the destination address.

10. The system according to claim 8, wherein the write request further carries a read request identifier, the read request identifier is used to indicate that the first unit needs to obtain the operand, the shared memory further comprises a buffer, the buffer is connected to the control unit,

the control unit is used for storing the operand in the buffer according to the reading request identification after the operand is obtained;

and the control unit is used for sending a response signal to the first unit after the operation result is written into the destination address, wherein the response signal carries the storage information of the operand in the buffer.

11. The system of claim 10,

the first unit is used for sending a read request to a shared memory according to the storage information after receiving the response signal;

and the control unit is used for responding to the read request to acquire the operand according to the storage information after receiving the read request, and returning the operand to the first unit.

12. An access device for a shared memory space, the device being applied to a first unit, the first unit being capable of accessing the shared memory space, the first unit being a processor or a core in the processor, the device comprising:

the first sending module is used for sending a write request to the shared memory, wherein the write request carries an operator and a destination address, so that the shared memory obtains an operand according to the destination address, performs operation on the operand by using the operator to obtain an operation result, and writes the operation result into the destination address.

13. The apparatus of claim 12, wherein the write request further carries a read request identifier, wherein the read request identifier is used to indicate that the first unit needs to obtain the operand, and wherein the write request is further used to cause the shared memory to store the operand in a buffer after obtaining the operand.

14. The apparatus of claim 13, further comprising:

a first receiving module, configured to receive a response signal returned by the shared memory in response to the write request, where the response signal carries storage information of the operand in the buffer;

and the second sending module is used for sending a read request to a shared memory according to the storage information so as to access the buffer to obtain the operand.

15. An access device for a shared memory space, the access device being applied to a shared memory, the device comprising:

a second receiving module, configured to receive a write request, where the write request carries an operator and a destination address;

and the operation module is used for acquiring an operand according to the destination address, adopting the operator to operate the operand to obtain an operation result, and writing the operation result into the destination address.

16. The apparatus of claim 15, further comprising:

the storage module is used for storing the operand in a buffer after the operand is obtained if the write request also carries a read request identifier; the read request identifier is used for indicating that an opposite end sending the write request needs to acquire the operand;

and the response module is used for responding to the write request and returning a response signal, wherein the response signal carries the storage information of the operand in the buffer.

17. The apparatus of claim 16, further comprising:

a third receiving module, configured to receive a read request, where the read request carries storage information of the operand in the cache;

and the return module is used for acquiring the operand according to the storage information and returning the operand.

18. An apparatus for shared memory access, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to carry out the method of any one of claims 1 to 3 when executing the instructions;

alternatively, the processor is configured to carry out the method of any one of claims 4 to 6 when executing the instructions.

19. A non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the method of any one of claims 1 to 3;

alternatively, the computer program instructions, when executed by a processor, implement the method of any of claims 4 to 6.

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a method, an apparatus, and a system for accessing a shared storage space, and a storage medium.

Background

In a multi-core processor system, a plurality of cores generally need to cooperate to complete the same task, so that the problem that how to ensure the consistency of data and improve the parallel operation efficiency of the multi-core processor is an important problem in the multi-core processor system often occurs when a plurality of cores perform read-write operation on a shared storage space of the same address.

Disclosure of Invention

In view of the foregoing, it is desirable to provide an access method, an access device, an access system, and a storage medium for a shared storage space.

According to an aspect of the present disclosure, there is provided an access method for a shared memory space, which is applied to a first unit, the first unit being capable of accessing the shared memory space, the first unit being a processor or a core in the processor, the method including:

According to another aspect of the present disclosure, there is provided an access method of a shared memory space, applied to a shared memory, the method including:

receiving a write request, wherein the write request carries an operational character and a destination address;

According to another aspect of the present disclosure, there is provided a system comprising: a first unit and a shared memory, and,

According to another aspect of the present disclosure, there is provided an access apparatus for a shared memory space, applied to a first unit, the first unit being capable of accessing the shared memory space, the first unit being a processor or a core in the processor, the apparatus including:

According to another aspect of the present disclosure, there is provided an access apparatus for a shared memory space, applied to a shared memory, the apparatus including:

a second receiving module, configured to receive a write request, where the write request carries an operator and a destination address;

According to another aspect of the present disclosure, there is provided an apparatus for access of a shared memory space, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the above method when executing the instructions.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.

By arranging the operation unit in the shared memory to realize the operation process on the shared memory, the read operand does not need to be returned to the first unit (the processor or the core of the processor) in time, and the shared memory can directly execute the operation on the operand to obtain an operation result and then write the operation result into the shared memory. According to the system disclosed by the invention, the interactive process can be reduced, and most of time of two links of acquiring data and writing data is saved, so that the execution delay of the process of reading, modifying and writing is reduced. Especially for the last level shared memory space in the hierarchical shared memory, the access path from the first unit to the last level shared memory space may be long, and the effect of reducing the execution delay using the system of the present disclosure will be more obvious.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a diagram illustrating a process of obtaining control of an access lock in the related art;

FIG. 2 is a diagram illustrating a process of performing read/write operations on a shared memory space in the related art;

FIG. 3 shows a block diagram of a system according to an embodiment of the present disclosure;

FIG. 4 shows a block diagram of a system according to an embodiment of the present disclosure;

FIG. 5 illustrates an interaction diagram of an access method of a shared memory space according to an embodiment of the present disclosure;

FIG. 6 shows a schematic diagram of a write operation process according to an embodiment of the present disclosure;

FIG. 7 shows a schematic diagram of a read operation process according to an embodiment of the present disclosure;

FIG. 8 shows a block diagram of an access device sharing a memory space according to an embodiment of the present disclosure;

FIG. 9 shows a block diagram of an access device sharing a memory space according to an embodiment of the present disclosure;

FIG. 10 shows a block diagram of an access device sharing a memory space according to an embodiment of the present disclosure;

FIG. 11 is a block diagram illustrating an apparatus for access of a shared memory space in accordance with an exemplary embodiment;

FIG. 12 is a block diagram illustrating an apparatus for access of a shared memory space in accordance with an example embodiment.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

When multiple processors or multiple cores in one processor need to perform read-write operations on a Shared Memory space, the conventional implementation method is based on an access lock, that is, the system configures one access lock for each Shared Memory space (Shared Memory). When a Master such as a CPU, an IPU, a GPU, or an external device is going to access a shared memory space in a conventional implementation manner, a control right of a corresponding access lock needs to be acquired first, and after the control right is acquired successfully, a set of operations (simply referred to as "Read-Write-after-Read operation") of "Read-Modify-Write" can be performed on the content in the shared memory space. The aim is to maintain the consistency of data in the shared storage space and ensure the conflict-free access of a plurality of masters to the shared storage.

Fig. 1 is a schematic diagram showing a process of acquiring control right to access a lock in the related art. Fig. 2 is a schematic diagram illustrating a process of performing a read/write operation on a shared storage space in the related art. The specific process of the write-after-read operation implemented based on the access lock can be referred to fig. 1 and 2. As shown in fig. 1, the first step of Master0 issuing a write-after-read operation is described: control of the access lock is obtained. The Cache (Cache memory) may be a Cache of each level, and each Master may Access a shared memory space in the Cache, or may Access an Access Locks library to obtain a lock. Access Locks are a block of memory in which Access Locks are stored, each lock having a segment of shared memory banks (Cache lines) corresponding to it. The process of acquiring the lock can be represented by curves shown in the steps of (i) and (ii) in fig. 1, the Master0 accesses the Access Locks first, finds the Access lock corresponding to the target shared memory strip, modifies the state of the Access lock into an occupied mark, and returns to the state of the Access lock before modification, and if the state of the Access lock before modification shows that the Access lock is not occupied, the Master0 acquires the lock successfully; if the status of the access lock before modification indicates that it is already occupied, Master0 fails to acquire the lock and Master0 attempts to acquire the access lock again.

When the Master0 successfully acquires the lock, the target shared memory bank can be accessed, and the Master0 accesses the shared memory bank by four steps: firstly, acquiring target data (firstly, secondly, two steps in FIG. 2); modifying the data; writing the modified data into the same address in the shared storage space, and modifying the state of the Access lock corresponding to the modified data in the Access Locks into an unoccupied state (step three in fig. 2); cache reply write response (step (r) in FIG. 2).

In the write-after-read operation of the shared storage space, there are many ways of modifying data in "read + modify + write", and the principle is to take the acquired data as an operand to participate in a certain operation, and take the obtained calculation result as new data. In the conventional method, the process of modifying data is completed in the Master, so the Master is generally provided with an arithmetic unit, and the arithmetic unit completes the process of modifying data. For example, the INC (increment plus) operation:

wherein, a is the acquired data as one operand of INC, B is the other operand, D is the operation result, and the Master finally writes D into the storage address of data a again.

The method for implementing the read-write operation based on the access lock has two obvious disadvantages:

the Master has more operation flows;

secondly, when the data flow path between the Master and the Cache is long (the time delay of the Master accessing the Cache is long), if a plurality of masters initiate write-after-read operation to the same shared memory strip, only serial access is available, and the access efficiency is low.

In order to solve the above technical problem, the present disclosure provides a system, which may include: a first unit and a shared memory.

Wherein a first unit can access the shared memory space, which can be a unit that can actively initiate a request (e.g., a write request or a read request) to the shared memory. For example, the first unit may send a write request to the shared memory, where the write request may carry an operator and a destination address.

And the shared memory receives the write request, acquires an operand according to the destination address, adopts the operator to operate the operand to obtain an operation result, and writes the operation result into the destination address.

The first unit and the shared memory may be located on the same chip, and the shared memory may also be an off-chip memory, which is not limited by the present disclosure.

FIG. 3 shows a block diagram of a system according to an embodiment of the present disclosure. In a possible implementation manner, the first unit may be a Master, and the Master may be a processor, or a core in the processor, or an external device, that is, the first unit may be the processor, or the core in the processor. The processor may be a general-purpose processor, such as a Central Processing Unit (CPU), an artificial intelligence Unit (IPU) for performing artificial intelligence operations, or a microprocessor, an embedded processor, an arm (advanced RISC machine) processor, a GPU (Graphics Processing Unit), a video processor, a video encoding and decoding processor, a DSP (digital signal processor), an NPU (neural-network Processing Unit), an Application Specific Integrated Circuit (ASIC) chip, a Field Programmable Gate Array (FPGA) chip, or the like. The artificial intelligence operations may include machine learning operations, brain-like operations, and the like. The machine learning operation comprises neural network operation, k-means operation, support vector machine operation and the like. The artificial intelligence processor can also comprise one or a combination of more of a GPU, an NPU, a DSP, an ASIC chip and an FPGA chip. The present disclosure is not limited to a particular type of processor. The external device may be a device provided with a processor.

The shared memory may be configured by any type or structure of memory, for example, a shared memory may be configured by a memory configured by a magnetic core memory, a semiconductor memory, a magnetic disk, or the like, a random access memory or a sequential memory may be used, a random access memory may be used, a permanent memory or a non-permanent memory may be used, a main memory, an auxiliary memory, a Cache memory (Cache), a control memory, or the like may be used, and the present disclosure does not specifically limit the shared memory.

As shown in fig. 3, one or more first units may be included in the system, and each of the one or more first units may send a write request (or a read request) to the shared memory. When the plurality of first units send requests (for example, write requests or read requests) to the shared memory, the shared memory may sequentially execute according to the order in which the requests are received, that is, for the plurality of masters, the requests may be simultaneously initiated to the address field of the same shared memory, but the requests are executed in series in the shared memory, so that the access efficiency is improved.

The operator in the write request may be an operation indicating what property should be performed for the request, and the destination address in the write request may point to a segment of shared memory space in the shared memory, in which an operand corresponding to the operator is stored. Therefore, after the shared memory receives the write request, the corresponding segment of the shared memory space can be searched according to the destination address, the operand is obtained from the segment of the shared memory space, then the operand is operated by adopting the operator to obtain the operation result, and the operation result is written into the destination address, so that the write operation can be completed.

FIG. 4 shows a block diagram of a system according to an embodiment of the present disclosure. As shown in fig. 4, in a possible implementation manner, the shared memory includes a shared storage space for storing shared data, and an Arithmetic Unit, where the Arithmetic Unit may be configured to perform operations corresponding to operators, and the Arithmetic Unit may be an Arithmetic and Logic Unit (ALU), or another type of module that can modify data, which is not limited in this disclosure. The shared memory may further include a control unit, and the control unit may be connected to the shared memory space and the arithmetic unit, respectively.

The control unit can be realized by a special hardware circuit, or by general processing hardware (such as a CPU, a single chip, a field programmable logic device FPGA, etc.) in combination with executable logic instructions to execute the working process of the control unit. The present disclosure does not limit the specific implementation of the control unit.

In a possible implementation manner, the control unit is configured to, after receiving the write request, obtain the operand from the shared storage space according to the destination address; the control unit is used for sending an operation instruction to the operation unit according to the operator and the operand; the operation unit is used for operating the operand according to the operation instruction to obtain an operation result and sending the operation result to the control unit; the control unit is used for writing the operation result into the destination address.

For example, the control unit may receive a write request sent by the first unit, parse the write request, obtain an operator and a destination address, then search a corresponding segment of shared storage space in the shared storage space according to the destination address, and read an operand from the segment of shared storage space. After the operands are obtained, operation instructions can be generated according to the operators and the operands and sent to the operation unit. After receiving the operation instruction, the operation unit can execute the operation instruction to realize the operation of the operand to obtain an operation result, then the operation result is returned to the control unit, and the control unit writes the operation result into the destination address, thereby completing the write operation.

In a possible implementation manner, after the shared memory performs the write operation, a response signal may also be returned to the first unit to indicate that the operation corresponding to the write request is completed, as shown by the signal flow indicated by the arrow pointing to the left in fig. 4.

The operation process is realized on the shared memory by arranging the operation unit in the shared memory, the read operand does not need to be returned to the first unit in time, the shared memory can directly execute the operation on the operand to obtain an operation result, and then the operation result is written in. According to the system disclosed by the invention, the interactive process can be reduced, and most of time of two links of acquiring data and writing data is saved, so that the execution delay of the process of reading, modifying and writing is reduced. Especially for the last level shared memory space in the hierarchical shared memory, the access path from the first unit to the last level shared memory space may be long, and the effect of reducing the execution delay using the system of the present disclosure will be more obvious.

In a possible implementation manner, the write request may further carry a read request identifier, where the read request identifier is used to indicate that the first unit needs to obtain the operand, that is, indicate that the first unit needs to obtain the operand after receiving a write request response.

In one possible implementation, as shown in fig. 4, the shared memory further includes a buffer. The Buffer may be an Origin Data Buffer (ODB for short) for storing the operand, the Buffer may be connected to the control unit, and the control unit is configured to store the operand in the Buffer according to the read request identifier after acquiring the operand; and the control unit is used for sending a response signal to the first unit after the operation result is written into the destination address, wherein the response signal carries the storage information of the operand in the buffer.

In a possible implementation manner, a read request identification bit may be set in the write request, and a specific identification of the read request identification bit may be used to indicate whether the first unit needs to obtain the operand, and therefore, the read request identification bit may include: read request identification, no need read request identification. In one example, the read request flag may be set to different values to represent different flags, for example, the read request flag may be set to 0 or 1, where 1 represents the read request flag, and 0 represents that the read request flag is not needed. It should be noted that the above example is only one possible implementation manner of the present disclosure, and does not limit the scope of the present disclosure in any way, and those skilled in the art can understand that the above process can also be implemented in other manners.

According to the above embodiment, after receiving the write request, the control unit may further determine whether an operand needs to be returned to the first unit according to information of the read request identification bit carried in the write request. If the write request carries the read request identifier, the control unit may determine that the operand needs to be returned to the first unit, and in this case, the control unit may store the operand in the buffer after obtaining the operand. Then, the control unit may send an operation instruction to the arithmetic unit according to the operator and the operand; the operation unit is used for operating the operand according to the operation instruction to obtain an operation result and sending the operation result to the control unit; the control unit is used for writing the operation result into the destination address. After the control unit writes the operation result into the destination address, a response signal may be sent to the first unit, where the response signal may carry storage information of the operand in the buffer, such as a storage address.

In a possible implementation manner, the first unit is configured to send a read request to a shared memory according to the storage information after receiving the response signal; and the control unit is used for responding to the read request to acquire the operand according to the storage information after receiving the read request, and returning the operand to the first unit.

After receiving the response signal, the first unit may analyze the response signal to obtain the storage information, and then generate a read request according to the storage information, where the read request carries the storage information. The first unit sends a read request to the shared memory, after receiving the read request, the control unit of the shared memory analyzes the read request to obtain storage information, searches the buffer according to the storage information to obtain an operand, and returns the operand to the first unit.

If the write request carries the identification of the read-free request, the control unit may determine that the operand is not required to be returned to the first unit. In this case, the control unit may not need to store the operand in the buffer after the operand is acquired.

By the method, the system can be compatible with the common applications in the industry, and in some applications, the first unit needs to acquire the operand before modification for other purposes. Therefore, according to the system of the above embodiment, by carrying the read request identifier when initiating the write request, it is possible to return the operand before modification to the first unit, so as to solve the above problem.

For the above first unit, the first unit can access the shared memory space, and the first unit may be a unit capable of actively initiating a request, for example, a write request or a read request may be initiated to the shared memory: the present disclosure also provides an access method of a shared storage space, which may include:

step S11, sending a write request to the shared memory, where the write request carries an operator and a destination address, so that the shared memory obtains an operand according to the destination address, performs an operation on the operand by using the operator to obtain an operation result, and writes the operation result into the destination address.

For shared memory above: the present disclosure also provides another access method of a shared storage space, which may include:

step S20, receiving a write request, wherein the write request carries an operator and a destination address;

step S21, obtaining an operand according to the destination address, performing an operation on the operand by using the operator to obtain an operation result, and writing the operation result into the destination address.

In step S22, the shared memory returns a response signal to the first unit after completing the operation of the write request.

Fig. 5 is an interaction diagram illustrating an access method of a shared storage space according to an embodiment of the present disclosure, as shown in fig. 5, in step S11, the first unit sends a write request to the shared storage, where the write request carries an operator and a destination address; in step S20, the shared memory receives a write request; then step S21 is executed by the shared memory to obtain an operand according to the destination address, perform an operation on the operand by using the operator to obtain an operation result, and write the operation result into the destination address; in step S22, the shared memory returns a response signal to the first unit after completing the operation of the write request.

Compare the process of step S11 to step S22 in fig. 5 with the process of fig. 1+ fig. 2: in fig. 5, only two interactions of step S11 and step S22 are required to complete the write operation, whereas in the process of fig. 1+ fig. 2, 6 interactions are required. According to the comparison process, the access method of the shared storage space can greatly reduce the interactive process and reduce the execution delay of the process of 'reading, modifying and writing'.

In a possible implementation manner, the write request may further carry a read request identifier, where the read request identifier may be used to indicate that the operand needs to be obtained, and the write request may be further used to enable the shared memory to store the operand in a buffer after the operand is obtained.

In this embodiment, for the above shared memory, the method for accessing a shared memory space of the present disclosure may further include:

step S23, if the write request also carries a read request identifier, storing the operand in a buffer after obtaining the operand; wherein the read request identifier is used to indicate that the first unit needs to obtain the operand;

step S24, returning a response signal in response to the write request, where the response signal carries information stored in the buffer by the operand.

In this embodiment, for the above end where the first unit is located, the method for sharing the storage space may further include:

step S12, receiving a response signal returned by the shared memory in response to the write request, where the response signal carries information of the operand stored in the buffer;

step S13, sending a read request to the shared memory according to the storage information, so as to access the buffer to obtain the operand.

As shown in fig. 5, in step S23, after receiving the write request, the shared memory may further determine whether an operand needs to be returned to the first unit according to information of a read request identification bit carried in the write request, and if the write request also carries a read request identification, the shared memory stores the operand in the buffer after obtaining the operand; step S24, returning a response signal in response to the write request in step S11, where the response signal carries the storage information of the operand in the buffer. In step S12, the first unit receives a response signal returned by the shared memory in response to the write request, and may parse the response signal to obtain the storage information; in step S13, the first unit sends a read request to the shared memory according to the storage information. For the shared memory above, following the above procedure, the method may further comprise:

step S25, receiving a read request, where the read request carries storage information of the operand in the buffer;

and step S26, acquiring the operand according to the storage information, and returning the operand.

As shown in fig. 5, after step S13, in step S25, the shared memory receives a read request sent by the first unit, where the read request carries storage information of the operand in the buffer; in step S26, the shared memory obtains the operand according to the storage information, and returns the operand to the first unit.

It should be noted that, for the explanation of any feature in the method described above in fig. 5, the contents of the system part above can be referred to.

Application example

The method and system of the present disclosure are described below with one specific operation as an example of an application scenario. Fig. 6 shows a schematic diagram of a write operation process according to an embodiment of the present disclosure, and fig. 7 shows a schematic diagram of a read operation process according to an embodiment of the present disclosure.

The purpose of the present disclosure is to improve the efficiency of the system executing the write after read by adjusting the system structure and the operation flow on the premise of ensuring the data consistency. The basic idea of the method for realizing the write-after-read operation is to reduce the access interaction between the Master and the Cache. For example: master0 will "modify" DEC (create) the shared data A, and the expression is:

the method for realizing the write-after-read operation comprises the steps that a Master0 firstly initiates a write request to a Cache, the write request comprises an operand B, the address of the operand A and the operator are transmitted to the Cache in a write request mode, the Cache obtains the operand A from a shared storage space according to the address of the operand A, then performs arithmetic logic operation inside the Cache to obtain D, and finally the Cache stores the D into the address of the operand A. This process may refer to fig. 6, where curves (r) and (c) in fig. 6 represent command interaction between the Master and the Cache, a command stream from the Master to the Cache represents a write request, and a response signal is transmitted from the Cache to the Master to the command stream to indicate that the Cache has performed a write operation.

The method for implementing the read-write operation based on the access lock has a difference in system structure, namely the location arrangement of the ALU. In this disclosure, the ALU is moved from the Master to the Cache, which is done to reduce the execution latency of the flow "read + modify + write". Because the access path from the Master to the Cache may be long, especially if the Cache is the Last Level Cache (LLC) in the system. In the present disclosure, after the operand is read, the Cache may modify the operand directly according to the operator and then write. Therefore, the design of the present disclosure saves most of the time of the two links of acquiring data and writing data.

The present disclosure also supplements a read command for compatibility with software commonly used in the industry. In some applications, the Master (first element) needs to fetch the shared operands before modification for some use. However, in the present disclosure, the result of the write request cannot return the shared operand before modification to the Master, so to compensate for this use, a read operation is also provided in the present disclosure.

If the Master needs to not only initiate a write request, but also acquire a shared operand before modification, an identifier that needs a read request may be carried when the write request is initiated (most buses support carrying some extra information). When the Cache executes a write request, after the operand is acquired, the operand can be stored in the OriginData Buffer (ODB) in addition to the operation on the operand. After the Cache executes the AWC, when a response signal is returned to the Master, the storage information of the operand (Origin Data) before modification in the ODB may be carried on the bus together, and returned to the Master.

After receiving the response signal of the write request, the Master may initiate a read request to the Cache, and the command stream thereof may refer to fig. 7. After the Master0 sends out a read request, the ODB in the Cache is directly accessed to obtain Origin Data.

If the Master only needs to initiate a write request and does not need to acquire the shared operand before modification, the Master does not need to carry the identifier of the read request when initiating the write request. When the Cache processes the write request, the operand before modification is not stored in the ODB.

When a plurality of masters need to initiate write-after-read operation to the same Shared storage space, the first step is that the plurality of masters initiate write requests, the Cache executes the write requests in sequence according to the order of the received commands, and after the current write request is executed (after the ALU calculation result is written into the Shared Memory), the Cache can execute the next write request. In the method, the Cache is used for executing the write requests with the same target address in order-preserving mode so as to achieve the purpose of maintaining the data consistency. Therefore, it can be seen that in the present disclosure, for multiple masters, a read-write request can be issued to the same shared address segment at the same time, but the execution in the Cache is serial.

It should be noted that:

a) the Master is all equipment and processors capable of accessing the Cache;

b) the data flow bus supports all bus protocols capable of transmitting read data, write data and user-defined information;

c) the ALU module can also be other modules capable of modifying data;

d) the Cache can be all levels of caches or memories which can be accessed by a Master in the system.

Compared with the traditional implementation method, the implementation method of the write-after-read operation has high efficiency and flexibility.

High efficiency

In the disclosure, if the method is applied to a system with a long path delay between the Master and the Cache, the Master only needs to initiate a write request once under the condition that the Master does not need to acquire Origin Data, and the time delay for initiating the write request is approximately the same as the time delay for acquiring Data in the conventional method. Therefore, the efficiency of the method for realizing the write-after-read operation is far higher than that of the traditional method based on the access lock.

In addition, under the implementation mode of the write-after-read operation based on the access lock, when a plurality of masters initiate the write-after-read operation to the same segment of shared storage space in the same time period, only serial access can be performed. In the invention, when a plurality of masters initiate write-after-read operations to the same segment of shared memory at the same time period, the locks are not limited to be acquired, and the locks can be sent in parallel, but in order to maintain the data consistency of the locks, the Cache can internally and serially execute write requests. T1 is used to indicate the time when the current write-after-read operation will block the next write-after-read operation with the same target address when the conventional access lock based scheme is used; here, T2 indicates when the current write-after-read operation blocks other masters from issuing write-after-read operations with the same target address when the method of the present disclosure is employed. The meanings of T1 and T2 both include: read latency, ALU computation latency, and write latency. The read and write latencies of T2 are much less than the latency of T1 because both reads and writes of T2 occur inside the Cache, while reads and writes of T1 occur on the transmission path between the Master and the Cache. The present disclosure can effectively increase the efficiency of the write-after-read operation.

Flexibility

The method and the device can select whether Origin Data is returned or not, and when the Master initiates the read request, the current Master and other masters are not influenced to initiate other write requests or read requests.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

It should be further noted that, although the steps in the flowchart of fig. 5 are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 5 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

Fig. 8 shows a block diagram of an access device sharing a memory space according to an embodiment of the present disclosure. The apparatus is applied to a first unit, which can access a shared memory space, for example, the first unit can actively initiate a request (write request or read request) to the shared memory space, the first unit is a processor or a core in the processor, and for the description of the processor, see above.

As shown in fig. 8, the apparatus may include:

the first sending module 51 is configured to send a write request to the shared memory, where the write request carries an operator and a destination address, so that the shared memory obtains an operand according to the destination address, performs an operation on the operand by using the operator to obtain an operation result, and writes the operation result into the destination address.

According to the device disclosed by the invention, the interactive process can be reduced, and most of time of two links of acquiring data and writing data is saved, so that the execution delay of the process of reading, modifying and writing is reduced. Especially for the last level shared memory space in the hierarchical shared memory, the access path from the first unit to the last level shared memory space may be long, and the effect of reducing the execution delay by using the method of the present disclosure will be more obvious.

In a possible implementation manner, the write request further carries a read request identifier, where the read request identifier is used to indicate that the first unit needs to acquire the operand, and the write request is further used to enable the shared memory to store the operand in a buffer after the operand is acquired.

In one possible implementation, the apparatus further includes:

a first receiving module 52, configured to receive a response signal returned by the shared memory in response to the write request, where the response signal carries storage information of the operand in the buffer;

and a second sending module 53, configured to send a read request to the shared memory according to the storage information, so as to access the buffer to obtain the operand.

Fig. 9 shows a block diagram of an access device sharing a memory space according to an embodiment of the present disclosure. The device is applied to a shared memory, and comprises:

a second receiving module 61, configured to receive a write request, where the write request carries an operator and a destination address;

and the operation module 62 is configured to obtain an operand according to the destination address, perform an operation on the operand by using the operator to obtain an operation result, and write the operation result into the destination address.

Fig. 10 shows a block diagram of an access device sharing a memory space according to an embodiment of the present disclosure.

In one possible implementation, as shown in fig. 10, the apparatus further includes:

a storage module 63, configured to store the operand in a buffer after obtaining the operand if the write request further carries a read request identifier; the read request identifier is used for indicating that an opposite end sending the write request needs to acquire the operand;

a response module 64, configured to return a response signal in response to the write request, where the response signal carries information about the operand stored in the buffer.

In one possible implementation, the apparatus further includes:

a third receiving module 65, configured to receive a read request, where the read request carries storage information of the operand in the buffer;

and a returning module 66, configured to obtain the operand according to the storage information, and return the operand.

FIG. 11 is a block diagram illustrating an apparatus 800 for access of a shared memory space in accordance with an example embodiment. For example, the apparatus 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.

Referring to fig. 11, the apparatus 800 may include one or more of the following components: processing component 802, memory 804, power component 806, multimedia component 808, audio component 810, input/output (I/O) interface 812, sensor component 814, and communication component 816.

The processing component 802 generally controls overall operation of the device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing components 802 may include one or more processors 820 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

The memory 804 is configured to store various types of data to support operations at the apparatus 800. Examples of such data include instructions for any application or method operating on device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.

Power components 806 provide power to the various components of device 800. The power components 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the apparatus 800.

The multimedia component 808 includes a screen that provides an output interface between the device 800 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the device 800 is in an operating mode, such as a shooting mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the apparatus 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.

The sensor assembly 814 includes one or more sensors for providing various aspects of state assessment for the device 800. For example, the sensor assembly 814 may detect the open/closed status of the device 800, the relative positioning of components, such as a display and keypad of the device 800, the sensor assembly 814 may also detect a change in the position of the device 800 or a component of the device 800, the presence or absence of user contact with the device 800, the orientation or acceleration/deceleration of the device 800, and a change in the temperature of the device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 816 is configured to facilitate communications between the apparatus 800 and other devices in a wired or wireless manner. The device 800 may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the apparatus 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.

In an exemplary embodiment, a non-transitory computer-readable storage medium, such as the memory 804, is also provided that includes computer program instructions executable by the processor 820 of the device 800 to perform the above-described methods.

FIG. 12 is a block diagram illustrating an apparatus 1900 for access of a shared memory space, according to an example embodiment. For example, the apparatus 1900 may be provided as a server. Referring to fig. 12, the device 1900 includes a processing component 1922 further including one or more processors and memory resources, represented by memory 1932, for storing instructions, e.g., applications, executable by the processing component 1922. The application programs stored in memory 1932 may include one or more modules that each correspond to a set of instructions. Further, the processing component 1922 is configured to execute instructions to perform the above-described method.

The device 1900 may also include a power component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input/output (I/O) interface 1958. The device 1900 may operate based on an operating system stored in memory 1932, such as Windows Server, MacOS XTM, UnixTM, LinuxTM, FreeBSDTM, or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 1932, is also provided that includes computer program instructions executable by the processing component 1922 of the apparatus 1900 to perform the above-described methods.

It should be understood that the above-described apparatus embodiments are merely illustrative and that the apparatus of the present disclosure may be implemented in other ways. For example, the division of the units/modules in the above embodiments is only one logical function division, and there may be another division manner in actual implementation. For example, multiple units, modules, or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented.

In addition, unless otherwise specified, each functional unit/module in each embodiment of the present disclosure may be integrated into one unit/module, each unit/module may exist alone physically, or two or more units/modules may be integrated together. The integrated units/modules may be implemented in the form of hardware or software program modules.

If the integrated unit/module is implemented in hardware, the hardware may be digital circuits, analog circuits, etc. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and the like. The processor may be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, ASIC, etc., unless otherwise specified. Unless otherwise specified, the Memory unit may be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive Random Access Memory rram (resistive Random Access Memory), Dynamic Random Access Memory dram (Dynamic Random Access Memory), Static Random Access Memory SRAM (Static Random-Access Memory), enhanced Dynamic Random Access Memory edram (enhanced Dynamic Random Access Memory), High-Bandwidth Memory HBM (High-Bandwidth Memory), hybrid Memory cubic hmc (hybrid Memory cube), and so on.

The integrated units/modules, if implemented in the form of software program modules and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The present disclosure may be systems, methods, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The foregoing may be better understood in light of the following clauses:

clause a1. a method for accessing a shared memory space, applied to a first unit, the first unit having access to the shared memory space, the first unit being a processor or a core in a processor, the method comprising:

Clause a2. according to the method of clause a1, the write request further carries a read request identification, the read request identification indicating that the first unit needs to obtain the operand, the write request further causing the shared memory to store the operand in a buffer after obtaining the operand.

Clause A3 the method of clause a2, the method further comprising:

receiving a response signal returned by the shared memory in response to the write request, wherein the response signal carries the storage information of the operand in the buffer;

and sending a read request to a shared memory according to the storage information so as to access the cache to obtain the operand.

Clause a4. a method for accessing a shared memory space, applied to a shared memory, the method comprising:

receiving a write request, wherein the write request carries an operational character and a destination address;

Clause a5 the method of clause a4, the method further comprising:

and returning a response signal in response to the write request, wherein the response signal carries the storage information of the operand in the buffer.

Clause A6. the method of clause a5, further comprising:

receiving a read request, wherein the read request carries storage information of the operand in the buffer;

and acquiring the operand according to the storage information and returning the operand.

Clause a7. a system, comprising: a first unit and a shared memory, and,

Clause A8 the system of clause a7, the shared memory includes a control unit, a shared memory space, and an arithmetic unit, the control unit being connected to the shared memory space and the arithmetic unit, respectively.

Clause a9 the system of clause A8, the control unit being configured to, upon receiving the write request, retrieve the operand from the shared memory space according to the destination address;

the control unit is used for sending an operation instruction to the operation unit according to the operator and the operand;

the control unit is used for writing the operation result into the destination address.

Clause a10, according to the system of clause A8, the write request may further carry a read request identifier indicating that the first unit needs to obtain the operand, the shared memory further comprises a buffer, the buffer being connected to the control unit,

the control unit is used for storing the operand in the buffer according to the reading request identification after the operand is obtained;

Clause a11, the system of clause a10,

the first unit is used for sending a read request to a shared memory according to the storage information after receiving the response signal;

Clause a12, an access apparatus for a shared memory space, applied to a first unit, the first unit being capable of accessing the shared memory space, the first unit being a processor or a core in a processor, the apparatus comprising:

Clause a13 the apparatus of clause a12, wherein the write request further carries a read request identifier indicating that the first unit needs to obtain the operand, the write request further causing the shared memory to store the operand in a buffer after obtaining the operand.

Clause a14 the apparatus of clause a13, the apparatus further comprising:

and the second sending module is used for sending a read request to a shared memory according to the storage information so as to access the buffer to obtain the operand.

Clause a15. an access device for a shared memory space, applied to a shared memory, the device comprising:

a second receiving module, configured to receive a write request, where the write request carries an operator and a destination address;

Clause a16 the apparatus of clause a15, the apparatus further comprising:

and the response module is used for responding to the write request and returning a response signal, wherein the response signal carries the storage information of the operand in the buffer.

Clause a17 the apparatus of clause a16, the apparatus further comprising:

a third receiving module, configured to receive a read request, where the read request carries storage information of the operand in the cache;

and the return module is used for acquiring the operand according to the storage information and returning the operand.

Clause a18, an address assignment device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the method of any one of clauses a 1-A3 when executing the instructions;

alternatively, the processor is configured to carry out the method of any one of clauses a4 to clause a6 when the instructions are executed.

Clause a19 a non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method of any of clauses a 1-A3;

alternatively, the computer program instructions, when executed by a processor, implement the method of any of clauses a4 to clause a 6.

The embodiments of the present disclosure have been described in detail, and the principles and embodiments of the present disclosure are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present disclosure. Meanwhile, a person skilled in the art should, based on the idea of the present disclosure, change or modify the specific embodiments and application scope of the present disclosure. In view of the above, the description is not intended to limit the present disclosure.

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