阅读说明：本技术 一种基于饱和压降检测的并联igbt延时过流保护电路 (A kind of parallel IGBT delay current foldback circuit based on saturation voltage drop detection ) 是由 马红星 董诗阳 唐厚君 杨喜军 谢伟新 韩永馗 方万 孟祥群 田威 于 2019-08-22 设计创作，主要内容包括：本发明涉及一种基于饱和压降检测的并联IGBT延时过流保护电路,其特征在于：包括PWM脉冲主回路和饱和压降延时检测控制电路,所述PWM脉冲主回路将控制系统发来的控制脉冲转变为具有驱动能力的PWM驱动脉冲,驱动IGBT开通和关断；与门U1和U3对饱和压降延时检测控制电路生成的过流故障信号进行处理,当该过流故障信号为高电平时,PWM脉冲主回路逻辑不变；当该过流故障信号为低电平时,无论控制脉冲是高电平还是低电平,与门U1和U3输出均为低电平,则IGBT驱动脉冲均为低电平,实现IGBT的过流保护。本发明中对IGBT饱和压降进行延时检测,避免IGBT开通时饱和压降不稳定造成的误保护,提高了电路的合理性和可靠性。(The present invention relates to a kind of parallel IGBT delay current foldback circuits detected based on saturation voltage drop; it is characterized by comprising pwm pulse major loops and saturation voltage drop delay detection control circuit; the control pulse transition that the pwm pulse major loop sends control system is the PWM driving pulse with driving capability, and driving IGBT is turned on and off；It is handled with the door U1 and U3 over current fault signal generated to saturation voltage drop delay detection control circuit, when the over current fault signal is high level, pwm pulse major loop logic is constant；When the over current fault signal is low level, it is low level with door U1 and U3 output, then IGBT driving pulse is low level, realizes the overcurrent protection of IGBT that no matter controlling pulse, which is high level or low level,.Delay detection is carried out to IGBT saturation voltage drop in the present invention, is accidentally protected caused by saturation voltage drop is unstable when IGBT being avoided to open, improves the reasonability and reliability of circuit.)

The current foldback circuit 1. a kind of parallel IGBT based on saturation voltage drop detection is delayed, it is characterised in that: including pwm pulse master Circuit and saturation voltage drop delay detection control circuit, the control pulse transition that the pwm pulse major loop sends control system For the PWM driving pulse with driving capability, IGBT is driven to turn on and off；It is delayed with door U1 and U3 to saturation voltage drop and detects control The over current fault signal of circuit evolving processed is handled, when the over current fault signal is high level, pwm pulse major loop logic It is constant；When the over current fault signal is low level, no matter controlling pulse is high level or low level, is exported with door U1 and U3 It is low level, then IGBT driving pulse is low level, realizes the overcurrent protection of IGBT.

The current foldback circuit 2. a kind of parallel IGBT based on saturation voltage drop detection according to claim 1 is delayed, it is special Sign is: the input of the saturation voltage drop delay detection control circuit is the pressure drop of IGBT hourglass source electrode, control pulse, is exported as overcurrent Fault-signal, saturation voltage drop delay detection control circuit includes: to generate over-current signal for the pressure drop of IGBT hourglass source electrode as input Over-current signal generative circuit, two control pulse delay circuits, in conjunction with the control pulse and over current fault signal shape of above-mentioned delay At fault comprehensive processing circuit.

The current foldback circuit 3. a kind of parallel IGBT based on saturation voltage drop detection according to claim 2 is delayed, it is special Sign is: the over-current signal generative circuit is using the saturation voltage drop that IGBT drains between source electrode as input, by by resistance The anode of comparator U5 is linked into after the RC filter circuit that R1 and capacitor C1 is constituted, and overcurrent reference voltage Vref1 is linked into ratio Compared with the cathode of device U5, input of the over-current signal of comparator U5 output as fault comprehensive processing circuit.

The current foldback circuit 4. a kind of parallel IGBT based on saturation voltage drop detection according to claim 3 is delayed, it is special Sign is: being provided with fast recovery diode between the IGBT drain electrode and RC filter circuit, prevents forceful electric power electric current adverse current control system It unites, is provided with offset compensation resistance between output end and the comparator anode of RC filter circuit, realizes the positive negative input pole of comparator Impedance matching.

The current foldback circuit 5. a kind of parallel IGBT based on saturation voltage drop detection according to claim 2 is delayed, it is special Sign is: two control pulse delay circuits be respectively used to control pulse 1 and 2 postpone, include first with NOT gate, RC charge-discharge circuit, comparator, the second NAND gate, the first reversed Schmidt trigger and the second reversed schmidt trigger Output voltage of the over current fault signal of device, control pulse and fault comprehensive processing circuit feedback after the first NAND gate is divided to two Road, is linked into the input terminal of the second NAND gate after reversed Schmidt trigger Reverse recovery all the way, and another way is filled by RC It is linked into the anode of comparator after discharge circuit, is compared, passes through with the delay reference voltage Vref2 of access comparator cathode RC parameter can realize the adjustment to the control pulse delay time, and the output end of comparator is linked into the input terminal of the second NAND gate, The output end of second NAND gate is linked into the input terminal of the second reversed Schmidt trigger, the second reversed Schmidt trigger it is defeated Voltage accesses fault comprehensive processing circuit out.

The current foldback circuit 6. a kind of parallel IGBT based on saturation voltage drop detection according to claim 5 is delayed, it is special Sign is: the RC charge-discharge circuit includes mosfet transistor, charge and discharge resistance and charge and discharge capacitance, the MOSFET crystal The grid of pipe is connected with the output end of the first NAND gate, and source electrode ground connection, drain electrode is connected to power supply by charge and discharge resistance, described to fill Discharge capacity both ends are connect with the source electrode and drain electrode of mosfet transistor respectively, and the output of RC charge-discharge circuit passes through current-limiting resistance The anode of comparator is accessed afterwards.

The current foldback circuit 7. a kind of parallel IGBT based on saturation voltage drop detection according to claim 2 is delayed, it is special Sign is: the fault comprehensive processing circuit includes NAND gate, and input is over-current signal generative circuit and control pulse delay The output signal of circuit, when overcurrent signal generating circuit output be high level, and control pulse delay circuit output be low electricity Usually, over current fault signal is high level, then circuit fault-free；Conversely, over-current signal production circuit output be high level and Controlling pulse daley output is high level, and over current fault signal is low level, then circuit is faulty.

The current foldback circuit 8. a kind of parallel IGBT based on saturation voltage drop detection according to claim 5 is delayed, device are special Sign is: the NAND gate output in the fault comprehensive processing circuit is connected with a delay circuit, which believes over current fault It number is delayed, handles over current fault to provide the sufficient time by governor circuit, delay time is ms grades.

Technical field

The present invention relates to a kind of IGBT delay current foldback circuit more particularly to a kind of parallel connections based on saturation voltage drop detection IGBT delay current foldback circuit.Belong to power electronics field.

Background technique

It is a typical IGBT parallel connection application circuit: 2 IGBT module (IGBT1 that conventional overcurrent protects circuit as shown in Figure 1 And IGBT2) drain electrode and source electrode be respectively connected together；Grid connects pwm pulse driving circuit, and R1 and R3 are gate-drive electricity Resistance, plays current limliting；D1 and D2 is voltage-stabiliser tube, prevents driving pulse electric voltage over press；R2 and R4 is gate pole to ground resistance, is prevented High-frequency Interference false triggering.

Traditional IGBT overcurrent protection principles and methods:

Such as Fig. 1, when PWM driving pulse is high level, IGBT conducting, electric current flows through IGBT, IGBT drain electrode at this time and source Voltage between pole is lower, about 0~5V or so.Our voltages are referred to as saturation voltage drop, the size of saturation voltage drop with flow through The electric current of IGBT is proportional, i.e., electric current is bigger, and IGBT saturation voltage drop is bigger.Therefore, it using this rule, can design hard Part circuit detects the saturation voltage drop of IGBT, (the corresponding saturation pressure of overcurrent protection threshold value when saturation voltage drop is greater than a certain setting value Depreciation), PWM driving pulse is turned off, IGBT is turned off, to prevent high current from burning out module.It is full by detection that here it is typical The principle of overcurrent protection is realized with pressure drop.

However, in practical applications, when PWM driving pulse becomes high level from low level, IGBT conducting, electric current stream It is logical, but saturation voltage drop can't be reduced to ideal numerical value at once, generally require just settle out by of short duration concussion.Its Typical waveform is as shown in Figure 2.It is the manufacturer of the length of time with module of t1~t2 in figure, model, related using factors such as times System, value is about 3~5us or so.

The shortcomings that traditional IGBT current foldback circuit:

1, traditional scheme at once detects saturation voltage drop when PWM driving pulse becomes high level from low level, and Overcurrent protection is carried out according to detected value.But it due to IGBT saturation voltage drop in t1~t2 time and unstable, is easy to happen The case where accidentally protecting.

2, traditional parallel IGBT current foldback circuit is mostly that two independent protection circuits are combined into one, and circuit structure is superfluous Remaining, component number is more, is not easy to analyze and safeguard.

Summary of the invention

The technical problem to be solved by the present invention is to simple, the components that provides a kind of circuit structure for the above-mentioned prior art Quantity is few, convenient for the parallel IGBT delay current foldback circuit based on saturation voltage drop detection for designing and safeguarding.

The present invention relates to the used technical solutions that solves the above problems are as follows: a kind of parallel connection based on saturation voltage drop detection IGBT delay current foldback circuit, including pwm pulse major loop and saturation voltage drop delay detection control circuit.

The control pulse transition that the pwm pulse major loop sends control system is the PWM driving with driving capability Pulse, driving IGBT are turned on and off.It is delayed with door U1 and U3 to saturation voltage drop and detects the over current fault letter that control circuit generates It number is handled, when the over current fault signal is high level, pwm pulse major loop logic is constant；When the over current fault signal When for low level, it is low level with door U1 and U3 output, then IGBT drives that no matter controlling pulse, which is high level or low level, Pulse is low level, realizes the overcurrent protection of IGBT.

Preferably, the input of the saturation voltage drop delay detection control circuit is the pressure drop of IGBT hourglass source electrode, controls pulse, defeated It is out over current fault signal, saturation voltage drop delay detection control circuit includes: to generate the pressure drop of IGBT hourglass source electrode as input Flow the over-current signal generative circuit of signal, two control pulse delay circuits, control pulse and overcurrent event in conjunction with above-mentioned delay Hinder the fault comprehensive processing circuit that signal is formed.

Preferably, the over-current signal generative circuit leads to using the saturation voltage drop that IGBT drains between source electrode as input It crosses after the RC filter circuit being made of resistance R1 and capacitor C1 and is linked into the anode of comparator U5, and overcurrent reference voltage Vref1 It is linked into the cathode of comparator U5, input of the over-current signal of comparator U5 output as fault comprehensive processing circuit.

Preferably, it is provided with fast recovery diode D1 between the IGBT drain electrode and RC filter circuit, prevents forceful electric power electric current Adverse current control system is provided with offset compensation resistance between output end and the comparator anode of RC filter circuit, realizes comparator Positive negative input pole impedance matching.

Preferably, two control pulse delay circuits are respectively used to postpone control pulse 1 and 2, wrap The first NAND gate, RC charge-discharge circuit, comparator, the second NAND gate, the first reversed Schmidt trigger and second is included reversely to apply Output of the over current fault signal of schmitt trigger, control pulse and fault comprehensive processing circuit feedback after the first NAND gate Voltage divides two-way, is linked into the input terminal of the second NAND gate by reversed Schmidt trigger all the way, and another way passes through RC charge and discharge It is linked into the anode of comparator after circuit, is compared with the delay reference voltage Vref2 of access comparator cathode, passes through RC Parameter can realize the adjustment to the control pulse delay time, and the output end of comparator is linked into the input terminal of the second NAND gate, the The output end of two NAND gates is linked into the input terminal of the second reversed Schmidt trigger, the output of the second reversed Schmidt trigger Voltage accesses fault comprehensive processing circuit.

Preferably, the RC charge-discharge circuit includes mosfet transistor, charge and discharge resistance and charge and discharge capacitance, described The grid of mosfet transistor is connected with the output end of the first NAND gate, and source electrode ground connection, drain electrode passes through charge and discharge resistance and power supply Connection, the both ends of the charge and discharge capacitance connect with the source electrode and drain electrode of mosfet transistor respectively, RC charge-discharge circuit it is defeated Pass through the anode of access comparator after current-limiting resistance out.

Preferably, the fault comprehensive processing circuit includes NAND gate, and input is over-current signal generative circuit and control The output signal of pulse delay circuit.When the output of overcurrent signal generating circuit is high level, and it is defeated to control pulse delay circuit When being out low level, over current fault signal is high level, then circuit fault-free；Conversely, the output of over-current signal production circuit is It is high level that high level and control pulse daley, which export, and over current fault signal is low level, then circuit is faulty.

Preferably, the NAND gate output in the fault comprehensive processing circuit is connected with a delay circuit, and the circuit is to mistake Stream fault-signal is delayed, and handles over current fault by governor circuit with the time for providing sufficient, delay time is generally ms grades.

Compared with the prior art, the advantages of the present invention are as follows:

1, two-way IGBT overcurrent protection electric current uses the same over-current signal generative circuit in the present invention, simplifies circuit and sets Meter.

2, delay detection is carried out to IGBT saturation voltage drop in the present invention, saturation voltage drop is unstable when IGBT being avoided to open causes Mistake protection, improve the reasonability and reliability of circuit.

Detailed description of the invention

Fig. 1 is existing typical IGBT parallel connection application circuit.

Fig. 2 is the relational graph of PWM driving pulse and IGBT saturation voltage drop.

Fig. 3 is pwm pulse major loop schematic diagram in the embodiment of the present invention.

Fig. 4 is saturation voltage drop delay detection control circuit schematic diagram in the embodiment of the present invention.

Fig. 5 is that pulse delay circuit timing diagram is controlled in the embodiment of the present invention.

Specific embodiment

The present invention will be described in further detail below with reference to the embodiments of the drawings.

As shown in Figure 3-4, the parallel IGBT delay overcurrent protection electricity that one of the present embodiment is detected based on saturation voltage drop Road, including pwm pulse major loop and saturation voltage drop delay detection control circuit.

The control pulse 1 and 2 that control system (single-chip microcontroller or DSP etc.) is sent is changed into tool by the pwm pulse major loop There is the PWM driving pulse 1 and 2 of driving capability, driving IGBT is turned on and off.Meanwhile over current fault can be believed with door U1 and U3 Numbers 1 and 2 are handled, and when the signal is high level (i.e. without over current fault), pwm pulse major loop logic is constant；When the letter When number being low level (having over current fault), no matter controlling pulse 1 and 2 is high level or low level, is exported with door U1 and U3 It is low level, then IGBT driving pulse 1 and 2 is low level, realizes the overcurrent protection of IGBT.

The over current fault signal 1 and 2 is delayed by saturation voltage drop detects control circuit generation, the saturation voltage drop delay The input for detecting control circuit is the pressure drop of IGBT hourglass source electrode, control pulse 1 and 2, is exported as over current fault signal 1 and 2.Saturation pressure It includes 4 parts that drop delay detection control circuit, which has altogether, is 1. over-current signal generative circuit, 2. and 3. prolongs for control pulse 1 and 2 When circuit, be 4. fault comprehensive processing circuit.Next each section circuit is explained in detail:

1. over-current signal generative circuit:

The input of circuit is the pressure drop of IGBT hourglass source electrode, is exported as over-current signal (high level is effective), and wherein D1 is fast restores Diode prevents forceful electric power electric current adverse current control system；R1 and C1 constitutes RC filter circuit, filters to the saturation voltage drop of acquisition Wave；R3 and R4 is pull-up resistor, and U5 is comparator, and R2 is offset compensation resistance, realizes the positive negative input pole impedance matching of comparator. Overcurrent reference voltage Vref1 is the corresponding saturation pressure depreciation of overcurrent protection threshold value, which should be according to the electric current of selected IGBT model It is determined with saturation voltage drop curve.Specifically, when electric current is lower than overcurrent protection threshold value, IGBT saturation voltage drop is lower than overcurrent base Quasi- voltage Vref1, comparator U5 output voltage are low level, are otherwise high level.That is U5 output is that high level explanation has occurred Over current fault.

3. 2. the control delay circuit of pulse 1 and 2:

U6, U9, U11, U14 are NAND gate, and T1 and T2 are that MOSFET, R5 and R8 are RC charge and discharge resistance, and C2 and C3 are RC Charge and discharge capacitance, T1, R5, C2 and T2, R8, C3 have respectively constituted 2 RC charge-discharge circuits；R6 and R9 be current-limiting resistance, U7 and U12 is comparator, and R7 and R10 are pull-up resistor, and U8, U10, U13, U15 are reversed Schmidt trigger.

The function of the circuit is delayed to control pulse 1 and 2, and delay time is set as 6us.Due to scheme 2. with figure 3. Principle is identical, is only illustrated for scheming 2. to circuit theory here.Assuming that over current fault signal 1 is high level, i.e., without mistake Flow failure.When control pulse 1 switchs to high level by low level, NAND gate U6 output is low level, and MOSFET T1 is turned off, this When power supply VCC charged by resistance R5 to capacitor C2, when C2 charging voltage lower than delay reference voltage Vref2 when, compare Device U7 is low level, and when charging voltage is higher than reference voltage, comparator is just changed into high level.By the way that resistance is rationally arranged The value of R5, capacitor C2 and the reference voltage Vref2 that is delayed, can make the delay for controlling pulse 1 be accurate to 6us or so, such as " U7 in Fig. 5 Output " waveform；Reversed Schmidt trigger U8 carries out Reverse recovery to the output voltage of NAND gate U6, such as " U8 output " in the following figure Waveform；NAND gate U9 and reversed Schmidt trigger U10 carries out logical combination to time delayed signal, and output is such as " U10 in Fig. 5 Output " waveform；

4. fault comprehensive processing circuit

By analyzing to obtain above, when over current fault occurs, 1. circuit exports high level, 2. and 3. circuit exports as control Square wave after the delay of pulse 1 and 2 6us.The effect of circuit 4. is to carry out NAND Logic operation to the two signals, and effect is: Within the 6us time of delay (t1~t2), because 1. circuit exports high level, and 2. and 3. circuit exports low level, therefore mistake Flowing fault-signal 1 and 2 is high level, i.e. circuit fault-free, realizes in delay time and does not handle over current fault；When 2. and 3. at the end of delay time, because 1. circuit exports high level, and output is high level to circuit, therefore over current fault signal 1 and 2 be low level, i.e. circuit is faulty, realizes delay time and handles later over current fault.In addition, overcurrent event It being delayed before barrier signal output, for handling over current fault to governor circuit, this time is generally ms grades for the delay, It may be configured as 1.5ms or so.But it is that nothing is prolonged that the fault-signal, which becomes low level (the case where over current fault occur) from high level, When, to realize instantaneous shutdown major loop pulse；But low level, when restoring to high level, be delayed 1.5ms, fills to control system The time of foot is protected.Delay circuit can be using the delay circuit or other existing in the control delay circuit of pulse 1 and 2 Delay circuit.

Over current fault signal Logic (by taking over current fault signal 1 as an example):

2. 4. the signal by being generated jointly by control pulse delay circuit with fault comprehensive processing circuit, when no over current fault When, which is high level, and the signal does not influence the normal logic of PWM driving pulse major loop at this time；When occur over current fault, The signal is low level, and PWM driving pulse major loop is forced to be locked as low level at this time, and no matter " control pulse 1 " is high electricity Flat or low level (U1 be with door, when over current fault signal 1 is low level, output must be low level).In addition, with non- The feedback of over current fault signal 1 has also been introduced in the input of door U6, and the purpose is to (over current fault signal 1 is during over current fault Low level), so that control pulse delay circuit is 2. failed, because an input of U6 is low level, then its output is height forever Level.

In addition to the implementation, all to use equivalent transformation or equivalent replacement the invention also includes there is an other embodiments The technical solution that mode is formed should all be fallen within the scope of the hereto appended claims.