Time measuring circuit

文档序号：174256 发布日期：2021-10-29 浏览：31次中文

阅读说明：本技术 时间测量电路 (Time measuring circuit ) 是由栗林英毅于 2020-03-16 设计创作，主要内容包括：为了实现低耗电动作和准确的时间测量,本发明的时间测量电路具备：逻辑电路(22),其利用停止信号(ROSC-STOP)分别掩蔽高速时钟(RCLK1)和使高速时钟(RCLK1)反相得到的高速时钟(RCLK2)；高速计数器(12a、12b),其对被停止信号(ROSC-STOP)掩蔽的高速时钟(ROSC-CLK1、ROSC-CLK2)进行计数；选择器(20),其选择高速计数器(12a、12b)的计数结果当中由未产生无法受理的时间宽度的时钟输入那一方计数器得到的计数结果；以及时间算出部(21),其根据选择器(20)所选择的计数结果来算出开始信号(ROSC-START)的输入起到停止信号(ROSC-STOP)的输入为止的时间间隔。(In order to realize low power consumption operation and accurate time measurement, a time measurement circuit of the present invention includes: a logic circuit (22) which masks the high-speed clock (RCLK1) and a high-speed clock (RCLK2) obtained by inverting the high-speed clock (RCLK1) by a STOP signal (ROSC _ STOP); high-speed counters (12a, 12b) for counting the high-speed clocks (ROSC _ CLK1, ROSC _ CLK2) masked by a STOP signal (ROSC _ STOP); a selector (20) for selecting a count result obtained by a counter to which a clock having no unacceptable time width is input, from among the count results of the high-speed counters (12a, 12 b); and a time calculation unit (21) that calculates the time interval from the input of the START signal (ROSC _ START) to the input of the STOP signal (ROSC _ STOP) on the basis of the count result selected by the selector (20).)

1. A time measurement circuit is characterized by comprising:

a flip-flop circuit configured to output an oscillation permission signal that becomes active at a timing when a start signal from the outside is input and that becomes inactive at a timing when a stop signal from the outside is input;

an oscillation circuit configured to generate a 1 st clock in a period in which the oscillation permission signal is valid;

a logic circuit configured to mask the 1 st clock and a 2 nd clock obtained by inverting the 1 st clock by the stop signal;

a 1 st counter configured to count the 1 st clock masked by the stop signal;

a 2 nd counter configured to count the 2 nd clock masked by the stop signal;

a selector configured to select a count result obtained by a counter to which a clock having no unacceptable time width is input, from among the count results of the 1 st counter and the 2 nd counter; and

and a time calculation unit configured to calculate a time interval between the input of the start signal and the input of the stop signal based on the count result selected by the selector after the input of the stop signal.

2. The time measurement circuit of claim 1,

the selector selects a count result of the 1 st counter in a range where the phase of the 1 st clock is 0 ° to less than a predetermined 1 st phase value, the 1 st phase value being a value less than 180 °, selects a count result of the 2 nd counter in a range where the phase of the 1 st clock is from the 1 st phase value to less than a predetermined 2 nd phase value, the 2 nd phase value being a value greater than or equal to 180 ° and less than 360 °, and selects a count result of the 1 st counter in a range where the phase of the 1 st clock is greater than or equal to the 2 nd phase value and less than 360 °.

3. Time measurement circuit according to claim 1 or 2,

the logic circuit is composed of a buffer circuit, an inverter, a first OR circuit, and a second OR circuit,

the buffer circuit takes the 1 st clock output from the oscillation circuit as an input,

the inverter is configured to generate the 2 nd clock by inverting the 1 st clock output from the oscillation circuit,

the first OR circuit is configured to OR-mask the 1 st clock output from the buffer circuit with the stop signal,

the second OR circuit is configured to OR-mask the 2 nd clock output from the inverter with the stop signal.

4. A time measurement circuit is characterized by comprising:

an oscillation circuit configured to generate a 1 st clock in a period in which the oscillation permission signal is valid;

a logic circuit configured to generate a 2 nd clock obtained by masking the 1 st clock with the stop signal;

a 1 st counter configured to count the 1 st clock;

a 2 nd counter configured to count the 2 nd clock;

5. The time measurement circuit of claim 4,

the selector selects a count result of the 2 nd counter in a range where the phase of the 1 st clock is 0 ° to less than a predetermined 1 st phase value, the 1 st phase value being a value less than 180 °, selects a count result of the 1 st counter in a range where the phase of the 1 st clock is from the 1 st phase value to less than a predetermined 2 nd phase value, the 2 nd phase value being a value greater than or equal to 180 ° and less than 360 °, and selects a count result of the 2 nd counter in a range where the phase of the 1 st clock is greater than or equal to the 2 nd phase value and less than 360 °.

6. Time measurement circuit according to claim 4 or 5,

the logic circuit is configured by an OR circuit configured to generate the 2 nd clock by OR masking the 1 st clock output from the oscillation circuit with the stop signal.

7. A time measurement circuit is characterized by comprising:

a test execution unit configured to perform a test of the time measurement circuit;

an operation setting circuit configured to select and output a 1 st start signal and a 1 st stop signal inputted from the outside at ordinary times, select and output a 2 nd start signal and a 2 nd stop signal outputted from the test execution unit when a test is executed, and output a 3 rd stop signal when the test is completed;

a flip-flop circuit configured to output an oscillation permission signal that becomes active at a timing when the 1 st start signal or the 2 nd start signal is input and that becomes inactive at a timing when the 1 st stop signal or the 3 rd stop signal is input;

an oscillation circuit configured to generate a 1 st clock in a period in which the oscillation permission signal is valid;

a logic circuit configured to mask the 1 st clock and a 2 nd clock obtained by inverting the 1 st clock by the 1 st stop signal or the 2 nd stop signal, respectively;

a 1 st counter configured to count a 1 st clock masked by the 1 st stop signal or the 2 nd stop signal;

a 2 nd counter configured to count a 2 nd clock masked by the 1 st stop signal or the 2 nd stop signal;

a time calculation unit configured to calculate a time interval from the input of the 1 st start signal to the input of the 1 st stop signal based on the count result selected by the selector after the input of the 1 st stop signal at ordinary times;

the test execution unit compares the count results of the 1 st counter and the 2 nd counter when executing a test, thereby performing the test of the oscillation circuit.

8. The time measurement circuit of claim 7,

9. The time measurement circuit of claim 8,

the test execution unit acquires and compares a count result of the 1 st counter when the phase of the 1 st clock is a value immediately before the 1 st phase value, or a value immediately after the 1 st phase value with a count result of the 2 nd counter, and further acquires and compares a count result of the 1 st counter when the phase of the 1 st clock is a value immediately before the 2 nd phase value, or a value immediately after the 2 nd phase value with a count result of the 2 nd counter.

10. The time measurement circuit of claim 9,

the test execution unit determines that the oscillation circuit is normal when the acquired count result of the 1 st counter matches the count result of the 2 nd counter, and determines that a failure has occurred in the oscillation circuit when the count result of the 1 st counter does not match the count result of the 2 nd counter.

11. Time measurement circuit according to claim 9 or 10,

the test execution unit subtracts 1 from the count result of the acquired 2 nd counter and then compares the count result of the 1 st counter with the count result of the 2 nd counter when the count result of the 1 st counter and the count result of the 2 nd counter are acquired when the phase of the 1 st clock is a value immediately before the 1 st phase value, or a value immediately after the 1 st phase value.

12. Time measurement circuit according to one of the claims 7 to 11,

the logic circuit includes:

a buffer circuit that receives the 1 st clock output from the oscillation circuit;

an inverter configured to generate the 2 nd clock by inverting the 1 st clock output from the oscillation circuit;

a mask release timing control circuit configured to generate a 4 th stop signal and a 5 th stop signal from the 2 nd stop signal when a test is performed, the 4 th stop signal masking the 1 st clock later than the 2 nd clock and releasing the masking later than the 2 nd clock, and the 5 th stop signal masking the 2 nd clock earlier than the 1 st clock and releasing the masking earlier than the 1 st clock;

a first OR circuit configured to OR-mask the 1 st clock output from the buffer circuit with the 1 st stop signal OR the 4 th stop signal; and

a second OR circuit configured to OR-mask a 2 nd clock output from the inverter with the 1 st stop signal OR the 5 th stop signal;

when the oscillation permission signal becomes active, the oscillation circuit, the buffer circuit, and the inverter operate so that the 2 nd clock becomes active before the 1 st clock.

13. Time measurement circuit according to one of claims 2, 5, 8,

when the count result selected by the selector is received when the phase of the 1 st clock is within a range of not less than 360 ° from the 1 st phase value, the time calculation unit subtracts 1 from the count result and calculates the time interval.

14. The time measurement circuit according to any one of claims 1 to 13,

further provided with an encoder that outputs a signal representing a phase value of an output of the oscillation circuit,

the selector selects one of the count results of the 1 st counter and the 2 nd counter according to a signal output from the encoder.

Technical Field

The present invention relates to a time measuring circuit capable of measuring time with high accuracy.

Background

When Time measurement with a psec level high resolution is performed, a method called TDC (Time-to-Digital Converter) using a gate delay of a logic circuit is widely known (see non-patent document 1). The TDC is generally configured based on dll (delay Locked loop) or pll (phase Locked loop). However, the DLL and PLL require time for stabilization of oscillation of the clock, and require the TDC to be operated before the time measurement is started, which makes it difficult to achieve low power consumption.

For example, an ultrasonic flowmeter for a gas meter needs to measure a propagation time difference of ultrasonic waves with low power consumption, high accuracy, and high resolution, and therefore, an operation period of a high-speed counter (oscillation period of a high-speed clock) needs to be shortened as much as possible. However, as described above, since the DLL TDC and the PLL TDC require time for stabilizing the oscillation of the delay circuit, the oscillation period of the high-speed clock is long, which is disadvantageous in terms of power consumption.

When the operation time of the TDC (oscillation time of the high-speed clock) is minimized to realize the low power consumption operation, a ring oscillator type configuration disclosed in patent document 1, for example, is considered.

Fig. 25 is a circuit diagram showing a configuration of a conventional ring oscillator TDC. The ring oscillator type TDC is constituted by a D flip-flop circuit 10, a ring oscillator 11, and a high-speed counter 12. The D flip-flop circuit 10 receives a 1-bit binary number "1" (1' b1) as a D input, receives an oscillation START signal ROSC _ START as a clock input, receives an oscillation STOP signal ROSC _ STOP as a reset input, and outputs an oscillation permission signal TDC _ EN. The ring oscillator 11 generates a high-speed clock TAP [2] during a period in which the oscillation permission signal TDC _ EN is active. The high-speed counter 12 counts the high-speed clock.

Fig. 26 is a timing chart illustrating an operation of the ring oscillator type TDC of fig. 25. The D flip-flop circuit 10 receives a 1-bit binary number "1" (1' b1) as a D input, receives the oscillation START signal ROSC _ START as a clock input, receives the oscillation STOP signal ROSC _ STOP as a reset input, and outputs the oscillation permission signal TDC _ EN which becomes active (High) when the oscillation START signal ROSC _ START rises and inactive (Low) when the oscillation STOP signal ROSC _ STOP rises as shown in fig. 26.

The ring oscillator 11 is composed of a NAND circuit 110, a buffer circuit 111-1, and a buffer circuit 111-2, the NAND circuit 110 takes a negative logical product of an oscillation permission signal TDC _ EN and a high-speed clock TAP [2], the buffer circuit 111-1 takes an output TAP [0] of the NAND circuit 110 as an input, the buffer circuit 111-2 takes an output TAP [1] of the buffer circuit 111-1 as an input, and the output TAP [2] thereof is output as a high-speed clock. The ring oscillator 11 generates a clock TAP [2] having a higher speed than the low speed clock (ROSC _ STOP) as shown in fig. 26 while the oscillation permission signal TDC _ EN outputted from the D flip-flop circuit 10 is active.

The high-speed counter 12 counts the rise of the high-speed clock TAP [2] and outputs a count result HS _ CNT.

However, in the ring oscillator type TDC shown in fig. 25, as shown at 100 in fig. 26, in the timing sequence of the oscillation STOP signal ROSC _ STOP, the ring oscillator 11 outputs a clock of a Low width which cannot be received by the flip-flop constituting the high-speed counter 12, and the value of the count result HS _ CNT of the high-speed counter 12 becomes not fixed, so that there is a problem that an accurate time cannot be measured. Hereinafter, in the present invention, the pulse having a minute width generated at the unexpected timing is referred to as a glitch.

For example, if the frequency of the high-speed clock TAP [2], which is the output of the ring oscillator 11, is 600MHz, the fact that the count value of the high-speed counter 12 is increased by "1" due to the false signal indicates that the time measurement value is a value 1.67nsec larger than the expected value. The ultrasonic flowmeter disclosed in patent document 1 requires time measurement with sub-nanosecond accuracy to achieve minute flow rate measurement, and therefore, the specification of the flow rate measurement value differing by ± 1.67ns from the expected value cannot satisfy the product specifications.

Documents of the prior art

Patent document

Patent document 1: japanese patent No. 4661714

Non-patent document

Non-patent document 1: stephan Henzler, "Time-to-Digital Converters", Springer,2010

Disclosure of Invention

Problems to be solved by the invention

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a time measurement circuit capable of realizing a low power consumption operation and accurate time measurement.

Means for solving the problems

A time measurement circuit (embodiment 1) of the present invention is characterized by comprising: a flip-flop circuit configured to output an oscillation permission signal that becomes active at a timing when a start signal from the outside is input and that becomes inactive at a timing when a stop signal from the outside is input; an oscillation circuit configured to generate a 1 st clock in a period in which the oscillation permission signal is valid; a logic circuit configured to mask the 1 st clock and a 2 nd clock obtained by inverting the 1 st clock by the stop signal; a 1 st counter configured to count the 1 st clock masked by the stop signal; a 2 nd counter configured to count the 2 nd clock masked by the stop signal; a selector configured to select a count result obtained by a counter to which a clock having no unacceptable time width is input, from among the count results of the 1 st counter and the 2 nd counter; and a time calculation unit configured to calculate a time interval between the input of the start signal and the input of the stop signal based on the count result selected by the selector after the input of the stop signal.

In an exemplary configuration of the time measurement circuit according to the present invention, the selector selects the count result of the 1 st counter in a range where the phase of the 1 st clock is from 0 ° to less than a predetermined 1 st phase value, the 1 st phase value is a value less than 180 °, the count result of the 2 nd counter is selected in a range where the phase of the 1 st clock is from the 1 st phase value to less than a predetermined 2 nd phase value, the 2 nd phase value is a value greater than or equal to 180 ° and less than 360 °, and the count result of the 1 st counter is selected in a range where the phase of the 1 st clock is greater than or equal to the 2 nd phase value and less than 360 °.

In an exemplary configuration of the time measurement circuit according to the present invention, the logic circuit includes a buffer circuit, an inverter, a first OR circuit, and a second OR circuit, the buffer circuit receives a 1 st clock output from the oscillation circuit, the inverter generates the 2 nd clock by inverting the 1 st clock output from the oscillation circuit, the first OR circuit performs an OR masking on the 1 st clock output from the buffer circuit by using the stop signal, and the second OR circuit performs an OR masking on the 2 nd clock output from the inverter by using the stop signal.

Further, a time measurement circuit (embodiment 2) of the present invention is characterized by including: a flip-flop circuit configured to output an oscillation permission signal that becomes active at a timing when a start signal from the outside is input and that becomes inactive at a timing when a stop signal from the outside is input; an oscillation circuit configured to generate a 1 st clock in a period in which the oscillation permission signal is valid; a logic circuit configured to generate a 2 nd clock obtained by masking the 1 st clock with the stop signal; a 1 st counter configured to count the 1 st clock; a 2 nd counter configured to count the 2 nd clock; a selector configured to select a count result obtained by a counter to which a clock having no unacceptable time width is input, from among the count results of the 1 st counter and the 2 nd counter; and a time calculation unit configured to calculate a time interval between the input of the start signal and the input of the stop signal based on the count result selected by the selector after the input of the stop signal.

In an exemplary configuration of the time measurement circuit according to the present invention, the selector selects the count result of the 2 nd counter in a range where the phase of the 1 st clock is from 0 ° to less than a predetermined 1 st phase value, the 1 st phase value is a value less than 180 °, the count result of the 1 st counter is selected in a range where the phase of the 1 st clock is from the 1 st phase value to less than a predetermined 2 nd phase value, the 2 nd phase value is a value of 180 ° or more and less than 360 °, and the count result of the 2 nd counter is selected in a range where the phase of the 1 st clock is from the 2 nd phase value or more and less than 360 °.

In an example of the configuration of the time measurement circuit according to the present invention, the logic circuit is configured by an OR circuit configured to generate the 2 nd clock by OR masking the 1 st clock output from the oscillation circuit with the stop signal.

Further, a time measurement circuit (embodiment 3) of the present invention is characterized by including: a test execution unit configured to perform a test of the time measurement circuit; an operation setting circuit configured to select and output a 1 st start signal and a 1 st stop signal inputted from the outside at ordinary times, select and output a 2 nd start signal and a 2 nd stop signal outputted from the test execution unit when a test is executed, and output a 3 rd stop signal when the test is completed; a flip-flop circuit configured to output an oscillation permission signal that becomes active at a timing when the 1 st start signal or the 2 nd start signal is input and that becomes inactive at a timing when the 1 st stop signal or the 3 rd stop signal is input; an oscillation circuit configured to generate a 1 st clock in a period in which the oscillation permission signal is valid; a logic circuit configured to mask the 1 st clock and a 2 nd clock obtained by inverting the 1 st clock by the 1 st stop signal or the 2 nd stop signal, respectively; a 1 st counter configured to count a 1 st clock masked by the 1 st stop signal or the 2 nd stop signal; a 2 nd counter configured to count a 2 nd clock masked by the 1 st stop signal or the 2 nd stop signal; a selector configured to select a count result obtained by a counter to which a clock having no unacceptable time width is input, from among the count results of the 1 st counter and the 2 nd counter; and a time calculation unit configured to calculate a time interval from the input of the 1 st start signal to the input of the 1 st stop signal based on the count result selected by the selector after the input of the 1 st stop signal at ordinary times; the test execution unit compares the count results of the 1 st counter and the 2 nd counter when executing a test, thereby performing the test of the oscillation circuit.

In addition, in an exemplary configuration of the time measurement circuit according to the present invention, the test execution unit may acquire and compare a count result of the 1 st counter when the phase of the 1 st clock is a value immediately before the 1 st phase value, or a value immediately after the 1 st phase value with a count result of the 2 nd counter, and further acquire and compare a count result of the 1 st counter when the phase of the 1 st clock is a value immediately before the 2 nd phase value, or a value immediately after the 2 nd phase value with a count result of the 2 nd counter.

In an exemplary configuration of the time measurement circuit according to the present invention, the test execution unit may determine that the oscillation circuit is normal when the acquired count result of the 1 st counter matches the count result of the 2 nd counter, and may determine that a failure has occurred in the oscillation circuit when the count result of the 1 st counter does not match the count result of the 2 nd counter.

In addition, in an exemplary configuration of the time measurement circuit according to the present invention, the test execution unit may be configured to, when the count result of the 1 st counter and the count result of the 2 nd counter are obtained when the phase of the 1 st clock is a value immediately before the 1 st phase value, or a value immediately after the 1 st phase value, subtract 1 from the count result of the 2 nd counter, and compare the count result of the 1 st counter with the count result of the 2 nd counter.

In an embodiment of the time measurement circuit according to the present invention, the logic circuit includes: a buffer circuit that receives the 1 st clock output from the oscillation circuit; an inverter configured to generate the 2 nd clock by inverting the 1 st clock output from the oscillation circuit; a mask release timing control circuit configured to generate a 4 th stop signal and a 5 th stop signal from the 2 nd stop signal when a test is performed, the 4 th stop signal masking the 1 st clock later than the 2 nd clock and releasing the masking later than the 2 nd clock, and the 5 th stop signal masking the 2 nd clock earlier than the 1 st clock and releasing the masking earlier than the 1 st clock; a first OR circuit configured to OR-mask the 1 st clock output from the buffer circuit with the 1 st stop signal OR the 4 th stop signal; and a second OR circuit configured to OR-mask a 2 nd clock output from the inverter with the 1 st stop signal OR the 5 th stop signal; when the oscillation permission signal becomes active, the oscillation circuit, the buffer circuit, and the inverter operate so that the 2 nd clock becomes active before the 1 st clock.

In addition, in an exemplary configuration of the time measurement circuit according to the present invention, when the count result selected by the selector is received when the phase of the 1 st clock is within a range of not less than 360 ° from the 1 st phase value, the time calculation unit subtracts 1 from the count result, and then calculates the time interval.

In addition, in an exemplary configuration of the time measurement circuit according to the present invention, the time measurement circuit further includes an encoder that outputs a signal indicating a phase value of an output of the oscillation circuit, and the selector selects one of count results of the 1 st counter and the 2 nd counter according to the signal output from the encoder.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, by providing a logic circuit for masking a 1 st clock generated by an oscillation circuit and a 2 nd clock obtained by inverting the 1 st clock by a stop signal, a 1 st counter for counting the 1 st clock masked by the stop signal, a 2 nd counter for counting the 2 nd clock masked by the stop signal, and a selector for selecting a count result obtained by inputting a clock having a time width which is not acceptable to the counter from among count results of the 1 st counter and the 2 nd counter, it is possible to realize a low power consumption operation and accurate time measurement independent of the input time of the stop signal.

Further, in the present invention, by providing a logic circuit which generates a 2 nd clock obtained by masking a 1 st clock generated by an oscillation circuit with a stop signal, a 1 st counter which counts the 1 st clock, a 2 nd counter which counts the 2 nd clock, and a selector which selects a count result obtained by a counter which has not generated an unacceptable time width among count results of the 1 st counter and the 2 nd counter, it is possible to realize a low power consumption operation and accurate time measurement independent of an input time of the stop signal.

Further, in the present invention, by providing a logic circuit which masks a 1 st clock generated by the oscillation circuit and a 2 nd clock obtained by inverting the 1 st clock by a 1 st stop signal or a 2 nd stop signal, respectively, a 1 st counter which counts the 1 st clock masked by the 1 st stop signal or the 2 nd stop signal, a 2 nd counter which counts the 2 nd clock masked by the 1 st stop signal or the 2 nd stop signal, and a selector which selects a count result obtained by inputting a clock which does not generate an unacceptable time width to the counter among count results of the 1 st counter and the 2 nd counter, it is possible to realize a low operation and accurate time measurement which does not depend on the input time of the stop power consumption signal. In the present invention, the oscillation circuit can be tested by providing the operation setting circuit and the test execution unit.

Drawings

Fig. 1 is a circuit diagram showing a configuration of a time measurement circuit according to embodiment 1 of the present invention.

Fig. 2 is a timing chart illustrating the operation of the time measuring circuit according to embodiment 1 of the present invention.

Fig. 3 is a circuit diagram showing the configuration of an edge detection circuit of the time measurement circuit according to embodiment 1 of the present invention.

Fig. 4 is a diagram showing a relationship between a high-speed clock and a time signal in embodiment 1 of the present invention.

Fig. 5 is a timing chart illustrating a method of correcting the count result of the high-speed clock in embodiment 1 of the present invention.

Fig. 6 is a timing chart illustrating a method of correcting the count result of the high-speed clock in embodiment 1 of the present invention.

Fig. 7 is a timing chart illustrating a method of correcting the count result of the high-speed clock in embodiment 1 of the present invention.

Fig. 8 is a timing chart illustrating a method of correcting the count result of the high-speed clock in embodiment 1 of the present invention.

Fig. 9 is a diagram illustrating the necessity or non-necessity of correction of the count result of the high-speed clock in embodiment 1 of the present invention.

Fig. 10 is a circuit diagram showing the configuration of the time measuring circuit according to embodiment 2 of the present invention.

Fig. 11 is a diagram showing a relationship between a high-speed clock and a time signal in embodiment 2 of the present invention.

Fig. 12 is a timing chart illustrating a method of correcting the count result of the high-speed clock in embodiment 2 of the invention.

Fig. 13 is a timing chart illustrating a method of correcting the count result of the high-speed clock in embodiment 2 of the present invention.

Fig. 14 is a timing chart illustrating a method of correcting the count result of the high-speed clock in embodiment 2 of the invention.

Fig. 15 is a timing chart illustrating a method of correcting the count result of the high-speed clock in embodiment 2 of the invention.

Fig. 16 is a diagram for explaining the necessity or non-necessity of correction of the count result of the high-speed clock in embodiment 2 of the present invention.

Fig. 17 is a circuit diagram showing the configuration of the time measuring circuit according to embodiment 3 of the present invention.

Fig. 18 is a circuit diagram showing the configuration of an operation setting circuit of the time measuring circuit according to embodiment 3 of the present invention.

Fig. 19 is a circuit diagram showing the configuration of a mask release timing control circuit of the time measurement circuit according to embodiment 3 of the present invention.

Fig. 20 is a block diagram showing the configuration of the time calculating unit of the time measuring circuit according to embodiment 3 of the present invention.

Fig. 21 is a timing chart illustrating an operation of the time measurement circuit according to embodiment 3 of the present invention during testing.

Fig. 22 is a timing chart illustrating the operation of the mask release timing control circuit in the test of the time measurement circuit according to embodiment 3 of the present invention.

Fig. 23 is a timing chart illustrating the operation of the mask release timing control circuit in the test of the time measurement circuit according to embodiment 3 of the present invention.

Fig. 24 is a block diagram showing an example of a configuration of a computer that realizes a time calculating unit of the time measuring circuit according to embodiment 1 to embodiment 3 of the present invention.

Fig. 25 is a circuit diagram showing an example of a configuration of a conventional ring oscillator TDC.

Fig. 26 is a timing chart illustrating an operation of the conventional ring oscillator TDC.

Detailed Description

[1 st embodiment ]

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram showing a configuration of a time measurement circuit according to embodiment 1 of the present invention. The time measurement circuit includes: a D flip-flop circuit 10 that receives a 1-bit binary number "1" (1' b1) as a D input, receives an oscillation START signal ROSC _ START from the outside as a clock input, receives an oscillation STOP signal ROSC _ STOP from the outside as a reset input, and outputs an oscillation permission signal TDC _ EN; a ring oscillator 11a (oscillation circuit) that generates a high-speed clock TAP [15] (1 st clock) during a period in which an oscillation permission signal TDC _ EN is active; a buffer circuit 13 that receives the high-speed clock TAP [15] and outputs a high-speed clock RCLK1 (clock No. 1); an inverter 14 that outputs a high-speed clock RCLK2 (2 nd clock) obtained by inverting the high-speed clock TAP [15 ]; an OR circuit 15 that outputs the result of logical sum of the output RCLK1 of the buffer circuit 13 and the oscillation STOP signal ROSC _ STOP as a high-speed clock ROSC _ CLK 1; and an OR circuit 16 that outputs the result of logical sum of the output RCLK2 of the inverter 14 and the oscillation STOP signal ROSC _ STOP as a high-speed clock ROSC _ CLK 2.

Further, the time measurement circuit includes: a high-speed counter 12a (1 st counter) that counts a high-speed clock ROSC _ CLK 1; a high-speed counter 12b (2 nd counter) that counts a high-speed clock ROSC _ CLK 2; an edge detection circuit 17 that detects a rising edge of the oscillation STOP signal ROSC _ STOP from the oscillation STOP signal ROSC _ STOP and the low-speed clock MCLK; a D flip-flop circuit 18a that latches a count result HS _ CNT1[8:0] of 8 bits of the high-speed counter 12 a; a DD flip-flop circuit 18b that latches a count result HS _ CNT2[8:0] of 8 bits of the high-speed counter 12 b; an encoder 19 that outputs a 5-bit time signal HS _ PHASE [4:0] indicating the PHASE value of the output of the ring oscillator 11 a; a selector 20 for selecting one of the 8-bit outputs LATCH1[8:0] and LATCH2[8:0] of the D flip-flop circuits 18a and 18 b; and a time calculation unit 21 that calculates a time interval from the rise of the oscillation START signal ROSC _ START to the rise of the oscillation STOP signal ROSC _ STOP based on the count result selected by the selector 20.

The buffer circuit 13, the inverter 14, and the OR circuits 15 and 16 constitute a logic circuit 22.

The ring oscillator 11a is composed of a NAND circuit 110, 15 buffer circuits 111-1 to 111-15, and 16D flip-flop circuits 112-1 to 112-16, the NAND circuit 110 takes a negative logical product of an oscillation permission signal TDC _ EN and a high speed clock TAP [15], the 15 buffer circuits 111-1 to 111-15 are cascade-connected to an output of the NAND circuit 110, and the 16D flip-flop circuits 112-1 to 112-16 take outputs of the NAND circuit 110 and the buffer circuits 111-1 to 111-15 as D inputs, respectively, and take an oscillation STOP signal ROSC _ STOP as a clock input.

Next, the operation of the time measuring circuit of the present embodiment will be described. Fig. 2 is a timing chart illustrating the operation of the time measuring circuit.

The D flip-flop circuit 10 receives a 1-bit binary number "1" (1' b1) as a D input, receives an oscillation START signal ROSC _ START as a clock input, receives an oscillation STOP signal ROSC _ STOP as a reset input, and outputs an oscillation permission signal TDC _ EN which becomes active (High) when the oscillation START signal ROSC _ START rises and inactive (Low) when the oscillation STOP signal ROSC _ STOP rises.

The ring oscillator 11a generates a clock TAP [15] having a higher speed than the low-speed clock MCLK during a period in which the oscillation permission signal TDC _ EN outputted from the D flip-flop circuit 10 is active.

The buffer circuit 13 receives the high-speed clock TAP [15] output from the ring oscillator 11a, and outputs a high-speed clock RCLK 1. The inverter 14 outputs a high-speed clock RCLK2 obtained by logically inverting the high-speed clock TAP [15] output from the ring oscillator 11 a. The buffer circuit 13 is inserted to match the phases of the high-speed clocks RCLK1 and RCLK 2.

The OR circuit 15 outputs the result of logical sum of the high-speed clock RCLK1 output from the buffer circuit 13 and the oscillation STOP signal ROSC _ STOP as the high-speed clock ROSC _ CLK 1. The OR circuit 16 outputs the result of logical sum of the high-speed clock RCLK2 output from the inverter 14 and the oscillation STOP signal ROSC _ STOP as the high-speed clock ROSC _ CLK 2.

The edge detection circuit 17 generates a reception permission signal HS _ CNT _ LAT indicating the timing of latching the 8-bit count result HS _ CNT1[8:0] of the high-speed counter 12a and the 8-bit count result HS _ CNT2[8:0] of the high-speed counter 12b, a high-speed counter reset signal HS _ CNT _ CLR for resetting the high-speed counters 12a, 12b, and a reception permission signal HS _ CNT _ EN indicating that data valid for the D flip-flop circuits 18a, 18b is stored, based on the oscillation STOP signal ROSC _ STOP and the low-speed clock MCLK.

Fig. 3 is a circuit diagram showing the configuration of the edge detection circuit 17. The edge detection circuit 17 is configured by a D flip-flop circuit 170, an inverter 171, a D flip-flop circuit 172, a D flip-flop circuit 173, a D flip-flop circuit 174, an XOR circuit 175, a D flip-flop circuit 176, and a D flip-flop circuit 178. The D flip-flop circuit 170 is clocked by an oscillation STOP signal ROSC _ STOP. The inverter 171 takes a signal obtained by inverting the output signal STOP _ DET of the D flip-flop circuit 170 as the D input of the D flip-flop circuit 170. The D flip-flop circuit 172 takes the output signal STOP _ DET of the D flip-flop circuit 170 as a D input and takes the low-speed clock MCLK as a clock input. The D flip-flop circuit 173 takes the output signal of the D flip-flop circuit 172 as the D input and takes the low-speed clock MCLK as the clock input. The D flip-flop circuit 174 has the output signal of the D flip-flop circuit 173 as the D input and the low-speed clock MCLK as the clock input. The XOR circuit 175 outputs the result of exclusive or of the output signal of the D flip-flop circuit 173 and the output signal of the D flip-flop circuit 174 as the charge permission signal HS _ CNT _ LAT. The D flip-flop circuit 176 receives the reception permission signal HS _ CNT _ LAT as an input D, receives the low-speed clock MCLK as a clock input, and outputs the reception permission signal HS _ CNT _ EN. The D flip-flop circuit 178 receives the permission signal HS _ CNT _ LAT as an input D, receives a result of inverting the low-speed clock MCLK as a clock input, and outputs a high-speed counter reset signal HS _ CNT _ CLR.

The High-speed counter 12a counts the rise of the High-speed clock ROSC _ CLK1 while the High-speed counter reset signal HS _ CNT _ CLR is inactive (High), and outputs a 8-bit count result HS _ CNT1[8:0 ]. The High-speed counter 12b counts the rise of the High-speed clock ROSC _ CLK2 while the High-speed counter reset signal HS _ CNT _ CLR is inactive (High), and outputs a 8-bit count result HS _ CNT2[8:0 ]. The count results HS _ CNT1[8:0] and HS _ CNT2[8:0] of the high-speed counters 12a and 12b are initialized to 0 when the high-speed counter reset signal HS _ CNT _ CLR falls.

The D flip-flop circuit 18a latches the 8-bit count result HS _ CNT1[8:0] of the high-speed counter 12a at the rising of the reception permission signal HS _ CNT _ LAT, and holds it until the next rising of the reception permission signal HS _ CNT _ LAT. The D flip-flop circuit 18b latches the 8-bit count result HS _ CNT2[8:0] of the high-speed counter 12b at the rising of the reception permission signal HS _ CNT _ LAT, and holds it until the next rising of the reception permission signal HS _ CNT _ LAT.

The encoder 19 outputs a 5-bit time signal HS _ PHASE [4:0] indicating the PHASE value of the output of the ring oscillator 11a, based on the 16-bit signal ROSC _ PHASE [15:0] output from the D flip-flop circuits 112-1 to 112-16. The time signal HS _ PHASE [4:0] is a signal obtained by encoding a 16-bit signal ROSC _ PHASE [15:0] into 5 bits.

The selector 20 selects, as a true value, the count result obtained by the high-speed counter on which no false signal (count error) is generated among the 8-bit count results LATCH1[8:0] and LATCH2[8:0] latched by the D flip-flop circuits 18a and 18b, based on the 5-bit time signal HS _ PHASE [4:0] output from the encoder 19.

The time calculating unit 21 receives the count result output from the selector 20 at the time point when the reception permission signal HS _ CNT _ EN becomes active (High). The time calculation unit 21 calculates a time interval from the rise of the oscillation START signal ROSC _ START to the rise of the oscillation STOP signal ROSC _ STOP based on the received count result.

Since the ring oscillator 11a STARTs oscillation when the ring oscillator TDC receives the oscillation START signal ROSC _ START indicating the START of measurement, it is sufficient to count the rise of TAP [15] which is the output of the ring oscillator 11a using the high-speed counter until the oscillation STOP signal ROSC _ STOP indicating the STOP of measurement is received.

Therefore, in the present embodiment, the output TAP [15] of the ring oscillator 11a and the inverted signal thereof are counted by the different high-speed counters 12a, 12b, respectively, and the count result on which no false signal is generated is selected from the obtained count results, thereby achieving a low power consumption operation and accurate time measurement.

More specifically, the high-speed clock RCLK1 obtained by passing the high-speed clock TAP [15] output from the ring oscillator 11a through the buffer circuit 13 and the high-speed clock RCLK2 obtained by logically inverting the high-speed clock TAP [15] by the inverter 14 are OR-masked with the oscillation STOP signal ROSC _ STOP in the OR circuits 15 and 16, and the high-speed clocks ROSC _ CLK1 and ROSC _ CLK2 obtained by the OR-masking are counted by the different high-speed counters 12a and 12b, respectively.

The above-described glitch may occur in the timing sequence of receiving the oscillation START signal ROSC _ START, but the PHASE relationship between the rising edge of the oscillation START signal ROSC _ START and the high-speed clocks RCLK1 and RCLK2 can be determined based on the time signal HS _ PHASE [4:0], and therefore, the count result obtained by the high-speed counter in which the glitch is not generated may be selected as the true value.

The relationship between the high-speed clocks RCLK1, RCLK2 and the time signal HS _ PHASE [4:0] is shown in FIG. 4. FIG. 4 shows the boundary between the lowest Low Width (Min Error) that the high-speed counters 12a, 12b cannot accept and the selection of LATCH1[8:0] and LATCH2[8:0] determined from the Min Error. Further, Δ t in FIG. 4 represents a delay time per 1 stage of the delay circuit (the NAND circuit 110 and the buffer circuits 111-1 to 111-15) of the ring oscillator 11 a.

In the present embodiment, the selector 20 selects, as a true value, the count result obtained by the high-speed counter on the side where no false signal (count error) is generated among the 8-bit count results LATCH1[8:0], LATCH2[8:0] latched by the D flip-flop circuits 18a, 18 b. Such selection may be made based on the value of the 5-bit time signal HS _ PHASE [4:0 ].

In the example of fig. 4, the selector 20 selects the count result LATCH1[8:0] in a range from 0 ° (the value of the time signal HS _ PHASE [4:0] is 0) to less than a prescribed 1 st PHASE value (101.25 ° in the present embodiment, the value of the time signal HS _ PHASE [4:0] is 9) of the high-speed clock RCLK1, the 1 st PHASE value being a value less than 180 °.

The selector 20 selects the count result LATCH2[8:0] in a range from the PHASE of the high-speed clock RCLK1 to a value smaller than a predetermined 2 nd PHASE value (281.25 ° in the present embodiment, and 25 as the value of the time signal HS _ PHASE [4:0]), the 2 nd PHASE value being 180 ° or more and smaller than 360 °, and selects the count result LATCH1[8:0] in a range from the PHASE of the high-speed clock RCLK1 to the PHASE value larger than the 2 nd PHASE value and smaller than 360 °.

That is, when any one of the 8-bit count results LATCH1[8:0] and LATCH2[8:0] is selected, the selector 20 selects, as a true value, the count result of the high-speed counter that counts the high-speed clock RCLK1 or RCLK2 whose elapsed time from the fall exceeds the time obtained by adding the predetermined margin width to the lowest Low width (Min Error).

For example, the selector 20 selects the count result LATCH1[8:0] during a period in which the elapsed time from the fall of the high-speed clock RCLK2 is not sufficiently more than the minimum Low width (Min Error) and the elapsed time from the fall of the high-speed clock RCLK1 is sufficiently more than the minimum Low width, and selects the count result LATCH2[8:0] during a period in which the elapsed time from the fall of the high-speed clock RCLK1 is not sufficiently more than the minimum Low width and the elapsed time from the fall of the high-speed clock RCLK2 is sufficiently more than the minimum Low width.

In actual design, the boundary between the range of HS _ PHASE violating the Low width and the selection of LATCH1[8:0] and LATCH2[8:0] is determined based on the data table and circuit layout information of IC (Integrated Circuit) manufacturing company. In the example of fig. 4, the boundary is determined on the premise that the minimum Low width holding period (Min Error) of the clocks of the flip-flops constituting the high-speed counters 12a and 12b is 250ps and the resolution of the TDC is 50 ps.

The glitch generated when the oscillation STOP signal ROSC _ STOP is asynchronously input to the ring oscillator 11a can be avoided by using the high-speed clocks ROSC _ CLK1 and ROSC _ CLK2 obtained by OR masking the high-speed clocks RCLK1 and RCLK2 with the oscillation STOP signal ROSC _ STOP as the clocks of the high-speed counters 12a and 12 b.

In some phase relationships between the high-speed clocks ROSC _ CLK1 and ROSC _ CLK2 and the oscillation STOP signal ROSC _ STOP, the time calculation unit 21 calculates a time interval from the rise of the oscillation START signal ROSC _ START to the rise of the oscillation STOP signal ROSC _ STOP after subtracting 1 from the value of LATCH1[8:0] or LATCH2[8:0 ].

For example, the example of fig. 5 shows a case where the rise of the oscillation STOP signal ROSC _ STOP is received at the time when the value of the time signal HS _ PHASE [4:0] is 0 (the PHASE of the high-speed clock RCLK1 is 0 °). At 101 of FIG. 5, the high speed clock ROSC _ CLK2 generates a glitch. The selector 20 selects the count result LATCH1[8:0] (HS _ CNT1[8:0]) by the above operation. When the value of the time signal HS _ PHASE [4:0] is 0 at the time when the reception permission signal HS _ CNT _ EN becomes active (High), the time calculation unit 21 does not need to subtract 1 from the received count result LATCH1[8:0 ].

The example of fig. 6 shows a case where the rise of the oscillation STOP signal ROSC _ STOP is received at the time when the value of the time signal HS _ PHASE [4:0] is 9 (the PHASE of the high-speed clock RCLK1 is 101.25 °). The selector 20 selects the count result LATCH2[8:0] (HS _ CNT2[8:0]) by the above operation. When the value of the time signal HS _ PHASE [4:0] is 9 at the time when the reception permission signal HS _ CNT _ EN becomes active (High), the time calculation unit 21 calculates the time interval after subtracting 1 from the received count result LATCH2[8:0 ].

The example of fig. 7 shows a case where the rise of the oscillation STOP signal ROSC _ STOP is received at the time when the value of the time signal HS _ PHASE [4:0] is 16 (the PHASE of the high-speed clock RCLK1 is 180 °). At 102 of FIG. 7, the high speed clock ROSC _ CLK1 generates a glitch. The selector 20 selects the count result LATCH2[8:0] (HS _ CNT2[8:0]) by the above operation. When the value of the time signal HS _ PHASE [4:0] at the time when the reception permission signal HS _ CNT _ EN becomes active (High) is 16, the time calculation unit 21 calculates the time interval after subtracting 1 from the received count result LATCH2[8:0 ].

The example of fig. 8 shows a case where the rise of the oscillation STOP signal ROSC _ STOP is received at the time when the value of the time signal HS _ PHASE [4:0] is 25 (the PHASE of the high-speed clock RCLK1 is 281.25 °). The selector 20 selects the count result LATCH1[8:0] (HS _ CNT1[8:0]) by the above operation. When the value of the time signal HS _ PHASE [4:0] at the time point when the reception permission signal HS _ CNT _ EN becomes active (High) is 25, the time calculation unit 21 calculates the time interval after subtracting 1 from the received count result LATCH1[8:0 ].

Fig. 4 shows how the above-described need or lack of correction of the count result is changed to the case of fig. 9. When the count result selected by the selector 20 is received when the phase of the high-speed clock RCLK1 is in the range of not less than the 1 st phase value and less than 360 °, the time calculation unit 21 may calculate the time interval after subtracting 1 from the count result.

In the present embodiment, the number of stages of the delay circuits (the NAND circuit 110 and the buffer circuits 111-1 to 111-15) of the ring oscillator 11a is set to 16 stages (TAP [0] to TAP [15]), but the present invention is not problematic even if the number of stages is 16 or more. However, if the number of stages is a power of 2, the combination of the count values (LATCH1[8:0], LATCH2[8:0]) of the high-speed counters 12a, 12b and the PHASE value (HS _ PHASE [4:0]) of the ring oscillator 11a can be simplified.

For example, the time measurement value in the case where LATCH1[8:0] is selected is obtained by connecting HS _ PHASE to the lower bit side and LATCH1 to the upper bit side like { LATCH1[8:0], HS _ PHASE [4:0 }. A simplified scheme of combination of the count value and the phase value in the case where the number of stages of the ring oscillator 11a is not a power of 2 is described in, for example, japanese patent No. 2868266.

[ example 2]

Next, embodiment 2 of the present invention will be explained. In embodiment 1, the signal RCLK1 obtained by passing the high-speed clock TAP 15 output from the ring oscillator 11a through the buffer circuit 13 and the signal RCLK2 obtained by logically inverting the high-speed clock TAP 15 by the inverter 14 are masked by the oscillation STOP signal ROSC _ STOP, but instead of the inverted signal output from the ring oscillator 11a, a signal which does not mask the high-speed clock TAP 15 output from the ring oscillator 11a and a signal which masks the high-speed clock TAP 15 output from the ring oscillator 11a may be prepared, and the signals may be counted by different high-speed counters, and then the count result obtained by the high-speed counter which does not generate the false signal may be selected.

Fig. 10 is a circuit diagram showing the configuration of the time measuring circuit of the present embodiment, and the same reference numerals are given to the same configurations as those in fig. 1. The time measuring circuit of the present embodiment is composed of a D flip-flop circuit 10, a ring oscillator 11a (oscillation circuit), high-speed counters 12a and 12b (1 st counter and 2 nd counter), an edge detection circuit 17, D flip-flop circuits 18a and 18b, an encoder 19, a selector 20a, a time calculating section 21, and an OR circuit 23 (logic circuit) which outputs a result of logical sum of a high-speed clock ROSC _ CLK1(TAP [15]) output from the ring oscillator 11a and an oscillation STOP signal ROSC _ STOP as a high-speed clock ROSC _ CLK 2.

The configuration and operation of the D flip-flop circuit 10 and the ring oscillator 11a are the same as those described in embodiment 1.

The High-speed counter 12a of the present embodiment counts the rise of the High-speed clock ROSC _ CLK1(TAP [15]) output from the ring oscillator 11a while the High-speed counter reset signal HS _ CNT _ CLR is inactive (High), and outputs a count result HS _ CNT1[8:0] of 8 bits.

On the other hand, the OR circuit 23 outputs the logical sum of the high-speed clock ROSC _ CLK1(TAP [15]) and the oscillation STOP signal ROSC _ STOP as the high-speed clock ROSC _ CLK 2. The High-speed counter 12b counts the rise of the High-speed clock ROSC _ CLK2 while the High-speed counter reset signal HS _ CNT _ CLR is inactive (High), and outputs a 8-bit count result HS _ CNT2[8:0 ].

The operations of the edge detection circuit 17, the D flip-flop circuits 18a and 18b, and the encoder 19 are the same as those described in embodiment 1.

In the present embodiment, the selector 20a also selects, as a true value, the count result obtained by the high-speed counter in which no false signal (count error) is generated among the 8-bit count results LATCH1[8:0] and LATCH2[8:0] latched by the D flip-flop circuits 18a and 18b, but the PHASE of the high-speed clock ROSC _ CLK1(TAP [15]) which is the switching boundary of the selection (the value of the time signal HS _ PHASE [4:0]) is different from that of embodiment 1 because the buffer circuit 13 and the inverter 14 are not used.

The relationship between ROSC _ CLK1(TAP [15]) and the time signals HS _ PHASE [4:0] is shown in FIG. 11. In the example of fig. 11, the selector 20a selects the count result LATCH2[8:0] in a range from 0 ° (0 is the value of the time signal HS _ PHASE [4:0]) to less than a predetermined 1 st PHASE value (123.75 ° in the present embodiment, 11 is the value of the time signal HS _ PHASE [4:0]) of the PHASE of the high-speed clock ROSC _ CLK1(TAP [15]) input to the high-speed counter 12a, and the 1 st PHASE value is a value less than 180 °.

The selector 20a selects the count result LATCH1[8:0] in a range from the PHASE of the high-speed clock ROSC _ CLK1(TAP [15]) being 1 st PHASE value to a value smaller than a predetermined 2 nd PHASE value (303.75 ° in the present embodiment, and 27 being the value of the time signal HS _ PHASE [4:0]), the 2 nd PHASE value being 180 ° or more and smaller than 360 °, and selects the count result LATCH2[8:0] in a range from the PHASE of the high-speed clock ROSC _ CLK1(TAP [15]) being 2 nd PHASE value or more and smaller than 360 °.

In the example of fig. 11, similarly to fig. 4, the boundary is determined on the premise that the minimum Low width holding period (Min Error) of the clocks of the flip-flops constituting the high-speed counters 12a and 12b is 250ps and the resolution of the TDC is 50 ps.

As in embodiment 1, the time calculation unit 21 receives the count result output from the selector 20a when receiving the rise of the permission signal HS _ CNT _ LAT, and calculates the time interval from the rise of the oscillation START signal ROSC _ START to the rise of the oscillation STOP signal ROSC _ STOP.

Thus, the present embodiment can obtain the same effects as those of embodiment 1.

In this embodiment, in some phase relationship between the high-speed clock ROSC _ CLK2 and the oscillation STOP signal ROSC _ STOP, the time calculation unit 21 needs to calculate the time interval from the rise of the oscillation START signal ROSC _ START to the rise of the oscillation STOP signal ROSC _ STOP after subtracting 1 from the value of the count result LATCH1[8:0] or LATCH2[8:0 ].

However, as described above, in the present embodiment, the PHASE of the high-speed clock ROSC _ CLK1(TAP [15]) (the value of the time signal HS _ PHASE [4:0]) that forms the switching boundary of the selection by the selector 20a (TAP [15]) is different from that in embodiment 1, and therefore, the determination as to whether or not to correct the count result is also different from that in embodiment 1.

For example, the example of fig. 12 shows a case where the oscillation STOP signal ROSC _ STOP rises when the time signal HS _ PHASE [4:0] has a value of 0 (the PHASE of ROSC _ CLK1(TAP [15]) is 0 °). At 103 of FIG. 12, the high speed clock ROSC _ CLK1 generates a glitch. The selector 20 selects the count result LATCH2[8:0] (HS _ CNT2[8:0]) by the above operation. When the value of the time signal HS _ PHASE [4:0] is 0 at the time when the reception permission signal HS _ CNT _ EN becomes active (High), the time calculation unit 21 does not need to subtract 1 from the received count result LATCH2[8:0 ].

Fig. 13 shows an example in which the oscillation STOP signal ROSC _ STOP rises when the time signal HS _ PHASE [4:0] has a value of 11 (the PHASE of the high-speed clock ROSC _ CLK1(TAP [15]) is 123.75 °). The selector 20 selects the count result LATCH1[8:0] (HS _ CNT1[8:0]) by the above operation. When the value of the time signal HS _ PHASE [4:0] at the time when the reception permission signal HS _ CNT _ EN becomes active (High) is 11, the time calculation unit 21 calculates the time interval after subtracting 1 from the received count result LATCH1[8:0 ].

The example of fig. 14 shows a case where the oscillation STOP signal ROSC _ STOP is received at the timing when the value of the time signal HS _ PHASE [4:0] is 16 (the PHASE of the high speed clock ROSC _ CLK1(TAP [15]) is 180 °). At 104 of FIG. 14, the high speed clock ROSC _ CLK2 generates a glitch. The selector 20 selects the count result LATCH1[8:0] (HS _ CNT1[8:0]) by the above operation. When the value of the time signal HS _ PHASE [4:0] at the time when the reception permission signal HS _ CNT _ EN becomes active (High) is 16, the time calculation unit 21 calculates the time interval after subtracting 1 from the received count result LATCH1[8:0 ].

The example of fig. 15 shows a case where the oscillation STOP signal ROSC _ STOP rises when the time signal HS _ PHASE [4:0] has a value of 27 (the PHASE of the high speed clock ROSC _ CLK1(TAP [15]) is 303.75 °). The selector 20 selects the count result LATCH2[8:0] (HS _ CNT2[8:0]) by the above operation. When the value of the time signal HS _ PHASE [4:0] at the time when the reception permission signal HS _ CNT _ EN becomes active (High) is 27, the time calculation unit 21 calculates the time interval after subtracting 1 from the received count result LATCH2[8:0 ].

Fig. 11 shows how the above-described need or lack of correction of the count result is changed to the case of fig. 16. As in embodiment 1, when the count result selected by the selector 20 is received when the phase of the high-speed clock RCLK1 is in the range of not less than 1 st phase value and less than 360 °, the time calculation unit 21 may calculate the time interval after subtracting 1 from the count result.

[ example 3 ]

Next, embodiment 3 of the present invention will be explained. Fig. 17 is a circuit diagram showing the configuration of the time measurement circuit of the present embodiment, and the same reference numerals are given to the same configurations as those in fig. 1 and 10. The time measuring circuit of the present embodiment includes a D flip-flop circuit 10, a ring oscillator 11a (oscillation circuit), high-speed counters 12a and 12b (1 st counter and 2 nd counter), a buffer circuit 13, an inverter 14, an edge detection circuit 17a, D flip-flop circuits 18a and 18b, an encoder 19, a selector 20, a time calculating unit 21a, and an operation setting circuit 24, the operation setting circuit 24 selects and outputs an oscillation START signal ROSC _ START (1 st START signal) and an oscillation STOP signal ROSC _ STOP (1 st STOP signal) which are input from the outside at ordinary times, a START signal DBG _ START (2 nd START signal) and a STOP signal DBG _ STOP (2 nd STOP signal) outputted from a test execution unit described later are selected and outputted when a test is executed, and outputs a stop signal ROSC _ STOPb (3 rd stop signal) at the end of the test.

Further, the time measurement circuit of the present embodiment includes: a mask release timing control circuit 25 that generates, when the test is performed, a stop signal for masking the high-speed clock RCLK1 later than the high-speed clock RCLK2 and releasing the masking later than the high-speed clock RCLK2 and a stop signal for masking the high-speed clock RCLK2 earlier than the high-speed clock RCLK1 and releasing the masking earlier than the high-speed clock RCLK1, based on a stop signal ROSC _ STOPa output from the action setting circuit 24; an OR circuit 26 that outputs the logical sum of the high-speed clock RCLK1 and the stop signal output from the mask release timing control circuit 25 as a high-speed clock ROSC _ CLK 1; and an OR circuit 27 that outputs the result of logical sum of the high-speed clock RCLK2 and the stop signal output from the mask release timing control circuit 25 as the high-speed clock ROSC _ CLK 2.

The buffer circuit 13, the inverter 14, the mask release timing control circuit 25, and the OR circuits 26 and 27 constitute a logic circuit 28.

As shown in fig. 17, this embodiment is obtained by adding an operation setting circuit 24, a mask release time control circuit 25, and OR circuits 26 and 27 to embodiment 1, wherein the operation setting circuit 24 can START the ring oscillator 11a based on START and STOP signals (DBG _ START, DBG _ STOP) from the time measuring circuit 21a, and the mask release time control circuit 25 controls mask release times of the high-speed clocks RCLK1 and RCLK 2.

Fig. 18 is a circuit diagram showing the configuration of the operation setting circuit 24. Fig. 19 is a circuit diagram showing the configuration of the mask release timing control circuit 25. As shown in fig. 18, the operation setting circuit 24 includes a selector 240, a selector 241, AND an AND circuit 242. The selector 240 selects one of the oscillation STOP signal ROSC _ STOP and the STOP signal DBG _ STOP output from the time calculation unit 21a based on the selection instruction signal ROSC _ SEL output from the time calculation unit 21a, and outputs the selected signal as the STOP signal ROSC _ STOP. The selector 241 selects either one of the oscillation START signal ROSC _ START and the START signal DBG _ START output from the time calculation unit 21a based on the selection instruction signal ROSC _ SEL, and outputs the selected signal as the START signal ROSC _ START. The AND circuit 242 outputs a result of a negative logical product of the stop signal ROSC _ STOPa output from the selector 240 AND the TEST instruction signal ROSC _ TEST output from the time calculation unit 21a as the stop signal ROSC _ STOPb.

The D flip-flop circuit 10 of the present embodiment is clocked by a START signal ROSC _ START output from the operation setting circuit 24 instead of the oscillation START signal ROSC _ START, and is reset by a STOP signal ROSC _ STOP output from the operation setting circuit 24 instead of the oscillation STOP signal ROSC _ STOP.

The D flip-flop circuits 112-1 to 112-16 of the ring oscillator 11a of the present embodiment are clocked by the STOP signal ROSC _ STOPb instead of the oscillation STOP signal ROSC _ STOP.

The edge detection circuit 17a of the present embodiment receives the STOP signal ROSC _ STOPa instead of the oscillation STOP signal ROSC _ STOP, and generates a reception permission signal HS _ CNT _ LAT which becomes effective (High) when the Low-speed clock MCLK immediately after the STOP signal ROSC _ STOPa rises, a High-speed counter reset signal HS _ CNT _ CLR which becomes effective (Low) when the reception permission signal HS _ CNT _ LAT falls, and a reception permission signal HS _ CNT _ EN which is obtained by delaying the oscillation STOP signal ROSC _ STOPa by 1/2 clocks of the Low-speed clock MCLK, based on the STOP signal ROSC _ STOPa, the Low-speed clock MCLK, and the TEST instruction signal ROSC _ TEST.

Fig. 20 is a block diagram showing the configuration of the time calculation unit 21a according to the present embodiment. The time calculation unit 200 realizes the same functions as the time calculation unit 21 of embodiments 1 and 2. The test execution unit 201 performs a test of the delay circuits (the NAND circuit 110 and the buffer circuits 111-1 to 111-15) of the ring oscillator 11 a.

Next, the operation of the time measuring circuit of the present embodiment will be described. Fig. 21 is a timing chart illustrating an operation at the time of testing of the time measurement circuit according to the present embodiment.

When the TEST is executed, the TEST execution unit 201 sets the TEST instruction signal ROSC _ TEST to an active High level and sets the selection instruction signal ROSC _ SEL to a High level, for example, as shown in fig. 21, in accordance with an instruction from the user.

Since the selection instruction signal ROSC _ SEL is at a High level, the selector 240 of the operation setting circuit 24 selects the oscillation STOP signal ROSC _ STOP and the STOP signal DBG _ STOP output from the test execution unit 201, and outputs the STOP signal DBG _ STOP as the STOP signal ROSC _ STOP.

Since the selection instruction signal ROSC _ SEL is at a High level, the selector 241 of the operation setting circuit 24 selects the oscillation START signal ROSC _ START and the START signal DBG _ START of the START signal DBG _ START output from the test execution section 201 to output as the START signal ROSC _ START.

The AND circuit 242 of the operation setting circuit 24 outputs a result of negation of the stop signal ROSC _ STOPa output from the selector 240 AND the TEST instruction signal ROSC _ TEST output from the TEST execution unit 201 as the stop signal ROSC _ STOPb. As a result, the stop signal ROSC _ STOPb is inactive (Low) during the period in which the TEST instruction signal ROSC _ TEST is at the High level during the TEST. Further, for example, when the TEST instruction signal ROSC _ TEST becomes Low after the TEST is ended in accordance with an instruction from the user, the STOP signal ROSC _ STOP becomes effective (High) at the time point when the STOP signal DBG _ STOP rises.

Therefore, the D flip-flop circuit 10 sets the oscillation permission signal TDC _ EN to active (High) when the first START signal ROSC _ START (DBG _ START) under test rises, and sets the oscillation permission signal TDC _ EN to inactive (Low) when the stop signal ROSC _ stop rises, and therefore the ring oscillator 11a operates so as to be free-running during the period in which the oscillation permission signal TDC _ EN is active (High).

At normal times, the TEST instruction signal ROSC _ TEST becomes Low, and when the oscillation STOP signal ROSC _ STOP is input, the oscillation STOP signal ROSC _ STOP is output as a STOP signal ROSC _ STOP.

When the test is executed, the test execution section 201 periodically issues the STOP signal DBG _ STOP in synchronization with the low-speed clock MCLK, but the ring oscillator 11a does not STOP even if the STOP signal DBG _ STOP becomes High level.

Then, the test execution unit 201 acquires a 5-bit time signal HS _ PHASE [4:0] output from the encoder 19 at the time of rising of the STOP signal DBG _ STOP, and acquires 8-bit count results LATCH1[8:0] and LATCH2[8:0] latched by the D flip-flop circuits 18a and 18b from the value of the time signal HS _ PHASE [4:0 ].

Since the frequency of the ring oscillator 11a is not constant and is not synchronized with the low-speed clock MCLK, even if the test execution section 201 periodically acquires the time signal HS _ PHASE [4:0], the acquired value changes randomly.

The test execution unit 201 acquires and compares the count results LATCH1[8:0] and LATCH2[8:0] when the PHASE of the high-speed clock RCLK1 is a value (the value of the time signal HS _ PHASE [4:0] is 8) immediately before the 1 st PHASE value (101.25 °, the value of the time signal HS _ PHASE [4:0] is 9) based on the value of the time signal HS _ PHASE [4:0 ]. In addition, the test execution section 201 may also acquire and compare the count results LATCH1[8:0], LATCH2[8:0] when the phase of the high-speed clock RCLK1 is the 1 st phase value. Further, the test execution section 201 may also acquire and compare the count results LATCH1[8:0], LATCH2[8:0] when the PHASE of the high-speed clock RCLK1 is a value immediately after the 1 st PHASE value (the value of the time signal HS _ PHASE [4:0] is 10). In fig. 21, Phase1 indicates these times.

Further, the test execution section 201 acquires and compares the count results LATCH1[8:0] and LATCH2[8:0] when the PHASE of the high-speed clock RCLK1 is a value (the value of the time signal HS _ PHASE [4:0] is 24) immediately before the 2 nd PHASE value (281.25 °, the value of the time signal HS _ PHASE [4:0] is 25). In addition, the test execution section 201 may also acquire and compare the count results LATCH1[8:0], LATCH2[8:0] when the phase of the high-speed clock RCLK1 is the 2 nd phase value. Further, the test execution section 201 may also acquire and compare the count results LATCH1[8:0], LATCH2[8:0] when the PHASE of the high-speed clock RCLK1 is a value immediately after the 2 nd PHASE value (the value of the time signal HS _ PHASE [4:0] is 26). In fig. 21, Phase2 indicates these times.

At the time of these phases 1, 2, the values of the count results LATCH1[8:0] and LATCH2[8:0] should be count values that do not violate the Low width in the high-speed counters 12a, 12b, and therefore the test execution unit 201 compares the count results LATCH1[8:0] and LATCH2[8:0] acquired at the time of Phase1, and similarly compares the count results LATCH1[8:0] and LATCH2[8:0] acquired at the time of Phase 2.

Then, when the count result LATCH1[8:0] matches LATCH2[8:0], the test execution unit 201 determines that the delay circuits (the NAND circuit 110 and the buffer circuits 111-1 to 111-15) of the ring oscillator 11a are normal, and when the count result LATCH1[8:0] does not match LATCH2[8:0], the test execution unit 201 determines that a failure has occurred in the delay circuits. As a method of outputting the determination result, for example, a method of displaying the content of informing the determination result or a method of transmitting information informing the determination result to the outside is available.

Since the high-speed clocks RCLK1 and RCLK2 are out of phase with the oscillation STOP signal ROSC _ STOP, the mask release timing based on the oscillation STOP signal ROSC _ STOP needs to be controlled by the mask release timing control circuit 25 when the test as in this embodiment is performed.

As shown in fig. 19, the mask release timing control circuit 25 includes an AND circuit 250, an AND circuit 251, a D flip-flop circuit 252, a D flip-flop circuit 253, AND a D flip-flop circuit 254. The AND circuit 250 outputs the result of the logical product of the high-speed clock RCLK1 output from the buffer circuit 13 AND the TEST instruction signal ROSC _ TEST output from the time calculation unit 21 a. The AND circuit 251 outputs the result of the logical product of the high-speed clock RCLK2 output from the inverter 14 AND the TEST instruction signal ROSC _ TEST. The D flip-flop circuit 252 receives the stop signal ROSC _ STOPa output from the operation setting circuit 24 as a D input, AND receives an output of the AND circuit 251 as a clock input. The D flip-flop circuit 253 takes the output STOP _ RCLK2_ D1 of the D flip-flop circuit 252 as a D input and takes the STOP signal ROSC _ STOPa as a clock input. The D flip-flop circuit 254 takes the output STOP _ RCLK2_ D2 of the D flip-flop circuit 253 as a D input, AND takes the output of the AND circuit 250 as a clock input.

The OR circuit 26 outputs the high-speed clock RCLK1, the result of the logical sum of the output STOP _ RCLK1_ D3 (4 th STOP signal) of the D flip-flop circuit 254 of the mask release timing control circuit 25, and the STOP signal ROSC _ STOPa as the high-speed clock ROSC _ CLK 1.

The OR circuit 27 outputs the result of logical sum of the high-speed clock RCLK2, the output STOP _ RCLK2_ D2 (5 th STOP signal) of the D flip-flop circuit 253 of the mask release timing control circuit 25, and the STOP signal ROSC _ STOPa as the high-speed clock ROSC _ CLK 2.

Fig. 22 is a timing chart for explaining the operation of the mask release timing control circuit 25. Further, FIG. 22 shows the case where the value of the time signal HS _ PHASE [4:0] is 24 or 25. The ring oscillator 11a, the buffer circuit 13, and the inverter 14 according to embodiments 1 to 3 operate to alternately raise the High-speed clocks RCLK2 and RCLK1 as the rise of the High-speed clock RCLK2 → the rise of the High-speed clock RCLK1 → the rise of the High-speed clock RCLK2 → the rise of the High-speed clock RCLK1 when the oscillation permission signal TDC _ EN becomes active (High).

Therefore, as shown at 105 in fig. 22, at the start of the operation, the high-speed counter 12b (HS _ CNT2[8:0]) and the high-speed counter 12a (HS _ CNT1[8:0]) start count-up in this order. Therefore, at the time of mask release, the timing of mask release is also controlled in the order of rising of high-speed clock RCLK2 → rising of high-speed clock RCLK1 → rising of high-speed clock RCLK2 → rising of high-speed clock RCLK1 as in the timing chart of fig. 22.

STOP _ RCLK2_ D1 of fig. 22 represents the output of the D flip-flop circuit 252, STOP _ RCLK2_ D2 represents the output of the D flip-flop circuit 253, and STOP _ RCLK1_ D3 represents the output of the D flip-flop circuit 254. The output STOP _ RCLK2_ D2 of the D flip-flop circuit 253 is used for masking of the high-speed clock RCLK2 in the OR circuit 27. Further, the output STOP _ RCLK1_ D3 of the D flip-flop circuit 254 is used for masking of the high-speed clock RCLK1 in the OR circuit 26.

As described above, since the output STOP _ RCLK2_ D2 of the D flip-flop circuit 253 falls before the output STOP _ RCLK1_ D3 of the D flip-flop circuit 254 and the high-speed clock RCLK2 releases the masking before the high-speed clock RCLK1, the count-up is restored in the order of the high-speed counter 12b (HS _ CNT2[8:0]) and the high-speed counter 12a (HS _ CNT1[8:0]) even at the time of releasing the masking, as shown at 106 in fig. 22.

In the present embodiment, as described above, the count results LATCH1[8:0] and LATCH2[8:0] are compared at the timings of Phase1, Phase2, and when the value of the timing signal HS _ Phase [4:0] is 24, 25, or 26 (when the Phase of the high-speed clock RCLK1 is a value immediately before the 2 nd Phase value, or a value immediately after the 2 nd Phase value), if the delay circuit of the ring oscillator 11a is not failed, the count results LATCH1[8:0] and LATCH2[8:0] are surely matched as shown at 107 in fig. 22.

On the other hand, when the value of the time signal HS _ PHASE [4:0] is 8, 9, or 10 (when the PHASE of the high-speed clock RCLK1 is a value immediately before the 1 st PHASE value, a 1 st PHASE value, or a value immediately after the 1 st PHASE value), the count value of one of the latches 2[8:0] is 1 greater than the count result LATCH1[8:0] because the high-speed clock ROSC _ CLK2 rises 1 times more than the ROSC _ CLK1 as shown in fig. 23 at 108.

Therefore, when the value of the time signal HS _ PHASE [4:0] is 8, 9, or 10, the test execution unit 201 compares the count result LATCH1[8:0] with the LATCH2[8:0] after the subtraction after subtracting 1 from the count result LATCH2[8:0], determines that the delay circuit of the ring oscillator 11a is normal when the count result LATCH1[8:0] matches the LATCH2[8:0], and determines that the delay circuit has failed when the count result LATCH1[8:0] does not match the LATCH2[8:0 ].

The normal operation is the same as in embodiment 1. As described above, since the TEST instruction signal ROSC _ TEST is at the High level when the TEST is executed, the AND circuits 250 AND 251 of the mask release timing control circuit 25 enable the operation of the mask release timing control circuit 25. On the other hand, since the TEST instruction signal ROSC _ TEST is at a Low level at ordinary times, the operation of the mask release timing control circuit 25 becomes invalid (the outputs of the AND circuits 250 AND 251 are always at a Low level).

At normal times, the OR circuit 26 outputs the logical sum of the high-speed clock RCLK1 output from the buffer circuit 13 and the STOP signal ROSC _ STOPa (ROSC _ STOP) as the high-speed clock ROSC _ CLK1, similarly to the OR circuit 15 of embodiment 1. The OR circuit 27 outputs the logical sum of the high-speed clock RCLK2 output from the inverter 14 and the STOP signal ROSC _ stopp (ROSC _ STOP) as the high-speed clock ROSC _ CLK2, similarly to the OR circuit 16.

By using the self-test function of the present embodiment, it is not necessary to select a tester capable of controlling the distance between the oscillation START signal ROSC _ START and the oscillation STOP signal ROSC _ STOP at a resolution of several tens of ps as a tester for IC factory inspection, and the test can be performed without inputting the oscillation START signal ROSC _ START and the oscillation STOP signal ROSC _ STOP from the outside, so that the test time of the IC mounted with the time measurement circuit can be shortened. As a result, the present embodiment can contribute to cost reduction of the IC.

The time calculating units 21 and 21a of the time measuring circuits described in embodiments 1 to 3 can be realized by a computer having a cpu (central Processing unit), a storage device, and an interface, and a program for controlling these hardware resources. The configuration of the computer is illustrated in fig. 24. The computer includes a CPU 300, a storage device 301, and an interface device (hereinafter, abbreviated as I/F) 302. The selector 20, the edge detection circuits 17, 17a, the D flip-flop circuits 18a, 18b, the encoder 19, the operation setting circuit 24, and the mask release timing control circuit 25 are connected to the I/F302. In such a computer, a program for implementing the present invention is stored in the storage device 301. The CPU 300 executes the processing described in embodiments 1 to 3 in accordance with the program stored in the storage device 301.

Industrial applicability

The invention can be applied to the technology for measuring psec time.

Description of the symbols

10. 18a, 18b, 112-1 to 112-16, 252 to 254 … D flip-flop circuits, 11a … ring oscillators, 12a, 12b … high-speed counters, 13, 111-1 to 111-15 … buffer circuits, 14 … inverters, 15, 16, 2326, 27 … OR circuits, 17a … edge detection circuits, 19 … encoders, 20a, 240, 241 … selectors, 21a, 200 … time calculation sections, 22, 28 … logic circuits, 24 … operation setting circuits, 25 … mask release time control circuits, 110 … NAND circuits, 201 … test execution sections, 242, 250, 251 … AND circuits.

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