阅读说明：本技术 页表结构 (Page table structure ) 是由 A·L·桑德伯格 S·迪斯特尔霍斯特 于 2020-01-03 设计创作，主要内容包括：本发明公开了一种用于地址转译的页表结构,该页表结构可包括相对类型页表条目,对于该相对类型页表条目,可使用相对偏移值来指定到下一层级页表条目或经转译地址的地址指针,该相对偏移值指示该地址指针相对于参考点基地址的偏移。(A page table structure for address translation may include a relative type page table entry for which an address pointer to a next level page table entry or translated address may be specified using a relative offset value indicating an offset of the address pointer from a reference point base address.)

1. An apparatus, comprising:

memory management circuitry to translate a memory address based on page table entries defined in a page table structure, the page table structure comprising a plurality of page table levels stored in a memory system; and

page table walk circuitry to obtain the page table entries from the page table structure for use by the memory management circuitry, each page table entry identifying an address pointer to identify one of: a translated address and an address of a sub page table at a next level of the page table structure; wherein:

when a given page table entry is a relative type page table entry that is a relative offset value indicating an offset of the address pointer relative to a reference point base address determined for the given page table entry, the page table walk circuitry is configured to determine the address pointer from the reference point base address and the relative offset value.

2. The apparatus of claim 1, wherein when the given page table entry is an absolute type page table entry specifying an absolute address value that directly specifies the address pointer, the page table walk circuitry is configured to determine the address pointer from the absolute address value.

3. The apparatus of claim 2, wherein the page table walk circuitry is configured to determine whether the given page table entry is the relative type or the absolute type based on a type indicator specified in a parent page table entry at a previous level of the page table structure.

4. The apparatus of any one of claims 2 and 3, wherein the page table walk circuitry is configured to signal a fault in response to detecting that a sub-page table entry of the given page table entry is of the absolute type when the given page table entry is of the relative type.

5. The apparatus of any one of claims 2 to 4, wherein a top level page table entry of the page table structure is restricted to the absolute type page table entry.

6. The apparatus of any preceding claim, wherein a leaf page table entry for which the address pointer identifies the translated address is allowed to be the relative type page table entry.

7. The apparatus of any of the preceding claims, wherein the page table walk circuitry is configured to determine a size-aligned address as the reference point base address of the given page table entry, the size-aligned address corresponding to a result of aligning an address of a page table that includes the given page table entry with an address size boundary selected based on a size parameter specified for the given page table entry by a parent page table entry of the given page table entry.

8. The apparatus of any one of claims 1 to 6, wherein the page table walk circuitry is configured to obtain the reference point base address of the given page table entry from a selected entry of a block table, the selected entry of the block table selected based on a block table entry identifier specified in a parent page table entry of the given page table entry.

9. The apparatus of any of the preceding claims, wherein the relative type page table entry is associated with a size parameter, the reference point base address and the size parameter together identifying a bounding address region of the address pointer specified by the relative type page table entry.

10. The apparatus of claim 9, wherein when the given page table entry is the relative type page table entry, the page table walk circuit is configured to signal a fault when the address pointer specified by a descendant page table entry of the given page table entry is outside the boundary address region identified for the given page table entry.

11. The apparatus of any of claims 9 and 10, wherein the size parameter is specified directly in a parent page table entry of the relative type page table entry.

12. The apparatus of any one of claims 9 and 10, wherein the size parameter is specified in a selected entry of a block table, the selected entry of the block table selected based on a block table entry identifier specified in a parent page table entry of the relative type page table entry.

13. The apparatus of claim 7, wherein when the given page table entry is the relative type page table entry, the page table walk circuitry is configured to signal a fault when the size parameter identified for a sub-page table entry of the given page table entry indicates a size larger than the size parameter associated with the given page table entry.

14. A method, comprising:

performing a page table walk to obtain page table entries from a page table structure for translating a memory address, the page table structure comprising a plurality of page table levels stored in a memory system, each page table entry identifying an address pointer for identifying one of: a translated address and an address of a sub page table at a next level of the page table structure; wherein:

when a given page table entry is a relative type page table entry that is a relative offset value that indicates an offset of the address pointer relative to a reference point base address determined for the given page table entry, determining the address pointer from the reference point base address and the relative offset value.

15. A computer program, comprising:

page table walk program logic to obtain page table entries from a page table structure, the page table structure comprising a plurality of page table levels, each page table entry identifying an address pointer to identify one of: a translated address and an address of a sub page table at a next level of the page table structure; wherein:

when a given page table entry is a relative type page table entry that is a relative offset value that indicates an offset of the address pointer relative to a reference point base address determined for the given page table entry, the page table walk program logic is configured to determine the address pointer from the reference point base address and the relative offset value.

16. A storage medium storing the computer program according to claim 15.

17. An apparatus, comprising:

memory management circuitry to translate a memory address based on page table entries defined in a page table structure, the page table structure comprising a plurality of page table levels stored in a memory system; and

page table walk circuitry to obtain the page table entries from the page table structure for use by the memory management circuitry, each page table entry identifying an address pointer to identify one of: a translated address and an address of a sub page table at a next level of the page table structure; wherein:

when a given page table entry specifies a descendant entry restricted indicator, the page table walk circuitry is configured to signal a fault when a descendant page table entry of the given page table entry identifies an address pointer that is outside a boundary address region identified by the given page table entry.

18. The apparatus of claim 17, wherein the boundary address region comprises a specified size region starting from a reference point base address;

the given page table entry specifies a size parameter, the size parameter indicating the specified size.

19. The apparatus of claim 18, wherein the reference point base address comprises a size-aligned address corresponding to a result of aligning an address of a page table that includes a sub-page table entry of the given page table entry with an address size boundary selected based on the size parameter.

20. The apparatus of claim 17, wherein the given page table entry specifies a block table entry identifier that identifies an entry of a block table that specifies a reference point base address and a size of the boundary address region.

21. A method, comprising:

performing a page table walk to obtain page table entries from a page table structure for translating a memory address, the page table structure comprising a plurality of page table levels stored in a memory system, each page table entry identifying an address pointer for identifying one of: a translated address and an address of a sub page table at a next level of the page table structure;

signaling a fault in response to detecting that a given page table entry specifies a descendant entry limit indicator and that a descendant page table entry of the given page table entry identifies an address pointer that is outside a boundary address region identified by the given page table entry.

22. A computer program, comprising:

page table walk program logic to obtain page table entries from a page table structure, the page table structure comprising a plurality of page table levels, each page table entry identifying an address pointer to identify one of: a translated address and an address of a sub page table at a next level of the page table structure; wherein:

when a given page table entry specifies a descendant entry restricted indicator, the page table walk program logic is configured to signal a fault when a descendant page table entry of the given page table entry identifies an address pointer that is outside a bounding address region identified by the given page table entry.

23. A storage medium storing a computer program according to claim 22.