阅读说明：本技术 具有逻辑瓦片的虚拟阵列的fpga及其配置和操作的方法 (The method of the FPGA and its configuration and operation of virtual array with Logical tile ) 是由 A·科扎祖克 成·C·王 A·M·阿布雅卡尔 于 2018-05-09 设计创作，主要内容包括：一种集成电路,包括逻辑瓦片的物理阵列,其中,每个逻辑瓦片包括周边和多个外部I/O,所述多个外部I/O设置在逻辑瓦片的周边上的布局中,其中,每个逻辑瓦片的外部I/O的布局是相同的。物理阵列包括逻辑瓦片的第一虚拟阵列,该第一虚拟阵列被编程为执行数据处理操作、包括物理阵列的第一多个逻辑瓦片。物理阵列还包括逻辑瓦片的第二虚拟阵列,该第二虚拟阵列被编程为执行第二操作、包括物理阵列的第二多个逻辑瓦片。第二多个逻辑瓦片与第一多个逻辑瓦片不同。在一个实施例中,第一虚拟阵列的数据处理操作的执行独立于第二虚拟阵列的第二操作的执行。(A kind of integrated circuit, the physical array including Logical tile, wherein, each Logical tile includes periphery and multiple exterior I/O, the multiple exterior I/O is arranged in the layout on the periphery of Logical tile, wherein exterior I/O layout of each Logical tile is identical.Physical array includes the first virtual array of Logical tile, which is programmed to execute data processing operation, more than first including physical array a Logical tiles.Physical array further includes the second virtual array of Logical tile, which is programmed to execute the second operation, more than second including physical array a Logical tiles.A Logical tile more than second is different from more than first a Logical tiles.In one embodiment, execution of the execution of the data processing operation of the first virtual array independently of the second operation of the second virtual array.)

1. a kind of integrated circuit, comprising:

Programmable/configurable logic circuit system with periphery, the programmable/configurable logic circuit system include:

The physical array of Logical tile, wherein each Logical tile in the physical array of the Logical tile includes being arranged in Multiple exterior I/O in public layout on the periphery of Logical tile, wherein the physical array of Logical tile include:

First virtual array of Logical tile, first virtual array have periphery and the physical array including Logical tile More than first a Logical tiles, wherein in operation, the first virtual array of Logical tile be programmed to execute data processing behaviour Make, wherein more than first a Logical tiles of the first virtual array of Logical tile include:

The first Logical tile with periphery, the periphery include:

The first part on periphery forms at least part of the periphery of programmable/configurable logic circuit system, wherein be located at Exterior I/O in the first part on the periphery of the first Logical tile be exterior I/O of first virtual array of (a) Logical tile with And (b) be configured as being directly connected to the circuit system outside the physical array of Logical tile, and

The second part on periphery, in the inside of the periphery of the first virtual array of Logical tile, wherein being located at the first Logical tile Periphery second part on exterior I/O be the first virtual array virtual i/o；And

Second virtual array of Logical tile, second virtual array have physical array peripheral, including Logical tile A Logical tile more than second, wherein each Logical tile more than second in a Logical tile be in more than first a Logical tiles The different Logical tile of Logical tile, and wherein, in operation, the second virtual array of Logical tile is programmed to execute Second operation, and wherein more than second a Logical tiles of the second virtual array of Logical tile include:

One or more Logical tiles with periphery, the periphery include:

The first part on periphery forms at least part of the periphery of programmable/configurable logic circuit system, wherein be located at Exterior I/O in the first part on the periphery of one or more Logical tiles be (a) second virtual array external l/O and (b) it is configured as being directly connected to the circuit system outside the physical array of Logical tile, and

The second part on periphery, positioned at Logical tile the second virtual array periphery inside and with the first Logical tile The second part on periphery is adjacent, wherein exterior I/O on the second part on the periphery of one or more logics is (a) It the virtual i/o of two virtual arrays and (b) is configured as being directly connected to the virtual i/o of the first virtual array.

2. integrated circuit according to claim 1, in which:

First virtual array of Logical tile is received the first clock signal and is executed at data using first clock signal Reason operation, and

Second virtual array of Logical tile receives second clock signal and executes the second behaviour using the second clock signal Make, and wherein the first clock signal is different from second clock signal.

3. integrated circuit according to claim 1, in which:

More than first a Logical tiles of the first virtual array of Logical tile are the continuous logics watt of the physical array of Logical tile Piece.

4. integrated circuit according to claim 1, in which:

A Logical tile more than the first of first virtual array is made of the whole column or row Logical tile of the physical array of Logical tile.

5. integrated circuit according to claim 1, in which:

First virtual array of Logical tile is substantially made of microcontroller.

6. integrated circuit according to claim 1, in which:

At least one Logical tile of first virtual array of Logical tile includes:

Periphery, the periphery form at least part of the periphery of programmable/configurable logic circuit system, wherein being located at this extremely Multiple external l/O on the periphery of a few Logical tile are directly to the first virtual array of the Logical tile of memory Exterior I/O, and

Circuit system can be configured to via exterior I/O first part on the periphery for being located at least one Logical tile Data are written from memory read data and to memory.

7. integrated circuit according to claim 1, in which:

In operation, second void of the execution of the data processing operation of the first virtual array of Logical tile independently of Logical tile The execution of second operation of matroid column.

8. integrated circuit according to claim 1, in which:

Each Logical tile in the physical array of Logical tile includes interference networks, which includes in Logical tile Multiple multiplexers.

9. integrated circuit according to claim 8, in which:

The interference networks in each Logical tile in second virtual array of Logical tile are interconnected to via mesh interconnection network Another Logical tile in second virtual array of Logical tile.

10. a kind of method for the field programmable gate array for configuring integrated circuit, the field programmable gate array includes that (i) is deposited The memory and (ii) that store up data have programmable/configurable logic circuit system of periphery, the programmable/configurable logic Circuit system includes the physical array of Logical tile, wherein each Logical tile in the physical array of Logical tile includes week Side and multiple exterior I/O, the multiple exterior I/O are arranged in the layout on the periphery of Logical tile, wherein each logic watt Exterior I/O layout of piece is identical, which comprises

Read configuration data stored in memory, wherein the configuration data includes the first configuration data and the second configuration Data；

Configuration data is applied to the physical array of Logical tile with the Logical tile configuration in the physical array by Logical tile At one or more scheduled configurations, comprising:

First configuration data is applied to more than first a Logical tiles in the physical array of Logical tile to configure Logical tile The first virtual array, wherein the first virtual array of Logical tile include more than first a Logical tiles, to execute the first data Processing operation, and

Second configuration data is applied to more than second a Logical tiles in the physical array of Logical tile to configure Logical tile The second virtual array, wherein the second virtual array of Logical tile include more than second a Logical tiles, to execute the second data Processing operation；And

Wherein, in operation, the first virtual array of Logical tile executes second independently of the second virtual array of Logical tile Data processing operation and execute the first data processing operation.

11. according to the method described in claim 10, wherein:

Configuration data is applied to the Logical tile in physical array of the physical array of Logical tile to configure Logical tile also Including composite bit stream is applied to more than first a Logical tiles and more than second a Logical tiles, wherein composite bit stream includes First configuration data and the second configuration data.

12. according to the method for claim 11, in which:

First configuration data is encryption data.

13. according to the method described in claim 10, wherein:

Configuration data is applied to the Logical tile in physical array of the physical array of Logical tile to configure Logical tile also Including discretely:

First bit stream is applied to more than first a Logical tiles, wherein the first bit stream includes the first configuration data, and

Second bit stream is applied to more than second a Logical tiles, wherein the second bit stream includes the second configuration data.

14. according to the method for claim 13, in which:

First configuration data is encryption data.

15. according to the method described in claim 10, further include:

In memory by configuration data storage.

16. according to the method described in claim 10, wherein:

Configuration data is applied to the Logical tile in physical array of the physical array of Logical tile to configure Logical tile also Including reading configuration data from memory.

17. a kind of integrated circuit, comprising:

Programmable/configurable logic circuit system with periphery, the programmable/configurable logic circuit system includes logic The physical array of tile, wherein each Logical tile in the physical array of Logical tile includes periphery and multiple exterior I/O, The multiple exterior I/O is arranged in the layout on the periphery of Logical tile, wherein exterior I/O cloth of each Logical tile Office is identical, wherein the physical array of Logical tile includes:

First virtual array of Logical tile, first virtual array have periphery and the physical array including Logical tile More than first a Logical tiles, wherein in operation, the first virtual array of Logical tile be programmed to execute data processing behaviour Make；And

Second virtual array of Logical tile, second virtual array have physical array peripheral, including Logical tile A Logical tile more than second, wherein each Logical tile more than second in a Logical tile be in more than first a Logical tiles The different Logical tile of Logical tile, and wherein, in operation, the second virtual array of Logical tile is programmed to execute Second operation；And

Wherein, in operation, the execution of the data processing operation of the first virtual array of Logical tile is independently of Logical tile The execution of second operation of the second virtual array.

18. integrated circuit according to claim 17, in which:

More than first a Logical tiles of the first virtual array of Logical tile are the continuous logics watt of the physical array of Logical tile Piece.

19. integrated circuit according to claim 17, in which:

A Logical tile more than the first of first virtual array is made of the whole column or row Logical tile of the physical array of Logical tile.

20. integrated circuit according to claim 17, in which:

First virtual array of Logical tile is substantially made of microcontroller.

Detailed description of the invention

The present invention can be realized in conjunction with embodiment shown in the accompanying drawings.These drawings show not Tongfangs of the invention Face, and in appropriate circumstances, similar structure, circuit, circuit system, the group shown in different attached drawings is similarly marked Part, material and/or element reference number and refer to title.It should be appreciated that other than those of being particularly shown out, structure, The various combinations of component, material and/or element are expected and within the scope of the invention.It is worth noting that, retouching here It states and is not necessarily to be construed as being for example reason relative to other embodiments or embodiment for the embodiment or embodiment of " exemplary " It is thinking, preferred or advantageous；On the contrary, it is intended to reflect or indicate that (one or more) embodiment is that (one or more) " is shown Example " embodiment.

The block diagram that Figure 1A shows such as example integrated circuit indicates that the example integrated circuit includes control circuit system System, timing or clock circuitry and programmable/(it includes multiple Logical tiles, each logic to configurable logic circuit system Tile generally includes Ihousands of transistors, and (certain transistors can interconnect answers for the multichannel for example with two or more inputs With device, the multiplexer is electrically interconnected into network and is connected to the operation for for example determining multiplexer when programmed Associated data storage elements, input pin and/or look-up table))；

Figure 1B shows the object of multiple Logical tiles of programmable multiple exemplary embodiments of for example exemplary FPGA The block diagram for managing array indicates that wherein the input/output of Logical tile can promote Logical tile and/or may be programmed/can configure to patrol Collect the communication between the circuit system outside circuit system；It is worth noting that, programmable/configurable logic circuit system can be with Including multiple programmable logic tiles, wherein each Logical tile includes multiple multiplexers, these multiplexers electricity is mutually It is connected in network (for example, hierarchical network and/or mesh network；Exemplary Internet is illustrated in United States Patent (USP) 9,503,092 Network, the United States Patent (USP) are incorporated herein by reference)；

Fig. 1 C shows the frame of a part of the example logic tile of programmable/configurable logic circuit system of Figure 1A Figure indicates that wherein Logical tile includes logic and I/O, for example, multiple (i) logical block, each logical block includes for example multiple looks into Look for table, arithmetic block, data multiplexer, trigger and control/reset circuit system, (ii) I/O (I/O circuit system or block, On its periphery that Logical tile is set, periphery or edge, outside the circuit system and tile to promote Logical tile (also, In one embodiment, may be programmed/Logical tile the array external of configurable logic) circuit system between interconnection, and (iii) interference networks being made of one or more multiplexers or switch, the interference networks can be arranged or be configured to In interference networks with multiple switch matrix or switch matrix grade, for example to execute or promote the integrated circuit being currently configured In normal operating or the execution of period logical operation；It is worth noting that, I/O (for example, to the signal of Logical tile entrance/ The physical points exited -- its form of ownership is intended to fall in the scope of the present invention) generally along the entire periphery, outer of Logical tile Enclose or boundary setting (for example, have square or in the case where rectangular shape-referring to Figure 1B in all four sides in Logical tile and Fig. 1 D)；It is worth noting that, I/O means input/output (it can be unidirectional conductor and/or bidirectional conductors) and/or more A input/output (that is, more than one unidirectional conductor and/or more than one bidirectional conductors)；

Fig. 1 D shows the block diagram of the example logic tile of programmable/configurable logic circuit system of Figure 1A-Fig. 1 C It indicates, wherein exterior I/O (in one embodiment, being electrically coupled to I/O circuit system or block) of Logical tile is in the example Property embodiment in be located at rectangle Logical tile all sides on (that is, along Logical tile entire periphery spread)；Physical array In each Logical tile there is periphery or the public layout of exterior I/O placed outside in Logical tile；It is worth noting that, Exterior I/O is separated or independent and/or can compile with the I/O of the Logical tile of the intraconnection for the network in Logical tile Between Logical tile in journey/configurable logic circuit system physical array；

What some aspects according to the present invention were shown in block diagram form in Fig. 2A-Fig. 2 D includes programmable/configurable logic The exemplary embodiment of the FPGA of circuit system, the logic circuitry have functionally or operate upper " subregion " or be arranged to The physical array of multiple Logical tiles of multiple virtual arrays, wherein in these illustrative exemplary embodiments, multiple logics The physical array of tile is arranged to two virtual arrays, the two virtual arrays include virtual array 1, is programmed/configuration/and limits It is set to the first virtual array (there is M Logical tile, wherein M is positive integer) for realizing the first function/operation Logical tile, And virtual array 2, it is programmed/configuration/and is limited to realize the second virtual array (tool of the second function/operation Logical tile Have N number of Logical tile, wherein N is positive integer) (A referring to fig. 2)；It is worth noting that, virtual array 1 and 2 receives separation/difference Clock signal and/or common clock signal, including isolated exterior I/O to be communicated with the circuit system outside FPGA；And It communicates with one another via virtual i/o (B and Fig. 2 C referring to fig. 2) and/or interference networks (C and Fig. 2 D referring to fig. 2)；It can be special with the U.S. Mode described and illustrated in benefit 9,503,092 realizes this interference networks, it may for example comprise hierarchical network and mesh network Mixed mode framework, and in one embodiment, virtual array is via configurable mesh interconnection network (for example, at one It is the superlative degree of mixed mode switched fabric framework in embodiment) interconnection；As described above, the Logical tile in virtual array Data and control signal can be passed to the logic of another virtual array (for example, adjacent virtual array) via virtual i/o Tile；In one embodiment, virtual i/o be positioned at Logical tile periphery on Logical tile " not used " exterior I/ O (referring to Fig. 1 C and Fig. 1 D), the periphery of the Logical tile physically periphery phase with the neighbor logic tile of adjacent virtual array It is right, wherein exterior I/O on the periphery of Logical tile is located on the periphery or periphery of virtual array and may be programmed/can match Set the Logical tile array of logic circuitry periphery or periphery inside (that is, the periphery of Logical tile be not located at it is programmable/can On the periphery or periphery of configuration logic system (also, thus it is not used in the circuit system for being connected to Logical tile array external System)) when, such exterior I/O is " not used "；In fact, even if in the periphery of programmable/configurable logic circuit system Or on periphery, it can also not use or exterior I/O of disabling logic tile；Virtual i/o can be configured or for electrically connecting to Virtual i/o on adjacent/opposite logical tile of programmable/configurable logic circuit system；Therefore, in the exemplary embodiment In, this virtual i/o is not used exterior I/O of adjacent/opposite logical tile (that is, can be used for being connected to Logical tile battle array The I/O for arranging external circuit system and communicating, if such I/O, which is located at, may be programmed/configurable logic circuit system On periphery or periphery), such not used exterior I/O is used to provide the direct communication between Logical tile, the logic Tile is adjacent virtual array in these embodiments；

What some aspects according to the present invention were shown in block diagram form in Fig. 3 A- Fig. 3 C includes programmable/configurable logic The exemplary embodiment of the FPGA of circuit system, the logic circuitry have functionally or operate upper " subregion " or be arranged to Multiple virtual arrays (in exemplary embodiment shown here, more than two virtual array) of physical logic tile it is multiple The physical array of Logical tile；The physical array of multiple Logical tiles can be arranged X virtual array, and (wherein X is just whole Number), this X virtual array includes being programmed/configuration/to be limited to realize virtual array 1, the first function/operation f (1) logic The first virtual array (having M Logical tile, wherein M is positive integer) of tile, virtual array 2 is programmed, and/configuration/limits To realize that the second virtual array of the second function/operation f (2) Logical tile (has N number of Logical tile, wherein N is just whole Number) etc. and virtual array X, be programmed/configuration/be limited to realize the second function/operation f (x) Logical tile virtual array Column (there is Y Logical tile, wherein Y is positive integer) (referring to Fig. 3 A)；It is worth noting that, each virtual array may include The physical logic tile of identical or different quantity, and can be in any way about programmable/configurable logic circuit system The physical array of Logical tile carry out tissue, any mode include for example with column (referring to Fig. 3 A), with row (referring to Fig. 3 B), with And with row and column (referring to Fig. 3 C)；In addition, virtual array can (i) receive separation/different clock signal and/or common clock Signal, (ii) include isolated exterior I/O (be communicated with the circuit system outside FPGA) and (iii) via virtual i/o and/or Switch matrix interference networks communicate with each other (see, for example, Fig. 2 B- Fig. 2 D and associated description)；

Fig. 4 A- Fig. 4 D is shown in block diagram form the programmable/configurable of the FPGA of some aspects according to the present invention and patrols The exemplary embodiment of the physical array of multiple Logical tiles of circuit system is collected, the physical array of plurality of Logical tile exists It functionally or operates upper " subregion " or is arranged to multiple virtual arrays of physical logic tile, wherein the physical array of Logical tile (one or more of the virtual array including Logical tile), which can be configured as, is generated separately multiple ratios via compiler Spy's stream (it is designed to realize given function/operation f (i)), wherein each bit stream indicates or correspond to Logical tile The configuration data of associated virtual array, and hereafter generate compiling or composite bit stream, compiling or composite bit stream work as The physical array (each virtual array including physical logic tile) of the Logical tile of FPGA is configured when being implemented or realizing；Tool Body, about Fig. 4 A, compiler generates f (1), f (2) bit stream, and in one embodiment, subsequently generate for configuring or Program FPGA Logical tile physical array f (1)+f (2) combination or composite bit stream；About Fig. 4 B, compiler is raw At f (1), f (2) ... f (x) bit stream, and in one embodiment, the logic for configuring or programming FPGA is subsequently generated F (1)+f (2) of the physical array of tile+... the combination of+f (x) or composite bit stream；About Fig. 4 C, compiler generates f (1) ..., f (y) bit stream, and subsequently generate the f (1) of the physical array of Logical tile for configuring or programming FPGA+... The combination of+f (y) or composite bit stream；Also, about Fig. 4 D, compiler generates f (1), f (2) ... f (x), f (y) bit Stream, and such bit stream is used, generate f (1)+f (2) for configuring or programming the physical array of the Logical tile of FPGA + ... the combination of+f (x)+f (y) or composite bit stream；It is worth noting that, the function of the virtual array of physical logic tile/ Operation f (i) can be individual feature/operate or including in relation to or unrelated function/operation combination multiple function/operations (all displacement and combination are intended to fall in the scope of the present invention for it)；In addition, for the sake of clarity, I/O is not shown (for example, outer Portion I/O and virtual i/o), clock characteristics and/or memory, however, exemplary embodiment can use it is described and illustrated herein Any I/O framework (see, for example, Fig. 1 C, Fig. 1 D and Fig. 2 B- Fig. 2 D), clock architecture (see, for example, Fig. 2 B- Fig. 2 D, Fig. 5 A and Fig. 5 B) and/or memory architecture (see, for example, Fig. 2 B- Fig. 2 D and Fig. 7 C)；

Fig. 5 A be shown in block diagram form some aspects according to the present invention functionally or operate upper " subregion " or cloth It is set to the exemplary embodiment of the physical array of multiple Logical tiles of two virtual arrays, wherein in illustrative exemplary reality It applies in example, the physical array of multiple Logical tiles is arranged to (i) and is programmed/configuration/and is limited to realize the first function/operation f (1) the first virtual array (have M Logical tile, wherein M is positive integer) of Logical tile, and (ii) be programmed/configure/ It is limited to realize that the second virtual array of the second function/operation f (2) Logical tile (has N number of Logical tile, wherein N is just Integer), and wherein each virtual array receives one or more clock signals and netted clock, one or more clock letters Number and netted clock can be assigned to each Logical tile and by Logical tile for performing various functions/operate；It is worth note Meaning, control circuit system can for example make it possible to real about such a or multiple virtual array by Logical tile Existing one or more functions/operation, in one or more physical logic tiles and/or in one of virtual array or both It is interior to use netted clock (instead of other clock signals)；Control circuit system can in starting or initialization (for example, via with / controlled/in setting and establish the data mode of the memory of clock domain) and/or during the normal operating of FPGA or integrated circuit Dynamically control/establish clock domain.

Fig. 5 B shown in the form of schematic block diagram the Logical tile in the physical array of Logical tile clock distribution and The exemplary embodiment of transmission circuit system, wherein clock distribution and transmission circuit system include multiple outputting and inputting path (be in the embodiment shown four paths, labeled as " northern clock path ", " eastern clock path ", " southern clock path " and " western clock path "), to generate the Logical tile clock signal with expectation or programmable deflection (skew), and in addition receive Clock network (for by the Logical tile in the virtual array of netted clock signal transmission to such as Logical tile), which can Can be used for the circuit of Logical tile via the output for being selectively enabled (one or more) clock selecting multiplexer System；In one embodiment, this clock selecting multiplexer responsively exports netted clock signal or inside generates/obtains Clock signal out is as tile clock, and the tile clock is by the circuit system of Logical tile for executing or carrying out such as function And/or operation；Control circuit system can be enabled to via (one or more) multiplexer as control at one Or one or more function in multiple physical logic tiles and about one or more virtual arrays realization by Logical tile Can/operate with netted clock (instead of other clock signals) (referring also to Fig. 5 A)；It is worth noting that, in United States Patent (USP) 9, The some aspects of clock distribution and transmission circuit system are discussed in detail in 240,791 (in order to show/the clock point of explanation figure 5B With the purpose in terms of these with transmission circuit system, which is incorporated herein by reference)；

Fig. 6 shows some aspects according to the present invention in conjunction with certain information about virtual array 1 in form of a block diagram and exists Functionally or operates upper " subregion " or be arranged to the exemplary implementation of the physical array of multiple Logical tiles of two virtual arrays Example, the internal resource of the virtual array 1 including some aspects according to the present invention；It is worth noting that, virtual array 1 operates quilt Be configured to data processor, microcontroller and/or DSP, wherein associated Logical tile include/provide support and/or supplement The logic circuitry of DSP (that is, the first function/operation), and virtual array 2 can be for example with interconnection by user configuration Logic, accelerator, data encryption engine, filter, encoder, state machine and/or the memory of network are (that is, the second function/behaviour Make)；In addition, certain Logical tiles of the physical array of Logical tile are electrically connected on " bottom " edge/periphery of physical array To memory (for example, SRAM, DRAM and MRAM) to be read from data and be written to data；

The netted of the grade 4 of a part of the exemplary embodiment of Fig. 2A, Fig. 2 C and Fig. 2 D is shown in block diagram form in Fig. 7 A Connection, wherein in one embodiment, the interference networks of virtual array are via the interference networks of configurable net, annulus etc. (under Referred to herein as " mesh network ") connection, for example, such as (being integrally incorporated herein by reference) with United States Patent (USP) 9,503,092 Described and illustrated in mode realize；In the illustrative exemplary embodiment, the highest of mixed mode switched fabric framework Grade is that (here, the five-star multiple switch matrix of the Logical tile of virtual array 1 is connected to virtual array 1 for netted interconnection Five-star one in the multiple switch matrix of this grade in the Logical tile and at least one Logical tile of virtual array 2 Or multiple switch matrix；(in fact, the signal exported by the switch of grade 4 is not with this in the illustrative exemplary embodiment A little signals propagate through mesh network and change hierarchical structure；That is, signal can be from the grade 4 of the Logical tile of virtual array 1 Switch advance, then to the switch in the grade 4 of the Logical tile of virtual array 2, then return to the logic watt of virtual array 1 Switch in the grade 4 of piece；It is worth noting that, in one embodiment of Fig. 7 A, in other switch matrix (SM) grade (that is, grade 1,2 and 3) in use hierarchical network/interconnection；Nevertheless, another mesh network/grade can be implemented as one or more layerings The substitution of grade and replacement (for example, grade 2 can be mesh network or grade 2 and 4 can be by the mesh network that horizontally and vertically " jumps " Network replacement, in addition to " jump " in each direction 4 other than the prime 4)；

The exemplary embodiment of 2 × 2 physical arrays including virtual array, virtual array is shown in block diagram form in Fig. 7 B Including Logical tile 00 and Logical tile 01；In an illustrative embodiment, exterior I/O between Logical tile 00 and 01 is banned With, and it is used as virtual i/o with exterior I/O of the juxtaposed Logical tile 00 and 01 of Logical tile 10 and 11 respectively, virtual i/o mentions For the electrical interface or communication path between the Logical tile in virtual array and other Logical tiles of physical array；It is this virtual The other parts for the Logical tile and physical array that I/O can be used in virtual array are (such as, such as to provide or promote void Communication path between matroid column, virtual array are configured as or execute data processor, microcontroller, accelerator, data and add The operation of ciphertext engine, filter, DSP, encoder and/or state machine) and other Logical tiles of physical array (it can be The part of another virtual array) between transmission of control signals, data, order and address information；It is worth noting that, in the reality It applies in example, virtual i/o corresponds to the exterior I/O being not used in the Logical tile of the interface circuitry of Logical tile array external (see, for example, Fig. 1 D) (here, which is not located at the virtual array or physical array of programmable/configurable logic circuit system Periphery or periphery on-therefore, be not used in the circuit system for being connected to programmable/configurable logic circuit exterior but can be with For adjacent with from virtual array and physically opposite Logical tile (for example, different virtual arrays adjacent and physically phase Pair Logical tile or Logical tile physical array array and other Logical tiles) I/O interface；

Illustrative programmable/configurable logic circuit of some aspects according to the present invention is shown in block diagram form in Fig. 7 C System, wherein in this exemplary embodiment, programmable/configurable logic circuit system includes four Logical tiles, wherein patrolling It collects tile 00 and 01 and is configured or programmed to virtual array 1；Memory I/O of Logical tile is arranged in the periphery of Logical tile Portion, virtual i/o the Logical tile of virtual array 1 is set and be not virtual array the Logical tile of part between, Yi Jishe Setting the exterior I/O placed outside virtual array/physical array can be by the circuit system of programmable/configurable logic circuit exterior System access；It is worth noting that, memory is arranged in void in the exemplary embodiment of 2 × 2 physical arrays of Logical tile The logic of Logical tile and the illustrative programmable/configurable logic circuit system embodiment rest part in matroid column Between tile 10 and 11, and memory I/O of Logical tile is connected to promote the communication with memory (that is, patrolling from adjacent Volume tile read data and/or from neighbor logic tile to memory be written data and/or from adjacent memory read data and/ Or from adjacent memory to Logical tile write-in data-such as U.S. Patent application No.15/239,958 (by quoting the U.S. Patent application is integrally incorporated herein) described in and show；In one embodiment, this memory may be used as it is local or Pocket memory is used for the virtual array to be used (for example, storage intermediate computations), wherein during executing functions or operations, Logical tile in virtual array can write data into except the array of Logical tile during the operation of Logical tile Memory and from the memory read data；It is worth noting that, in one embodiment, memory is arranged at (i) Dual-ported memory between Logical tile 00 and Logical tile 01 and (ii) Logical tile 10 and Logical tile 11；Again, It can be using the void being arranged between (i) Logical tile 00 and Logical tile 10 and (ii) Logical tile 01 and Logical tile 11 Quasi- I/O carrys out the transmission of control signals between the Logical tile of the other parts of Logical tile and physical array in virtual array (for example, be configured as or execute data processor, microcontroller, logic, accelerator, data encryption engine, filter, Communication bus is provided between the virtual array of the operation of DSP, encoder and/or state machine)；This virtual i/o is for providing Not used exterior I/O of the neighbor logic tile of direct communication between Logical tile；And

What some aspects according to the present invention were shown in block diagram form in Fig. 8 A- Fig. 8 E includes programmable/configurable logic The exemplary embodiment of the FPGA of circuit system, the logic circuitry have functionally or operate upper " subregion " or be arranged to The physical array of multiple Logical tiles of one or more virtual arrays of physical logic tile；It is worth noting that, logic watt One or more virtual arrays of piece can completely or partially positioned at Logical tile physical array periphery or outside place or It is fully located inside it；Each virtual array may include the physical logic tile of identical or different quantity, and can be to appoint Where formula about the physical array of the Logical tile of programmable/configurable logic circuit system carries out tissue；In addition, although not showing Out, still (one or more) virtual array can (i) receive separation/different clock signal and/or common clock signal, It (ii) include isolated exterior I/O (be communicated with the circuit system outside FPGA), and (iii) via virtual i/o and/or switch Matrix interconnection network communicates with each other (see, for example, Fig. 2 B- Fig. 2 D and associated description).

Equally, many inventions described and illustrated herein.The present invention is also not necessarily limited in fact neither limited to any single aspect Example is applied, any combination and/or displacement of these aspects and/or embodiment are also not necessarily limited to.Each aspect of the invention and/or in fact Applying example can be used alone or be applied in combination with one or more of the other aspect of the invention and/or embodiment.Succinctly to rise See, many not separation discussion herein in these combinations and displacement.It in addition, for the sake of clarity, is shown in the whole of attached drawing I/O (for example, exterior I/O and virtual i/o), clock characteristics and/or memory are shown in example property embodiment.However, in order to avoid, Exemplary embodiment (for example, Fig. 3 A- Fig. 3 C, Fig. 4 A- Fig. 4 D and Fig. 8 A- Fig. 8 E) that is described herein and showing can be using herein Any I/O framework or embodiment (see, for example, Fig. 1 C, Fig. 1 D, Fig. 2 B- Fig. 2 D and Fig. 7 B), the switched fabric for describing and showing The network architecture or embodiment (see, for example, Fig. 7 A), clock architecture or embodiment are (see, for example, Fig. 2 B- Fig. 2 D, Fig. 5 A and figure 5B) and/or memory architecture or embodiment (see, for example, Fig. 2 B- Fig. 2 D and Fig. 7 C).

Specific embodiment

In a first aspect, the FPGA has functionally and/or grasps the present invention relates to a kind of integrated circuit including FPGA The physics of Logical tile (for example, continuous Logical tile) on work in the multiple virtual arrays of " subregion " to form Logical tile Array, wherein each virtual array includes one or more Logical tiles.The virtual array of the physical array of Logical tile can be with It is the physics continuation subset of the Logical tile in the physical array of such as Logical tile.The virtual array of Logical tile, which can be, patrols The physics of Logical tile in the physical array of volume tile continuously or discontinuously subset.The virtual array of Logical tile can be compiled Journey configures or is limited to realize one or more specific and/or scheduled function/operations, such as data processor or microcontroller Device (for example, DSP and associated logic circuitry).Virtual array can also be programmed, and/configuration/is limited to realize other spies Fixed and/or scheduled function/operation, the logic such as with interference networks is (for example, with first as processor or controller Virtual array interface), accelerator, data encryption engine, filter, encoder, DSP (realize for example one or more multipliers- Accumulator circuit and/or operation), state machine and/or memory.It is worth noting that, it is associated with each virtual array or point Area is that the quantity of the Logical tile in each virtual array can be with other virtual arrays of the physical array of the Logical tile of FPGA It arranges identical or different.

The virtual array of Logical tile can be programmed, configure and/or be limited to (i) independently of in other virtual arrays One or more (or all) operations execute, (ii) during all or part of the operation of FPGA completely or partially independently Operation executes, or one or more of (iii) and other virtual arrays (or all) together or dependent on other virtual arrays One or more of column (or all) execute or operate.In fact, in one embodiment, in the virtual array of Logical tile One or more can be programmed, configure or be limited to operate or hold independently of one or more of other virtual arrays Row its function and Logical tile one or more of the other virtual array can be programmed, configure or be limited to one or Multiple virtual arrays are operated together or dependent on one or more virtual arrays.It is worth noting that, Logical tile is every The independence of a virtual array and the whole for relying on operation combine and displacement is intended to fall in the scope of the present invention.

With reference to Figure 1A-Fig. 1 D, in brief, in one embodiment, FPGA of the invention includes among other can Programming/configurable logic circuit system, the logic circuitry include the physical array of Logical tile.As described above, each patrolling It collects tile and generally includes Ihousands of transistors, these transistors can be configured as execution combination and/or sequence function is (simple And/or complicated).In one embodiment, each logical block may include one or more multiplexers or switch, and this Or multiple multiplexers or switch can be arranged in the multiple switch matrix or switch matrix grade of interference networks, for example to exist In the normal operating of integrated circuit or period executes logical operation (being based on the current-configuration of (one or more) logical block), and (ii) I/O (I/O pin and associated I/O circuit system or block)-is for example, be arranged in the periphery of Logical tile, periphery or side I/O pin and I/O circuit system associated with this I/O pin or block on edge, to promote the circuit system of Logical tile Interconnection between system and the circuit system of programmable/configurable logic circuit exterior.It is worth noting that, each logic watt Exterior I/O (I/O pin and associated I/O circuit system/block) of piece is generally along the entire periphery of Logical tile or boundary Spread-for example, in the case where Logical tile has rectangular or rectangular shape in four sides.(see, for example, Fig. 1 D).Therefore, In In one embodiment, each Logical tile in Logical tile array has public exterior I/O cloth on the periphery of Logical tile Office (this has advantageously facilitated the tiling (tiling) of the Logical tile in physical array).

In one aspect of the invention, the physical array of Logical tile of the invention is functionally or operation is upper " subregion " To form one or more virtual arrays of Logical tile (each virtual array includes one or more physical logic tiles). The virtual array of (one or more) Logical tile is programmed, configures or is limited to realize at concrete function/operation, such as data Manage device, microcontroller, logic (for example, with another virtual array (for example, processor or controller) interface), accelerator, data Crypto engine, filter, DSP, encoder and/or state machine.For example, in one embodiment, can be compiled with reference to Fig. 2A-Fig. 2 D The physical array of journey/configurable logic circuit system Logical tile is partitioned two virtual arrays, each virtual array packet Include one or more physical logic tiles.In this embodiment, virtual array 1 and virtual array 2 respectively include Logical tile The physics continuation subset of Logical tile in physical array.Virtual array 1, which is programmed ,/configuration/is limited to realize function f (1) (example Such as, data processor or microcontroller (for example, DSP with support logic circuit system)) and virtual array 2 be programmed/ It configures/is limited to and realize f (2) (for example, the support logic with interference networks is (for example, with the as processor or controller One virtual array interface), accelerator, data encryption engine, filter, encoder, state machine and/or memory).Logical tile Physical array M Logical tile it is associated with virtual array 1 or functionally or operate upper subregion to form virtual array 1, and N number of Logical tile of the physical array of Logical tile is associated with virtual array 2 or functionally or operate upper subregion With formed virtual array 2- wherein M and N be positive integer (i.e. 1,2,3 ...), M and N can be identical integer or different Integer.

It is worth noting that, the physical array of Logical tile can functionally or operation upper " subregion " is at entire physics battle array The subset of column, to form more than two virtual array of Logical tile.(see, for example, Fig. 3 A- Fig. 3 C).It can design, match Each virtual array is set or limited to realize one or more (or whole) unique or not exclusive functions or operations.In fact, to the greatest extent Virtual array is described as being programmed, configure or be limited to realize or executes function by many embodiments of pipe, but the function can be Individual feature/operation or it is multiple in relation to or unrelated function/operation (for example, in relation to function/operation combination).

In addition, the physical array of Logical tile and/or the virtual array of Logical tile can be any size (row or column) And/or shape (that is, row is relative to column).For example, with reference to Fig. 3 A- Fig. 3 C, the physical array of multiple Logical tiles can be arranged At X virtual array (wherein X is positive integer), function/operation f (1) virtual array is realized including being programmed, configuring or be limited to Column 1 (have M Logical tile, wherein M is positive integer), are programmed/configuration/and are limited to realize that function/operation f (2) is virtual Array 2 (there is N number of Logical tile, wherein N is positive integer) etc., and be programmed/configuration/and be limited to realize function/operation f (x) virtual array X (there is Y Logical tile, wherein Y is positive integer).As described above, such function can be one or more A (or whole) unique or not exclusive functions or operations.It is worth noting that, each virtual array may include identical or not With quantity physical logic tile and can in any way about programmable/configurable logic circuit system Logical tile Physical array carry out tissue, any mode includes that for example (referring to Fig. 3 A, wherein virtual array is relative to physical array to arrange for column Mode subregion/tissue), row (referring to Fig. 3 B, wherein virtual array is relative to physical array with line mode subregion/tissue) and Row and column (referring to Fig. 3 C, wherein virtual array is relative to physical array neither in a manner of column nor with line mode subregion/tissue). It is worth noting that, virtual array is also although each virtual array can be shown as including multiple continuous Logical tiles It may include one or more discrete Logical tiles (that is, having the virtual array and the void of one or more Logical tiles Other Logical tiles of matroid column are discontinuous).

It, can be with one in programmed/configured/restriction Logical tile virtual array with reference to Fig. 2A-Fig. 2 D and Fig. 3 A- Fig. 3 C Or multiple (or all), to be operated independently of one or more of other virtual arrays (or whole).For example, with reference to figure 2A and Fig. 3 A- Fig. 3 C, virtual array 1 can during all or part of operation of FPGA relative to virtual array 2 completely or portion Divide and is operating independently.In addition, in one embodiment, virtual array 1 can be programmed, configures or be limited to independently of virtual array X is arranged to operate and operate dependent on virtual array 2.(see, for example, Fig. 3 A and Fig. 3 C).It is worth noting that, Logical tile The independence of each virtual array and the whole for relying on operation combine and displacement is intended to fall in the scope of the present invention.

With reference to Fig. 2 B- Fig. 2 D, the virtual array of Logical tile can be relative to by (one or more) other virtual arrays The signal clock for receiving, generating and/or using includes, receives, generating and/or using one or more exclusive signals (or clock Domain) and/or not exclusive clock signal (or clock domain).For example, (it is received 1 clock of (one or more) array by virtual array 1 And use) can be it is identical or different with the characteristic of 2 clock of (one or more) array (it is received and used by virtual array 2) Characteristic (for example, frequency and/or phase).In addition to this, or it is replaced, two or more in virtual array are (or complete Portion) it can be generated and/or use one or more common clock signals (or public clock domain clock), for example to promote simultaneously operating (for example, between the circuit system of this virtual array or the circuit system of this virtual array and external circuitry it Between).(see, for example, (one or more) array clock in Fig. 2 B)).In fact, two or more in virtual array (or all) common clock signal (or public clock domain clock) can be used, and one or more virtual arrays of Logical tile can To include, generate and/or using (one or more) different clock signal (or (one or more) different clock domain).Value It is noted that on the basis of virtual array one by one, (or not about the one or more different clocks signals for using and generating Same clock domain) and the whole combinations and displacement of one or more common clock signal (or public clock domain clock) be intended to fall within the present invention In the range of.

Logical tile in virtual array can directly with other virtual arrays of Logical tile one or more logics Tile communication.With reference to Fig. 2 B and Fig. 2 C, in one embodiment, the Logical tile in one or more virtual arrays be can be used Virtual i/o communicates (example from other Logical tiles (for example, one or more Logical tiles of one or more different virtual arrays) Such as, data, control and/or address signal), in one embodiment, virtual i/o be Logical tile " not used " exterior I/ O (referring to Fig. 1 C and Fig. 1 D) is somebody's turn to do " not used " exterior I/O and is located at patrolling with such as the adjacent of adjacent virtual array for Logical tile On the physically opposite periphery in the periphery of volume tile.When I/O be not used in outside FPGA or programmable/configurable logic circuit system (for example, when exterior I/O of Logical tile is not located at periphery or the week of the physical array of Logical tile when the circuit system communication in portion (that is, exterior I/O on the periphery of Logical tile is located on the periphery or periphery of virtual array and programmable logic when on side The periphery of the Logical tile array of circuit system or the inside on periphery), this exterior I/O is " not used ".I/O external In on the periphery or periphery of virtual array and in the case where the periphery or periphery inside of Logical tile array, " not used " outside Portion I/O can be re-used as virtual i/o, and virtual i/o can be configured or for electrically connecting to programmable/configurable logic circuit Not used exterior I/O (for example, virtual i/o of adjacent virtual array) on adjacent/opposite logical tile of system.Here, The direct communication-between the Logical tile in the physical array of Logical tile is provided using this virtual i/o in the embodiment In, Logical tile is the Logical tile in adjacent virtual array.

Therefore, in one embodiment, virtual array 1 and virtual array 2 include virtual i/o with connect or promote them it Between communication.(Logical tile 00 and 01 for seeing also Fig. 7 B).This virtual i/o can be in the Logical tile of virtual array 1 and 2 Between (and between other Logical tiles of physical array) transmit/receive control, address and/or data-signal.For example, one In a embodiment, virtual i/o provides or promotes communication path, with (i) input data (a) in (such as, data processor, micro- Controller, accelerator, data encryption engine, filter, DSP, encoder and/or state machine) it uses in functions or operations, And/or input data and/or (ii) are being executed by Logical tile when (b) executing functions or operations (for example, encryption) on it Virtual array execute functions or operations (for example, cryptographic operation) after output data.

It is worth noting that, one in exterior I/O of one or more Logical tiles, some or all (no matter (one Or multiple) whether Logical tile be virtual array) it can be " not used ", although these exterior I/O are located in Logical tile Physical array periphery or periphery on.Here, exterior I/O is not used in the circuit system outside the physical array with Logical tile Communication.In fact, in one embodiment, the not direct electricity with programmable/configurable logic circuit exterior of virtual array Road system communication, therefore there is no exterior I/O.In this embodiment, the virtual array of Logical tile can via virtual i/o and/ Or interference networks or construction directly lead to other Logical tiles of physical array (for example, Logical tile in another virtual array) Letter.

With reference to Fig. 2 C and Fig. 2 D, other than virtual i/o, or it is replaced, in one embodiment, the one of Logical tile Interference networks can be used in a or multiple virtual arrays or construction is communicated with one or more of the other virtual array of Logical tile. Such as when powering on, starting, (it can be with during initialize or reinitialize, and/or in reset or similarly-ordered/operation Before the configuration of the virtual array of Logical tile, period/simultaneously or after), this switched fabric network or structure can be configured It makes.In one embodiment, one or more Logical tiles of virtual array can be based on or use United States Patent (USP) 9,503,092 One or more of the one or more networks and another virtual array that describe and/or show in (it is incorporated herein by reference) A Logical tile interconnection.In fact, giving one or more of the Logical tile in virtual array in addition to this or instead of it (or all) can also carry out based on or using one or more networks for describing and/or show in United States Patent (USP) 9,503,092 Interconnection.

For example, the Logical tile in two virtual arrays can be communicated via mixed mode interconnection architecture or network, Wherein in Logical tile and mesh network (for example, the multiple switch of the given state in Logical tile is interconnected to different virtual arrays Column another Logical tile in same stages a number of other switches) in realize hierarchical network, be embodied as connect virtual array In Logical tile (for example, in one embodiment, netted interconnection be mixed mode switched fabric framework the superlative degree-referring to Such as wherein the interference networks in one or more (or all) Logical tile of virtual array 1 and virtual array 2 are most by Fig. 7 A- Advanced each switch matrix is connected in (i) Logical tile multiple switch matrix of this grade and (ii) virtual array 2 extremely Five-star multiple switch matrix in a few Logical tile).It is worth noting that, between Logical tile in virtual array Whole combinations of communication (within and) are intended to fall in the scope of the present invention in the middle.In addition, one or more virtual arrays Whole combinations of communication (including form and method) between the circuit system outside the physical array of Logical tile are intended to fall within In the scope of the present invention.

With continued reference to Fig. 2 B- Fig. 2 D, in one embodiment, the virtual array of Logical tile may include and/or use Physically different or isolated exterior I/O.In addition to this or it is replaced, the virtual array of Logical tile includes and/or using object Public I/O in reason.In fact, one or more of virtual array of Logical tile (or all) may include and/or adopt With physically different or isolated I/O and physically public I/O.On the basis of virtual array one by one, it is physically separated I/O and the whole combinations and displacement of physically public I/O be intended to fall in the scope of the present invention.

As described above, one or more of virtual array of Logical tile (or all) can " shared " circuit system, Memory (for example, DRAM, SRAM etc.), clock generates or alignment circuit system (for example, PLL, DLL, oscillator) and/or in object Other " resources " in reason outside the entire physical array of continuous Logical tile.For example, with reference to Fig. 2 B, virtual array 1 and void Matroid column 2 be coupled to clock forming circuit system (for example, with reception oscillator circuit system one or more output) and/or Accessible identical physics insertion or separate memory.In one embodiment, can will physics associated with FPGA it is embedding Enter or separate memory is segmented or subregion, so that in certain sub-arrays, block or the page and specific virtual array or virtual array Two or more associated or dispensings or two or more being exclusively used in specific virtual array or virtual array.

As described above, in one embodiment, FPGA of the invention uses U.S. Patent application No.15/239, retouched in 958 The framework stated and/or shown, wherein memory setting is between Logical tile and adjacent with Logical tile.(see, for example, figure 7C).In brief, (it can be separately the Logical tile and other Logical tiles that separate memory is arranged in virtual array A part of one virtual array or virtual array) Logical tile 10 and 11 between.Logical tile is via memory I/O connection To memory to promote communication (such as in U.S. Patent application No.15/239, described and illustrated in 958, from neighbor logic to depositing Reservoir reads data and/or data is written from memory to neighbor logic.For example, in one embodiment, memory is setting Dual-ported memory between (i) Logical tile 00 and Logical tile 01 and (ii) Logical tile 10 and Logical tile 11.Value It obtains it is noted that being arranged between (i) Logical tile 00 and Logical tile 10 and (ii) Logical tile 01 and Logical tile 11 Virtual i/o can be used between the Logical tile of the other parts of Logical tile and physical array in virtual array passing (for example, virtual i/o is connected to the communication bus between virtual array, which is matched for defeated control signal, address and data Be set to or execute data processor, microcontroller, logic, accelerator, data encryption engine, filter, DSP, encoder and/or Other Logical tiles of state machine and physical array are (for example, with another virtual array (for example, processor or controller) interface Operation).

It is worth noting that, memory can be any type, type, size and/or configuration.

It is complete to program or configure the physical array-of Logical tile that any technology that is currently known or developing later can be used These technologies of portion are intended to fall in the scope of the present invention.In one embodiment, each of restriction, configuration or programmed logic tile The bit stream of virtual array is discretely applied to physical array (as separation or different bit streams), to discretely program Or each virtual array of configuration.In another embodiment, (for example, passing through one or more compilers) is each virtual array (for example, discretely) generates the bit for indicating or correspond to the configuration data of the configuration of associated virtual array of Logical tile Stream.Then bit stream associated with the virtual array of Logical tile is supplied to compiler, which uses bit stream Generating combination, compiling or " merging " bit stream, such bit stream indicate or correspond to the physical array of Logical tile Configuration data-Logical tile physical array include Logical tile each virtual array.Hereafter, composite bit stream is broadcasted Or the physical array applied to Logical tile, composite bit stream program or configure again programmable/configurable logic circuit of FPGA The physical array of the Logical tile of system, thus by (one or more that the subset dispensing or subregion of Logical tile are Logical tile It is a) virtual array.

For example, one or more compilers are generated separately related to the virtual array of Logical tile with reference to Fig. 4 A- Fig. 4 D The bit stream of the virtual array (it is designed or programmed to realize one or more functions/operation) of connection or expression Logical tile, And composite bit stream is generated or compiled using such bit stream.Then configure or program FPGA's using composite bit stream Physical array-Logical tile physical array of Logical tile includes each virtual array of physical logic tile.Here, compound Bit stream is broadcasted or programs or configure each virtual array applied to physical array Logical tile to realize one or more Predetermined function/operation.That is, by by physical array subregion be Logical tile (one or more) virtual array in The subset of Logical tile, by composite bit stream broadcast or applied to the entire physical array of Logical tile, to program or configure The each virtual array of physical array-of the Logical tile of programmable/configurable logic circuit system of FPGA is designed or programmed To realize one or more functions/operation (for example, processor, controller, accelerator, data encryption engine, filter, coding Device, DSP (realize for example one or more multiplier-accumulator circuits and/or execute one or more multiplier-accumulator behaviour Make), state machine).Therefore, in this embodiment it is possible to be generated separately the bit stream of virtual array, hereafter (for example, via one A or multiple compilers) by bit stream and the other bit stream combinations of physical array, compiling or the " conjunction that correspond to Logical tile And ", then composite bit stream is implemented, broadcasts or realizes with while configuring the virtual array of the physical logic tile of FPGA, from It and operate FPGA can.

It is worth noting that, in one embodiment, it can lock, fix and/or one or more of encryption logic tile A virtual array (for example, realizing pre-qualified function/operation) so that cannot configure/reconfigure, limit, modifying and/more Change the configuration (for example, before physical array of configuration Logical tile) of the virtual array.In addition to this or replace it, one or A number of other virtual arrays (realizing for example identical or different function/operation) can be unlocked, can limiting or can repair Change, allow to configure/reconfigure, determine and/or limit the configuration of the second virtual array.For example, in one embodiment In, the physical array of Logical tile includes the one or more virtual arrays for the Logical tile for being " locked ", fixing and/or encrypting Column, so that the first user or designer are denied access the configuration data of one or more of these virtual arrays (to prohibit Only program, configure, redefine or modify function/operation of above-mentioned (one or more) virtual array).In addition, one or more It is " unlocked ", programmable, can limiting or revisable that a other virtual arrays can be, so that the first user or design Person is not denied access the configuration data of one or more of those virtual arrays (to not be program-inhibited, configure, limit Or function/operation of this (one or more) virtual array of modification).In this way, the first user can program or limit Certain virtual arrays, without programming or limiting other virtual arrays, (and/or even access programs such other virtual arrays Data).

In this embodiment it is possible to by the way that via separation or different bit streams, discretely application is limited, configures or is programmed (one or more) bit stream of each of " locking " and " unlocked " virtual array of Logical tile, to program or configure The physical array of Logical tile.In another embodiment, (using compiler) combination or compiling and Logical tile can be passed through The associated bit stream of " locking " and " unlocked " virtual array come using composite bit stream it is (as described above) programming or configuration The physical array of Logical tile, hereafter can broadcast, carry out, application or realize with physical array (it includes above-mentioned virtual array) Associated compound or combined configuration bit-stream, to program or configure " locking " and " unlocked " virtual array of FPGA, with Operate FPGA can.For example, in one embodiment, virtual array 1 can be " locking " virtual array with reference to Fig. 4 A, and Virtual array 2 can be " unlocked " virtual array.Here, compiler can be generated including (it is designed to virtual array 1 The the first function/operation for being " locked ", fixing and/or encrypting is realized, so that the first user or designer are program-inhibited, match Set, limit or modify) associated bit stream and (it can be " unlocked ", so that user can compile with virtual array 2 Journey can limit or configurable) composite file or bit stream of associated bit stream.Hereafter, it can use or broadcast compound ratio Spy's stream is to program or configure the entire physical array of FPGA (it is also programmed or configuration locking and unlocked virtual array).

It is worth noting that, can have one or more " locking " virtual arrays and one or more " unlocked " void Such process or technology are used in those of matroid column embodiment.(see, for example, Fig. 4 B- Fig. 4 D).For example, with reference to Fig. 4 B, Virtual array 1 and virtual array x can be " locking " virtual array, and at least virtual array 2 can be " unlocked " virtually Array.Other virtual arrays (if any) can be " locking " or " unlocked ".Here, one or more compilers (i) generate is associated or corresponding bit stream with f (1), f (2) ... f (x), and hereafter (ii) is passed through using each bit stream Combine each bit stream and generate composite bit stream, with generate with f (1)+f (2)+...+f (x) be associated or corresponding combination or Composite bit stream.Then composite bit stream can be applied or is broadcast to programmable/configurable logic circuit system of FPGA, with Programmed logic tile physical array (its provide physical array functionally and/or to operate upper " subregion " be physical logic tile Functionally and/or operate upper associated subset, with " is formationed " or offer virtual array of the invention).

It is described herein and show many inventions.Although have been described and show certain embodiments of the present invention, feature, Attribute and advantage, it should be appreciated that, many other and different and/or similar embodiments of the invention, feature, attribute and Advantage is clear from description and explanation.Therefore, the embodiment of the present invention described and illustrated herein, feature, attribute and excellent Point it is not exhaustive, and it is to be understood that these other similar and different embodiments of the invention, feature, attribute and Advantage is within the scope of the invention.

In fact, the present invention is also not necessarily limited to embodiment neither limited to any single aspect, be also not necessarily limited to these aspects and/ Or any combination and/or displacement of embodiment.In addition, each aspect of the invention and/or embodiment can be used alone or It is applied in combination with one or more of the other aspect of the invention and/or embodiment.

For example, can be (or complete with one or more of programmed/configured/restriction virtual array of Logical tile of the invention Portion), to be operated independently of one or more of other virtual arrays (or whole).In the virtual array of Logical tile Such a or multiple (or all) can be operating independently completely or partially during all or part of operation of FPGA.In In one embodiment, one or more of virtual array of Logical tile can be programmed, and/configuration/is limited to independently of other One or more of virtual array (or all) come operate and the identical or different virtual array of Logical tile in one Or multiple it can be programmed/configuration/and be limited to be operated dependent on one or more of other virtual arrays (or all). It is worth noting that, the whole combinations and displacement of the independence of each virtual array of Logical tile and dependence operation are intended to fall within this In the range of invention.

In addition, as described above, (one or more) virtual array of the physical array of Logical tile can use now Any clock circuitry and technology known or developed later.For example, in one embodiment, virtual array uses netted clock Circuit system and technology.For example, in one embodiment, the physical array of multiple Logical tiles is by cloth with reference to Fig. 5 A and Fig. 5 B Two virtual arrays are set to, the two virtual arrays include being programmed/configuration/to be limited to realize the first function/operation f (1) It virtual array 1 (have M Logical tile, wherein M is positive integer) and is programmed/configuration/and is limited to realization the second function/operation The virtual array 2 (there is N number of Logical tile, wherein N is positive integer) of f (2).Each virtual array can receive one or more Isolated clock signal and netted clock, the clock signal of one or more separation and netted clock can be assigned to Each Logical tile is simultaneously used by Logical tile to perform various functions/operate.The control circuit system of FPGA can make it possible to Enough in one or more physical logic tiles of virtual array and about one or more virtual arrays by Logical tile The one or more functions of realization/operate with netted clock (instead of other clock signals).It is worth noting that, netted clock Circuit system (and netted clock) can describe and/or show in Fig. 2A-Fig. 2 D, Fig. 3 A- Fig. 3 C and Fig. 4 A- Fig. 4 D any It is realized in virtual array embodiment.

For example, with reference to Fig. 5 B, in one embodiment, control circuit system via receive multiple clock signals (including when Clock network clock) multiplexer control selections make it possible for clock network signal.In this embodiment, logic watt The clock distribution and transmission circuit system of Logical tile in the physical array of piece include multiple paths that output and input (shown Four paths-in embodiment are labeled as " northern clock path ", " eastern clock path ", " southern clock path " and " Xi Shizhonglu Diameter ") to generate the Logical tile clock signal with expectation or programmable deflection, and in addition connect (via netted Clock layout) Receive clock network signal.By selectively controlling (one or more) clock selecting multiplexer, Logical tile is using given Clock signal (for example, netted clock signal).That is, in one embodiment, clock selecting multiplexer is responsively Netted clock signal or the internal clock signal for generating/obtaining are exported as tile clock, tile clock by Logical tile electricity Road system is for executing or carrying out such as function and/or operation.Control circuit system can be via such (one or more) The control of clock selecting multiplexer makes it possible in one or more physical logic tiles and about by Logical tile One or more virtual arrays realize one or more functions/operate with netted clock (instead of other clock signals).

It is worth noting that, here United States Patent (USP) 9,240 can be used with modifying in the mode as set forth in about clock network, 791 clock distribution and transmission circuit system.United States Patent (USP) 9,240,791 is incorporated herein by the following way in this, when for illustrating/explaining The various aspects of clock distribution and transmission circuit system, but be modified to include multiplexer so that responsively select will be by logic watt The circuit system of piece is used to execute or carry out the clock signal (for example, netted clock signal) of such as function and/or operation.

In addition, one or more virtual arrays of Logical tile can be programmed, configure or be limited to realize it is currently known Or any function/operation developed later.For example, in one embodiment, one or more virtual arrays are programmed or configure For data processor, microcontroller, accelerator, data encryption engine, filter and/or encoder.(in Fig. 6, see also, The exemplary embodiment for being configured or programmed to the virtual array 1 of micro controller unit (has and for example multiplies via one or more Musical instruments used in a Buddhist or Taoist mass-accumulator circuit configures and/or is configured as to execute the DSP of one or more multiplier-accumulators operations).

In addition, one or more virtual arrays of Logical tile can completely or partially be located at the physics battle array of Logical tile The periphery of column is placed or is fully located inside it outside.(see, for example, Fig. 8 A- Fig. 8 E).As described above, in the object of Logical tile In the case that reason array includes multiple virtual arrays, virtual array may include the physical logic tile of identical or different quantity, And can the physical array in any way about the Logical tile of programmable/configurable logic circuit system carry out tissue. All combination and displacement are intended to fall in the scope of the present invention.With reference to Fig. 8 A- Fig. 8 E, although being not shown, (one or more It is a) virtual array can (i) receive separation/different clock signal and/or common clock signal, (ii) includes isolated outside I/O (communicate with the circuit system outside FPGA) and (iii) lead to each other via virtual i/o and/or switch matrix interference networks Believe (see, for example, Fig. 2 B- Fig. 2 D and description associated therewith).

In addition, not being to show I/O in all exemplary embodiments of attached drawing (for example, exterior I/O for the sake of clarity And virtual i/o), clock characteristics and/or memory.However, in order to avoid the described herein and exemplary embodiment (example that shows Such as, Fig. 3 A- Fig. 3 C, Fig. 4 A- Fig. 4 D and Fig. 8 A- Fig. 8 E) any I/O framework/embodiment described and illustrated herein can be used (see, for example, Fig. 1 C, Fig. 1 D, Fig. 2 B- Fig. 2 D and Fig. 7 B), the switched fabric network architecture/embodiment (see, for example, Fig. 7 A), Clock architecture/embodiment (see, for example, Fig. 2 B- Fig. 2 D, Fig. 5 A and Fig. 5 B) and/or memory architecture/embodiment are (referring to example Such as, Fig. 2 B- Fig. 2 D and Fig. 7 C).

It is worth noting that, CAD can be used in various circuits, circuit system and technology disclosed herein Tool describes, and in its behavior, register transmitting, logic module, transistor, layout geometries and/or other characteristics Aspect expression (or expression) is the data and/or instruction embodied in various computer-readable mediums.May be implemented this circuit, Circuit system, place and route expression file and other objects format include but is not limited to support such as C, Verilog and The format of the behavior language of HLDL etc, the format of the register stage description language of support RTL etc, and support such as GDSII, The format of the geometry description language of GDSIII, GDSIV, CIF, MEBES etc and times that be currently known or developing later What its format and/or language.The computer-readable medium that this format data and/or instruction can be embodied includes but unlimited In various formats non-volatile memory medium (for example, optics, magnetism or semiconductor storage medium) and can be used for passing through nothing Line, optics or wired signaling media or any combination thereof transmit the carrier wave of this format data and/or instruction.Pass through carrier wave Transmit this format data and/or instruction example include but is not limited to via one or more data-transfer protocols (for example, HTTP, FTP, SMTP etc.) transmitting (upload, download, Email etc.) on internet and/or other computer networks.

In fact, when the time receiving is inscribed in computer system via one or more computer-readable mediums, foregoing circuit This expression based on data and/or instruction can be by the processing entities in computer system (for example, one or more handled Device) it is handled in conjunction with one or more of the other computer program is carried out, other computer programs include but is not limited to that netlist generates Program, placement and wired program etc., with generate this circuit physical behavior indicate or image.Hereafter, for example, pass through so that The one or more masks for the various assemblies for being used to form circuit can be generated in device manufacturing processes, can be manufactured in device It is middle to use this expression or image.

In addition it is possible to use CAD and/or testing tool indicate disclosed herein various via emulation Circuit, circuit system and technology.The emulation of the circuit of realization, circuit system, place and route and/or technology is it is possible thereby to by counting Calculation machine system realize, wherein via computer system simulation, duplication and/or prediction be achieved in this circuit, circuit system, The characteristic and operation of layout and technology.The invention further relates to these of the circuit of the present invention, circuit system and/or the technology that are achieved in Kind emulation, and it is intended that fall within the scope of the present invention.Corresponding to it is this emulation and/or testing tool it is computer-readable Medium, which is also intended to, to be fallen within the scope of the present invention.

Mean to retouch about the embodiment it is worth noting that, " one embodiment " or " embodiment " (or similar) is mentioned above The a particular feature, structure, or characteristic stated can be included, using and/or be incorporated in one, Yi Xiehuo of the embodiment of the present invention In whole.The use of the phrase " in one embodiment " or " in another embodiment " (or similar) in this specification goes out Identical embodiment is not referred to now, nor the necessarily mutually exclusive separation of one or more of the other embodiment or substitution Embodiment is also not necessarily limited to single exclusiveness embodiment.This is equally applicable to term " embodiment ".The present invention neither limited to appoint What single aspect is also not necessarily limited to embodiment, is also not necessarily limited to any combination and/or displacement of these aspects and/or embodiment.This Outside, each aspect of the invention and/or embodiment can individually use or with one or more of the other aspect of the invention and/ Or embodiment is applied in combination.For brevity, it does not separate discussion herein and/or certain displacements and combination is shown.

In addition, as described above, being described herein as the embodiment of " exemplary " or embodiment is not necessarily to be construed as such as phase It is ideal, preferred or advantageous for other embodiments or embodiment；On the contrary, it be intended to convey or indicate embodiment or Multiple embodiments are (one or more) example embodiments.

It is many other to those skilled in the art although describing the present invention in certain specific aspects Modifications and variations are apparent.It should therefore be understood that without departing from the scope and spirit of the present invention, it can be with not The mode for being same as specifically describing implements the present invention.Therefore, the embodiment of the present invention should be considered as illustrating in all respects Property/illustrative rather than restrictive.

It is worth noting that, term " includes ", " including ", "comprising", " including ", " having " and " having " or its is any Other modifications are intended to cover non-exclusive inclusion, so that process, method, circuit, article or equipment including element list are not Only include those elements, and may include not expressly listed or other members that this process, method, article or equipment are intrinsic Part.In addition, the use of term " connection ", " connected ", " being connected to " or " connection " should be construed broadly in entire this document It is to include directly or indirectly (for example, via one or more conductors and/or intermediary device/element (active or passive) and/or warp By inductance or capacitive coupling)), unless otherwise indicated (for example, using term " being directly connected to " or " being directly connected ").

The term " first " of this paper, " second " etc. do not indicate any sequence, quantity or importance, but are used for a member Part is distinguished with another element.In addition, term " one (a) " and " one (an) " herein does not indicate the limitation of quantity, and It is to indicate that there are the projects cited at least one.

In addition, term " Logical tile " means the design cell or block of multiple transistors (being typically more than thousands of), it is multiple Transistor is connected or is configured to such as programmable component (for example, programmable logic components), in this application, Logical tile energy Enough it is connected to one or more adjacent " Logical tiles ".Term (i) " integrated circuit " means processor, control apart from the others Device, state machine, gate array, SOC, PGA and/or FPGA.

In addition, term " circuit system " mean apart from the others circuit (either integrated or other), one group this The circuit of sample, one or more processors, one or more state machines, the one or more processors for realizing software, one or Multiple gate arrays, programmable gate array and/or field programmable gate array, or one or more circuits (either integrated Or it is other), one or more state machines, one or more processors, the one or more processors for realizing software, one Or the combination of multiple gate arrays, programmable gate array and/or field programmable gate array.Term " data " means apart from the others (one or more) current or voltage signal (plural number or odd number), either analog form or digital form, can be single Bit (or similar) or multiple bits (or similar).In addition, term " initialization operation " means that (or it is deposited in robust type memory portion Storage element) and/or integrated circuit power on, start, initializing, reinitializing, configure and/or reconfigure operation.Term Data processing operation mean include Digital Signal Processing, coding, decoding, encryption, decryption and/or other forms data processing Operation.