阅读说明：本技术 一种一步1.5位逐次逼近型模数转换器 (A kind of 1.5 gradual approaching A/D converters of a step ) 是由 李登全 刘云鹏 刘马良 朱樟明 丁瑞雪 杨银堂 于 2019-07-12 设计创作，主要内容包括：本发明属于模数转换器领域,具体涉及一种一步1.5位逐次逼近型模数转换器,包括：自举开关、开关电容阵列、比较器组、异步时钟产生电路、控制逻辑电路、寄存器、译码器。本发明通过采用自举开关、开关电容阵列、比较器组、异步时钟产生电路、控制逻辑电路、寄存器、译码器相构成的模数转换器,可以通过对量化结果进行自纠正,使得本申请具有比较周期短、转换速率快、转换精度高的有益效果。(The invention belongs to analog-digital converter fields, and in particular to 1.5 gradual approaching A/D converters of an a kind of step, comprising: bootstrapped switch, switched capacitor array, comparator group, asynchronous clock generation circuit, control logic circuit, register, decoder.The analog-digital converter that the present invention is mutually constituted by using bootstrapped switch, switched capacitor array, comparator group, asynchronous clock generation circuit, control logic circuit, register, decoder, it can be by carrying out self-correction to quantized result, so that the application has the beneficial effect that compares cycle is short, conversion rate is fast, conversion accuracy is high.)

1. a kind of 1.5 gradual approaching A/D converters of a step characterized by comprising bootstrapped switch, switching capacity battle array Column, comparator group, asynchronous clock generation circuit, control logic circuit, register, decoder；

The input terminal of the bootstrapped switch is connect with the analog signal output；The input terminal of the switched capacitor array and institute The output end connection of bootstrapped switch is stated, the output end of the switched capacitor array is connect with the input terminal of the comparator group；Institute The first output end for stating comparator group is connect with the input terminal of the asynchronous clock generation circuit, and the second of the comparator group is defeated Outlet is connect with the input terminal of the control logic circuit；The output end of the asynchronous clock generation circuit and the comparator group Clock signal input terminal connection；First output end of the control logic circuit is connect with the input terminal of the register, institute The second output terminal for stating control logic circuit is connect with the control signal input of the switched capacitor array；The register Output end is connect with the input terminal of the decoder；The output end output digit signals of the decoder.

2. 1.5 gradual approaching A/D converters according to claim 1, which is characterized in that the switching capacity battle array Column include the first sub switch capacitor array, the second sub switch capacitor array, third sub switch capacitor array and the 4th sub switch electricity Hold array；

The first sub switch capacitor array, the second sub switch capacitor array, the third sub switch capacitor array and institute The signal input part for stating the 4th sub switch capacitor array is connect with the output end of the bootstrapped switch；The first sub switch capacitor Array, the second sub switch capacitor array, the third sub switch capacitor array and the 4th sub switch capacitor array Control signal input is connect with the second output terminal of the control logic circuit.

3. 1.5 gradual approaching A/D converters according to claim 2, which is characterized in that the sub switch capacitor Array includes specific capacitance (C_R) and parallel connection weighted capacitors group (C₁、C₂、C₃…C_N+2(N-4)), N >=4；

Specific capacitance (the C_R) and the sub switch capacitor array weighted capacitors group (C₁、C₂、C₃…C_N+2(N-4), N >=4) Top crown be all connected with the output end of the sub switch capacitor array；Weighted capacitors group (the C₁、C₂、C₃…C_N+2(N-4), N >= 4) non-moving end of bottom crown connection single-pole double-throw switch (SPDT) group, the single-pole double-throw switch (SPDT) group selection connect external power supply (VDD) and ground terminal (GND)；Specific capacitance (the C_R) bottom crown meet common mode reference voltage end (VCM)；The single-pole double throw The control signal input of switch is connect with the second output terminal of the control logic circuit.

4. 1.5 gradual approaching A/D converters according to claim 1, which is characterized in that the comparator group packet Include first comparator, the second comparator, third comparator, the 4th comparator, the 5th comparator；

The clock signal input terminal of the first comparator and the 5th comparator is connect with ground terminal (GND), and described second compares Device, third comparator, the 4th comparator clock signal input terminal connect with the output end of the asynchronous clock generation circuit；

The first input end of the first comparator is connect with the output end of the switched capacitor array, the first comparator Second input terminal is for inputting external common-mode reference voltage (VCM)；

The first input end and the second input terminal of second comparator are connect with the output end of the switched capacitor array；

The first input end of the third comparator is connect with the output end of the switched capacitor array with the second input terminal；

The first input end of 4th comparator is connect with the output end of the switched capacitor array with the second input terminal；

The first input end of 5th comparator is used to input external common-mode reference voltage (VCM), the 5th comparator Second input terminal is connect with the output end of the switched capacitor array.

5. 1.5 gradual approaching A/D converters according to claim 1, which is characterized in that the asynchronous clock produces Raw circuit includes the first nor gate, the second nor gate and the first NAND gate；

First input end, the second input terminal of first nor gate are all connected with the first output end of the comparator group；It is described The first input end of first NAND gate is connect with the output end of first nor gate, the second input terminal of first NAND gate It inputs external sampling clock inversion signal (CSN)；The first input end of second nor gate is defeated with first NAND gate Second input terminal of outlet connection, second nor gate inputs external sampling clock signal (CS).

6. 1.5 gradual approaching A/D converters according to claim 1, which is characterized in that the control logic electricity Road includes 2N-2 control logic unit, i.e. the first control logic unit, the second control logic unit ... 2N-2 control logic Unit, N >=4；

The first control logic unit, the second control logic unit ... N-1 control logic are unit cascaded；The N control Logic unit, N+1 control logic unit ... 2N-3 control logic are unit cascaded.

7. 1.5 gradual approaching A/D converters according to claim 1, which is characterized in that the control logic list Member includes PMOS tube PM1, PM2, PM3, PM4, PM5, PM6, PM7, NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8 With the second NAND gate, the first phase inverter (I1), the second phase inverter (I2), third phase inverter (I3), the 4th phase inverter (I4)；

The source grounding of described NMOS tube NM3, NM5, NM7, NM8；The PMOS tube PM1, PM2, PM3, PM4, PM5, PM6, The source electrode of PM7 inputs external power supply (VDD)；The second output terminal of the grid of NMOS tube NM1, NM6 and the comparator group Connection；The source electrode of the NMOS tube M1 connects the drain electrode of the NMOS tube NM3, described in the drain electrode connection of the NMOS tube NM1 The source electrode of NMOS tube NM2；The grid of the NMOS tube NM3 connects the grid of the NMOS tube NM5；The leakage of the NMOS tube NM5 Pole connects the source electrode of the NMOS tube NM6；The drain electrode of the NMOS tube NM6 is connect with the source electrode of the NMOS tube NM4；It is described The grid of NMOS tube NM2 is connect with the grid of the NMOS tube NM4, and the drain electrode of the NMOS tube NM4 is with the PMOS tube PM2's The output end of drain electrode connection, the grid intersection point and adjacent upper level control logic unit of the NMOS tube NM2 and NMOS tube NM4 connects It connects；The drain electrode of the NMOS tube NM2 is connect with the drain electrode of the PMOS tube PM1；The grid and the PMOS of the PMOS tube PM1 The grid of pipe PM2 connects, and the grid of the PMOS tube PM1 connect intersection point with the grid of the PMOS tube PM2 and also inputs outside Portion's sampling clock inversion signal (CSN))；The drain electrode of the grid of the PMOS tube PM3 and the PMOS tube PM1 and NMOS tube NM2 Drain electrode intersection point connection；The grid of the PMOS tube PM4 and the drain electrode of the PMOS tube PM2 and the drain electrode intersection point of NMOS tube NM4 Connection, the PMOS tube PM3 connect the drain electrode of the PMOS tube PM4, and with the input terminal of first phase inverter (I1) and institute State the drain electrode connection of NMOS tube NM7；The grid of the NMOS tube NM7 inputs external sampling clock signal (CS)；Described first is anti- The output end of phase device (I1) is separately connected the grid of the PMOS tube PM5 and the grid of NMOS tube NM8；The PMOS tube PM5 with The grid of NMOS tube NM8 connects, and the drain electrode of the PMOS tube PM5 is connect with the source electrode of the PMOS tube PM6；Described second with it is non- Two input terminals of door pass through third phase inverter (I3) respectively and the 4th reverser (I4) connects the output end of the comparator group, The output end of second NAND gate is connect with the grid of the PMOS tube PM6, the drain electrode of the NMOS tube NM8 and the PMOS The drain electrode of pipe PM6 connects；The previous control logic unit passes through the PMOS in the control logic unit of adjacent two Pipe PM6 connect NMOS tube NM2, the NM4 grid of the latter control logic unit with the drain electrode intersection point of the NMOS tube NM8 Intersection point；The grid of the PMOS tube PM7 is connect with the drain electrode of the PMOS tube PM8, the drain electrode of the PMOS tube PM7 and described the The input terminal of two phase inverters (I2) connects, and the control of the output end and the switched capacitor array of second phase inverter (I2) is believed The connection of number input terminal；The drain electrode of the grid of the PMOS tube PM8 and the PMOS tube PM7, second phase inverter (I2) it is defeated Enter end connection；The output end of first phase inverter (I1) is also connected with the grid intersection point of the NMOS tube NM3 and NMOS tube NM5； The drain electrode of the PMOS tube PM1 connect intersection point with the drain electrode of the NMOS tube NM2 and connect PMOS tube with the PMOS tube PM7 grid The intersection point of PM8 drain electrode；The drain electrode of the PMOS tube PM2 and the drain electrode connection intersection point of NMOS tube NM4 connect the PMOS tube PM7's Drain electrode connect intersection point with the grid of PMOS tube PM8；The grid of the PMOS tube PM3 connect the PMOS tube PM7 grid with it is described PMOS tube PM8 drain electrode intersection point, the grid of the PMOS tube PM4 connect the PMOS tube PM7 drain electrode and the PMOS tube PM8 Grid connect intersection point.

8. 1.5 gradual approaching A/D converters according to claim 1, which is characterized in that the register includes First enable signal input terminal of 2N-2 d type flip flop and the 5th phase inverter (I5), the d type flip flop inputs external sampling signal (CS), the second enable signal input terminal of the d type flip flop inputs external sampling clock signal by the 5th phase inverter (I5) (CS), the signal input part of the d type flip flop is connect with the output end of the control logic circuit.

9. 1.5 gradual approaching A/D converters according to claim 1, which is characterized in that the decoder includes First half adder, the second half adder, the first~the N-1 full adder, the first~the N-2 and door and the 5th NOT gate I5~N+1 are non- Door IN+1, N >=4；

Described first is connect by the 5th NOT gate I5 with the register with the first input end of door, and described first with door Second input terminal is connect with the register；The first input end of the N-2 and door is posted by N+1 NOT gate IN+1 with described Second input terminal of storage connection, the N-2 and door is connect with the register；The input terminal of first full adder connects The first input end of the output end of the register, the second~the N-1 full adder connects the output end of the register；Institute The first output end for stating the first full adder is connect with the first input end of first half adder, and the second of first half adder Input terminal connects ground terminal (GND), the first input end of the second output terminal of first full adder and second half adder Connection, the second input terminal of second half adder are connect with the output end of the N-2 and door；The N-2 and door it is defeated Outlet is connect with the second input terminal of the N-1 full adder；The output end of the first~N-3 and door respectively with the N- Second input terminal of 3~bis- full adders connects, the N-2 full adder, N-1 full adder the second input terminal be all connected with ground connection It holds (GND).

Technical field

The invention belongs to analog-digital converter fields, and in particular to a kind of 1.5 gradual approaching A/D converters of a step.

Background technique

Gradual approaching A/D converter (SAR ADC, successive approximation register Analog To Digital), it is constantly to be quantified to the input signal after sampling in conversion process each time using binary chop Approach, so that the continuous approaching simulation signal of digital code, finally obtains the digital signal to be exported.Since successive approximation modulus turns The advantages that structure of parallel operation is simple, low in energy consumption, therefore, gradual approaching A/D converter is in wearable device and medical instrument etc. Low-power consumption demand field is widely adopted.Portable medical imaging system has been integrated with multi-functional such as X-ray, ultrasonic wave On SoC (System on Chip, system on chip), it is desirable that analog-digital converter have low-power consumption, resolution ratio between 9 to 12, Sample rate is more than 400MS/s.

It is limited to the structure of single comparator, conventional successive is approached type analog-to-digital converter and can only be measured in each compares cycle Change 1 digit numeric code, referred to as 1-bit/cycle gradual approaching A/D converter.The successive approximation modulus of one N precision turns Parallel operation at least needs N number of compares cycle, and conversion rate is very restricted.The conventional successive approach type modulus in quantizing process Converter can not carry out self-correction to wrong quantized result, and resolution ratio is very limited.

Summary of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a kind of 1.5 successive approximations of a step Analog-digital converter.The technical problem to be solved in the present invention is achieved through the following technical solutions:

1.5 gradual approaching A/D converters of an a kind of step, comprising: bootstrapped switch, switched capacitor array, comparator Group, asynchronous clock generation circuit, control logic circuit, register, decoder；

The input terminal of the bootstrapped switch is connect with the analog signal output；The input terminal of the switched capacitor array It is connect with the output end of the bootstrapped switch, the input terminal of the output end of the switched capacitor array and the comparator group connects It connects；First output end of the comparator group is connect with the input terminal of the asynchronous clock generation circuit, the comparator group Second output terminal is connect with the input terminal of the control logic circuit；The output end of the asynchronous clock generation circuit and the ratio Clock signal input terminal compared with device group connects；First output end of the control logic circuit and the input terminal of the register connect It connects, the second output terminal of the control logic circuit is connect with the control signal input of the switched capacitor array；It is described to post The output end of storage is connect with the input terminal of the decoder；The output end output digit signals of the decoder.

In one embodiment of the invention, the switched capacitor array includes four identical sub switch capacitor arrays, That is the first sub switch capacitor array, the second sub switch capacitor array, third sub switch capacitor array and the 4th sub switch capacitor battle array Column；

The first sub switch capacitor array, the second sub switch capacitor array, the third sub switch capacitor array It is connect with the signal input part of the 4th sub switch capacitor array with the output end of the bootstrapped switch；First sub switch Capacitor array, the second sub switch capacitor array, the third sub switch capacitor array and the 4th sub switch capacitor battle array The control signal input of column is connect with the second output terminal of the control logic circuit.

In one embodiment of the invention, the sub switch capacitor array includes specific capacitance C_RWith adding for parallel connection Weigh capacitor group (C₁、C₂、C₃…C_N+2(N-4), N >=4)；The specific capacitance C_RWith the weighted capacitance of the sub switch capacitor array Device group (C₁、C₂、C₃…C_N+2(N-4), N >=4) top crown be all connected with the output end of the sub switch capacitor array；The weighting electricity Container group (C₁、C₂、C₃…C_N+2(N-4), N >=4) bottom crown connection single-pole double-throw switch (SPDT) group non-moving end, the single-pole double throw opens It closes group selection and connects external power supply VDD and ground terminal GND；The specific capacitance C_RBottom crown connect common mode reference voltage end VCM；The control signal input of the single-pole double-throw switch (SPDT) is connect with the second output terminal of the control logic circuit.

In one embodiment of the invention, the comparator group includes that first comparator, the second comparator, third compare Device, the 4th comparator, the 5th comparator；

The clock signal input terminal of the first comparator and the 5th comparator is connect with ground terminal GND, second ratio Clock signal input terminal compared with device, third comparator, the 4th comparator connects with the output end of the asynchronous clock generation circuit It connects；

The first input end of the first comparator is connect with the output end of the switched capacitor array, and described first compares Second input terminal of device is for inputting external common-mode reference voltage VCM；

The first input end and the second input terminal of second comparator connect with the output end of the switched capacitor array It connects；

The first input end and the second input terminal of the third comparator connect with the output end of the switched capacitor array It connects；

The first input end and the second input terminal of 4th comparator connect with the output end of the switched capacitor array It connects；

The first input end of 5th comparator is for inputting external common-mode reference voltage VCM, the 5th comparator The second input terminal connect with the output end of the switched capacitor array.

In one embodiment of the invention, the asynchronous clock generation circuit includes the first nor gate, the second nor gate With the first NAND gate；

First input end, the second input terminal of first nor gate are all connected with the first output end of the comparator group； The first input end of first NAND gate is connect with the output end of first nor gate, and the second of first NAND gate is defeated Enter end input external sampling clock inversion signal CSN；The first input end of second nor gate and first NAND gate Second input terminal of output end connection, second nor gate inputs external sampling clock signal CS.

In one embodiment of the invention, the control logic circuit includes 2N-2 control logic unit, i.e., and first Control logic unit, the second control logic unit ... 2N-2 control logic unit, N >=4；

The first control logic unit, the second control logic unit ... N-1 control logic are unit cascaded；The N Control logic unit, N+1 control logic unit ... 2N-3 control logic are unit cascaded.

In one embodiment of the invention, the control logic unit include PMOS tube PM1, PM2, PM3, PM4, PM5, PM6, PM7, NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8 and the second NAND gate, the first phase inverter I1, second are instead Phase device I2, third phase inverter I3, the 4th phase inverter I4；

The source grounding of described NMOS tube NM3, NM5, NM7, NM8；The PMOS tube PM1, PM2, PM3, PM4, PM5, The source electrode of PM6, PM7 input external power supply VDD；Second output of the grid of NMOS tube NM1, NM6 and the comparator group End connection；The source electrode of the NMOS tube M1 connects the drain electrode of the NMOS tube NM3, described in the drain electrode connection of the NMOS tube NM1 The source electrode of NMOS tube NM2；The grid of the NMOS tube NM3 connects the grid of the NMOS tube NM5；The leakage of the NMOS tube NM5 Pole connects the source electrode of the NMOS tube NM6；The drain electrode of the NMOS tube NM6 is connect with the source electrode of the NMOS tube NM4；It is described The grid of NMOS tube NM2 is connect with the grid of the NMOS tube NM4, and the drain electrode of the NMOS tube NM4 is with the PMOS tube PM2's The output end of drain electrode connection, the grid intersection point and adjacent upper level control logic unit of the NMOS tube NM2 and NMOS tube NM4 connects It connects；The drain electrode of the NMOS tube NM2 is connect with the drain electrode of the PMOS tube PM1；The grid and the PMOS of the PMOS tube PM1 The grid of pipe PM2 connects, and the grid of the PMOS tube PM1 connect intersection point with the grid of the PMOS tube PM2 and also inputs outside Portion sampling clock inversion signal CSN；The grid of the PMOS tube PM3 and the drain electrode of the PMOS tube PM1 and the leakage of NMOS tube NM2 The connection of pole intersection point；The grid of the PMOS tube PM4 is connect with the drain electrode intersection point of the drain electrode of the PMOS tube PM2 and NMOS tube NM4, The PMOS tube PM3 connects the drain electrode of the PMOS tube PM4, and with the input terminal of the first phase inverter I1 and the NMOS tube The drain electrode of NM7 connects；The grid of the NMOS tube NM7 inputs external sampling clock signal CS；The first phase inverter I1's is defeated Outlet is separately connected the grid of the PMOS tube PM5 and the grid of NMOS tube NM8；The grid of the PMOS tube PM5 and NMOS tube NM8 Pole connection, the drain electrode of the PMOS tube PM5 are connect with the source electrode of the PMOS tube PM6；Two inputs of second NAND gate End connects the output end of the comparator group by third phase inverter I3 and the 4th reverser I4 respectively, second NAND gate Output end is connect with the grid of the PMOS tube PM6, and the drain electrode of the NMOS tube NM8 is connect with the drain electrode of the PMOS tube PM6； The previous control logic unit passes through the PMOS tube PM6 and the NMOS tube in the control logic unit of adjacent two The drain electrode intersection point of NM8 connects NMOS tube NM2, the NM4 grid intersection point of the latter control logic unit；The PMOS tube The grid of PM7 is connect with the drain electrode of the PMOS tube PM8, and draining for the PMOS tube PM7 is defeated with the second phase inverter I2 Enter end connection, the output end of the second phase inverter I2 is connect with the control signal input of the switched capacitor array；It is described The grid of PMOS tube PM8 is connect with the input terminal of the drain electrode of the PMOS tube PM7, the second phase inverter I2；Described first is anti- The output end of phase device I1 is also connected with the grid intersection point of the NMOS tube NM3 and NMOS tube NM5；The drain electrode of the PMOS tube PM1 with The drain electrode connection intersection point of the NMOS tube NM2 connect the intersection point of PMOS tube PM8 drain electrode with the PMOS tube PM7 grid；It is described The drain electrode of PMOS tube PM2 and the drain electrode connection intersection point of NMOS tube NM4 connect the drain electrode of the PMOS tube PM7 with PMOS tube PM8's Grid connects intersection point；The grid of the PMOS tube PM3 connects the friendship of the PMOS tube PM7 grid and PMOS tube PM8 drain electrode Point, the drain electrode that the grid of the PMOS tube PM4 connects the PMOS tube PM7 connect intersection point with the grid of the PMOS tube PM8.

In one embodiment of the invention, the register includes 2N-2 d type flip flop and the 5th phase inverter I5, described First enable signal input terminal of d type flip flop inputs external sampling signal CS, the second enable signal input terminal of the d type flip flop External sampling clock signal CS, the signal input part of the d type flip flop and the control logic are inputted by the 5th phase inverter I5 The output end of circuit connects.

In one embodiment of the invention, the decoder includes the first half adder, the second half adder, the first~the N- 1 full adder, the first~the N-2 and door and the 5th NOT gate I5~N+1 NOT gate IN+1, N >=4；

Described first is connect by the 5th NOT gate I5 with the register with the first input end of door, described first with Second input terminal of door is connect with the register；The first input end of the N-2 and door passes through N+1 NOT gate IN+1 and institute It states register to connect, the second input terminal of the N-2 and door is connect with the register；The input terminal of first full adder The output end of the register is connected, the first input end of the second~the N-1 full adder connects the output of the register End；First output end of first full adder is connect with the first input end of first half adder, first half adder The second input terminal connect ground terminal GND, the first of the second output terminal of first full adder and second half adder is defeated Enter end connection, the second input terminal of second half adder is connect with the output end of the N-2 and door；The N-2 and door Output end connect with the second input terminal of the N-1 full adder；The output end of the first~N-3 and door respectively with it is described Second input terminal of the full adder of N-3~bis- connects, the N-2 full adder, N-1 full adder the second input terminal be all connected with Ground terminal GND.

Beneficial effects of the present invention:

The present invention is patrolled by using bootstrapped switch, switched capacitor array, comparator group, asynchronous clock generation circuit, control The analog-digital converter that circuit, register, decoder are mutually constituted is collected, it can be by carrying out self-correction to quantized result, so that this Shen There please be the beneficial effect that compares cycle is short, conversion rate is fast, conversion accuracy is high.

The present invention is described in further details below with reference to accompanying drawings and embodiments.

Detailed description of the invention

Fig. 1 is 1.5 gradual approaching A/D converter structural block diagrams of an a kind of step provided in an embodiment of the present invention；

Fig. 2 is a kind of switching capacity battle array of 1.5 gradual approaching A/D converters of a step provided in an embodiment of the present invention Column circuits figure；

Fig. 3 is a kind of comparator group electricity of 1.5 gradual approaching A/D converters of a step provided in an embodiment of the present invention Lu Tu；

When Fig. 4 is a kind of comparator group of 1.5 gradual approaching A/D converters of a step provided in an embodiment of the present invention Zhong Tu；

Fig. 5 is that a kind of asynchronous clock of 1.5 gradual approaching A/D converters of a step provided in an embodiment of the present invention produces Raw circuit circuit diagram；

Fig. 6 is a kind of control logic electricity of 1.5 gradual approaching A/D converters of a step provided in an embodiment of the present invention Line structure schematic diagram；

Fig. 7 is a kind of control logic list of 1.5 gradual approaching A/D converters of a step provided in an embodiment of the present invention First circuit diagram；

Fig. 8 is a kind of register architecture of 1.5 gradual approaching A/D converters of a step provided in an embodiment of the present invention Schematic diagram；

Fig. 9 is a kind of decoder architecture of 1.5 gradual approaching A/D converters of a step provided in an embodiment of the present invention Schematic diagram.

Specific embodiment

Further detailed description is done to the present invention combined with specific embodiments below, but embodiments of the present invention are not limited to This.

Referring to Figure 1, Fig. 1 is 1.5 gradual approaching A/D converter knots of an a kind of step provided in an embodiment of the present invention Structure block diagram, comprising: bootstrapped switch, switched capacitor array, comparator group, asynchronous clock generation circuit, control logic circuit, deposit Device, decoder；

The input terminal of the bootstrapped switch is connect with the analog signal output；The input terminal of the switched capacitor array It is connect with the output end of the bootstrapped switch, the input terminal of the output end of the switched capacitor array and the comparator group connects It connects；First output end of the comparator group is connect with the input terminal of the asynchronous clock generation circuit, the comparator group Second output terminal is connect with the input terminal of the control logic circuit；The output end of the asynchronous clock generation circuit and the ratio Clock signal input terminal compared with device group connects；First output end of the control logic circuit and the input terminal of the register connect It connects, the second output terminal of the control logic circuit is connect with the control signal input of the switched capacitor array；It is described to post The output end of storage is connect with the input terminal of the decoder, the output end output digit signals of the decoder.

The present invention is patrolled by using bootstrapped switch, switched capacitor array, comparator group, asynchronous clock generation circuit, control The analog-digital converter that circuit, register, decoder are mutually constituted is collected, it can be by carrying out self-correction to quantized result, so that this Shen There please be the beneficial effect that compares cycle is short, conversion rate is fast, conversion accuracy is high.

In one embodiment of the invention, the switched capacitor array includes four identical sub switch capacitor arrays, That is the first sub switch capacitor array, the second sub switch capacitor array, third sub switch capacitor array and the 4th sub switch capacitor battle array Column；

The first sub switch capacitor array, the second sub switch capacitor array, the third sub switch capacitor array It is connect with the signal input part of the 4th sub switch capacitor array with the output end of the bootstrapped switch；First sub switch Capacitor array, the second sub switch capacitor array, the third sub switch capacitor array and the 4th sub switch capacitor battle array The control signal input of column is connect with the second output terminal of the control logic circuit.

In one embodiment of the invention, the sub switch capacitor array includes specific capacitance C_RWith adding for parallel connection Weigh capacitor group (C₁、C₂、C₃…C_N+2(N-4), N >=4)；The specific capacitance C_RWith the weighted capacitance of the sub switch capacitor array Device group (C₁、C₂、C₃…C_N+2(N-4), N >=4) top crown be all connected with the output end of the sub switch capacitor array；The weighting electricity Container group (C₁、C₂、C₃…C_N+2(N-4), N >=4) bottom crown connection single-pole double-throw switch (SPDT) group non-moving end, the single-pole double throw opens It closes group selection and connects external power supply VDD and ground terminal GND；The specific capacitance C_RBottom crown connect common mode reference voltage end VCM；The control signal input of the single-pole double-throw switch (SPDT) is connect with the second output terminal of the control logic circuit.

Further, Fig. 2 is referred to, Fig. 2 is 1.5 successive approximation moduluses of an a kind of step provided in an embodiment of the present invention The switched capacitor array circuit figure of converter, the input terminal of the first sub switch capacitor array and the input terminal of the sub- capacitor array of third The positive phase signals of input difference analog signal, the input terminal of the second sub switch capacitor array and the input terminal of the 4th sub- capacitor array The inversion signal of input difference analog signal；First sub switch capacitor array, the second sub switch capacitor array, third sub switch electricity Hold array and the 4th sub switch capacitor array is sequentially output output signal VP1, output signal VN1, output signal VP2 and output letter Number VN2；After first compares cycle, as output signal VP1 > VN1, generating a thermometer-code is 1, is patrolled in control It collects under circuit control, C in the first sub switch capacitor array₁₀₁、C₁₀₂Bottom crown respectively from power end VDD, ground terminal GND set To ground terminal GND, ground terminal GND；C in second sub switch capacitor array₂₀₁、C₂₀₂Bottom crown respectively from ground terminal GND, power supply End VDD is set to power end VDD, power end VDD；C in third sub switch capacitor array₃₀₁、C₃₀₂Bottom crown respectively from ground connection End GND, power end VDD are set to ground terminal GND, ground terminal GND；C in 4th sub switch capacitor array₄₀₁、C₄₀₂Bottom crown Power end VDD, power end VDD are set to from power end VDD, ground terminal GND respectively；If VP1 < VN1, a thermometer-code is generated It is 0, under control logic circuit control, C in the first sub switch capacitor array₁₀₁、C₁₀₂Bottom crown respectively from VDD, GND set To VDD, VDD, C in the second sub switch capacitor array₂₀₁、C₂₀₂Bottom crown be set to GND, GND, third from GND, VDD respectively C in sub switch capacitor array₃₀₁、C₃₀₂Bottom crown be set to VDD, VDD, the 4th sub switch capacitor array from GND, VDD respectively Middle C₄₀₁、C₄₀₂Bottom crown be set to GND, GND from VDD, GND respectively.

After second compares cycle, as VP1 > VN1, VP2 > VN2, generating two thermometer-codes is 11, is being controlled Under logic circuit control, C in the first sub switch capacitor array₁₀₃、C₁₀₄、C₁₀₅Bottom crown respectively from power end VDD, ground terminal GND, ground terminal GND are set to ground terminal GND, ground terminal GND, ground terminal GND；C203 in second sub switch capacitor array, C204、C₂₀₅Bottom crown respectively from ground terminal GND, power end VDD, power end VDD be set to power end VDD, power end VDD, Power end VDD；C in third sub switch capacitor array₃₀₃、C₃₀₄、C₃₀₅Bottom crown respectively from ground terminal GND, power end VDD, electricity Source VDD is set to ground terminal GND, ground terminal GND, power end VDD；C in 4th sub switch capacitor array₄₀₃、C₄₀₄、C₄₀₅'s Bottom crown is set to power end VDD, power end VDD, power end VDD from power end VDD, ground terminal GND, ground terminal GND respectively； If VP1<VN1, VP2>VN2, generating two thermometer-codes is 01, under logic control circuit control, the first sub switch capacitor battle array C in column₁₀₃、C₁₀₄、C₁₀₅Bottom crown be set to power end VDD, electricity from power end VDD, ground terminal GND, ground terminal GND respectively Source VDD, ground terminal GND, C in the second sub switch capacitor array₂₀₃、C₂₀₄、C₂₀₅Bottom crown respectively from ground terminal GND, power supply End VDD, power end VDD are set to ground terminal GND, ground terminal GND, power end VDD, C in third sub switch capacitor array₃₀₃、 C₃₀₄、C₃₀₅Bottom crown respectively from ground terminal GND, power end VDD, power end VDD be set to ground terminal GND, ground terminal GND, Power end VDD, C in the 4th sub switch capacitor array₄₀₃、C₄₀₄、C₄₀₅Bottom crown respectively from power end VDD, ground terminal GND, connect Ground terminal GND is set to power end VDD, power end VDD, ground terminal GND；If VP1 < VN1, VP2 < VN2 generate two thermometers Code 00, under control logic circuit control, C in the first sub switch capacitor array₁₀₃、C₁₀₄、C₁₀₅Bottom crown respectively from power end VDD, ground terminal GND, ground terminal GND are set to power end VDD, power end VDD, power end VDD；Second sub switch capacitor array Middle C₂₀₃、C₂₀₄、C₂₀₅Bottom crown respectively from ground terminal GND, power end VDD, power end VDD be set to ground terminal GND, ground connection Hold GND, ground terminal GND；C in third sub switch capacitor array₃₀₃、C₃₀₄、C₃₀₅Bottom crown respectively from ground terminal GND, power end VDD, power end VDD are set to power end VDD, power end VDD, power end VDD；C in 4th sub switch capacitor array₄₀₃、C₄₀₄、 C₄₀₅Bottom crown respectively from power end VDD, ground terminal GND, ground terminal GND be set to ground terminal GND, ground terminal GND, ground connection Hold GND.

In third compares cycle into the 6th compares cycle, control logic circuit is changed according to the comparison result of comparator Signal is controlled, control signal changes capacitor C_1mC_1(m+1)C_1(m+2), C=C_2(m+1)C_2(m+2)、C_3mC_3(m+1)C_3(m+2)And C_4mC_4(m+1) C4_(m+2)Bottom crown set mode, wherein m=6,9,12, setting after set method and above-mentioned second compares cycle Position method is identical, and remaining capacitor bottom crown set mode remains unchanged.

After the 6th compares cycle, as VP1 > VN1, VP2 > VN2, generating two thermometer-codes is 11, is being patrolled It collects under control circuit control, C in the first sub switch capacitor array₁₁₅、C₁₁₆Bottom crown respectively from power end VDD, ground terminal GND It is set to ground terminal GND, ground terminal GND；C in second sub switch capacitor array₂₁₅、C₂₁₆Bottom crown respectively from ground terminal GND, Power end VDD is set to power end VDD, power end VDD；C in third sub switch capacitor array₃₁₅、C₃₁₆Bottom crown respectively from Ground terminal GND, power end VDD are set to ground terminal GND, ground terminal GND；C in 4th sub switch capacitor array₄₁₅、C₄₁₆Under Pole plate is set to power end VDD, power end VDD from power end VDD, ground terminal GND respectively；As VP1 < VN1, VP2 > VN2, produce Raw two thermometer-codes are 01, under control logic circuit control, C in the first sub switch capacitor array₁₁₅、C₁₁₆Bottom crown still Keep power end VDD, ground terminal GND SM set mode；C in second sub switch capacitor array₂₁₅、C₂₁₆Bottom crown still keep being grounded Hold GND, power end VDD SM set mode；C in third sub switch capacitor array₃₁₅、C₃₁₆Bottom crown still keep ground terminal GND, electricity Source VDD SM set mode；C in 4th sub switch capacitor array₄₁₅、C₄₁₆Bottom crown still keep power end VDD, ground terminal GND SM set mode；As VP1 < VN1, VP2 < VN2, generating two thermometer-codes is 00, under control logic circuit control, the first son C in switched capacitor array₁₁₅、C₁₁₆Bottom crown be set to power end VDD, power end from power end VDD, ground terminal GND respectively VDD；C in second sub switch capacitor array₂₁₅、C₂₁₆Bottom crown be set to ground terminal from ground terminal GND, power end VDD respectively GND, ground terminal GND；C in third sub switch capacitor array₃₁₅、C₃₁₆Bottom crown set respectively from ground terminal GND, power end VDD Power end VDD, power end VDD are arrived in position；C in 4th sub switch capacitor array₄₁₅、C₄₁₆Bottom crown respectively from power end VDD, connect Ground terminal GND is set to ground terminal GND, ground terminal GND.

After the 7th compares cycle, 14 thermometer-codes are finally generated, 8 can be obtained after decoder is converted Binary digital code.

In one embodiment of the invention, the comparator group includes that first comparator, the second comparator, third compare Device, the 4th comparator, the 5th comparator；

The clock signal input terminal of the first comparator and the 5th comparator is connect with ground terminal GND, second ratio Clock signal input terminal compared with device, third comparator, the 4th comparator connects with the output end of the asynchronous clock generation circuit It connects；

The first input end of the first comparator is connect with the output end of the switched capacitor array, and described first compares Second input terminal of device is for inputting external common-mode reference voltage (VCM)；

The first input end and the second input terminal of second comparator connect with the output end of the switched capacitor array It connects；

The first input end and the second input terminal of the third comparator connect with the output end of the switched capacitor array It connects；

The first input end and the second input terminal of 4th comparator connect with the output end of the switched capacitor array It connects；

The first input end of 5th comparator is for inputting external common-mode reference voltage VCM, the 5th comparator The second input terminal connect with the output end of the switched capacitor array.

Specifically, referring to Fig. 3, Fig. 3 is that 1.5 successive approximation moduluses of an a kind of step provided in an embodiment of the present invention turn The comparator group circuit diagram of parallel operation, first comparator include two input terminals, respectively correspond the output of first switch capacitor array Hold VP1 and common mode reference voltage VCM, clock signal input terminal ground connection；Second comparator includes two input terminals, respectively corresponds the The output end VP1 of the one switched capacitor array and output end VN1 of second switch capacitor array, the timing diagram of clock control signal is such as Shown in Fig. 4, clock signal input terminal input clock controls signal CLK1；Third comparator includes two input terminals, is respectively corresponded The output end VP2 of the third switched capacitor array and output end VN1 of second switch capacitor array, when clock signal input terminal inputs Clock signal CLK2；4th comparator include two input terminals, respectively correspond third switched capacitor array output end VP2 and The output end VN2 of 4th switched capacitor array, clock signal input terminal input clock control signal CLK3；5th comparator includes Two input terminals, respectively correspond the output end VN2 of common mode reference voltage VCM and the 4th switched capacitor array, clock signal input End ground connection.

Further, the differential output signal A of the second comparator includes Ap and An；The differential output signal of third comparator C includes Cp and Cn；The differential output signal B of 4th comparator includes Bp and Bn.

In one embodiment of the invention, the asynchronous clock generation circuit includes the first nor gate, the second nor gate With the first NAND gate；

First input end, the second input terminal of first nor gate are all connected with the first output end of the comparator group； The first input end of first NAND gate is connect with the output end of first nor gate, and the second of first NAND gate is defeated Enter end input external sampling clock inversion signal CSN；The first input end of second nor gate and first NAND gate Second input terminal of output end connection, second nor gate inputs external sampling clock signal CS.

Specifically, referring to Fig. 5, Fig. 5 is that 1.5 successive approximation moduluses of an a kind of step provided in an embodiment of the present invention turn The asynchronous clock generation circuit circuit diagram of parallel operation, the output of the second nor gate generate asynchronous clock signal CLKc, asynchronous clock signal CLKc is again by can produce comparator group clock signal clk 1, CLK2 and CLK3 with combinational logic circuits such as doors.

In one embodiment of the invention, Fig. 6 is referred to, Fig. 6 is an a kind of step 1.5 provided in an embodiment of the present invention The control logic circuit structural schematic diagram of gradual approaching A/D converter, the control logic circuit include that 2N-2 control is patrolled Collect unit, i.e. the first control logic unit, the second control logic unit ... 2N-2 control logic unit, N >=4；

The first control logic unit, the second control logic unit ... N-1 control logic are unit cascaded；The N Control logic unit, N+1 control logic unit ... 2N-3 control logic are unit cascaded.

In one embodiment of the invention, Fig. 7 is referred to, Fig. 7 is an a kind of step 1.5 provided in an embodiment of the present invention The control logic element circuit schematic diagram of gradual approaching A/D converter, the control logic unit include PMOS tube PM1, PM2, PM3, PM4, PM5, PM6, PM7, NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8 and the second NAND gate, One phase inverter I1, the second phase inverter I2, third phase inverter I3, the 4th phase inverter I4；

The source grounding of described NMOS tube NM3, NM5, NM7, NM8；The PMOS tube PM1, PM2, PM3, PM4, PM5, The source electrode of PM6, PM7 input external power supply VDD；Second output of the grid of NMOS tube NM1, NM6 and the comparator group End connection；The source electrode of the NMOS tube M1 connects the drain electrode of the NMOS tube NM3, described in the drain electrode connection of the NMOS tube NM1 The source electrode of NMOS tube NM2；The grid of the NMOS tube NM3 connects the grid of the NMOS tube NM5；The leakage of the NMOS tube NM5 Pole connects the source electrode of the NMOS tube NM6；The drain electrode of the NMOS tube NM6 is connect with the source electrode of the NMOS tube NM4；It is described The grid of NMOS tube NM2 is connect with the grid of the NMOS tube NM4, and the drain electrode of the NMOS tube NM4 is with the PMOS tube PM2's The output end of drain electrode connection, the grid intersection point and adjacent upper level control logic unit of the NMOS tube NM2 and NMOS tube NM4 connects It connects；The drain electrode of the NMOS tube NM2 is connect with the drain electrode of the PMOS tube PM1；The grid and the PMOS of the PMOS tube PM1 The grid of pipe PM2 connects, and the grid of the PMOS tube PM1 connect intersection point with the grid of the PMOS tube PM2 and also inputs outside Portion sampling clock inversion signal CSN；The grid of the PMOS tube PM3 and the drain electrode of the PMOS tube PM1 and the leakage of NMOS tube NM2 The connection of pole intersection point；The grid of the PMOS tube PM4 is connect with the drain electrode intersection point of the drain electrode of the PMOS tube PM2 and NMOS tube NM4, The PMOS tube PM3 connects the drain electrode of the PMOS tube PM4, and with the input terminal of the first phase inverter I1 and the NMOS tube The drain electrode of NM7 connects；The grid of the NMOS tube NM7 inputs external sampling clock signal CS；The first phase inverter I1's is defeated Outlet is separately connected the grid of the PMOS tube PM5 and the grid of NMOS tube NM8；The grid of the PMOS tube PM5 and NMOS tube NM8 Pole connection, the drain electrode of the PMOS tube PM5 are connect with the source electrode of the PMOS tube PM6；Two inputs of second NAND gate End connects the output end of the comparator group by third phase inverter I3 and the 4th reverser I4 respectively, second NAND gate Output end is connect with the grid of the PMOS tube PM6, and the drain electrode of the NMOS tube NM8 is connect with the drain electrode of the PMOS tube PM6； The previous control logic unit passes through the PMOS tube PM6 and the NMOS tube in the control logic unit of adjacent two The drain electrode intersection point of NM8 connects NMOS tube NM2, the NM4 grid intersection point of the latter control logic unit；The PMOS tube The grid of PM7 is connect with the drain electrode of the PMOS tube PM8, and draining for the PMOS tube PM7 is defeated with the second phase inverter I2 Enter end connection, the output end of the second phase inverter I2 is connect with the control signal input of the switched capacitor array；It is described The grid of PMOS tube PM8 is connect with the input terminal of the drain electrode of the PMOS tube PM7, the second phase inverter I2；Described first is anti- The output end of phase device I1 is also connected with the grid intersection point of the NMOS tube NM3 and NMOS tube NM5；The drain electrode of the PMOS tube PM1 with The drain electrode connection intersection point of the NMOS tube NM2 connect the intersection point of PMOS tube PM8 drain electrode with the PMOS tube PM7 grid；It is described The drain electrode of PMOS tube PM2 and the drain electrode connection intersection point of NMOS tube NM4 connect the drain electrode of the PMOS tube PM7 with PMOS tube PM8's Grid connects intersection point；The grid of the PMOS tube PM3 connects the friendship of the PMOS tube PM7 grid and PMOS tube PM8 drain electrode Point, the drain electrode that the grid of the PMOS tube PM4 connects the PMOS tube PM7 connect intersection point with the grid of the PMOS tube PM8.

Specifically, control logic circuit includes 14 control logic units, i.e. the first control logic list in the present embodiment Member~the 14th control logic unit, differential output signal Ap, An of the second comparator input the first control logic unit respectively Differential signal input Op, On of~the seven control logic unit；Differential output signal Bp, Bn of 4th comparator are inputted respectively 8th control logic unit~the 12nd control logic unit differential signal input Op, On；The difference of third comparator is defeated Signal Cp, Cn inputs differential signal input Op, On of the 14th control logic unit respectively out；The first of control logic unit Enable signal input terminal inputs external sampling clock signal CS, and the second enable signal input terminal inputs external sampling clock inversion letter Number CSN.

Specific in control logic unit, when sampling, SAR control logic output code Ci and SAR control logic anti-phase output Code Ci ' is charged to VDD.After a compares cycle, differential input end Op, On of control logic unit have one end SAR control logic output code Ci and SAR control logic anti-phase output code Ci ' is pulled down to low potential by level change；When SAR is controlled Logic output code Ci or SAR control logic anti-phase output code Ci ' processed have one for low potential when, the touching of SAR control logic unit Signalling Ti is pulled down to low potential, and present discharge access is turned off, and compares it and exports result to be latched at SAR control logic defeated Code Ci and SAR control logic anti-phase output code Ci ' out, and generate the signal Ci_a of control switch capacitor array.

In one embodiment of the invention, the register includes 2N-2 d type flip flop and the 5th phase inverter (I5), institute The first enable signal input terminal input external sampling signal (CS) of d type flip flop is stated, the second enable signal of the d type flip flop is defeated Enter end by the 5th phase inverter (I5) input external sampling clock signal (CS), the signal input part of the d type flip flop with it is described The output end of control logic circuit connects.

Specifically, referring to Fig. 8, Fig. 8 is that 1.5 successive approximation moduluses of an a kind of step provided in an embodiment of the present invention turn The register architecture schematic diagram of parallel operation, 14 d type flip flops compose in parallel register, and d type flip flop uses C²MOS structure is realized, defeated Enter signal for control signal Ci_a and sampled clock signal CS, exports Ai, Bi and Ci and give junior's decoder；First d type flip flop~ Tenth four d flip-flop sequentially inputs control signal Ci_a, and is sequentially output thermometer-code A₁~A₇、B₂~B₇、C₇。

In one embodiment of the invention, the decoder includes the first half adder, the second half adder, the first~the N- 1 full adder, the first~the N-2 and door and the 5th NOT gate I5~N+1 NOT gate IN+1, N >=4；

Described first is connect by the 5th NOT gate I5 with the register with the first input end of door, described first with Second input terminal of door is connect with the register；The first input end of the N-2 and door passes through N+1 NOT gate IN+1 and institute It states register to connect, the second input terminal of the N-2 and door is connect with the register；The input terminal of first full adder The output end of the register is connected, the first input end of the second~the N-1 full adder connects the output of the register End；First output end of first full adder is connect with the first input end of first half adder, first half adder The second input terminal connect ground terminal GND, the first of the second output terminal of first full adder and second half adder is defeated Enter end connection, the second input terminal of second half adder is connect with the output end of the N-2 and door；The N-2 and door Output end connect with the second input terminal of the N-1 full adder；The output end of the first~N-3 and door respectively with it is described Second input terminal of the full adder of N-3~bis- connects, the N-2 full adder, N-1 full adder the second input terminal be all connected with Ground terminal GND.

Further, Fig. 9 is referred to, Fig. 9 is 1.5 successive approximation moduluses of an a kind of step provided in an embodiment of the present invention The decoder architecture schematic diagram of converter, decoder are complete including the first half adder~second half adder, the first full adder~7th Add device, first and door~5th and door and the 5th NOT gate I9 of NOT gate I5~the 9th；First passes through the 5th with the first input end of door The output end of first d type flip flop of NOT gate I5 and register connects, and first is defeated with the second input terminal of door and third d type flip flop Outlet connection；Second is connect with the first input end of door by the output end of the 6th NOT gate I6 and the four d flip-flop of register, Second connect with the second input terminal of door with the output end of the 5th d type flip flop；The first input end of third and door is non-by the 7th The output end of 6th d type flip flop of door I7 and register connects, the 7th d type flip flop of the second input terminal register of third and door Output end connection；4th passes through the 8th d type flip flop output end company of the 8th NOT gate I8 and register with the first input end of door It connects, the 4th connect with the output end of the second input terminal of door and the 9th d type flip flop of register；5th with the first input end of door Connected by the output end of the 9th NOT gate I9 and the tenth d type flip flop of register, the 5th with the second input terminal and register of door The 11st d type flip flop output end connection；First and door output temperature meter code BD₂, second raises the price BD with door output temperature₃, the Three and door output temperature meter code BD₄, the 4th and door output temperature meter code BD₅, the 5th and door output temperature meter code BD₆。

Further, by NOT gate and with goalkeeper's thermometer-code A_iB_iThe thermometer-code of (i=2,3,4,5,6) from 00, 01,11 corresponding conversions are at 00,01,10, by full full adder by A₇B₇C₇Included in information be transformed into AD₇BD₇In；It uses again The adder that dislocation is added, which is arranged, is converted into binary code for thermometer-code.

Specifically, thermometer-code Ai carries out generating BDi with operation by NOT gate and thermometer-code Bi, to generate double figures Character code AiBDi (i=2,3,4,5,6)；Thermometer-code A₇、B₇、C₇Double figures character code AD is generated by the first full adder₇BD₇；Number Code BD₇Final output code D is generated by the first half adder with ground terminal GND₈；Thermometer-code AD₇And BD₆By the second half adder Generate final output code D₇With junior's carry；Thermometer-code A₆、BD₅Final output is generated by the second full adder with higher level's carry Code D₆With junior's carry；Thermometer-code A₅、BD₄Final output code D is generated by third full adder with higher level's carry₅It is grading under Position；Thermometer-code A₄、BD₃Final output code D is generated by the 4th full adder with higher level's carry₄With junior's carry；Thermometer-code A₃、BD₂Final output code D is generated by the 5th full adder with higher level's carry₃With junior's carry；Thermometer-code A₂, ground terminal GND Final output code D is generated by the 6th full adder with higher level's carry₂With junior's carry；Thermometer-code A₁, ground terminal GND and higher level Carry generates final output code D by the 7th full adder₁。

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, In Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention Protection scope.