阅读说明：本技术 旗标保持电路以及旗标保持方法 (Flag holding circuit and flag keeping method ) 是由 四辻哲章 于 2019-05-20 设计创作，主要内容包括：本发明提供一种可抑制电路规模的增大且在规定期间内保持旗标的旗标保持电路以及旗标保持方法。旗标保持电路具有：连接于电压提供线且根据输入信号而将电容器充电的旗标设定部、基于电容器的充电电压来输出表示0或1的输出信号的旗标判定部、及将电容器放电的放电部。旗标设定部包含：泄漏抑制开关,第一端连接于旗标判定部与放电部之间的连接线,第二端根据输入信号的信号电平而连接于电压提供线或接地线,根据向控制端提供的泄漏控制信号而将电压提供线或接地线与连接线连接或切断；及泄漏抑制开关控制部,根据时钟信号而生成信号电平变化为比电源电压更大的值的泄漏控制信号,并提供给泄漏抑制开关的控制端。(The present invention provide it is a kind of can inhibit circuit scale increase and during the prescribed period in keep flag flag holding circuit and flag keeping method.Flag holding circuit include be connected to voltage line is provided and according to input signal and by the flag portion of capacitor charging, exported based on the charging voltage of capacitor indicate 0 or 1 output signal flag determination unit and by the discharge part of capacitor discharge.Flag portion includes: leakage inhibits switch, first end is connected to the connecting line between flag determination unit and discharge part, second end is connected to voltage according to the signal level of input signal and provides line or ground line, provides voltage to line or ground line according to the leakage control signal provided to control terminal and connect or cut off with connecting line；And leakage inhibits switching controlling part, and signal level variation is generated according to clock signal and is the leakage control signal of the value bigger than supply voltage, and is supplied to the control terminal that leakage inhibits switch.)

1. a kind of flag holding circuit, is equipped on radio frequency identification tag circuit, the radio frequency identification tag circuit passes through from reading The electric wave for writing device device receives electric power offer, and is received and sent messages between the read-and-write device by wireless near field communication, The flag holding circuit receives the setting of the flag of the value with 0 or 1 for the information transmit-receive and keeps the flag, The flag holding circuit is characterized in that

Capacitor；

Flag portion is connected to the voltage for being provided based on the electric power from the read-and-write device and being provided supply voltage and provides Line receives the offer of input signal, and the capacitor is charged according to the input signal；

Flag determination unit exports the output signal of expression 0 or 1 based on the charging voltage of the capacitor；And

Discharge part, by the capacitor discharge,

One end of the capacitor is connected to the connecting line for connecting the flag determination unit with the discharge part, and the other end Ground connection,

The flag portion includes:

Leakage inhibits switch, and first end is connected to the connecting line, second end company according to the signal level of the input signal Be connected to the voltage and line or ground line be provided, according to the leakage control signal for being supplied to control terminal by the voltage provide line or It connects or cuts off between ground line and the connecting line；And

Leakage inhibits switching controlling part, receives the offer of clock signal, generates signal level variation according to the clock signal For the leakage control signal of the value bigger than the supply voltage, and it is supplied to the control terminal that the leakage inhibits switch.

2. flag holding circuit according to claim 1, which is characterized in that the leakage inhibits switching controlling part according to institute The maximum value stated clock signal and generate signal level becomes 2 times of the leakage control signal of the supply voltage, and mentions Supply the control terminal that the leakage inhibits switch.

3. flag holding circuit according to claim 2, which is characterized in that the leakage inhibits switching controlling part to receive table Show the offer of the write control signal during flag, middle generation signal level is in the power supply during the flag The signal changed between voltage and 2 times of voltage of the supply voltage is supplied to described as the leakage control signal Leakage inhibits the control terminal of switch.

4. flag holding circuit according to any one of claim 1 to 3, which is characterized in that the leakage inhibits switch It is to be made of metal oxide semiconductor transistor, one of source electrode and drain electrode is connected to described as the first end Connecting line, another one are connected to the voltage as the second end and provide line or ground line, and grid is as the control terminal And receive the offer of the leakage control signal.

5. flag holding circuit according to any one of claim 1 to 4 characterized by comprising

Refresh determination unit, determines whether the voltage of the connecting line is more than defined threshold value；And

Operation control part, based on the judgement for refreshing determination unit as a result, inhibiting the dynamic of switching controlling part to control the leakage Make,

The operation control part presses down the leakage when the voltage of the connecting line is judged as the defined threshold value or less Switching controlling part processed inhibits the control terminal of switch to provide the leakage control signal to the leakage,

When the voltage of the connecting line is judged as being more than the defined threshold value, make the leakage that switching controlling part be inhibited to stop Only the control terminal of switch is inhibited to provide the leakage control signal to the leakage.

6. flag holding circuit according to claim 5, which is characterized in that the refreshing determination unit includes: Schmidt is anti- Phase device, in the input for the reversal voltage that input terminal receives invert the current potential of the connecting line, and based on the reversal voltage and The comparison result of first threshold and second threshold indicates whether the voltage of the connecting line is more than the regulation from output end output Threshold value judgement result.

7. a kind of flag holding circuit characterized by comprising

Flag portion is connected to supply voltage and first node, according to input signal to described in first node offer Supply voltage or the offer for blocking the supply voltage；

Capacitor is connected to the first node, is charged by the supply voltage；

Flag determination unit is connected to the first node, determines flag based on the charging voltage of the capacitor；And

Discharge part is connected to the first node, by the capacitor discharge,

The flag portion includes:

Leakage inhibits switch, receives the offer of the input signal, is connected to electricity according to the signal level of the input signal Pressure provides line or ground line, and according to the leakage control signal for being supplied to control terminal and by the voltage provide line or ground line with It connects or cuts off between the first node；And

Leakage inhibits switching controlling part, receives the offer of clock signal, generates signal level variation according to the clock signal For the leakage control signal of the value bigger than the supply voltage, and it is supplied to the control terminal that the leakage inhibits switch.

8. a kind of flag keeping method is as performed by flag holding circuit according to claim 5, which is characterized in that Include the following steps:

Receive the electric power from the read-and-write device to provide；

The offer of the input signal and the clock signal is provided；

The capacitor is charged according to the input signal；

The output signal of expression 0 or 1 is exported based on the charging voltage of the capacitor；And

By the capacitor discharge, and

The step of capacitor is charged according to the input signal includes following step:

Whether the voltage for determining the connecting line is more than defined threshold value；And

The voltage for being determined as the connecting line be it is described as defined in below threshold value when, make the leakage inhibition switching controlling part to The leakage inhibits the control terminal of switch to provide the leakage control signal, is more than described in the voltage for being determined as the connecting line When defined threshold value, make described leak that switching controlling part be inhibited to stop inhibiting to let out described in the control terminal offer of switch to the leakage Leakage control signal.

Technical field

The present invention relates to one kind in the label of radio frequency identification (Radio Frequency Identification, RFID) Keep the flag holding circuit and flag keeping method of flag (flag).

Background technique

In recent years, using the wireless communication of short distance from the embedding mark for having the information such as identity (Identification, ID) RFID (Radio Frequency Identification) technology that information is obtained in label attracts attention.The wireless communication of RFID System is the reader for carrying out information reading by the embedding label for having the information such as ID and using electric wave in a non contact fashion to label (reader writer) is constituted.It is (following using the wireless communication system for itself not having the RFID of the passive label of power supply Referred to as passive type RFID) it is by label and to provide power supply to label using electric wave and read the reading of information in a non contact fashion Device is write to be constituted.

In passive type RFID, it is equipped with for the flag of the information comprising " 0 " and " 1 " to be kept fixed period in the label Remaining time (persistence time) (such as Japanese Patent Laid-Open 2010-109340 bulletin (patent document 1)).Example Such as, the EPC of electronic product code (Electronic Product Code, EPC)^TMIt is provided in global (global) standard: in meeting It talks about in (session) S2, session S3 and session SL, the flag of the holding more than 2 seconds from reader provides disappearance to the power supply of label.

Summary of the invention

[problem to be solved by the invention]

In the label of passive type RFID, by being set to transistor (transistor) on or off in flag portion, And capacitor (capacitor) is charged to carry out the setting of flag.In order to make the transistor turns, need to make source-drain voltages Maximum value be less than grid voltage maximum value.Therefore, supply voltage VDD is applied to the grid of transistor, to the source of transistor Pole applies the reference voltage VREF for being lower than supply voltage VDD.

But it in order to generate the reference voltage VREF for being lower than supply voltage VDD, needs in addition to be arranged by supply voltage VDD Generate the adjuster (regulator) of reference voltage VREF.The circuit of RFID label tag is totally needed using from from reader The electric power that picks up is received in electric wave to act, to the movement limited power of adjuster distribution.If being intended to reduce the dynamic of adjuster as possible Make electric current and is divided from supply voltage VDD by reference voltage VREF, then it is in need a large amount of using high resistance, and chip area increases The problem of (that is, chip cost increase).

The present invention is to form in view of the issue, and its purpose is to provide the flag holding circuits of RFID a kind of, can The increase of suppression circuit scale, and power supply provide disappear after also during the prescribed period in keep flag.

[technical means to solve problem]

Flag holding circuit of the invention be equipped on by the electric wave from read-and-write device receive electric power provide, and with Radio frequency identification (the Radio Frequency to be received and sent messages between the read-and-write device by wireless near field communication Identification, RFID) tag circuit, and receiving is used for setting for the flag of the value with 0 or 1 of the information transmit-receive Determine and keep the flag, the flag holding circuit is characterized in that including: capacitor；Flag portion, is connected to and is based on The voltage that electric power from the read-and-write device provides and provides supply voltage provides line, receives the offer of input signal, and The capacitor is charged according to the input signal；Flag determination unit exports table based on the charging voltage of the capacitor Show 0 or 1 output signal；And discharge part, by the capacitor discharge, one end of the capacitor, which is connected to, sentences the flag Determine the connecting line that portion is connect with the discharge part, and the other end is grounded, the flag portion includes: leakage inhibits switch, First end is connected to the connecting line, and second end is connected to the voltage according to the signal level of the input signal and provides line Or ground line, the voltage is provided to line or ground line and the connecting line according to the leakage control signal for being supplied to control terminal Between connect or cutting；And leakage inhibits switching controlling part, receives the offer of clock signal, is generated according to the clock signal Signal level variation is the leakage control signal of the bigger value of the supply voltage, and is supplied to the leakage inhibition and opens The control terminal of pass.

Moreover, flag holding circuit of the invention includes: flag portion, it is connected to supply voltage and first node, root The supply voltage is provided to the first node according to input signal or the offer of the supply voltage is provided；Capacitor, even It is connected to the first node, is charged by the supply voltage；Flag determination unit is connected to the first node, is based on the electricity The charging voltage of container determines flag；And discharge part, it is connected to the first node, by the capacitor discharge, the flag Mark configuration part includes: leakage inhibits switch, receives the offer of input signal, is connected according to the signal level of the input signal Line or ground line are provided in voltage, and provides the voltage to line or ground connection according to the leakage control signal for being supplied to control terminal It connects or cuts off between line and the first node；And leakage inhibits switching controlling part, receives the offer of clock signal, according to institute It states clock signal and generates signal level variation and be the leakage control signal of the value bigger than the supply voltage, and provide Inhibit the control terminal of switch to the leakage.

Moreover, flag keeping method of the invention includes the following steps: to receive to mention from the electric power of the read-and-write device For；The offer of the input signal and the clock signal is provided；The capacitor is charged according to the input signal；It is based on The charging voltage of the capacitor indicates 0 or 1 output signal to export；And by the capacitor discharge, according to the input The step of signal charges the capacitor includes the following steps: to determine whether the voltage of the connecting line is more than defined threshold； And when the voltage for being determined as the connecting line is the defined threshold value or less, the leakage is made to inhibit switching controlling part to institute Stating leakage inhibits the control terminal of switch to provide the leakage control signal, and is more than described in the voltage for being determined as the connecting line When defined threshold value, make described leak that switching controlling part be inhibited to stop inhibiting to let out described in the control terminal offer of switch to the leakage Leakage control signal.

[The effect of invention]

Flag holding circuit according to the present invention can inhibit the increase of circuit scale and also exist after power supply is provided and disappeared Flag is kept in specified time limit.

Detailed description of the invention

Fig. 1 be the holding for the flag for schematically showing each session during figure.

Fig. 2 is the circuit diagram for indicating the structure of flag holding circuit of the present embodiment.

Fig. 3 is to indicate that leakage inhibits the circuit diagram of the structure of switch driver.

Fig. 4 is to indicate that leakage inhibits the timing diagram of the movement of switch driver.

Fig. 5 is the figure for schematically showing the parasitic diode generated in discharge part.

Fig. 6 is to indicate to provide the figure of the input voltage of corresponding transistor MD2 and the time change of electric current with there is non-transformer.

Fig. 7 is the figure for schematically showing the parasitic diode that leakage inhibits switch MSL.

Fig. 8 is the time change of the current potential of the input/output signal and internal node in the movement for indicate flag holding circuit Timing diagram.

Fig. 9 is the circuit diagram for indicating the structure of flag holding circuit of comparative example.

Figure 10 is the circuit diagram for indicating the structure of flag holding circuit of embodiment 2.

Figure 11 A is the circuit diagram for indicating to refresh the structure of determination unit.

Figure 11 B is the figure for indicating to refresh the relationship of decision threshold and flag decision threshold.

The explanation of symbol

100,200: flag holding circuit

10,20: flag portion

11,21: discharge part

12,22: flag determination unit

13: refreshing determination unit

FSI, JI: phase inverter

SD: leakage inhibits switch driver

MSL: leakage inhibits switch

SI, SIR: schmitt inverter

ND1, RND:NAND

INV1, INV2, INV3: phase inverter

SDI1, SDI2, SDI3: phase inverter

Specific embodiment

Desired embodiment of the invention is described in detail below.In addition, the explanation and attached drawing of each embodiment below In, identical reference marks is marked to substantially the same or of equal value part.

[embodiment 1]

The flag holding circuit 100 of the present embodiment is equipped on RFID's (Radio Frequency Identification) Tag circuit.Tag circuit receives the offer of the power supply from reader via wireless near field communication.Therefore, only in label electricity Power supply offer is provided when road is located in prescribed limit apart from reader, stops power supply when leaving in the prescribed limit and provides. In the following description, there will be the case where power supply from reader provides to be referred to as " having power supply offer ", will have no from read-write The case where power supply of device provides is referred to as " non-transformer offer ".

Moreover, in RFID tag circuit, need to set for the flag of (inventory) of making an inventory, and according to EPC The EPC of (Electronic Product Code)^TMGlobal standard is interior during the prescribed period to keep the flag.The holding of flag Period is each session setting for S0, S1, S2, S3 and SL.

Fig. 1 is the guarantor for schematically showing the flag of each session for session S1, session S2, session S3 and session SL Figure during holding.In addition, herein in regard to session S0 illustration omitted.

In session S0, flag can not also be kept when non-transformer provides, needs to be always maintained at flag when there is power supply offer. In session S1, when being set with flag " 1 ", no matter there is non-transformer offer to be required to keep within 0.5 second~5 seconds specified time limits Flag " 1 ".In contrast, when being set with flag " 1 ", needing to provide disappearance in power supply in session S2, session S3 and session SL Afterwards, flag " 1 " is kept within the specified time limit more than 2 seconds.

The flag holding circuit 100 of the present embodiment be conversate S2, session S3 and the flag in session SL setting and The circuit of holding.

Fig. 2 is the circuit diagram for indicating the structure of flag holding circuit 100 of the present embodiment.Flag holding circuit 100 has Capacitor (capacitor) CF receives input signal in, clock signal clk and the write control signal of logic circuit offer (not shown) W_en and the charge and discharge for carrying out capacitor CF, and to be exported in the form of the flag of " 0 " or " 1 ".Moreover, as described above, only taking When the tag circuit of load flag holding circuit 100 is located in prescribed limit apart from reader, Xiang Qibiao holding circuit 100 carries out electricity Source provides.

Flag holding circuit 100 has capacitor CF, flag portion 10, discharge part 11 and flag determination unit 12.Capacitor CF One of terminal and node NVF connection as the connecting line between discharge part 11 and flag determination unit 12, another terminal Ground connection.

Flag portion 10 includes phase inverter FSI, transistor MSP, transistor MSN, leakage inhibition switch MSL and leakage suppression Switch driver SD processed.

Phase inverter FSI receives the input signal in of logic circuit offer (not shown), and the logic that will make input signal in The signal (hereinafter referred to as inversion input signal) of level reversion is supplied to transistor MSP and the respective grid of transistor MSN.

Transistor MSP is by metal-oxide semiconductor (MOS) (the Metal Oxide as the first conductive type Semiconductor, MOS) the P channel type MOS transistor of transistor constituted.The source electrode of transistor MSP is connected to voltage and mentions For line (supply voltage VDD).Transistor MSN is by as the MOS with the second conductive type that the first conductive type is opposite conductivity type Transistor, N channel type MOS transistor constituted.The source electrode of transistor MSN is grounded.The leakage of transistor MSP and transistor MSN Pole is connected to each other, and is connected to node NFS.Transistor MSP and transistor MSN are according to the inversion input signal for being supplied to grid And it is controlled as on or off.

It is, for example, to be made of N channel type MOS transistor that leakage, which inhibits switch MSL,.Leakage inhibits the drain electrode warp of switch MSL The drain electrode of transistor MSP and transistor MSN are connected to by node NFS.Leakage inhibits the source electrode of switch MSL to be connected to node NVF.Leakage inhibits backgate (back gate) ground connection of switch MSL.In order to make leakage that switch MSL be inhibited to connect, need to be compared to The voltage that the supply voltage VDD of voltage max between drain-source is bigger is supplied to grid.

It is the control circuit for the grid that control leakage inhibits switch MSL that leakage, which inhibits switch driver SD,.Leakage inhibits to open Clock signal clk and write control signal w_en that driver SD receives logic circuit offer (not shown) are closed, leakage control is generated Signal NCS processed is simultaneously supplied to the grid that leakage inhibits switch MSL.

Fig. 3 is to indicate that leakage inhibits the circuit diagram of the structure of switch driver SD.Leakage inhibits switch driver SD for example Be by transistor MSD1, transistor MSD2, capacitor (capacitor) CSD1, capacitor (capacitor) CSD2, with non-(NAND) door ND1, Phase inverter SDI1, phase inverter SDI2 and phase inverter SDI3 are constituted.

Transistor MSD1 and transistor MSD2 is, for example, to be made of N channel type MOS transistor.Transistor MSD1 and crystal The source electrode of pipe MSD2 is connected to voltage and provides line (supply voltage VDD).The grid of transistor MSD1 is connected to node NBST.Crystal The drain electrode of pipe MSD2 is connected to node NBST.

One end of capacitor CSD1 is connected to the drain electrode of transistor MSD1 and the grid of transistor MSD2.Capacitor CSD1's is another End is connected to the output end of NAND gate ND1 and the input terminal of phase inverter SDI1.

One end of capacitor CSD2 is connected to the drain electrode of the grid and transistor MSD2 of transistor MSD1 via node NBST. The other end of capacitor CSD2 is connected to the output end of phase inverter SDI1.

NAND gate ND1 receives the input of clock signal clk and write control signal w_en, and export clock signal clk with The signal of the negative logic product of write control signal w_en.

The input terminal of phase inverter SDI1 is connected to the output end of NAND gate ND1 and the other end of capacitor CSD1.Phase inverter The signal for being supplied to input terminal is inverted and is supplied to capacitor CSD2 by SDI1.

Phase inverter SDI2 receives the input of write control signal w_en, and exports the logic electricity for making write control signal w_en Redress turn signal.

Phase inverter SDI3 receives the output signal of phase inverter SDI2 (that is, keeping the logic level of write control signal w_en anti- The signal turned) input, and the signal using logic level through inverting is exported as leakage control signal NCS.Phase inverter SDI3 Positive power supply terminal be connected to node NBST, negative power supply terminal ground connection.Therefore, leakage control signal NCS become have with The signal of the corresponding signal level of the current potential of node NBST.

Fig. 4 is to indicate that leakage inhibits the timing diagram of the movement of switch driver SD.When there is power supply offer, to NAND gate ND1 provides clock signal clk.Write control signal w_en is the signal that signal level variation is logic level " 0 " and " 1 ", and It is the signal for inhibiting the triggering (trigger) of control of the switch driver SD to leakage inhibition switch MSL as leakage.

During write control signal w_en is logic level " 0 " (that is, close), to capacitor CSD1 and capacitor CSD2 into The charging of row supply voltage VDD.Therefore, the current potential of node NBST becomes the level of supply voltage VDD.It is exported from phase inverter SDI3 Leakage control signal NCS be logic level " 0 " in the same manner as write control signal w_en, become earthing potential signal electricity It is flat.

When write control signal w_en becomes logic level " 1 " (that is, opening), the current potential of node NBST becomes to power supply electricity The current potential of pressure VDD level, which is added, is synchronously changing into current potential obtained by the signal of supply voltage VDD level with clock signal clk. That is, the potential level of node NBST is changed between VDD and 2 × VDD with the timing synchronous with clock signal clk.

The leakage control signal NCS exported from phase inverter SDI3 becomes signal level and synchronously changes with clock signal clk For the signal of VDD and 2 × VDD.Therefore, in during write control signal w_en is opened, by signal level maximum become 2 × The leakage control signal NCS of VDD is supplied to the grid that leakage inhibits switch MSL.

In this way, flag portion 10 is connected to power supply (supply voltage VDD) and the node NVF as first node, it is based on Input signal in and to node NVF provide supply voltage VDD or block power supply provide.

Referring again to Fig. 2, discharge part 11 include current source ID, capacitor (capacitor) CD, transistor MD1, transistor MD2 and Transistor MDS.

One end of current source ID is connected to voltage and provides line.One end of capacitor CD is connected to node NVD, other end ground connection.

Transistor MD1 is made of N channel type MOS transistor.The grid (control terminal) of transistor MD1 and drain electrode (the Two ends) it is connected to the other end of current source ID.The source electrode (first end) and backgate of transistor MD1 is grounded.Transistor MD1 is by electric current The electric current of source ID flowing is converted to DC voltage.

Transistor MD2 is mutual conductance (transconductance) element that capacitor CF discharges via node NVF.Crystal Pipe MD2 is, for example, to be made of N channel type MOS transistor.The source electrode (the first output end) and backgate of transistor MD2 is grounded.It is brilliant The drain electrode (second output terminal) of body pipe MD2 is connected to node NVF.The grid (control signal) of transistor MD2 is connected to node NVD。

Transistor MDS is the control switch for controlling the input voltage of transistor MD2.Transistor MDS is, for example, by N channel type MOS transistor is constituted.The source electrode (first end) of transistor MDS is connected to node NVD.The drain electrode (second end) of transistor MDS It is connected to the other end of current source ID, the grid of transistor MD1 and drain electrode.That is, the drain electrode of transistor MDS is connected to current source ID Electric current through transistor MDS conversion made of DC voltage node.

Power-on reset signal PR is provided from grid of electrification reset (power on reset) the portion POR to transistor MDS.In When having power supply from from reader to tag circuit to provide, electrification reset portion POR is using the signal of supply voltage VDD level as powering on Reset signal PR is applied to the grid of transistor MDS.And have no way of reader to the power supply of tag circuit provide when, electrification reset Portion POR is applied to the grid of transistor MDS using the signal of earth level as power-on reset signal PR.Therefore, power supply mentions For when transistor MDS become conducting, non-transformer provide when transistor MDS become shutdown.

Discharge part 11 is discharged capacitor CF using the drain current of transistor MD2.At this point, the letter of power-on reset signal POR Number level is different depending on there is non-transformer to provide, and the conducting of transistor MDS, which turns off, also to be changed, thus the drain current of transistor MD2 Also different depending on there is non-transformer to provide.Moreover, parasitic diode and crystalline substance of the drain current of transistor MD2 by transistor MDS The influence of reverse leakage current in the parasitic diode of body pipe MD2.

Fig. 5 is the parasitic diode PD2 for schematically showing the parasitic diode PD1 and transistor MD2 of transistor MDS Figure.

Parasitic diode PD1 with relative to capacitor CD and mode arranged side by side node NVD and ground connection between generate.In crystal When pipe MDS is turned off, due to the reverse leakage current generated in parasitic diode PD1, capacitor CD slowly discharges, node NVD's Current potential slowly reduces.

Fig. 6 be when power supply offer is provided with non-transformer provide when, transistor MD2 grid voltage and drain current The figure of time change.

When there is power supply offer, the grid voltage of transistor MD2 becomes fixation and (determines with the current value by current source ID The equal value of the grid voltage of transistor MD1).The drain current of transistor MD2 also becomes fixed as a result,.

On the other hand, when non-transformer provides, the parasitic diode of the grid voltage of transistor MD2 due to transistor MDS The electric discharge of capacitor CD caused by the reverse leakage current of PD1, and slowly reduce.The drain current of transistor MD2 is also slowly as a result, It reduces.

Referring again to Fig. 5, parasitic diode PD2 with relative to transistor MD2 and mode arranged side by side in node NVF and ground connection Between generate.The reverse leakage current generated in this parasitic diode PD2 becomes electricity together with the drain current of transistor MD2 Hold the discharge current of CF.Therefore, even simultaneously non-transformer provides and the grid voltage and drain current of transistor MD2 are essentially a zero When, also due to the reverse leakage current in parasitic diode PD2, and the discharge current of capacitor CF does not become zero.

Moreover, parasitism two pole of the discharge current of capacitor CF in addition to drain current and transistor MD2 by transistor MD2 Other than the influence of pipe, the leakage also by flag portion 10 inhibits the parasitic diode of switch MSL to be influenced.

Fig. 7 is the figure for schematically showing the parasitic diode PD3 of transistor MSL.Parasitic diode PD3 is relative to electricity Hold CF and mode arranged side by side generates between node NVF and ground connection.

The reverse leakage current generated in parasitic diode PD3 becomes together with the discharge current caused by discharge part 11 The discharge current of capacitor CF.Therefore, even and have no way of discharge current caused by discharge part 11 when, also due to parasitic diode Reverse leakage current in PD3, and the discharge current of capacitor CF does not become zero.

Referring again to Fig. 2, flag determination unit 12 includes Schmidt (Schmitt) phase inverter SI and phase inverter JI.Schmidt The judgement signal DS of L level or H level is supplied to phase inverter JI according to the voltage level of node NVF by phase inverter SI.Phase inverter JI will make to determine that the signal of signal DS reversion is exported as output signal OUT.

Schmitt inverter SI is the schmidt trigger phase inverter that input and output have lagging characteristics.Schmitt inverter SI With output voltage from L (low) level change be H (height) level when input threshold voltage vt h_LH and output voltage it is electric from H Input threshold voltage vt h_HL (Vth_HL > Vth_LH) when flat variation is L level.Therefore, even node NVF is power supply Voltage VDD and when the medium voltage of ground connection, binaryzation will be exported through electric current by being also avoided that.

Output signal OUT is L level, determines node NVF of the signal DS from L level variation for H level from H level variation Voltage become flag determine decision threshold voltage Vth_jdg.Therefore, there is power supply offer, and the voltage of node NVF is to sentence When determining threshold voltage vt h_jdg or more, determine that signal DS becomes L level, output signal OUT becomes H level.Moreover, there is electricity Source provide, and the voltage of node NVF be less than decision threshold voltage Vth_jdg when, determine signal DS become H level, output signal OUT becomes L level.On the other hand, and non-transformer provide when, no matter the voltage of node NVF and decision threshold voltage Vth_jdg Size how, output signal OUT becomes L level.

Next, the timing diagram referring to Fig. 8 is illustrated the movement of the flag holding circuit 100 of the present embodiment.In addition, There is the length during power supply offer very short compared with during non-transformer offer (for example, having during power supply offer for 10 μ Sec grades, be 1sec grades during non-transformer offer), but this sentences approximate length and schematically shows.

Firstly, flag holding circuit 100 carries out the write-in of flag " 0 " in the state of having power supply offer.To flag Portion 10 provides the input signal in for indicating the L level of " 0 ".Input signal is made to the grid offer of transistor MSP and transistor MSN The signal of the H level of the logic level reversion of in, transistor MSP become shutdown, and transistor MSN becomes conducting.Node as a result, NFS becomes the current potential near ground connection.

Switch driver SD is inhibited to provide the write control signal w_en of clock signal clk and H level leakage.Leakage suppression Signal level maximum is supplied to leakage suppression as 2 times of the leakage control signal NCS of supply voltage VDD by switch driver SD processed The grid for making switch MSL makes leakage that switch MSL be inhibited to connect.

When leakage, which inhibits switch MSL to become, connects, capacitor CF is discharged, the current potential of node NVF becomes near ground connection.By Become near ground connection in the current potential of node NVF, thus the discharge current caused by discharge part 11 becomes zero.Moreover, because node The current potential of NVF be ground connection nearby, thus flag determination unit 12 output L level (earth level) output signal OUT.

Then, flag holding circuit 100 carries out the write-in of flag " 1 " in the state of having power supply offer.To flag Portion 10 provides the input signal in for indicating the H level of " 1 ".Input signal is made to the grid offer of transistor MSP and transistor MSN The signal of the L level of the logic level reversion of in, transistor MSP become conducting, and transistor MSN becomes shutdown.Node as a result, NFS becomes the current potential near supply voltage VDD.

Switch driver SD is inhibited to provide the write control signal w_en of clock signal clk and H level leakage.Leakage suppression Signal level maximum correspondingly, is become 2 times of the leakage control signal NCS of supply voltage VDD by switch driver SD processed It is supplied to the grid that leakage inhibits switch MSL, inhibits switch MSL control for conducting leakage.

When leakage inhibits switch MSL to become conducting, capacitor CF is charged, the current potential of node NVF becomes supply voltage VDD Near.Although the discharge current fixed to ground connection flowing of discharge part 11, flag portion 10 is bigger to the charging of capacitor CF, because And node NVF is maintained near supply voltage VDD.Flag determination unit 12 is thus defeated since node NVF is near supply voltage VDD The output signal OUT of H level out.

Next, flag holding circuit 100 in the state that non-transformer provides, carries out the holding movement of flag " 1 ".

When the electric wave from reader provides interruption, provides disappearance to the power supply of tag circuit from reader, L level Write control signal w_en is provided to leakage and inhibits switch driver SD.Leakage inhibits switch driver SD correspondingly, The leakage control signal NCS of L level is supplied to the grid that leakage inhibits switch MSL.Leakage inhibits control switch MSL as a result, As disconnection.

After setting flag " 1 ", the charging of the voltage near supply voltage VDD, thus the electricity of node NVF are carried out to capacitor CF Position becomes near supply voltage VDD.At this point, as shown in Figure 6, the drain current of transistor MD2 slowly reduces, and by parasitism The reverse leakage current that diode (PD2 and PD3) generates together slowly discharges capacitor CF.The current potential of node NVF is slow as a result, It is slow to reduce.

Before at the time of node NVF is lower than the decision threshold voltage Vth_jdg that flag determines, keep flag " 1 ".From electricity Source becomes flag until providing at the time of playing node NVF at the time of disappearance lower than the decision threshold voltage Vth_jdg that flag determines During mark is kept.

As described above, each portion of the flag holding circuit 100 of the present embodiment is based on supply voltage VDD and acts, power supply System is single.It especially in flag portion 10, is acted based on supply voltage VDD, and leaks and inhibit switch driver SD raw Leakage control signal NCS at 2 times of the signal level with supply voltage VDD as maximum value, and be supplied to leakage and inhibit The grid of switch MSL.In order to make leakage that switch MSL be inhibited to connect, need to make the maximum value of grid voltage to be greater than source drain electricity The maximum value of pressure, and according to the flag holding circuit 100 of the present embodiment, supply voltage VDD can be supplied to leakage and inhibit switch The drain electrode of MSL, and the leakage control signal NCS of the signal level with 2 × VDD is supplied to leakage and inhibits switch MSL's Grid.

Fig. 9 is the structure for indicating the flag holding circuit of the comparative example different from the flag holding circuit 100 of the present embodiment Circuit diagram.The flag holding circuit of comparative example has flag portion 20, discharge part 21 and flag determination unit 22.

Flag portion 20 receives the offer of the input signal ctrl as H level in the setting of flag " 1 ".For letting out Leakage inhibits the grid of switch MSW, via the phase inverter INV1 and phase inverter INV2 using supply voltage VDD as operation voltage, and Apply the signal for making the signal level supply voltage VDD level of input signal ctrl.At this point, inhibiting switch MSW for leakage Drain electrode, via using less than supply voltage VDD reference voltage VREF be used as operation voltage phase inverter INV3, and offer make it is defeated The signal level for entering signal ctrl is the signal of benchmark voltage VREF level.Leakage inhibits switch MSW to become connection, thus capacitor CF is charged until the level of reference voltage VREF.

In the flag holding circuit of comparative example, additionally needs and generate the special of the reference voltage VREF for being less than supply voltage VDD Adjuster.The circuit of RFID label tag totally needs to move using the electric power picked up from the reception electric wave from reader Make, distributes to the movement limited power of adjuster.If being intended to reduce the action current of adjuster as possible from supply voltage VDD by base Quasi- voltage VREF partial pressure, then need largely to use high resistance, and chip area increases.

In contrast, leakage, which inhibits switch driver SD to generate, has power supply in the flag holding circuit 100 of the present embodiment Thus leakage control signal NCS of 2 times of the signal level of voltage VDD as maximum value inhibits the grid of switch MSL to leakage The voltage for being greater than drain electrode is provided, because without the dedicated adjuster for generating reference voltage VREF.

RFID tag circuit can not know when the offer of the electric wave from reader is interrupted in advance.Moreover, RFID label tag is electric Road needs to act merely with by the finite power obtained by the rectification of the electric wave of reader, thus preferably low current acts. In the flag holding circuit 100 of the present embodiment, no matter when electric wave, which interrupts, keeps flag in a period of can be more than fixed.And And it is not necessary that dedicated adjuster is in addition arranged, thus can be acted with low action current, and avoid the increase of chip cost.

Therefore, it according to the flag holding circuit 100 of the present embodiment, can inhibit the increase of circuit scale, and mentioned in power supply Flag is kept for also during the prescribed period (specifically, during more than 2 seconds) interior after disappearing.

[embodiment 2]

Next, the flag holding circuit 200 to embodiment 2 is illustrated.The flag holding circuit 200 of the present embodiment with The flag holding circuit 100 of embodiment 1 similarly, is mounted in RFID tag circuit, and according to the EPC of EPC^TMGlobal standard Come the circuit of setting and the holding of the flag in the S2 that conversates, session S3 and session SL.

Figure 10 is the circuit diagram for indicating the structure of flag holding circuit 200 of the present embodiment.Flag holding circuit 200 is having There are the aspect with (AND) door RAD for refreshing the input of NAND gate RND and two that determination unit 13, three inputs, the flag with embodiment 1 Holding circuit 100 is different.

Whether the current potential for refreshing 13 predicate node NVF of determination unit is more than threshold voltage vt h_ref, and exports judgement result. The input terminal for refreshing determination unit 13 is connected to node NVF, and output end is connected to an input terminal of NAND gate RND.

Figure 11 A is the circuit diagram for indicating to refresh the structure of determination unit 13.Refreshing determination unit 13 includes transistor MRP, electric current Source IR and schmitt inverter SIR.

Transistor MRP is, for example, to be made of P channel type MOS transistor.The source electrode of transistor MRP is connected to voltage offer Line (supply voltage VDD), drain electrode are connected to node NRI.The grid of transistor MRP is connected to node NVF.

One end of current source IR is connected to the drain electrode of node NRI and transistor MRP.The other end of current source IR is grounded.Electricity Stream source IR has the current value of the electric current when transistor MRP is conducting, flowed between the source drain of limit transistor MRP, prevents The function of high current is moved in fluid stopping.

Schmitt inverter SIR is the schmidt trigger phase inverter that input and output have lagging characteristics.Schmitt inverter SIR have input voltage from L level variation be H level when threshold voltage and input voltage from H level change be L level when Threshold voltage.Therefore, it when even node NRI is supply voltage VDD and the medium voltage of ground connection, is also avoided that through electric current And binaryzation will be exported.

Referring again to Figure 10, the current potential (that is, charging voltage of capacitor CF) for refreshing determination unit 13 in node NVF is higher than threshold value When voltage Vth_ref, the output signal NRF of H level is exported.On the other hand, it is lower than threshold voltage vt h_ in the current potential of node NVF When ref, refresh the output signal NRF that determination unit 13 exports L level.

Input signal in is provided to the first input end of NAND gate RND.Refreshing is provided to the second input terminal of NAND gate RND Control signal rf_en.Refresh control signal rf_en is the two-value letter for inhibiting the movement of switch driver SD for controlling leakage Number, it is provided by logic circuit is (not shown).The output signal for refreshing determination unit 13 is provided the third input terminal of NAND gate RND NRF.NAND gate RND exports the signal of L level when being supplied to the signal of three input terminals and being H level, any one be L level When export H level signal.

Write control signal w_en is provided to the first input end of AND gate RAD.The second input terminal of AND gate RAD is connected to The output end of NAND gate RND receives the offer of the output signal of NAND gate RND.AND gate RAD in write control signal w_en and When the output signal of NAND gate RND is H level, the signal of H level is exported to leakage to the input for inhibiting switch driver SD End.AND gate RAD write control signal w_en and NAND gate RND output signal any one be L level when, by L level Signal exports to leakage the input terminal for inhibiting switch driver SD.

NAND gate RND and AND gate RAD have as according to refresh determination unit 13 judgement result come control leakage inhibition open Close the function of the operation control part of the movement of driver SD.That is, equal in write control signal w_en and refresh control signal rf_en When for H level, when NAND gate RND receives to refresh the output signal NRF for the L level that determination unit 13 provides, AND gate RAD is by H electricity Flat signal is supplied to the input terminal that leakage inhibits switch driver SD.On the other hand, when NAND gate RND from refresh determination unit 13 When receiving the offer of output signal NRF of H level, when input signal in is H level, AND gate RAD mentions the signal of L level Supply leakage inhibits the input terminal of switch driver SD.

Next, being illustrated to the movement of the flag holding circuit 200 of the present embodiment.

Firstly, flag holding circuit 200 carries out the write-in of flag " 0 " in the state of having power supply offer.To flag Portion 10 provides the input signal in for indicating the L level of " 0 ".Input signal is made to the grid offer of transistor MSP and transistor MSN The signal of the H level of the logic level reversion of in, transistor MSP become shutdown, and transistor MSN becomes conducting.Node as a result, NFS becomes the current potential near ground connection.

The input signal in of L level is provided to the first input end of NAND gate RND.The output signal of NAND gate RND as a result, As H level.

AND gate RAD will be supplied to leakage with the output signal of write control signal w_en identity logic and inhibit switch driving Device SD.In the write-in of flag " 0 ", the signal level of write control signal w_en is H level, thus inhibits switch to drive leakage Dynamic device SD provides the write control signal w_en of H level.Leakage inhibits switch driver SD that signal level maximum is become power supply The leakage control signal NCS of 2 times of voltage VDD is supplied to the grid that leakage inhibits switch MSL, makes leakage that switch MSL be inhibited to connect It is logical.

When leakage inhibits switch MSL to connect, capacitor CF is discharged, the current potential of node NVF becomes near ground connection.Due to section The current potential of point NVF be ground connection nearby, thus the discharge current caused by discharge part 11 is as zero.Moreover, because the electricity of node NVF Position for ground connection nearby, thus flag determination unit 12 output L level (earth level) output signal OUT.

Next, flag holding circuit 200 carries out the write-in of flag " 1 " in the state of having power supply offer.Flag is set Determine portion 10 and the input signal in for indicating the H level of " 1 " is provided.Moreover, when beginning is written, from logic circuit (not shown) to flag It marks configuration part 10 and the refresh control signal rf_en of L level is provided.

The letter for the L level for inverting the logic level of input signal in is provided to the grid of transistor MSP and transistor MSN Number, transistor MSP, which becomes, to be connected, and transistor MSN becomes shutdown.Node NFS becomes the current potential near supply voltage VDD as a result,.

The refresh control signal rf_en of L level is provided to the second input terminal of NAND gate RND.NAND gate RND as a result, Output signal becomes H level.

AND gate RAD will be supplied to leakage with the output signal of write control signal w_en identity logic and inhibit switch driving Device SD.In the write-in of flag, the signal level of write control signal w_en is H level, thus inhibits switch driving to leakage The write control signal w_en of device SD offer H level.Leakage inhibits switch driver SD correspondingly, by signal level maximum 2 times of the leakage control signal NCS as supply voltage VDD is supplied to the grid that leakage inhibits switch MSL, and leakage is inhibited to open MSL control is closed to connect.

When leakage, which inhibits switch MSL to become, connects, capacitor CF is charged, the current potential of node NVF becomes supply voltage VDD Near.Although the discharge current fixed to ground connection flowing of discharge part 11, flag portion 10 is bigger to the charging of capacitor CF, because And the current potential of node NVF maintains near supply voltage VDD.Flag determination unit 12 is supply voltage due to the current potential of node NVF Near VDD, thus export the output signal OUT of H level.

It is attached by node NVF (that is, charging voltage of capacitor CF) is charged to supply voltage VDD from write-in When the close time, the signal level of refresh control signal rf_en is switched to H level by logic circuit (not shown).

The input signal in of H level is provided as the first input end to NAND gate RND, provides H electricity to the second input terminal The state of flat refresh control signal rf_en.NAND gate RND output makes the logical inverse for refreshing the output signal NRF of determination unit 13 The signal turned.

Refresh the output signal that determination unit 13 exports H level when the current potential of node NVF is higher than threshold voltage vt h_ref NRF exports the output signal NRF of L level when being lower than threshold voltage vt h_ref.Therefore, it is higher than threshold in the current potential of node NVF When threshold voltage Vth_ref, the output signal of NAND gate RND becomes L level, and the output signal of AND gate RAD becomes L level.It is another Aspect, when the current potential of node NVF is lower than threshold voltage vt h_ref, the output signal of NAND gate RND becomes H level, AND gate The output signal of RAD becomes H level.

In this way, when the current potential (that is, charging voltage of capacitor CF) of node NVF is higher than threshold voltage vt h_ref, AND gate The output signal of RAD becomes L level, inhibits the signal of switch driver SD input L level to leakage.Therefore, leakage inhibits to open Driver SD is closed to generate the leakage control signal NCS of L level and be supplied to the grid that leakage inhibits switch MSL.Leakage suppression as a result, Making switch MSL becomes disconnection, thus the charging action of capacitor CF stops.

Then, when the stopping due to charging action and discharging action is dominant, the current potential of node NVF get lower than threshold value electricity When pressing Vth_ref, the output signal of AND gate RAD becomes H level, inhibits the letter of switch driver SD input H level to leakage Number.Therefore, leakage inhibits switch driver SD to generate the leakage control signal NCS of H level and is supplied to leakage inhibition switch MSL Grid.Leakage inhibits switch MSL to become connection as a result, thus carries out the charging of capacitor CF again.

As described above, the flag holding circuit 200 of the present embodiment is starting to charge movement after the stipulated time, saves When the current potential of point NVF is more than threshold voltage vt h_ref, stop charging action.In addition, node NVF potential drop down to threshold value When voltage Vth_ref, charge again.

Therefore, as long as there is power supply offer, the current potential of node NVF ensures threshold voltage vt h_ref or more.That is, node NVF Current potential become power supply offer will stop before, maintain threshold voltage vt h_ref or more voltage level state.Cause This, if the charging voltage of capacitor CF is during Vth_ref is until being discharged to the decision threshold voltage Vth_jdg that flag determines More than 2 seconds, then during can ensure that the flag more than 2 seconds is kept.

Figure 11 B is the decision threshold voltage Vth_jdg for indicating to refresh the threshold voltage vt h_ref determined and flag determines The figure of relationship.If setting the charging voltage of capacitor CF at the time of power supply offer stopping as Vth_ref, as long as from the moment During until the charging voltage of capacitor CF is discharged to the level of the decision threshold voltage Vth_jdg of flag judgement (shown in figure T_ref to t_hd) more than 2 seconds, then can ensure that the EPC according to EPC^TMSession S2, session S3 and the session SL of global standard In flag keep during.

In the flag holding circuit 200 of the present embodiment, in the same manner as the flag holding circuit 100 of embodiment 1, leakage inhibits Switch driver SD, which generates the leakage control signal NCS of 2 times of the signal level with VDD and is supplied to leakage, inhibits switch The grid of MSL, because without dedicated adjuster is in addition arranged.It therefore, can according to the flag holding circuit 200 of the present embodiment The increase of suppression circuit scale and the setting and holding for carrying out flag.

Moreover, after the charging for starting capacitor CF, stopping after specified time limit in the flag holding circuit 200 of the present embodiment Only charging action, whenever node NVF current potential be lower than threshold voltage vt h_ref when make leakage inhibit switch driver SD movement and Carry out the charging again of capacitor CF.Therefore, action current can substantially be cut down.

For example, the flag holding circuit 200 from the present embodiment is different, if inhibiting switch to leakage in the write-in of flag 1 Driver SD is continuously applied clock signal clk, then leaks and persistently produce in the NAND gate or phase inverter inhibited in switch driver SD It is raw to run through electric current.

In contrast, being inhibited obtained by the movement of switch driver SD in the flag holding circuit 200 of the present embodiment by leakage Through electric current until the charging voltage of capacitor CF discharges near supply voltage VDD and is reduced to threshold voltage vt h_ref Time interval (0~t_ref of Figure 11 B) and generate.The virtual value of action current caused by through electric current is by following formula (1) It indicates.

[number 1]

For example, being discharged to if setting the frequency of clock signal clk as 1MHz (period: 1 μ sec) near supply voltage VDD Time interval (t1-t0) until threshold voltage vt h_ref is 1 second, and 1 charging needs 16 clocks, then caused by through electric current The virtual value of action current can be reduced to 1/250 (=4/1000:16 × 10^-6Square root) left and right.

Therefore, according to the flag holding circuit 200 of the present embodiment, it can inhibit action current, and the phase more than fixation Flag is kept between (for example, during more than 2 seconds).

In addition, the present invention is not limited to the embodiments.For example, inhibiting switch driving to leakage in the embodiment Device SD generates the leakage control signal NCS that signal level changes in such a way that maximum value is as 2 times of supply voltage VDD and provides The structure of the grid of switch MSL is inhibited to be illustrated to leakage.But the signal level of leakage control signal NCS is not limited to 2 times of supply voltage VDD.That is, as long as leakage inhibits switch driver SD so that leakage inhibits the grid voltage of switch MSL to be greater than Leakage control signal NCS with the signal level bigger than supply voltage VDD is supplied to by the mode of source-drain voltages Leakage inhibits the grid of switch MSL.

Moreover, inhibiting the source electrode of switch MSL to connect to by the leakage formed by N channel type MOS transistor in the embodiment The case where being connected to node NVF, drain electrode is connected to node NFS is illustrated.But leakage inhibit switch MSL source electrode and As long as any one is connected to node NFS for drain electrode, another one is connected to node NVF.

Moreover, being connected to the other end of current source ID to the drain electrode of transistor MDS in the embodiment, source electrode is connected to The case where node NVD, is illustrated.But as long as the source electrode of transistor MDS and drain electrode any one be connected to current source ID, separately One is connected to node NVD.