阅读说明：本技术 存储器装置及其制造方法 (Memory device and its manufacturing method ) 是由 颜英竹 张维哲 于 2018-05-25 设计创作，主要内容包括：本发明提出了一种存储器装置及其制造方法,其中存储器装置的制造方法,该方法包含形成氧化物层于半导体基底上,形成隔离结构于半导体基底和氧化物层中,隔离结构定义出主动区,形成字线和位线于半导体基底中,其中位线位于字线上方,移除氧化物层,形成凹陷部位于隔离结构与位线之间,以及形成储存节点接点于凹陷部内。此外,由俯视观之,存储器装置包含的储存节点接点与相对应的主动区重叠。(The invention proposes a kind of memory device and its manufacturing methods, the wherein manufacturing method of memory device, this method includes to form oxide skin(coating) on semiconductor base, isolation structure is formed in semiconductor base and oxide skin(coating), isolation structure defines active region, forms wordline and bit line in semiconductor base, its neutrality line is located above wordline, oxide skin(coating) is removed, forms depressed area between isolation structure and bit line, and forms storage node contact in recessed portion.In addition, by overlooking sight, the storage node contact that memory device includes and corresponding active area overlapping.)

1. a kind of manufacturing method of memory device characterized by comprising

Monoxide layer is formed in semiconductor substrate；

An isolation structure is formed in the semiconductor base and the oxide skin(coating), which defines an active region；

A wordline and a bit line are formed in the semiconductor base, wherein the bit line is located above the wordline；

The part oxide skin(coating) is removed, to form a depressed area between the isolation structure and the bit line；And

A storage node contact is formed in the recessed portion.

2. the manufacturing method of memory device as described in claim 1, which is characterized in that forming the isolation structure includes:

An isolated groove is formed in the semiconductor base and the oxide skin(coating)；

One first dielectric material is inserted in a section below of the isolated groove, which includes silica；And

With one second dielectric material the isolated groove is filled up, which includes silicon nitride, wherein the isolation structure Top surface and the top surface of the storage node contact are coplanar.

3. the manufacturing method of memory device as described in claim 1, which is characterized in that forming the wordline includes:

A wordline groove is formed in the semiconductor base and the oxide skin(coating)；

In forming the wordline in the wordline groove；And

The wordline groove is filled up with a dielectric material, which includes silicon nitride.

4. the manufacturing method of memory device as described in claim 1, which is characterized in that forming the bit line includes:

A bit line trenches are formed in the semiconductor base and the oxide skin(coating)；

A wall is formed in the side wall of the bit line trenches；

A conductive part of the bit line is formed in the bit line trenches；And

The bit line trenches are filled up with a dielectric material, which includes silicon nitride, wherein the top surface of the bit line and the storage The top surface of node contact is coplanar.

5. the manufacturing method of memory device as described in claim 1, which is characterized in that further include and forming the storage node Before contact, the semiconductor base is etched via the recessed portion, to form a recessed portion deepened.

6. the manufacturing method of memory device as claimed in claim 5, which is characterized in that the storage node contact is formed in this In the recessed portion of intensification, and the storage node contact includes one first conductive part and one second conducting position in first conductive part Top, the material of first conductive part include polysilicon, and the material of second conductive part includes metal.

7. the manufacturing method of memory device as described in claim 1, which is characterized in that further include and forming the storage node Before contact, one ion implantation technology is carried out to the semiconductor base via the recessed portion, to form a doped region in the recess Below portion.

8. a kind of memory device characterized by comprising

There is semiconductor substrate an isolation structure to be disposed therein and define an active region；

One wordline and a bit line, are set in the semiconductor base, and wherein the bit line is located above the wordline；And

One storage node contact, is set between the isolation structure and the bit line, wherein by overlooking sight, the storage node contact With the corresponding active area overlapping.

9. memory device as claimed in claim 8, which is characterized in that by overlooking sight, the area of the storage node contact Less than or equal to the area of the corresponding active region.

10. memory device as claimed in claim 8, which is characterized in that the top surface of the storage node contact and the isolation junction The top surface of structure is coplanar.

11. memory device as claimed in claim 8, which is characterized in that the bit line includes a conductive part and a dielectric cap layer It is set on the conductive part, the material of the dielectric cap layer includes silicon nitride, and the top surface of the storage node contact and the bit line Top surface is coplanar.

12. memory device as claimed in claim 8, which is characterized in that the isolation structure includes one first dielectric section and one Second dielectric section is located in first dielectric section, and the material of first dielectric section includes silica, and the material of second dielectric section Material includes silicon nitride.

13. memory device as claimed in claim 8, which is characterized in that it is semiconductor-based that the storage node contact is set to this In bottom, which includes one first conductive part and one second conducting position above first conductive part, this first The material of conductive part includes polysilicon, and the material of second conductive part includes metal.

Technical field

The present invention is about semiconductor device, particularly with regard to memory device and its manufacturing method.

Background technique

Dynamic random access memory (dynamic random access memory, DRAM) is that various electronic products are answered With common semiconductor device, dynamic random access memory has multiple unit born of the same parents (unit cell), each unit born of the same parents packet Containing capacitor and transistor, capacitor reads and writees the switch of data as control for temporarily storing data, transistor. The source electrode of transistor is connected to bit line (bit line), and the grid of transistor is connected to wordline (word line), and transistor is responded Control signal from wordline and transmit the data between bit line and capacitor.

In recent years, it in order to the service speed of accelerated semiconductor device and meet the needs of semiconductor device miniatureization, needs Improve the product volume density of dynamic random access memory.However, the product volume density for increasing dynamic random access memory to deposit The technique of reservoir is more complicated and difficult.Therefore, the manufacture of the memory of persistently miniatureization is overcome there are still many needs Problem.

Summary of the invention

In memory device, storage node contact (storage node contact) and active region (active Area overlapping) becomes a challenge with lasting miniatureization.According to an embodiment of the present invention, the manufacture of memory device is provided Method, so that storage node contact and corresponding active area overlapping, storage node contact can be fully located at corresponding master Within the scope of dynamic area, and it can achieve zero offset between storage node contact and corresponding active region.Meanwhile this manufacturing method It does not need to form additional mask for storage node contact, therefore can simplify the processing step of memory device.

In some embodiments, the manufacturing method of memory device is provided, this manufacturing method include formed oxide skin(coating) in On semiconductor base；Isolation structure is formed in semiconductor base and oxide skin(coating), isolation structure defines active region；Form word In semiconductor base, neutrality line is located above wordline for line and bit line；Oxide skin(coating) is removed, to form depressed area in isolation Between structure and bit line；And storage node contact is formed in recessed portion.

In some embodiments, memory device is provided, it includes semiconductor bases, are disposed therein with isolation structure And define active region；Wordline and bit line are set in semiconductor base, and neutrality line is located above wordline；And storage node Contact is set between isolation structure and bit line, wherein by overlooking sight, storage node contact and corresponding active area overlapping.

Second dielectric section of some embodiments according to the present invention, the upper layer of isolation structure can be made of silicon nitride, cover The first dielectric section of the lower layer made of silica is covered, therefore in each processing step of subsequent progress, isolation junction will not occur The material loss of structure, can be to avoid occurring short circuit problem between the adjacent unit born of the same parents of memory device, and then promotes memory device The yields and reliability set.

Detailed description of the invention

In order to which the objects, features and advantages of the embodiment of the present invention can be clearer and more comprehensible, institute's accompanying drawings are cooperated to make below detailed Carefully it is described as follows:

Fig. 1 shows some embodiments according to the present invention, the partial schematic plan view of memory device.

Fig. 2A-Fig. 2 D, Fig. 3 A- Fig. 3 C, Fig. 4 A- Fig. 4 O and Fig. 5 A- Fig. 5 E show some embodiments according to the present invention, system The diagrammatic cross-section in each stage of memory device is made, wherein Fig. 4 B, Fig. 4 F, Fig. 4 N are to be painted along the line B-B of Fig. 1, are schemed 4C, Fig. 4 G, Fig. 4 O are to be painted along the line C-C of Fig. 1, remaining schema is to be painted along the line A-A of Fig. 1.

Fig. 6 A- Fig. 6 B shows other embodiments according to the present invention, manufactures the section in the intermediate stage of memory device Schematic diagram is painted along the line A-A of Fig. 1.

Drawing reference numeral:

100~solid state image pickup device；

101~semiconductor base；

103~oxide skin(coating)；

105~pad nitration case；

107~isolated groove；

109~the first dielectric materials；

109 '~the first dielectric section；

110~wordline；

111~groove；

113~the second dielectric materials；

113 '~the second dielectric section；

115~wordline groove；

116,143,171~ion implantation technology；

117~trap and channel region；

119~gate dielectric；

120~bit line；

The conductive part of 120 '~bit line；

121,133,133 ', 149,175~barrier layer；

The conductive layer of 123~wordline；

125,137~dielectric material；

127~bit line trenches；

129,129 '~wall；

130~active region；

131~conductive material；

131 '~bit line contact；

135, the conductive layer of 135 '~bit line；

137 '~dielectric cap layer；

139,141~recessed portion；

140~isolation structure；

145~lightly mixed drain area；

147~the first conductive parts；

150,150 '~storage node contact；

151~the second conductive parts；

153~dielectric lining；

160~capacitor；

161~first electrode；

163~dielectric layer；

165~second electrode；

167~interlayer dielectric layer；

173~doped region；

177~conductive part；

D1, D2, D3, D4, D5, D6, D7~depth；

T1~thickness.

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on this Embodiment in invention, relevant technical staff in the field's every other reality obtained without making creative work Example is applied, the range of protection of the invention is belonged to.

Refering to fig. 1, some embodiments of display according to the present invention, the partial schematic plan view of memory device 100 are Make schema clearly recognizable, Fig. 1 is only painted the subelement of memory device 100.As shown in Figure 1, memory device 100 Comprising isolation structure 140, defines and be isolated the active region 130 that structure 140 surrounds.In some embodiments, active region 130 Plane figure be the strip region for favouring X-axis and Y-axis, and memory device 100 also extends comprising a plurality of along the y axis Wordline (word line) 110 and a plurality of bit line (bit line) 120 extended along the x axis.

In some embodiments, there is two wordline 110 and one in each active region 130 of memory device 100 Bit line 120, wordline 110 and bit line 120 are interwoven.In addition, memory device 100 also includes storage node contact 150, According to an embodiment of the present invention, by overlooking sight, storage node contact 150 is overlapped with corresponding active region 130, this overlapping includes Storage node contact 150 partly overlaps or completely overlapped with corresponding active region 130.In some embodiments, when storage saves When point contact 150 partly overlaps with corresponding active region 130, the area of storage node contact 150 is less than corresponding active The area in area 130；When storage node contact 150 and completely overlapped corresponding active region 130, storage node contact 150 Area is equal to the area of corresponding active region 130.Embodiment according to the present invention, no matter storage node contact 150 and opposite The active region 130 answered partly overlaps or completely overlapped, and storage node contact 150 is all made generally to be fully located at active region 130 In the range of.As shown in Figure 1, some embodiments according to the present invention, when storage node contact 150 and corresponding active region 130 it is completely overlapped when, the boundary alignment on the boundary of storage node contact 150 and corresponding active region 130, so that storage node The substantially zero offset (zero-shift) overlapping with active region 130 of contact 150.

Refering to Fig. 2A-Fig. 2 D, some embodiments of display according to the present invention, manufacture memory device 100 it is some in Between the stage diagrammatic cross-section, Fig. 2A-Fig. 2 D be painted along the line A-A of Fig. 1.As shown in Figure 2 A, semiconductor base is provided 101, for example, silicon crystal unit sequentially form oxide skin(coating) (oxide layer) 103 and pad nitration case on semiconductor base 101 (pad nitride layer) 105, the material of oxide skin(coating) 103 is, for example, silica, pads the material of nitration case 105 for example For silicon nitride, padding nitration case 105 can be formed by chemical vapor deposition process.Oxide skin(coating) 103 can be by pad oxide (pad Oxide layer) and tetraethoxysilane (tetraethoxysilane, TEOS) oxide layer composition, in some embodiments, The thickness T1 of oxide skin(coating) 103 is about 50nm.

Then, isolating trenches are formed in semiconductor base 101, oxide skin(coating) 103 and pad nitration case 105 by etch process Slot 107 can form patterning photoresist by photoresist coating, exposure and imaging and be used as etching mask before etch process, Or usable hard mask (hard mask), as etching mask, the opening for etching mask corresponds to the position of isolated groove 107 It sets.In some embodiments, depth D1 of the isolated groove 107 in semiconductor base 101 is about 350nm.

The first dielectric material 109 is inserted in isolated groove 107, and the first dielectric material 109 is also deposited on pad nitration case On 105, the first dielectric material 109 is, for example, silica.Later, using chemical mechanical grinding (Chemical Mechanical Polishing, CMP) technique remove isolated groove 107 other than the first dielectric material 109, herein pad 105 conductization of nitration case The stop-layer of mechanical lapping is learned, so that the top surface of the dielectric material 109 in isolated groove 107 and the top surface of pad nitration case 105 are total Plane.

Refering to Fig. 2 B, groove 111 is formed by the first dielectric material 109 in isolated groove 107 using etch process, and The first dielectric section 109 ' is generated in the section below of isolated groove 107.In some embodiments, the bottom surface of groove 111 is lower than half The depth D2 of the top surface of conductor substrate 101 is about 30nm.

Refering to Fig. 2 C, the second dielectric material 113 is inserted in groove 111, and the second dielectric material 113 is also deposited on pad nitrogen Change on layer 105, the second dielectric material 113 is, for example, silicon nitride.Refering to Fig. 2 D, to the second dielectric material 113 and pad nitration case 105 Etch-back (etch back) technique is carried out, the second dielectric material 113 and pad nitration case 105 of part are removed, in isolated groove 107 upper section generates the second dielectric section 113 ', the first dielectric section 109 ' and the second dielectric section 113 ' in isolated groove 107 Isolation structure 140 is constituted, and can be described as shallow trench isolation (shallow trench isolation, STI) structure, isolation structure 140 define the active region 130 of memory device 100, and the top surface of the top surface of isolation structure 140 and oxide skin(coating) 103 at this time It is coplanar.

Hookup 2D, with continued reference to Fig. 3 A- Fig. 3 C, some embodiments of display according to the present invention manufacture memory device The diagrammatic cross-section in 100 some intermediate stages is set, Fig. 3 A- Fig. 3 C is to be painted along the line A-A of Fig. 1.As shown in Figure 3A, it utilizes Etch process etches wordline groove 115 in semiconductor base 101 and oxide skin(coating) 103.Before etch process, it can pass through Photoresist coating, exposure and imaging formed patterning photoresist as etching mask, or use hard mask as etch mask, The opening for etching mask corresponds to the position of wordline groove 115.In some embodiments, wordline groove 115 is in semiconductor base Depth D3 in 101 is about 210nm.Then, ion implantation technology is carried out to semiconductor base 101 by wordline groove 115 116, the trap area (well) and the area channel (channel) are formed in the semiconductor base 101 of the bottom periphery of wordline groove 115 117。

Refering to Fig. 3 B, deposited in sequential gate dielectric 119, barrier (barrier) layer 121 and word in wordline groove 115 The conductive layer 123 of line, and the conductive layer 123 of gate dielectric 119, barrier (barrier) layer 121 and wordline is also deposited on oxidation It (is not painted) in nitride layer 103, the conductive layer 123 of wordline is but also as grid electrode layer.In some embodiments, gate dielectric 119 material is, for example, silica, and the material of barrier layer 121 is, for example, titanium nitride (TiN), the material of the conductive layer 123 of wordline Material is for example, tungsten (W).Later, the deposition materials of the conductive layer 123 of gate dielectric 119, barrier layer 121 and wordline are returned (etch back) technique is etched, forms the wordline 110 of embedding (buried) in wordline groove 115.In some embodiments, The top surface of wordline 110 is about 130nm lower than the depth D4 of the top surface of semiconductor base 101.

Refering to Fig. 3 C, dielectric material 125 is then filled up in wordline groove 115, and dielectric material 125 is also deposited on oxidation In nitride layer 103.In some embodiments, dielectric material 125 is, for example, silicon nitride.

As shown in Figure 4 A, it is formed in semiconductor base 101, oxide skin(coating) 103 and dielectric material 125 using etch process Bit line trenches 127, the bottom surface of bit line trenches 127 is higher than the top surface of wordline 110, and a part is left in wordline groove 115 Dielectric material 125 covers wordline 110.

In some embodiments, the bottom surface of bit line trenches 127 is about lower than the depth D5 of the top surface of semiconductor base 101 60nm.Meanwhile Fig. 4 B and Fig. 4 C is please referred to, it is respectively displayed on 110 surface of wordline and the bit line between two wordline 110 The diagrammatic cross-section of groove 127.As shown in Figure 4 B, along the line B-B of Fig. 1, bit line trenches 127 are formed in right above wordline 110 Dielectric material 125 in.As shown in Figure 4 C, along the line C-C of Fig. 1, bit line trenches 127 pass through dielectric material 125 and are formed in half In conductor substrate 101 and oxide skin(coating) 103, the position of bit line trenches 127 corresponds to the active region 130 between isolation structure 140.

Refering to Fig. 4 D, (conformally) forms wall 129 conformally on the side wall of bit line trenches 127 and bottom surface, And wall 129 is also formed on dielectric material 125.In some embodiments, the material of wall 129 is, for example, silicon nitride, And wall 129 can be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) technique.Although not drawing Show, also conformal landform layer 129, and wall at interval on the side wall of the bit line trenches 127 shown in Fig. 4 B and Fig. 4 C and bottom surface 129 are also formed on dielectric material 125.

Refering to Fig. 4 E, the wall 129 being located on the bottom surface of bit line trenches 127 is removed, using etch process to provide position Line contact (bit line contact) is used.It can be coated with by photoresist before etch process, exposure and imaging forms figure Case photoresist is as etching mask, while refering to fig. 1, to overlook sights, etch mask two wordline 110 of opening exposing it Between linear areas.

Refering to Fig. 4 F and Fig. 4 G, it is respectively displayed on right above wordline 110 and between two wordline 110, after etching The diagrammatic cross-section of wall 129.As illustrated in figure 4f, the bit line trenches 127 along the line B-B of Fig. 1, right above wordline 110 Interior wall 129 is not etched, and the wall 129 being located on dielectric material 125 is then etched removal.Such as Fig. 4 G institute Show, along the line C-C of Fig. 1, the wall 129 on the bottom surface of bit line trenches 127 and on dielectric material 125 is all etched shifting It removes, leaves behind the wall 129 on the side wall of bit line trenches 127, and the oxide skin(coating) 103 on semiconductor base 101 It being partially removed or removes completely, the depth D6 of bit line trenches 127 here can slightly be deepened, in some embodiments, Depth D6 is about 70nm.

Refering to Fig. 4 H, the conductive material 131 of bit line contact, and conductive material 131 are deposited as in bit line trenches 127 It is also deposited on wall 129.In some embodiments, conductive material 131 is, for example, polysilicon.Although not being painted, in Fig. 4 F With conductive material 131 is also deposited in bit line trenches 127 shown in Fig. 4 G, and conductive material 131 is also deposited on the dielectric material of Fig. 4 F On material 125 and on the semiconductor base 101 and isolation structure 140 of Fig. 4 G.

Refering to Fig. 4 I, etch back process is carried out to the conductive material 131 of Fig. 4 H, is formed on the bottom surface of bit line trenches 127 Bit line contact 131 '.Although it is not painted, meanwhile, the conductive material 131 along the line B-B and line C-C of Fig. 1, in bit line trenches 127 Also it is etched back quarter.

Refering to Fig. 4 J, the conductive layer 135 of deposited in sequential barrier layer 133 and bit line in bit line trenches 127, and barrier layer 133 and the conductive layer 135 of bit line be also deposited on wall 129.In some embodiments, the material of barrier layer 133 is, for example, Titanium nitride (TiN), the material of the conductive layer 135 of bit line are, for example, tungsten (W).Although be not painted, meanwhile, along Fig. 1 line B-B and Line C-C, the also conductive layer 135 of deposited in sequential barrier layer 133 and bit line in bit line trenches 127, and barrier layer 133 and bit line Conductive layer 135 be also deposited on the dielectric material 125 of Fig. 4 F and the semiconductor base 101 and isolation structure 140 of Fig. 4 G on.

Refering to Fig. 4 K, the conductive layer 135 of barrier layer 133 and bit line to Fig. 4 J carries out etch back process, in bit line trenches The conductive part 120 ' of the bit line 120 of embedding (buried) is formed in 127, conductive part 120 ' includes bit line contact 131 ', barrier layer 133 ' and conductive layer 135 '.In some embodiments, the top surface of the conductive part 120 ' of bit line 120 is lower than semiconductor base 101 Top surface.Although it is not painted, meanwhile, along the line B-B and line C-C of Fig. 1, barrier layer 133 and bit line in bit line trenches 127 Conductive layer 135 is also etched back quarter.

Refering to Fig. 4 L, dielectric material 137 is filled up in bit line trenches 127, and dielectric material 137 is also deposited on oxide skin(coating) 103 and the top of isolation structure 140 dielectric material 125 and wall 129 on.In some embodiments, dielectric material 137 is for example For silicon nitride.Although it is not painted, meanwhile, along the line B-B and line C-C of Fig. 1, dielectric material is also filled up in bit line trenches 127 137, and dielectric material 137 is also deposited on the dielectric material 125 of Fig. 4 F and the semiconductor base 101 and isolation structure of Fig. 4 G On 140.

Refering to Fig. 4 M, etch back process is carried out to the dielectric material 137 of 140 top of oxide skin(coating) 103 and isolation structure, and This etch back process removes the dielectric material 125 and wall 129 of 140 top of oxide skin(coating) 103 and isolation structure simultaneously, as a result Dielectric cap layer 137 ' is generated on the conductive layer 135 ' of bit line 120, and generates wall on the side wall of bit line trenches 127 129 ', form bit line 120.As shown in Fig. 4 M figure, the top surface (that is, upper surface of dielectric cap layer 137 ') of bit line 120 and oxygen at this time The top surface of compound layer 103 is coplanar.

Meanwhile refering to Fig. 4 N and Fig. 4 O, it is respectively displayed on right above wordline 110 and between two wordline 110, to Jie Electric material 137 carries out the diagrammatic cross-section of the dielectric cap layer 137 ' generated after etch back process and wall 129 '.Such as Fig. 4 N institute Show, along the line B-B of Fig. 1, the top surface of the bit line 120 right above wordline 110 and the top surface of dielectric material 125 are coplanar.Such as Shown in Fig. 4 O, along the line C-C of Fig. 1, the top surface of the bit line 120 between two wordline 110 and the top of semiconductor base 101 Face and the top surface of isolation structure 140 are coplanar.

Hookup 4M, with continued reference to Fig. 5 A- Fig. 5 E, some embodiments of display according to the present invention manufacture memory device The diagrammatic cross-section in 100 some intermediate stages is set, Fig. 5 A- Fig. 5 E is to be painted along the line A-A of Fig. 1.As shown in Figure 5A, it removes Oxide skin(coating) 103 forms recessed portion 139 between isolation structure 140 and bit line 120, and the depth of recessed portion 139 is also oxygen The thickness T1 (refering to Fig. 2A) of compound layer 103, e.g., about 50nm.In some embodiments, it can be moved by wet etch process Except oxide skin(coating) 103.Since wall 129 ' and the material of the second dielectric section 113 ' are different from the material of oxide skin(coating) 103, because This remove oxide skin(coating) 103 etch process will not wall 129 ' to bit line 120 and isolation structure 140 the second dielectric section 113 ' cause to damage, that is, the width of the second dielectric section 113 ' of the thickness of the wall 129 ' of bit line 120 and isolation structure 140 It can remain unchanged.

Refering to Fig. 5 B, in some embodiments, semiconductor base 101 is further etched via the recessed portion 139 of Fig. 5 A, is produced The recessed portion 141 of raw depth down.Due to the silica-base material of semiconductor base 101 and the silicon nitride material of wall 109 ' and every The silicon nitride material of the second dielectric section 113 ' from structure 140 has high degree of etch selectivity in etching, therefore can be accurate Control etching to semiconductor base 101, thickness and isolation structure 140 without will affect the wall 129 ' of bit line 120 The width of second dielectric section 113 '.

In some embodiments, it is counted since the top surface of isolation structure 140, the depth D7 of recessed portion 141 is about 100nm.In addition, before etching semiconductor base 101 via recessed portion 139, while refering to fig. 1, from sight is overlooked, is formed and hidden The active region 130 of a part other than 170 covering of cover active region 130 corresponding with storage node contact 150, in some implementations In example, above-mentioned mask 170 can be the photoetching agent pattern formed between two wordline 110, and covering is located at two wordline 110 Between active region 130, and above bit line 120.After generating recessed portion 141, mask 170 is removed, it then can be via Recessed portion 141 carries out ion implantation technology 143 to semiconductor base 101, forms lightly mixed drain area (lightly doped Drain, LDD) 145.

Refering to Fig. 5 C, the first conductive material layer (not being painted) is first deposited in recessed portion 141, in some embodiments, the One conductive layer is, for example, the polysilicon layer adulterated.Etch back process is carried out to the first conductive material layer, is formed in recessed portion 141 First conductive part 147 of storage node contact 150, the unfilled recessed portion 141 of the first conductive part 147.Then, in the first conductive part 147 top deposited in sequential barrier material layers (not being painted) and the second conductive material layer (not being painted) fill up recessed portion 141, and barrier Material layer and the second conductive material layer are also deposited on the region other than recessed portion 141.In some embodiments, barrier material layer For example, titanium nitride (TiN), the second conductive material layer are, for example, tungsten (W).Then, the barrier material layer of deposition and second is conductive Material layer etch-back forms the barrier layer 149 and the second conductive part 151 of storage node contact 150 in recessed portion 141.

As shown in Figure 5 C, in some embodiments, storage node contact 150 includes the first conductive part 147, barrier layer 149 With the second conductive part 151, wherein the second conductive part 151 is above the first conductive part 147, barrier layer 149 is between the first conductive part 147 and second between conductive part 151, and barrier layer 149 surrounds the second conductive part 151.According to an embodiment of the present invention, storage node The top surface of contact 150 and the top surface of isolation structure 140 are coplanar, and the top surface of storage node contact 150 also with bit line 120 Top surface is coplanar.

Refering to Fig. 5 D, dielectric lining 153, in some embodiments, the material of dielectric lining 153 are formed in the structure of Fig. 5 C Material for example, silicon nitride, dielectric lining 153 cover storage node contact 150, bit line 120 and isolation structure 140.

Refering to Fig. 5 E, capacitor 160 is formed in the structure of Fig. 5 D, and capacitor 160 passes through dielectric lining 153 and is electrically connected It is connected to storage node contact 150.First in dielectric lining 153 formed interlayer dielectric (interlayer dielectric, ILD) layer 167, in some embodiments, the material of interlayer dielectric layer 167 are, for example, silica.In 167 He of interlayer dielectric layer The opening of capacitor 160 is formed in dielectric lining 153.Can by interlayer dielectric layer 167 formed patterning photoresist or For hard mask as etching mask, the opening for etching mask corresponds to the position of capacitor 160.To interlayer dielectric layer 167 and dielectric Lining 153 is etched technique, forms the opening of capacitor 160.By in the opening of capacitor 160 and interlayer dielectric layer The material of deposited in sequential first electrode 161 on 167, dielectric layer 163 and second electrode 165, and above-mentioned deposition materials are carried out Flatening process completes depositing as shown in fig. 5e so that the top surface of capacitor 160 and the top surface of interlayer dielectric layer 167 are coplanar Reservoir device 100.

Fig. 6 A and Fig. 6 B show other embodiments according to the present invention, manufacture some scala medias of memory device 100 The diagrammatic cross-section of section, Fig. 6 A and Fig. 6 B are to be painted along the line A-A of Fig. 1.Hookup 5A is removing oxide refering to Fig. 6 A Layer 103 is formed after recessed portion 139, technique is not etched to semiconductor base 101, first via recessed portion 139 to semiconductor Substrate 101 carries out ion implantation technology (not being painted), forms lightly mixed drain area (LDD) 145.And then via recessed portion 139 Another road ion implantation technology 171 is carried out to semiconductor base 101, forms doped region 173.

Refering to Fig. 6 B, the deposited in sequential barrier material layer (not being painted) and conductive material layer is (not in the recessed portion 139 of Fig. 6 A It is painted) recessed portion 139 is filled up, and barrier material layer and conductive material layer are also deposited on the region other than recessed portion 139.One In a little embodiments, barrier material layer is, for example, titanium nitride (TiN), and conductive material layer is, for example, tungsten (W).Then, to barrier material Layer and conductive material layer carry out etch back process, form the barrier layer 175 and conductive part 177 of storage node contact 150 '.Herein In embodiment, storage node contact 150 ' includes barrier layer 175 and conductive part 177, and barrier layer 175 surrounds the side of conductive part 177 Wall and bottom, and there is doped region 173 in the lower section of neighbouring storage node contact 150 '.In this embodiment, doped region 173 can To provide effect similar with the first conductive part 147 shown in Fig. 5 C.Later, carry out Fig. 5 D and Fig. 5 E's in the structure of Fig. 6 B Processing step forms capacitor 160, completes memory device 100.

According to an embodiment of the present invention, storage is formed in generated recessed portion after removing the oxide skin(coating) for being located at active region Node contact, therefore storage node contact is formed as autoregistration (self-aligned) technique, does not need to be additionally formed and is used for The mask of storage node contact can complete the production of storage node contact, and the manufacture of memory device is allowed to save one The technique of road light shield makes the processing step of memory device more simplified.

Furthermore from sight is overlooked, storage node contact can be fully located in the range of active region, and in some implementations In example, storage node contact is overlapping with active region to can be zero shift, that is, the boundary of storage node contact can be with active The boundary alignment in area, product volume density is increased for this and size is increasingly for the memory device of miniatureization, can reduce storage Contact impedance between node contact and active region, and promote the efficiency and reliability of memory device.

In addition, according to an embodiment of the present invention, bit line is formed in the groove in semiconductor base, the top surface of bit line and storage The top surface of the top surface and isolation structure of depositing node contact is coplanar, that is, bit line be it is embedding in the semiconductor substrate, this makes position The problem of avalanche, will not occur for line, and then improve the reliability of memory device.

In addition, according to an embodiment of the present invention, in removing the technique that the oxide skin(coating) for being located at active region generates recessed portion, with And it is subsequent semiconductor base is etched in the technique for deepening recessed portion, due to the etching selectivity of the material of each element layer, Second dielectric section on the upper layer of isolation structure does not have material loss, that is, the width of isolation structure will not change, therefore stores The risk of short circuit, and the interval between the conductive part of bit line and storage node contact are not had between each unit born of the same parents of device device Layer there will not be material loss, that is, the thickness of wall will not change, therefore there will not be bit line and storage node contact Parasitic capacitance problems.

In addition, some embodiments according to the present invention, second dielectric section on the upper layer of isolation structure can be made of silicon nitride, Its first dielectric section for covering the lower layer made of silica, therefore in each processing step of subsequent progress, will not occur every Material loss from structure, can be to avoid occurring short circuit problem between the adjacent unit born of the same parents of memory device, and then promotes storage The yields and reliability of device device.

Although the embodiment of the present invention is disclosed above, these embodiments are not intended to limit the invention, in the present invention Related technical personnel are when it can be appreciated that without departing from the spirit and scope of the present invention in technical field, when can do it is a little more Dynamic and retouching.Therefore, subject to protection scope of the present invention ought be defined depending on claim.