阅读说明：本技术 半导体储存器结构及其字线制造方法 (Semiconductor memory structure and its wordline manufacturing method ) 是由 不公告发明人 于 2018-05-25 设计创作，主要内容包括：本发明提供一种半导体储存器结构及其字线制造方法,该制造方法在衬底中制备出多重式的字线凹槽,字线凹槽由深度不同的第一字线凹槽与第二字线凹槽水平连通而成,并基于该字线凹槽制作非对称埋入式的字线在衬底中。利用本发明制作得到的埋入式字线作为MOS管的栅极,可以增加MOS管源极与漏极之间的距离,从而使得MOS管具备更长的沟道,有效防止短沟道效应。本发明可以在同样的字线密度下增加字线与字线之间的有效距离,从而降低字线与字线之间的耦合。本发明中相邻两条字线的底端偏离方向相反,可以使得晶体管之间的耦合明显降低。(The present invention provides a kind of semiconductor memory structure and its wordline manufacturing method, the manufacturing method prepares the wordline groove of multiplex in the substrate, wordline groove is connected to by the first different wordline groove of depth with the second wordline groove level, and makes the wordline of asymmetric flush type in the substrate based on the wordline groove.Using the prepared embedded type word line of the present invention as the grid of metal-oxide-semiconductor, the distance between metal-oxide-semiconductor source electrode and drain electrode can be increased, so that metal-oxide-semiconductor has longer channel, effectively prevent short-channel effect.The present invention can increase the effective distance between wordline and wordline under same wordline density, to reduce the coupling between wordline and wordline.The bottom end offset direction of adjacent two wordline is on the contrary, can make the coupling between transistor be substantially reduced in the present invention.)

1. a kind of wordline manufacturing method of semiconductor memory structure, which comprises the steps of:

A substrate is provided, the substrate surface is formed with a substrate protective layer；

Multiple first openings are formed in the substrate protective layer, to form multiple substrates guarantor by first open space Sheath unit；

Formed a hard mask layer it is described first opening in and the substrate protective layer surface；

A photoresist layer is formed on the hard mask layer surface, and formed it is multiple second opening in the photoresist layer, with formed by By multiple photoresist units of second open space, wherein multiple photoresist units are successively arranged in first opening On on the substrate protective layer unit, the width of the width photoresist unit greatly thereon of first opening, And except the both ends of the prominent photoresist unit thereon in both ends of first opening, the substrate protective layer unit The width of the photoresist unit of width greatly thereon, and prominent thereon described in the both ends of the substrate protective layer unit Except the both ends of photoresist unit, so that the substrate in the opened range of second opening has by the hard exposure mask The first occlusion part and the second occlusion part formed is superimposed with the hard mask layer by the substrate protective layer that layer forms；

With the photoresist layer, the hard mask layer and the substrate protective layer collectively as exposure mask, it is recessed that etching obtains multiple wordline Slot in the substrate, the wordline groove have the first wordline concave part corresponding with first occlusion part position and The second wordline concave part corresponding with second occlusion part position, the first wordline concave part and second sub-line are recessed The depth of groove portion is different；

A plurality of wordline is formed in the substrate based on the wordline groove, and the wordline is recessed including being filled in first wordline The first wordline portion in groove portion and the second wordline portion being filled in the second wordline concave part.

2. the wordline manufacturing method of semiconductor memory structure according to claim 1, which is characterized in that form multiple institutes The first opening is stated to include the following steps: in the substrate protective layer

Hardmask material is formed in the substrate protective layer surface；

Photoresist layer is formed in the hard mask material layer surface；

Figure according to first opening is graphical by the photoresist layer；

With the hardmask material and the patterned photoresist layer collectively as exposure mask, etching obtains multiple described the One opening is in the substrate protective layer.

3. the wordline manufacturing method of semiconductor memory structure according to claim 1, which is characterized in that be based on the word Line groove forms a plurality of wordline and includes the following steps: in the substrate

Gate oxide is formed in the wordline groove surfaces

Diffusion barrier layer is formed on the gate oxide surface；

Conductive material is deposited in the diffusion barrier layer surface and fills the full wordline groove；

Carve, makes the conductive material lower than the upper surface of substrate.

4. the wordline manufacturing method of semiconductor memory structure according to claim 1, it is characterised in that: further include being formed Wordline protective layer is the wordline surface the step of.

5. the wordline manufacturing method of semiconductor memory structure according to claim 1, it is characterised in that: the substrate is protected The etch rate of sheath is less than the etch rate of the hard mask layer, so that the depth of the second wordline concave part is less than described The depth of first wordline concave part.

6. the wordline manufacturing method of semiconductor memory structure according to claim 1, it is characterised in that: the substrate is protected The material of sheath is selected from silica, silicon nitride, silicon carbide, silicon oxynitride, carbonitride of silicium, carbon silicon oxynitride and boron nitride institute structure At the one of which of group, the material of the hard mask layer is selected from silica, silicon nitride, silicon carbide, silicon oxynitride, carbon nitridation One of etching selectivity of silicon, carbon silicon oxynitride and the constituted group of boron nitride is higher than the material of the substrate protective layer Material.

7. the wordline manufacturing method of semiconductor memory structure according to claim 1, it is characterised in that: described first hides Stopper is of same size with second occlusion part.

8. the wordline manufacturing method of semiconductor memory structure according to claim 1, it is characterised in that: the wordline Deviate the central plane of the wordline in bottom end, wherein the central plane of the wordline is defined as across the wordline length direction End face center line and perpendicular to the plane of the wordline top surface.

9. the wordline manufacturing method of semiconductor memory structure according to claim 8, it is characterised in that: adjacent two words The bottom end offset direction of line is opposite.

10. the wordline manufacturing method of semiconductor memory structure according to claim 1, it is characterised in that: described first The junction in wordline portion and second wordline portion has re-entrant angle in one.

11. the wordline manufacturing method of semiconductor memory structure according to claim 1, it is characterised in that: the substrate In be more formed with isolation structure, the isolation structure defines multiple active areas in the substrate, and the wordline passes through described Active area and the isolation structure.

12. the wordline manufacturing method of semiconductor memory structure according to claim 1, it is characterised in that: at least one A active area is passed through by two wordline.

13. a kind of semiconductor memory structure characterized by comprising

Substrate；

Wordline groove is formed in the substrate, comprising the first wordline groove with the first depth and with the second depth Second wordline groove, the first wordline groove and the second wordline groove level connection, first depth are greater than described Second depth；

Wordline is formed by connecting by the first wordline portion and the second wordline portion, and it is recessed that first wordline portion is formed in first wordline In slot, second wordline portion is formed in the second wordline groove, and the center of the wordline is deviateed in the bottom end of the wordline Plane, wherein the central plane of the wordline is defined as the end face center line across the wordline length direction and perpendicular to institute The plane of wordline top surface is stated, the bottom end of the wordline is located at the bottom end of the first wordline groove.

14. semiconductor memory structure according to claim 13, it is characterised in that: first wordline portion and described the The junction in two wordline portions has re-entrant angle in one.

15. semiconductor memory structure according to claim 13, it is characterised in that: deviate the bottom end of adjacent two wordline It is contrary.

16. semiconductor memory structure according to claim 13, it is characterised in that: the semiconductor memory further includes The isolation structure being formed in the substrate, the isolation structure define multiple active areas, the wordline in the substrate Across the active area and the isolation structure.

17. semiconductor memory structure according to claim 13, it is characterised in that: at least one described active area quilt Two wordline pass through.

Technical field

The invention belongs to IC manufacturing field, it is related to a kind of semiconductor memory structure and its wordline manufacturing method.

Background technique

As semiconductor storage unit (such as dynamic random access memory (DRAM)) becomes highly integrated, unit cell exists Area in semiconductor substrate can correspondingly be gradually reduced, and include the channel in metal-oxide semiconductor (MOS) (MOS) transistor Length can be also gradually reduced, and the reduction of channel length easily causes the generation of short-channel effect.In order to maintain semiconductor storage unit It is highly integrated, need to take measures to limit short-channel effect.

Embedded type word line (alternatively referred to as buried gate) provides one kind newly to increase the integration density of semiconductor devices Selection.Embedded type word line refers to the inside that wordline is embedded in semiconductor substrate, can reduce significantly in wordline and bit line Between parasitic capacitance, significantly improve semiconductor devices voltage read operation reliability.Fig. 1 is shown as a kind of active area With the plane figure of wordline array, Fig. 2 is shown as the A-A ' of Fig. 1 to sectional view, wherein isolation structure 101, which is formed in, partly leads In body substrate 102, multiple active areas 103 are defined in the semiconductor substrate 102, and a plurality of wordline 104 is embedded to semiconductor substrate 102 In, and active area 103 and isolation structure 101 are passed through, matcoveredn 105 is formed above wordline 104.From Figure 2 it can be seen that existing bury Enter formula wordline using symmetrical structure.

With further increasing for integrated level, also start to face using the semiconductor memory structure of buried gate wordline Therefore how the problem of short-channel effect provides a kind of new semiconductor memory structure and its wordline manufacturing method, to prevent There is short-channel effect using the semiconductor memory structure of buried gate wordline, it is urgently to be resolved to become those skilled in the art An important technological problems.

Summary of the invention

In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of semiconductor memory structure and Its wordline manufacturing method, for solving highly integrated, the existing semiconductor using buried gate word line structure with device Reservoir configuration can not effectively prevent the problem of short-channel effect.

In order to achieve the above objects and other related objects, the present invention provides a kind of wordline manufacture of semiconductor memory structure Method includes the following steps:

S1: providing a substrate, and the substrate surface is formed with a substrate protective layer；

S2: multiple first openings are formed in the substrate protective layer, to be formed by the more of first open space A substrate protective layer unit；

S3: formed a hard mask layer it is described first opening in and the substrate protective layer surface；

S4: forming a photoresist layer on the hard mask layer surface, and forms multiple second openings in the photoresist layer, with Form multiple photoresist units by second open space, wherein multiple photoresist units are successively arranged in described the On one opening and on the substrate protective layer unit, the photoresist unit of the width of first opening greatly thereon Width, and except the both ends of the prominent photoresist unit thereon in both ends of first opening, the substrate protective layer The width of the photoresist unit of the width of unit greatly thereon, and the both ends of the substrate protective layer unit protrude thereon The photoresist unit both ends except so that the substrate in the opened range of second opening is with by described It first occlusion part of hard mask layer composition and it is superimposed form second with the hard mask layer by the substrate protective layer blocks Portion；

S5: with the photoresist layer, the hard mask layer and the substrate protective layer collectively as exposure mask, etching obtains multiple In the substrate, the wordline groove has the first wordline groove corresponding with first occlusion part position to wordline groove Portion and the second wordline concave part corresponding with second occlusion part position, the first wordline concave part and described second The depth of sub-line concave part is different；

S6: forming a plurality of wordline in the substrate based on the wordline groove, and the wordline includes being filled in described the The first wordline portion in one wordline concave part and the second wordline portion being filled in the second wordline concave part.

Optionally, multiple first openings are formed to include the following steps: in the substrate protective layer

S2-1: hardmask material is formed in the substrate protective layer surface；

S2-2: photoresist layer is formed in the hard mask material layer surface；

S2-3: the figure according to first opening is graphical by the photoresist layer；

S2-4: with the hardmask material and the patterned photoresist layer collectively as exposure mask, etching is obtained Multiple first openings are in the substrate protective layer.

Optionally, a plurality of wordline is formed in the substrate based on the wordline groove to include the following steps:

S6-1: gate oxide is formed in the wordline groove surfaces

S6-2: diffusion barrier layer is formed on the gate oxide surface；

S6-3: deposition conductive material is in the diffusion barrier layer surface and fills the full wordline groove；

S6-4: carve, make the conductive material lower than the upper surface of substrate.

Optionally, further include the steps that being formed wordline protective layer on the wordline surface.

Optionally, the etch rate of the substrate protective layer is less than the etch rate of the hard mask layer, so that described the The depth of two wordline concave parts is less than the depth of the first wordline concave part.

Optionally, the material of the substrate protective layer is selected from silica, silicon nitride, silicon carbide, silicon oxynitride, carbon nitridation The one of which of silicon, carbon silicon oxynitride and the constituted group of boron nitride, the material of the hard mask layer are selected from silica, nitridation Silicon, silicon carbide, silicon oxynitride, carbonitride of silicium, carbon silicon oxynitride and one of etching selection of the constituted group of boron nitride Than the material for being higher than the substrate protective layer.

Optionally, first occlusion part and second occlusion part is of same size.

Optionally, the central plane of the wordline is deviateed in the bottom end of the wordline, wherein the central plane of the wordline is fixed Justice is across the end face center line of the wordline length direction and perpendicular to the plane of the wordline top surface.

Optionally, the bottom end offset direction of adjacent two wordline is opposite.

Optionally, the junction in first wordline portion and second wordline portion has re-entrant angle in one.

Optionally, isolation structure is more formed in the substrate, the isolation structure defines multiple in the substrate Active area, the wordline pass through the active area and the isolation structure.

Optionally, at least one described active area is passed through by two wordline.

The present invention also provides a kind of semiconductor memory structures, comprising:

Substrate；

Wordline groove is formed in the substrate, deeply comprising the first wordline groove with the first depth and with second Second wordline groove of degree, the first wordline groove and the second wordline groove level connection, first depth are greater than Second depth；

Wordline is formed by connecting by the first wordline portion and the second wordline portion, and first wordline portion is formed in first word In line groove, second wordline portion is formed in the second wordline groove, and the wordline is deviateed in the bottom end of the wordline Central plane, wherein the central plane of the wordline is defined as across the end face center line of the wordline length direction and vertical Plane in the wordline top surface, the bottom end of the wordline are located at the bottom end of the first wordline groove.

Optionally, the junction in first wordline portion and second wordline portion has re-entrant angle in one.

Optionally, the bottom end offset direction of adjacent two wordline is opposite.

Optionally, the semiconductor memory further includes the isolation structure being formed in the substrate, the isolation structure Multiple active areas are defined in the substrate, and the wordline passes through the active area and the isolation structure.

Optionally, at least one described active area is passed through by two wordline.

As described above, semiconductor memory structure and its wordline manufacturing method of the invention, have the advantages that (1) present invention by preparing the wordline groove of multiplex in the substrate, and forms a plurality of wordline in substrate based on wordline groove In, since wordline groove is connected to by the first different wordline groove of depth with the second wordline groove level, gained word Line is asymmetric flush type, using the prepared embedded type word line of the present invention as the grid of metal-oxide-semiconductor, can increase metal-oxide-semiconductor The distance between source electrode and drain electrode, so that metal-oxide-semiconductor has longer channel, effectively prevent short-channel effect；(2) of the invention The effective distance between wordline and wordline can increased under same wordline density, to reduce the coupling between wordline and wordline It closes；(3) in the present invention, the bottom end offset direction of adjacent two wordline is on the contrary, make between a part of adjacent two wordline bottom ends Distance increase, the distance between a part of adjacent two wordline bottom ends reduce, and test result shows for adjacent two wordline The case where the distance between bottom end reduces, device performance influence is unobvious, and for the distance between adjacent two wordline bottom ends The case where increase, the coupling between transistor are substantially reduced.

Detailed description of the invention

Fig. 1 is shown as the plane figure of a kind of active area and wordline array in the prior art.

Fig. 2 is shown as the A-A ' of Fig. 1 to sectional view.

Fig. 3 is shown as the process flow chart of the wordline manufacturing method of semiconductor memory structure of the invention.

The surface that the wordline manufacturing method that Fig. 4 is shown as semiconductor memory structure of the invention provides is formed with substrate guarantor The diagrammatic cross-section of the substrate of sheath.

Fig. 5 is shown as the plane figure of active area in semiconductor memory structure of the invention, wordline and the first opening.

The wordline manufacturing method that Fig. 6-Fig. 7 is shown as semiconductor memory structure of the invention forms multiple first openings and exists Schematic diagram in the substrate protective layer.

The wordline manufacturing method that Fig. 8 is shown as semiconductor memory structure of the invention forms a hard mask layer described the One opening in and the substrate protective layer surface schematic diagram.

The wordline manufacturing method that Fig. 9 is shown as semiconductor memory structure of the invention forms a photoresist layer and covers firmly described Film surface, and form schematic diagram of multiple second openings in the photoresist layer.

Figure 10 be shown as the wordline manufacturing method of semiconductor memory structure of the invention with the photoresist layer, described cover firmly Collectively as exposure mask, etching obtains the schematic diagram of multiple wordline grooves in the substrate for film layer and the substrate protective layer.

The wordline manufacturing method that Figure 11-Figure 13 is shown as semiconductor memory structure of the invention is based on the wordline groove Form schematic diagram of a plurality of wordline in the substrate.

The wordline manufacturing method that Figure 14 is shown as semiconductor memory structure of the invention forms wordline protective layer described The schematic diagram on wordline surface.

Component label instructions

101 isolation structures

102 semiconductor substrates

103 active areas

104 wordline

105 protective layers

S1~S6 step

201 substrates

202 substrate protective layers

203 isolation structures

204 active areas

205 hardmask materials

206 photoresist layer

207 first openings

208 substrate protective layer units

209 hard mask layers

210 photoresist layers

211 second openings

212 photoresist units

213 first occlusion parts

214 second occlusion parts

215 wordline grooves

2151 first wordline concave parts

2152 second wordline concave parts

216 wordline

2161 first wordline portions

2162 second wordline portions

217 gate oxides

218 diffusion barrier layers

219 conductive materials

220 wordline protective layers

Re-entrant angle in θ

W₁The width of first opening

W₂, W₄The width of photoresist unit

W₃The width of substrate protective layer unit

The central plane of MM ' wordline

NN ' wordline top surface

Specific embodiment

Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from Various modifications or alterations are carried out under spirit of the invention.

Fig. 3 is please referred to Figure 14.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its Assembly layout kenel may also be increasingly complex.