阅读说明：本技术 半导体器件层叠封装件、半导体器件封装件及其制造方法 (Packaging part, semiconductor device package and its manufacturing method is laminated in semiconductor devices ) 是由 洪民基 李镕官 于 2019-01-24 设计创作，主要内容包括：半导体器件层叠封装件(PoP)包括：第一封装件；第二封装件；中介层；第一模塑层和第二模塑层。第一封装件包括第一衬底和第一衬底上的第一半导体芯片。第二封装件布置在第一封装件上,并包括第二衬底和第二衬底上的第二半导体芯片。中介层布置在第一封装件和第二封装件之间,并连接第一封装件和第二封装件。第一模塑层填充第一封装件和中介层之间的空间。第二模塑层覆盖中介层的上表面。(It includes: the first packaging part that packaging part (PoP), which is laminated, in semiconductor devices；Second packaging part；Intermediary layer；First molding layer and the second molding layer.First packaging part includes the first semiconductor chip on the first substrate and the first substrate.Second packaging part is arranged on the first packaging part, and including the second semiconductor chip on the second substrate and the second substrate.Intermediary layer is arranged between the first packaging part and the second packaging part, and connects the first packaging part and the second packaging part.First molding layer fills the space between the first packaging part and intermediary layer.The upper surface of second molding layer covering intermediary layer.)

1. packaging part is laminated in a kind of semiconductor devices, comprising:

First packaging part comprising the first semiconductor chip on the first substrate and first substrate；

Second packaging part, on first packaging part, second packaging part includes the second substrate and second substrate On the second semiconductor chip；

Intermediary layer, between first packaging part and second packaging part, the intermediary layer is electrically connected first envelope Piece installing and second packaging part；

First molding layer fills the space between first packaging part and the intermediary layer；And

Second molding layer covers the upper surface of the intermediary layer.

2. packaging part is laminated in semiconductor devices according to claim 1, wherein first molding layer and second mould Mould layer material having the same.

3. packaging part is laminated in semiconductor devices according to claim 1, wherein the thickness of second molding layer is less than institute State the distance between intermediary layer and second substrate.

4. packaging part is laminated in semiconductor devices according to claim 1, wherein first substrate includes groove, the ditch Slot has the bottom being located in first substrate, and

First semiconductor chip is mounted on the surface of the bottom of the restriction groove of first substrate.

5. packaging part is laminated in semiconductor devices according to claim 4, wherein first packaging part further comprises nothing Source electronic building brick, and

The passive electric components are arranged on the part arranged side by side with the groove vertical of the lower surface of first substrate.

It further comprise bottom filler, the bottom is filled out 6. packaging part is laminated in semiconductor devices according to claim 1 It fills object and fills space between first substrate and first semiconductor chip.

7. packaging part is laminated in semiconductor devices according to claim 6, wherein first substrate includes groove, and

At least part of the bottom filler fills the groove.

8. packaging part is laminated in semiconductor devices according to claim 1, wherein the intermediary layer has lower surface, and wrap It includes from the lower surface of the intermediary layer multiple supporting elements outstanding.

9. packaging part is laminated in semiconductor devices according to claim 1, further comprise be inserted in first substrate and Bulge-structure between first semiconductor chip,

Wherein the bulge-structure is electrically connected first substrate and first semiconductor chip.

10. packaging part is laminated in semiconductor devices according to claim 9, wherein the bulge-structure is described including being connected to The column of first semiconductor chip and the solder layer for connecting first substrate and the column.

11. packaging part is laminated in semiconductor devices according to claim 1, wherein first semiconductor chip is logic core Piece, and

Second semiconductor chip is memory chip.

12. a kind of semiconductor device package, comprising:

First substrate；

First semiconductor chip, on first substrate；

Intermediary layer, in the first semiconductor core on piece, the intermediary layer is electrically connected to first substrate；

Molded parts comprising the first molding layer and the second molding layer, first semiconductor chip are at least partially embedded institute The first molding layer is stated, and second molding layer covers the upper surface of the intermediary layer；

Second substrate, in second molding layer；

Second semiconductor chip, on second substrate；

First electric connector extends through first molding layer and is electrically connected first substrate and the intermediary layer； And

Second electric connector, extends through second molding layer, second electric connector be electrically connected the intermediary layer and Second substrate.

13. semiconductor device package according to claim 12, wherein the molded parts include epoxy mold chemical combination Object.

14. semiconductor device package according to claim 12, further comprises:

Second molded parts, on second substrate,

Wherein second molded parts cover second semiconductor chip.

15. semiconductor device package according to claim 12, wherein second electric connector is projected into described The top of the upper surface of two molding layer.

16. semiconductor device package according to claim 12, wherein there is groove in first substrate,

First semiconductor chip is mounted on the surface of the bottom of the restriction groove of first substrate；

The intermediary layer has lower surface and including multiple supporting element, and the multiple supporting element is protruded from the lower surface and face To the upper surface of first semiconductor chip.

17. packaging part is laminated in a kind of semiconductor devices, comprising:

First semiconductor device package comprising the first electronic substrate of the package on package and be arranged in it is described first electricity First semiconductor chip of the package on package being electrically connected on sub- substrate and with first electronic substrate；

Second semiconductor device package is arranged on first semiconductor device package, second semiconductor device Part packaging part includes the second electronic substrate of the package on package and is arranged in second electronic substrate and with described Second semiconductor chip of the package on package of two electronic substrates electrical connection；

Intermediary layer is inserted between first semiconductor device package and second semiconductor device package, institute It states intermediary layer to be made of insulating substrate and wiring of reallocating, the insulating substrate has respectively for first semiconductor devices The lower surface of packaging part and upper surface towards second semiconductor device package, the reallocation wiring include first leading Electrical pattern and the second conductive pattern, first conductive pattern is at the lower surface of the insulating substrate relative to the intermediary layer Exposure, second conductive pattern relative to the intermediary layer exposure and are electrically connected at the upper surface of the insulating substrate First conductive pattern；

Molded parts comprising the first molding layer and the second molding layer, described the first of first semiconductor device package Semiconductor chip is at least partially embedded first molding layer, and second molding layer is located at the insulation of the intermediary layer Between the upper surface of substrate and second semiconductor device package；

First electric connector extends through first molding layer, and first conductive pattern of the intermediary layer is electric It is connected to first electronic substrate；With

Second electric connector extends through second molding layer, and second conductive pattern of the intermediary layer is electric It is connected to second electronic substrate,

Wherein first molding layer covers the lower surface of the insulating substrate of the intermediary layer,

Second molding layer covers the upper surface of the insulating substrate of the intermediary layer, and

In first molding layer on opposite sides and the second molding layer area coverage having the same of the intermediary layer.

18. packaging part is laminated in semiconductor devices according to claim 17, wherein first molding layer and described second Molding layer molding compounds having the same.

19. packaging part is laminated in semiconductor devices according to claim 17, wherein second molding layer and described second Electronic substrate is spaced apart.

20. packaging part is laminated in semiconductor devices according to claim 17, wherein the molded parts make the intermediary layer The side surface of the insulating substrate be exposed to the outside of the package on package.

Technical field

Present inventive concept is related to multi-chip semiconductor device packaging part (such as package on package (package-on- Package, POP) type semiconductor package part) and manufacturing method.

Background technique

With the development of electronic industry, high-performance, high speed and compact electronic building brick demand have increased.In response to this Trend, the semiconductor chip of multiple stackings are already installed on single package substrate, or half including on one or more chips Conductor device packaging part has been stacked on another semiconductor device package.For example, having been developed embedded about the latter Packaging part (package-in-package, PIP) type semiconductor package part and package on package (POP) type semiconductor package part.

POP type semiconductor package part is generally included to be arranged between packaging part and lower packaging part and is encapsulated on being electrically connected The intermediary layer (interposer) of part and lower packaging part.However, may be in the manufacture of POP type semiconductor package part using intermediary layer In there are several q&rs.

Summary of the invention

The one aspect conceived according to the present invention provides a kind of package on package (POP) comprising: the first packaging part, institute Stating the first packaging part includes the first semiconductor chip on the first substrate and the first substrate；The second encapsulation on first packaging part Part, the second packaging part include the second semiconductor chip on the second substrate and the second substrate；First packaging part and the second packaging part Between intermediary layer, intermediary layer is electrically connected the first packaging part and the second packaging part；Fill the first packaging part and the second packaging part it Between space the first molding layer；And the second molding layer of the upper surface of covering intermediary layer.

The another aspect conceived according to the present invention, a kind of semiconductor device package, the semiconductor devices envelope are provided Piece installing includes: the first substrate；The first semiconductor chip on first substrate；The intermediary layer of first semiconductor core on piece, intermediary layer It is electrically connected to the first substrate；Molded parts comprising the first molding layer and the second molding layer, the first semiconductor chip is at least partly Ground is embedded in the first molding layer, and the second molding layer covers the upper surface of intermediary layer；The second substrate in second molding layer；Second lining The second semiconductor chip on bottom；First electric connector extends through the first molding layer and is electrically connected the first substrate and intermediary Layer；And second electric connector, extend through the second molding layer.Second electric connector is electrically connected intermediary layer and the second substrate.

The another aspect conceived according to the present invention, provides a kind of semiconductor device package, comprising: the first substrate；The The first semiconductor chip on one substrate；The intermediary layer of first semiconductor core on piece；Connect the first of the first substrate and intermediary layer Connecting component；Cover first molding layer of the first semiconductor chip and first connecting portion part；The second substrate on intermediary layer；Connection The second connecting portion part of intermediary layer and the second substrate, and cover second molding of a part of the side wall of second connecting portion part Layer.

The another aspect conceived according to the present invention provides a kind of semiconductor devices stacking packaging part (PoP), comprising: the Semiconductor device packaging part；The second semiconductor devices being arranged on the first semiconductor device package；It is inserted in the first half Intermediary layer between conductor device packaging part and the second semiconductor device package；Around the molded parts of intermediary layer molding；With And it extends through molded parts and is electrically connected to the first electric connector of intermediary layer and the first semiconductor package part and extends through Molded parts and the second electric connector for being electrically connected to intermediary layer and the second semiconductor package part.First semiconductor device package The first electronic substrate including PoP and be arranged in the first electronic substrate and be electrically connected to the first electronic substrate PoP the Semiconductor chip.Second semiconductor device package includes the second electronic substrate of PoP and is arranged in the second electronic substrate And it is electrically connected to the second semiconductor chip of the PoP of the second electronic substrate.Intermediary layer is by insulating substrate and wiring structure of reallocating At the insulating substrate has respectively for the lower surface of the first semiconductor device package and towards the second semiconductor packages The upper surface of part.Wiring of reallocating includes the first conductive pattern and the second conductive pattern, and the first conductive pattern is in insulating substrate Relative to intermediary layer exposure at lower surface, the second conductive pattern is at the upper surface of insulating substrate relative to intermediary layer exposure and electricity Connect the first conductive pattern.Molded parts include the first molding layer and the second molding layer, and the half of the first semiconductor device package Conductor chip is at least partially embedded the first molding layer, and the second molding layer is located at the upper surface and second of the insulating substrate of intermediary layer Between semiconductor device package.First electric connector extend through the first molding layer and by the first conductive pattern of intermediary layer electricity It is connected to the first electronic substrate.Second electric connector extends through the second molding layer and the second conductive pattern of intermediary layer is electrically connected It is connected to the second electronic substrate.First molding layer covers the lower surface of the insulating substrate of intermediary layer, and the second molding layer covers intermediary layer Insulating substrate upper surface.Moreover, the first molding layer and the second molding layer on opposite sides in intermediary layer are having the same Area coverage.

The another aspect conceived according to the present invention, a kind of side of manufacturing semiconductor devices package on package (PoP) is also provided Method, comprising: providing includes the first substrate and the first packaging part for installing the first semiconductor chip on the first substrate；First Semiconductor core on piece forms intermediary layer, to be connected to the first substrate；Molded parts are formed to fill the first packaging part and intermediary layer Between space and cover the upper surface of intermediary layer；And the second packaging part is formed on molded parts to be connected to intermediary layer.

Detailed description of the invention

Fig. 1 is the layout of package on package (POP) the type semiconductor package part conceived according to the present invention.

Fig. 2 is package on package (POP) the type semiconductor package part conceived according to the present invention intercepted along the line A-A' of Fig. 1 Exemplary sectional view.

Fig. 3 is package on package (POP) the type semiconductor package part conceived according to the present invention intercepted along the line A-A' of Fig. 1 Another exemplary sectional view.

Fig. 4 is package on package (POP) the type semiconductor package part conceived according to the present invention intercepted along the line A-A' of Fig. 1 Another exemplary sectional view.

Fig. 5 is package on package (POP) the type semiconductor package part conceived according to the present invention intercepted along the line A-A' of Fig. 1 Another exemplary sectional view.

Fig. 6 is package on package (POP) the type semiconductor package part conceived according to the present invention intercepted along the line A-A' of Fig. 1 Another exemplary sectional view.

Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11, Figure 12, Figure 13 and Figure 14 are package on package (POP) type semiconductor package parts Exemplary sectional view during its manufacturing process, show conceive according to the present invention for manufacturing package on package (POP) The example of the method for type semiconductor package part.

Figure 15, Figure 16 and Figure 17 are example of package on package (POP) the type semiconductor package part during its manufacturing process Sectional view, show the method for manufacturing package on package (POP) type semiconductor package part conceived according to the present invention Another example.

Figure 18 is exemplary sectional view of package on package (POP) the type semiconductor package part during its manufacturing process, is shown Another example for the method for manufacturing package on package (POP) type semiconductor package part conceived according to the present invention is gone out.

Specific embodiment

The various examples of present inventive concept are described more fully with reference to the drawings.However, present inventive concept can be with Many alternative forms are implemented, and should not be construed as limited to the example illustrated here.

Fig. 1 is the various examples of package on package (POP) the type semiconductor package part that can be applied to conceive according to the present invention Layout.

Fig. 2 be along Fig. 1 line A-A' intercept one as exemplary sectional view.

With reference to Fig. 1 and Fig. 2, the POP type semiconductor package part conceived according to the present invention may include the first packaging part 100, in Interlayer 200, the second packaging part 300, the first molded parts 250 and the second molded parts 350.Terms used herein " molding " can be with It is understood as referring to the component by molding or the layer by molding, i.e., a part of the layer formed by molding.

First packaging part 100 may include the first substrate 101 and the first semiconductor chip 120.

First substrate 101 can be package substrate.For example, the first substrate 101 can be printed circuit board (PCB) or ceramics Substrate.First substrate 101 may include single insulating layer or multiple insulation and wiring layer.First substrate 101 can have each other Opposite upper and lower surfaces.

Conductive pattern 104 and the first connection pad 106 can be arranged in the first lining on first lower conductive pattern 102, first On bottom 101.For example, the first lower conductive pattern 102 can be arranged on the lower surface of the first substrate 101, and conductive pattern on first Case 104 and the first connection pad 106 can be arranged on the upper surface of the first substrate 101.Therefore, the insulation of the first substrate 101 The wiring (including conductive pattern 102, conductive pattern 104, pad 106 etc.) of layer and the first substrate 101 constitutes electronic substrate (electronic substrate)。

Conductive pattern 104 and the first connection pad 106 may be coupled to circuit (example on first lower conductive pattern 102, first Such as, in the first substrate 101) wiring pattern.Conductive pattern 104 and the first connection weldering on first lower conductive pattern 102, first Disk 106 can be conducting element (trace or pad), and the wiring pattern of the first substrate 101 can be connected to by the conducting element It is external.

In some instances, the first substrate 101 includes circuit element 110 (electronic building brick).Circuit element 110 may include One or more active electronic components (for example, transistor) and/or one or more passive electric components (for example, at least one Capacitor, resistor or inductor).Fig. 2 shows circuit elements 110 to be arranged in the first substrate 101, but structure of the present invention Think without being limited thereto.On the contrary, circuit element 110 can be arranged on the upper surface or lower surface of the first substrate 101.

Connection terminal 140 can be arranged on the lower surface of the first substrate 101.For example, connection terminal 140 can adhere to First lower conductive pattern 102.Connection terminal 140 can have spheroid form or spherical form, but not limited to this.

First packaging part 100 can be electrically connected to external devices by connection terminal 140.Therefore, connection terminal 140 can be to First packaging part 100 provides electric signal and/or the electric signal exported from the first packaging part 100 can be supplied to external devices.

Connection terminal 140 can be formed by least one material selected from the group being made of following material: tin (Sn), lead (Pb), nickel (Ni), golden (Au), silver-colored (Ag), copper (Cu) and bismuth (Bi).

First semiconductor chip 120 may be mounted on the first substrate 101.In some instances, the first semiconductor chip 120 be non-memory chip, such as logic chip.For example, the first semiconductor chip 120 can be application processor (AP).

In the example shown, only one semiconductor chip is arranged on the first substrate 101, but present inventive concept is not limited to This.For example, multiple semiconductor chips can be arranged side by side on the first substrate 101, or the first lining can be sequentially stacked on On bottom 101.

In some instances, the first semiconductor chip 120 is mounted on the first substrate 101 by flip chip bonding method On.For example, the first bulge-structure 130 is inserted between the first substrate 101 and the first semiconductor chip 120, with electrical connection First substrate 101 and the first semiconductor chip 120.

In some instances, the first bulge-structure 130 may include the first rod structure 132 and the first solder layer 134.

First rod structure 132 can be prominent from the lower surface of the first semiconductor chip 120.First rod structure 132 can connect It is connected to the first semiconductor chip 120.First rod structure 132 can be by least one material selected from the group being made of following material It is formed: copper (Cu), copper alloy, nickel (Ni), nickel alloy, palladium (Pd), platinum (Pt), golden (Au) and cobalt (Co), but not limited to this.

First solder layer 134 can be arranged between the first rod structure 132 and the first substrate 101.First solder layer 134 can With the first rod structure of connection 132 and the first connection pad 106.First solder layer 134 can have spheroid form or spherical form, But not limited to this.First solder layer 134 may include at least one material selected from the group being made of following material: tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver-colored (Ag), zinc (Zn) and lead (Pb), but not limited to this.

Intermediary layer 200 is inserted between the first packaging part 100 and the second encapsulation 300.Intermediary layer 200 (insulating substrate) With upper and lower surfaces relative to each other.First packaging part 100 and the second packaging part 300 can be held by intermediary layer 200 It changes places and is connected to each other.Intermediary layer 200 can prevent 300 warpage of the first packaging part 100 and the second packaging part.

Intermediary layer 200 may include conductive pattern 204 on the second lower conductive pattern 202 and second.For example, the second lower conduction Pattern 202 can be arranged on the lower surface of intermediary layer 200 (insulating substrate), and conductive pattern 204 can be with cloth on second It sets on the upper surface of intermediary layer 200 (insulating substrate).

Conductive pattern 204 is connected to the wiring in the insulating substrate of intermediary layer 200 on second lower conductive pattern 202 and second Pattern.Conductive pattern 204 can be conducting element (for example, trace or pad) on second lower conductive pattern 202 and second, intermediary The wiring pattern of layer 200 can be connected to outside by the conducting element.Conductive pattern on second lower conductive pattern 202, second 204 and wiring pattern may be considered that composition reallocate wiring.Therefore, intermediary layer 200 can be by insulating substrate and reallocation cloth Line composition, signal are transmitted through insulating substrate by reallocation wiring.

In some instances, inserter 200 is by including that first connecting portion part 240 of electric connector is connected to the first substrate 101.First connecting portion part 240 can be arranged between the first substrate 101 and intermediary layer 200, to be electrically connected 101 He of the first substrate Intermediary layer 200.For example, first connecting portion part 240 can be electrically connected conductive pattern 104 and the second lower conductive pattern 202 on first. In some instances, as shown in Figure 1, in the plan view, multiple electric connectors of first connecting portion part 240 surround the first semiconductor Chip 120.

First connecting portion part 240 may include at least one material selected from the group being made of following material: tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver-colored (Ag), zinc (Zn) and lead (Pb), but not limited to this.

In the illustrated example shown in fig. 2, intermediary layer 200 is spaced apart with the first semiconductor chip 120, but present inventive concept is not It is limited to this.For example, intermediary layer 200 can be according to first semiconductor chip of dimension contacts 120 of first connecting portion part 240.

Second packaging part 300 can be arranged on intermediary layer 200.Second packaging part 300 may include 301 He of the second substrate Second semiconductor chip 320.

Second substrate 301 can be package substrate.For example, the second substrate 301 can be printed circuit board (PCB) or ceramics Substrate.Second substrate 301 may include single insulating layer or multiple insulation and wiring layer.Second substrate 301 can have each other Opposite upper and lower surfaces.

Conductive pattern 302 and the second connection pad 306 can be arranged on the second substrate 301 under third.For example, under third Conductive pattern 302 can be arranged on the lower surface of the second substrate 301, and the second connection pad 306 can be arranged in second On the upper surface of substrate 301.Therefore, one or more insulating layers of the second substrate 301 and the second substrate 301 wiring (including Conductive pattern 302, pad 306 etc.) constitute electronic substrate.

Conductive pattern 302 and the second connection pad 306 may be coupled to the wiring pattern in the second substrate 301 under third, For example, the wiring pattern of circuit.Conductive pattern 302 and the second connection pad 306 can be conducting element (for example, mark under third Line or pad), the wiring pattern of the second substrate 301 can be connected to outside by the conducting element.

In some instances, the second substrate 301 is by including that the second connecting portion part 340 of electric connector is connected to intermediary layer 200.Second connecting portion part 340 can be arranged between the second substrate 301 and intermediary layer 200, to be electrically connected 301 He of the second substrate Intermediary layer 200.For example, second connecting portion part 340 can be electrically connected on second conductive pattern 302 under conductive pattern 204 and third.

Second connecting portion part 340 may include at least one material selected from the group being made of following material: tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver-colored (Ag), zinc (Zn) and lead (Pb), but not limited to this.

Second semiconductor chip 320 may be mounted on the second substrate 301.In some instances, the second semiconductor chip 320 be memory chip.

In the example shown, only one semiconductor chip is arranged on the second substrate 301, but present inventive concept is not limited to This.For example, multiple semiconductor chips can be arranged side by side on the second substrate 301, or the second lining can be sequentially stacked on On bottom 301.

In some instances, the second semiconductor chip 320 is mounted on the second substrate 301 by the second bulge-structure 330. Second bulge-structure 330 can be arranged between the second substrate 301 and the second semiconductor chip 320, to be electrically connected the second substrate 301 and second semiconductor chip 320.In some instances, the second bulge-structure 330 includes the second rod structure 332 and the second weldering The bed of material 334.Second bulge-structure 330 can be similar to the first bulge-structure 130.Therefore, for brevity, will to omit second convex Play the detailed description of structure 330.

First molded parts 250 can cover the lower surface and upper surface of intermediary layer 200.For example, the first molded parts 250 It may include the first molding layer 254 between the first packaging part 100 and intermediary layer 200 and intermediary layer 200 and the second packaging part The second molding layer 252 between 300.First molding layer 254 and the second molding layer 252 can have identical area coverage, that is, As observed in the plan view, the first molding layer 254 and the second molding layer 252 can have the outside of identical size and shape Edge.

In some instances, the side (side edge) of the first molded parts 250 exposure intermediary layer 200.For example, the first molding Layer 254 and the second molding layer 252 can be separated from each other by intermediary layer 200.

First molding layer 254 can fill the space between the first packaging part 100 and intermediary layer 200.That is, first Molding layer 254 can extend to the lower surface of intermediary layer 200 from the upper surface of the first substrate 101.Therefore, the first molding layer 254 The first semiconductor chip 120 and first connecting portion part 240 can be covered.

In this case, first connecting portion part 240 penetrates and (extends through) the first molding layer 254, to be electrically connected first Upper conductive pattern 104 and the second lower conductive pattern 202.The circle of first connecting portion part 240 can be completely covered in first molding layer 254 All side surfaces.

In the figure 2 example, the first molding layer 254 is inserted between the first semiconductor chip 120 and intermediary layer 200, but It is that present inventive concept is without being limited thereto.For example, the first semiconductor chip 120 can contact intermediary layer 200, therefore the first molding layer 254 are not partly interposed between the first semiconductor chip 120 and intermediary layer 200.

Second molding layer 252 can cover the upper surface of intermediary layer 200.For example, the second molding layer 252 can be from intermediary layer 200 upper surface upwardly extends.

In some instances, the thickness of the second molding layer 252 is less than the distance between intermediary layer 200 and the second substrate 301. For example, as shown in Fig. 2, the first distance D1 from the upper surface of intermediary layer 200 to the upper surface of the second molding layer 252 is less than therefrom Second distance D2 of the upper surface of interlayer 200 to the lower surface of the second substrate 301.Second molding layer 252 can not contact second Substrate 301.Therefore, clearance G can be formed between the second molding layer 252 and the second substrate 301.

In some instances, clearance G can fill another insulating materials, such as underfill.

Second connecting portion part 340 can penetrate and (extend through) the second molding layer 252, with conductive pattern in electrical connection second 204 and third under conductive pattern 302.In some instances, second connecting portion part 340 is projected into the upper table of the second molding layer 252 On face.For example, the second molding layer 252 can only cover a part of the side surface of the excircle of second connecting portion part 340.

In some instances, 254 to the second molding layer 252 of the first molding layer is thick.For example, from the upper table of the first substrate 101 The third distance D3 of face to the lower surface of intermediary layer 200 is greater than from the upper surface of intermediary layer 200 to the upper table of the second molding layer 252 The distance D1 in face.However, present inventive concept is without being limited thereto.For example, size or the first semiconductor based on first connecting portion part 240 The size of chip 120, third distance D3 can be less than first distance D1.

First molded parts 250 include insulating materials.For example, the first molded parts 250 include insulative polymer material, it is all Such as epoxy molding compounds (EMC).

In some instances, the first molding layer 254 and the second molding layer 252 can be formed simultaneously.That is, can lead to It crosses identical manufacturing process and forms the first molding layer 254 and the second molding layer 252.Therefore, the first molding layer 254 and the second molding Layer 252 can be formed from the same material.For example, the first molding layer 254 and the second molding layer 252 can be by identical EMC It is formed.

Second molded parts 350 can be arranged on the second substrate 301.Second molded parts 350 can cover the second half Conductor chip 320.Second molded parts 350 include insulating materials.For example, the second molded parts 350 include insulating polymer material Material, such as EMC.Second molded parts 350 can have the material essentially identical with the first molded parts 250, but of the invention Conceive without being limited thereto.That is, the second molded parts 350 may include different from the material of the first molded parts 250 is constituted Material.

In the POP type semiconductor package part conceived according to the present invention, the first molded parts 250 be may be used as by One packaging part 100 is joined to the adhesive of intermediary layer 200.Because the first molded parts 250 cover intermediary layer 200 lower surface and Upper surface, it is possible to reduce or prevent the warpage of intermediary layer 200.Moreover, forming the first molding layer 254 and the second mould at the same time Mould layer 252 in the case where, can be effectively held in formed on the lower surface and upper surface of intermediary layer 200 material (for example, EMC flow equilibrium).

In addition, POP type is partly led because the second molding layer 252 is inserted between intermediary layer 200 and the second substrate 301 The thickness of body packaging part may remain in minimum.It is, therefore, possible to provide the POP type semiconductor of miniaturization.

Fig. 3 is another exemplary sectional view of package on package (POP) the type semiconductor package part conceived according to the present invention. For brevity, it will only briefly describe again or no longer description is identical with reference to those of Fig. 1 and Fig. 2 description element at all Element.

With reference to Fig. 3, in the POP type semiconductor package part conceived according to the present invention, the first substrate 101 may include groove T。

Groove T can be formed in the top of the first substrate 101.In some instances, the first semiconductor chip 120 is arranged On the surface of bottom for limiting groove T.For example, the first connection pad 106 can be arranged at the bottom of groove T.In addition, the One bulge-structure 130 can be electrically connected the first connection pad 106 and the first semiconductor chip 120.

Therefore, the distance between the first substrate 101 and intermediary layer 200 can be made to minimize.

In some instances, because the first substrate 101 for being formed with groove T may lack for circuit element 110 must Space is wanted, circuit element 110 is arranged on the lower surface of the first substrate 101.Circuit element 110 can be arranged in the first substrate On the part arranged side by side vertical with groove T of 101 lower surface.In some instances, the circuit on the lower surface of the first substrate 101 Element 110 is passive element, such as capacitor, resistor or inductor.

Fig. 4 is another exemplary sectional view of package on package (POP) the type semiconductor package part conceived according to the present invention. For brevity, it will only briefly describe again or no longer description is identical with those of description element referring to figs. 1 to Fig. 3 at all Element.

With reference to Fig. 4, in the example for the POP type semiconductor package part conceived according to the present invention, the first packaging part 100 packet Include bottom filler 150.

Bottom filler 150 can fill the space between the first substrate 101 and the first semiconductor chip 120.Bottom is filled out Filling object 150 can be fixed on the first semiconductor chip 120 on first substrate 101, to prevent 120 quilt of the first semiconductor chip It destroys.

Bottom filler 150 can cover the first bulge-structure 130.First bulge-structure 130, which can penetrate, (to be extended through Cross) bottom filler 150, with the first connection pad 106 of electrical connection and the first semiconductor chip 120.

Bottom filler 150 includes insulating materials.For example, bottom filler 150 includes insulative polymer material, such as EMC.In some instances, the material of bottom filler 150 is different from the material of the first molding layer 254.For example, bottom filler 150 may include mobility insulating materials more higher than the mobility of the first molding layer 254.Therefore, bottom filler 150 can be with Effectively fill the narrow space between the first substrate 101 and the first semiconductor chip 120.

At least part of bottom filler 150 can fill the groove T of the first substrate 101.However, present inventive concept is not It is limited to this.In some instances, the first substrate 101 does not include groove T.In this case, bottom filler 150 can be formed For a part and the first semiconductor chip 120 of contact of the upper surface of the first substrate 101 of covering.

Fig. 5 is another exemplary section of package on package (POP) the type semiconductor package part conceived according to the present invention Figure.For brevity, will only briefly describe again or at all no longer description with referring to figs. 1 to Fig. 4 describe those of element phase Same element.

With reference to Fig. 5, in the example for the POP type semiconductor package part conceived according to the present invention, intermediary layer 200 includes branch Support member 210.

Supporting element 210 is downwardly projected from the lower surface of intermediary layer 200 with the upper surface towards the first semiconductor chip 120. Supporting element 210 can support intermediary layer 200 on the first semiconductor chip 120.Accordingly it is possible to prevent intermediary layer 200 is bent.

Multiple supporting elements 210 can be formed.Four supporting elements 210 are shown in Fig. 5.However, present inventive concept is not limited to This.That is, five or more supporting elements 210 or three or less supporting element 210 can be formed.

In the example of hgure 5, the upper surface of first semiconductor chip 120 of all contacts of supporting elements 210, but structure of the present invention Think without being limited thereto.According to the size of first connecting portion part 240, some in supporting element 210 can be with the first semiconductor chip 120 Upper surface be spaced apart.

Fig. 6 is another exemplary section of package on package (POP) the type semiconductor package part conceived according to the present invention Figure.For brevity, those of Fig. 1 and Fig. 2 description element phase will be only briefly described or no longer described and refer at all again Same element.

In the example for the POP semiconductor package part conceived according to the present invention, the first semiconductor chip 120 passes through except Any one of various methods except cartridge chip joint method are mounted on the first substrate 101.

For example, the first semiconductor chip 120 can be mounted on the first substrate by the first bonding part 122 with reference to Fig. 6 On 101.The lower surface of first semiconductor chip 120 can adhere to the upper table of the first substrate 101 by the first bonding part 122 Face.First adhesive component 122 may include liquid-state epoxy resin, adhesive tape, conducting medium, or combinations thereof, but not limited to this.

In some instances, the first semiconductor chip 120 can be connected to the first substrate 101 by the first closing line 124. For example, the first chip bonding pad 126 on the upper surface of the first semiconductor chip 120 can be electrically connected to by the first closing line 124 First connection pad 106.However, present inventive concept is without being limited thereto.For example, the first semiconductor chip 120 can be alternatively by Bonding ribbon (bonding tape) is electrically connected to the first connection pad 106.

Second semiconductor chip 320 can be mounted on by various methods on the second substrate 301.

For example, as shown in fig. 6, the second semiconductor chip 320 can be mounted on the second substrate by the second bonding part 322 On 301.The lower surface of second semiconductor chip 320 can adhere to the upper table of the second substrate 301 by the second bonding part 322 Face.Second semiconductor chip 320 can be connected to the second substrate 301 by the second closing line 324.For example, the second closing line 324 It can connect the second chip bonding pad 326 of the second semiconductor chip 320 and the second connection pad 306 of the second substrate 310.

In some instances, multiple semiconductor chips can be stacked on the first substrate 101 or on the second substrate 301.Example Such as, third semiconductor chip 420 can be stacked on the second semiconductor chip 320.

Referring still to Fig. 6, third semiconductor chip 420 can be mounted on the second semiconductor by third bonding part 422 On chip 320.The lower surface of third semiconductor chip 420 can adhere to the second semiconductor core by third bonding part 422 The upper surface of piece 320.Third semiconductor chip 420 can be connected to the second substrate 301 by third closing line 424.For example, the Three closing lines 424 can connect the second connection of the third chip bonding pad 426 and the second substrate 301 of third semiconductor chip 420 Pad 306.

Fig. 7 to Figure 14 is the side for showing manufacture package on package (POP) the type semiconductor package part conceived according to the present invention The diagram in each stage in method.For brevity, it can only briefly describe or no longer description is retouched with reference to Fig. 1 and Fig. 2 at all Those of state the identical element of element.

With reference to Fig. 7, the first substrate 101 can be provided.

First substrate 101 can be package substrate.For example, the first substrate 101 can be printed circuit board (PCB) or ceramics Substrate.

Conductive pattern 104 and the first connection pad 106 can be arranged in the first lining on first lower conductive pattern 102, first On bottom 101.For example, the first lower conductive pattern 102 can be arranged on the lower surface of the first substrate 101.Conductive pattern on first 104 and first connection pad 106 can be arranged on the upper surface of the first substrate 101.

In some instances, circuit element 110 and the first substrate 101 are integrally formed.Circuit element 110 may include active electricity Sub-component (for example, transistor) or passive electric components (for example, capacitor, resistor or inductor).

With reference to Fig. 8, the first semiconductor chip 120 be may be mounted on the first substrate 101.For example, being formed with first thereon First semiconductor chip 120 of bulge-structure 130 may be mounted on the first substrate 101.Therefore, the first substrate 101 and first Semiconductor chip 120 can be electrically connected to each other.Therefore, it can be formed including the first substrate 101 and the first semiconductor chip 120 First packaging part 100.

In some instances, the first bulge-structure 130 may include the first rod structure 132 and the first solder layer 134.

With reference to Fig. 9, intermediary layer 200 be can be set on the first packaging part 100.Here, and in the following description, art Language " setting " can be understood as meaning to assemble or encapsulate etc..

Intermediary layer 200 may include conductive pattern 204 on the second lower conductive pattern 202 and second.For example, the second lower conduction Pattern 202 can be arranged on the lower surface of intermediary layer 200.Conductive pattern 204 can be arranged in the upper of intermediary layer 200 on second On surface.

Intermediary layer 200 can be formed as being connected to the first substrate 101.For example, first connecting portion part 240 can be formed in On one on conductive pattern 104, then intermediary layer 200 can be formed such that the second lower conductive pattern 202 of intermediary layer 200 connects To first connecting portion part 240.Therefore, first connecting portion part 240 can be electrically connected the first substrate 101 and intermediary layer 200.

In some instances, intermediary layer 200 is spaced apart with the first semiconductor chip 120.For example, first connecting portion part 240 Height (for example, third distance D3) can be greater than from the upper surface of the first substrate 101 to the upper table of the first semiconductor chip 120 The distance in face.However, present inventive concept is without being limited thereto.For example, the size based on first connecting portion part 240, intermediary layer 200 can be with Contact the first semiconductor chip 120.

With reference to Figure 10, the first substrate 101 and intermediary layer 200 can be inserted into mold 500.

Mold 500 may include the first mould part (or half) 502 and the second mould part (or half) 504.First mould Having part 502 can contact the lower surface of the first substrate 101.Second mould part 504 can be arranged at interval with intermediary layer 200 In the top of intermediary layer 200.Second mould part 504 can be spaced apart first distance D1 with the upper surface of intermediary layer 200.

Mold 500 can be metal die, but not limited to this.

With reference to Figure 11, mold 500 can be used and form the first molded parts 250.For example, moulding material can be injected Between one mould part 502 and the second mould part 504.Moulding material can be insulative polymer material, for example, EMC.

Therefore, the first molding layer 254 can be formed as filling the space between the first packaging part 100 and intermediary layer 200.Separately Outside, the second molding layer 252 can be formed as filling the space between intermediary layer 200 and the second mould part 504.In other words, First molded parts 250 can be formed as covering the lower surface and upper surface of intermediary layer 200.Because the second molding layer 252 is formed To fill the space between intermediary layer 200 and the second mould part 504, therefore the thickness of the second molding layer 252 can be with first Distance D1 is essentially identical.

With reference to Figure 12, the first substrate 101 and intermediary layer 200 can be cut into unit packaging part.

For example, the first substrate 101 and intermediary layer can be cut along the boundary in the region comprising the first semiconductor chip 120 200.Therefore, the side of intermediary layer 200 can be exposed and unit packaging part is consequently formed.

Before the first substrate 101 and intermediary layer 200 are cut into unit packaging part, mold 500 can be removed.

First substrate 101 etc. can be cut into unit packaging part after forming the first molded parts 250, but originally Inventive concept is without being limited thereto.First substrate 101 etc. can be cut into unit packaging part in each operation stage.For example, can be with After forming the second packaging part 300, first substrate 101 etc. is cut into unit packaging part.

With reference to Figure 13, hole H can be formed to expose the upper surface of intermediary layer 200.

For example, hole H can be formed with the upper surface of conductive pattern 204 in exposure second.According to the technique for being used to form hole H Characteristic, hole H can have conical by its shape.

Hole H can be formed by laser drilling process.For example, conductive pattern 204 on laser reirradiation second can be used On the second molding layer 252, with formed exposure second on conductive pattern 204 upper surface hole H.

With reference to Figure 14, second connecting portion part 340 can be formed to fill hole H.

Second connecting portion part 340 can be formed as the top for being projected into the second molding layer 252.Second molding layer 252 can be with Cover a part of the external peripheral surface of second connecting portion part 340.

Referring again to FIGS. 2, the second packaging part 300 and the second molded parts can be formed then in the second molding layer 252 350。

Second packaging part 300 may be coupled to second connecting portion part 340.For example, conductive under the third of the second packaging part 300 Pattern 302 may be coupled to second connecting portion part 340.Therefore, second connecting portion part 340 can be electrically connected intermediary layer 200 and Two substrates 301.

Second molded parts 350 can be formed on the second substrate 301.In addition, the second molded parts 350 can cover Two semiconductor chips 320.Second molded parts 350 are formed by insulating materials.For example, the second molded parts 350 are polymerize by insulation Object material is formed, such as EMC.

Figure 15 to Figure 17 is the side for showing manufacture package on package (POP) the type semiconductor package part conceived according to the present invention The diagram in each stage in another example of method.For brevity, it can only briefly describe again or not describe and join Examine those of Fig. 1 to Figure 14 description element and stage identical element and the stage.

With reference to Figure 15, the first substrate 101 including groove T can be provided.

For example, groove T can be formed in the top of the first substrate 101.In some instances, the first connection pad 106 It can be arranged on the surface of the bottom of the restriction groove T of the first substrate 101.

In some instances, circuit element 110 can be arranged on the lower surface of the first substrate 101.For example, circuit element 110 can be arranged on the part arranged side by side vertical with groove T of the lower surface of the first substrate 101.In some instances, circuit elements Part 110 is passive electric components, such as capacitor, resistor or inductor.

With reference to Figure 16, the first semiconductor chip 120 can be installed to the first substrate 101 in the bottom of groove T.

For example, the first bulge-structure 130 has can be set in the first semiconductor chip 120.Next, the first bulge-structure 130 may be coupled to the first connection pad 106.Therefore, the first semiconductor chip 120 may be mounted in groove T.

With reference to Figure 17, bottom filler 150 can be formed as filling the first substrate 101 and the first semiconductor chip 120 it Between space.

For example, bottom filler 150 can be formed as filling groove T.Bottom filler 150 can cover the first protrusion knot Structure 130.

In some instances, the first substrate 101 does not have groove T.In this case, bottom filler 150 can be with shape A part and the first semiconductor chip 120 of contact of upper surface as the first substrate 101 of covering.

Bottom filler 150 can be insulative polymer material, such as EMC.In some instances, bottom filler 150 It is the insulating materials with high fluidity.In some instances, bottom filler 150 is omitted.

Referring again to FIGS. 4, then, it can be by intermediary layer 200, the first molded parts 250, the second packaging part 300 and second Molded parts 350 are sequentially positioned on the first packaging part 100.

Intermediary layer 200, the first molded parts 250, the second packaging part 300 and the second molded parts 350 can with reference The similar mode of those of Fig. 2 and Fig. 9 to Figure 14 description mode is arranged.Therefore, these of manufacturing method will not be described in detail further Stage.

Figure 18 be show manufacture package on package (POP) the type semiconductor package part conceived according to the present invention method it is another The diagram in the stage in one example.For brevity, can only briefly describe again or do not describe with referring to figs. 1 to figure Those of 14 descriptions element and stage identical element and the stage.Figure 18 shows the processing after processing stage shown in Fig. 8 Stage.

With reference to Figure 18, the intermediary layer 200 including supporting element 210 be can be set on the first packaging part 100.

Including can be set from the intermediary layer 200 of the lower surface of intermediary layer 200 supporting element 210 outstanding in the first packaging part On 100.The supporting element 210 of intermediary layer 200 can be towards the upper surface of the first semiconductor chip 120.For example, intermediary layer 200 can To be formed so that its supporting element 210 contacts the upper surface of the first semiconductor chip 120.

Next, the first molded parts 250, the second packaging part 300 and the second molded parts 350 can sequentially be arranged.

First molded parts 250, the second packaging part 300 and the second molded parts 350 can with reference Fig. 2 and Figure 10 extremely Those of Figure 14 description similar mode of mode is arranged.Therefore, these stages of manufacturing method will not be described in detail further.

Although specifically illustrating and describing present inventive concept, ordinary skill people by reference to its various example Member will be understood that, in the case where not departing from the range of spirit and the present inventive concept being determined by the claims that follow of the invention, These examples can be carried out various changes of form and details.