阅读说明：本技术 小功率片内整流桥电路 (Small-power on-chip rectifier bridge circuit ) 是由 赵寿全 刘桂芝 于 2019-10-17 设计创作，主要内容包括：本发明涉及整流电路领域,公开了小功率片内整流桥电路,包括第一NMOS管、第二NMOS管、第一PMOS管、第二PMOS管、第一驱动控制电路和第二驱动控制电路,第一PMOS管的栅极和源极短接,第二PMOS管的栅极和源极短接,第一PMOS管的源极电连接第二PMOS管的源极,第一PMOS管的漏极电连接第一NMOS管的漏极,第二PMOS管的漏极电连接第二NMOS管的漏极,第一NMOS管的源极与第二NMOS管的源极均接地,第一驱动控制电路控制第一NMOS管的通断,第二驱动控制电路控制第二NMOS管的通断,第一NMOS管的漏极电连接第一交流输入端,第二NMOS管的漏极电连接第二交流输入端。本发明中交流电分别经第一PMOS管或者第二PMOS管输出直流信号,从而降低压降,提高整流效率。(The invention relates to the field of rectifier circuits, and discloses a small-power on-chip rectifier bridge circuit which comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first drive control circuit and a second drive control circuit, wherein the grid electrode and the source electrode of the first PMOS tube are in short circuit, the grid electrode and the source electrode of the second PMOS tube are in short circuit, the source electrode of the first PMOS tube is electrically connected with the source electrode of the second PMOS tube, the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are both grounded, the first drive control circuit controls the on-off of the first NMOS tube, the second drive control circuit controls the on-off of the second NMOS tube, the drain electrode of the. According to the invention, alternating current outputs direct current signals through the first PMOS tube or the second PMOS tube respectively, so that the voltage drop is reduced, and the rectification efficiency is improved.)

1. The on-chip rectifier bridge circuit of miniwatt is characterized in that: the power supply circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first drive control circuit and a second drive control circuit;

The grid electrode and the source electrode of the first PMOS tube are in short circuit, the grid electrode and the source electrode of the second PMOS tube are in short circuit, the source electrode of the first PMOS tube is electrically connected with the source electrode of the second PMOS tube, the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are all grounded, the first drive control circuit controls the on-off state of the first NMOS tube, the second drive control circuit controls the on-off state of the second NMOS tube, the drain electrode of the first NMOS tube is electrically connected with a first alternating current input end, and the drain electrode of the second NMOS tube is electrically connected with a second alternating current input end.

2. The on-die rectifier bridge circuit of claim 1, wherein: the first drive control circuit comprises a resistor R1, a third NMOS tube and a first voltage stabilizing unit, the source electrode and the drain electrode of the third NMOS tube are connected with the resistor R1 in parallel, the drain electrode of the third NMOS tube is electrically connected with the second alternating current input end, the source electrode of the third NMOS tube is electrically connected with the grid electrode and the first voltage stabilizing unit of the first NMOS tube respectively, and the grid electrode and the source electrode of the third NMOS tube are in short circuit.

3. the on-die rectifier bridge circuit of claim 2, wherein: the first voltage regulation unit is a voltage regulation diode D1, and the source of the third NMOS transistor is grounded through a voltage regulation diode D1.

4. The on-die rectifier bridge circuit of claim 2, wherein: the third NMOS tube can be replaced by a third PMOS tube, and the grid electrode and the source electrode of the third PMOS tube are in short circuit.

5. The on-die rectifier bridge circuit of claim 1, wherein: the second drive control circuit comprises a resistor R2, a fourth NMOS tube and a second voltage stabilizing unit, wherein the source electrode and the drain electrode of the fourth NMOS tube are connected with the resistor R2 in parallel, the drain electrode of the fourth NMOS tube is electrically connected with the first alternating current input end, the source electrode of the fourth NMOS tube is electrically connected with the grid electrode and the second voltage stabilizing unit of the second NMOS tube respectively, and the grid electrode and the source electrode of the fourth NMOS tube are in short circuit.

6. The on-die rectifier bridge circuit of claim 5, wherein: the second voltage regulation unit is a voltage regulation diode D2, and the source of the fourth NMOS transistor is grounded through a voltage regulation diode D2.

7. The on-die rectifier bridge circuit of claim 5, wherein: the fourth NMOS tube can be replaced by a fourth PMOS tube, and the grid electrode and the source electrode of the fourth PMOS tube are in short circuit.

8. The on-die rectifier bridge circuit of claim 1, wherein: the small-power on-chip rectifier bridge circuit and the main chip circuit can be integrally installed on the same wafer substrate, and the small-power on-chip rectifier bridge circuit provides working voltage for the main chip circuit.

Technical Field

the invention relates to the field of rectification circuits, in particular to a small-power on-chip rectifier bridge circuit.

Background

The traditional rectifier bridge circuit mainly comprises four diodes, alternating current is rectified into direct current output by utilizing the one-way conduction characteristic of the diodes, but the diodes have conduction voltage drop when being conducted, the conduction voltage drop is about 0.6V, and a rectifier circuit formed by a plurality of diodes has great power loss and can also increase the operating temperature.

The rectification circuit combined by the switch MOSFET and the active rectifier bridge control chip improves the problem of power loss caused by inherent voltage drop of the diode by utilizing lower conduction voltage drop of the switch MOSFET. However, the structure has the defects of more used separation devices and complex PCB layout, and meanwhile, the high complexity of the control chip of the active rectifier bridge brings higher cost pressure.

Disclosure of Invention

In view of the defects of the background art, the invention provides a small-power on-chip rectifier bridge circuit, and the technical problem to be solved is that the existing diode rectifier bridge circuit has great power loss in operation due to the conduction voltage drop of a diode; the rectifier circuit of the combination of the switching MOSFET and the active rectifier bridge control chip is costly.

In order to solve the technical problems, the invention provides the following technical scheme: the small-power on-chip rectifier bridge circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first drive control circuit and a second drive control circuit.

The grid electrode and the source electrode of the first PMOS tube are in short circuit, the grid electrode and the source electrode of the second PMOS tube are in short circuit, the source electrode of the first PMOS tube is electrically connected with the source electrode of the second PMOS tube, the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are both grounded, the first drive control circuit controls the on-off of the first NMOS tube, the second drive control circuit controls the on-off of the second NMOS tube, the drain electrode of the first NMOS tube is electrically connected with the first alternating current input end, and the drain electrode of the second NMOS tube is.

Further, the first drive control circuit comprises a resistor R1, a third NMOS tube and a first voltage stabilizing unit, wherein a source electrode and a drain electrode of the third NMOS tube are connected with the resistor R1 in parallel, the drain electrode of the third NMOS tube is electrically connected with the second alternating current input end, the source electrode of the third NMOS tube is electrically connected with a grid electrode of the first NMOS tube and the first voltage stabilizing unit respectively, and the grid electrode of the third NMOS tube is in short circuit with the source electrode.

Preferably, the first voltage regulation unit is a voltage regulation diode D1, and the source of the third NMOS transistor is grounded through a voltage regulation diode D1. And realizing that the grid-source voltage of the first NMOS tube is within the voltage-resistant controllable range of the device.

And the third NMOS transistor can be replaced by a third PMOS transistor, and the grid electrode and the source electrode of the third PMOS transistor are in short circuit.

Further, the second drive control circuit comprises a resistor R2, a fourth NMOS tube and a second voltage stabilizing unit, wherein a source electrode and a drain electrode of the fourth NMOS tube are connected with the resistor R2 in parallel, the drain electrode of the fourth NMOS tube is electrically connected with the first alternating current input end, the source electrode of the fourth NMOS tube is electrically connected with a grid electrode of the second NMOS tube and the second voltage stabilizing unit respectively, and the grid electrode and the source electrode of the fourth NMOS tube are in short circuit.

Preferably, the second voltage regulation unit is a voltage regulation diode D2, and the source of the fourth NMOS transistor is grounded through a voltage regulation diode D2. And the grid-source voltage of the second NMOS tube is within the voltage-resistant controllable range of the device.

The fourth NMOS transistor can be replaced by a fourth PMOS transistor, and the grid electrode and the source electrode of the fourth PMOS transistor are in short circuit.

Furthermore, a small-power on-chip rectifier bridge circuit and a main chip circuit can be integrally mounted on the same wafer substrate, and the small-power on-chip rectifier bridge circuit provides working voltage for the main chip circuit, so that integrated and miniaturized production is realized.

In first drive circuit and second drive circuit, the grid and the source electrode short circuit of NMOS pipe, the NMOS pipe through two drive circuit can realize switching on fast and closing of first NMOS pipe and second NMOS pipe, and then effectively restraines the appearance of ringing phenomenon, realizes the promotion of rectification efficiency.

After the grid electrodes and the source electrodes of the first PMOS tube and the second PMOS tube are in short circuit, when the drain electrode has forward voltage input, the first PMOS tube and the second PMOS tube are conducted, at the moment, the forward voltage outputs voltage through a parasitic diode of the PMOS tube, and the voltage drop of the parasitic diode is smaller than the conduction voltage drop of the diode.

Compared with the prior art, the invention has the beneficial effects that: output voltage drop during rectification can be effectively reduced through the first PMOS pipe and the second PMOS pipe, conduction loss is reduced, and rectification efficiency is improved. Secondly, the first NMOS tube and the second NMOS tube are used, so that the potential leakage problem between components can be eliminated. Finally, the first NMOS tube and the second NOMS tube can be quickly opened and closed through the third NMOS tube and the fourth NMOS tube, the ringing phenomenon is restrained, and the rectification efficiency is further improved.

Drawings

The invention has the following drawings:

FIG. 1 is a schematic structural view of the present invention;

FIG. 2 is a schematic diagram of a first driving circuit according to the present invention;

FIG. 3 is a diagram of a second driving circuit according to the present invention;

FIG. 4 is a circuit diagram of the present invention.

Detailed Description

the present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.

As shown in fig. 1 to 4, the on-chip rectifier bridge circuit of small power includes a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, a first driving control circuit 100, and a second driving control circuit 102.

The grid electrode and the source electrode of the first PMOS tube M3 are in short circuit, the grid electrode and the source electrode of the second PMOS tube M4 are in short circuit, the source electrode of the first PMOS tube M3 is electrically connected with the source electrode of the second PMOS tube M4, the drain electrode of the first PMOS tube M3 is electrically connected with the drain electrode of the first NMOS tube M1, the drain electrode of the second PMOS tube M4 is electrically connected with the drain electrode of the second NMOS tube M2, the source electrode of the first NMOS tube M1 and the source electrode of the second NMOS tube M2 are both grounded, the first drive control circuit 100 controls the on-off of the first NMOS tube M1, the second drive control circuit 102 controls the on-off of the second NMOS tube M2, the drain electrode of the first NMOS tube M1 is electrically connected with the first alternating current input end AC 45, and the drain electrode of the second NMOS tube M2 is electrically connected with the.

Further, the first driving control circuit 100 includes a resistor R1, a third NMOS transistor M5 and a first voltage stabilizing unit 104, a source and a drain of the third NMOS transistor M5 are connected in parallel with the resistor R1, a drain of the third NMOS transistor M5 is electrically connected to the second AC input terminal AC2, a source of the third NMOS transistor M5 is electrically connected to a gate of the first NMOS transistor M1 and the first voltage stabilizing unit 104, respectively, and a gate and a source of the third NMOS transistor M5 are shorted.

Preferably, the first voltage regulation unit 104 is a zener diode D1, and the source of the third NMOS transistor M5 is grounded through a zener diode D1. The grid-source voltage of the first NMOS transistor M1 is realized within the controllable range of the withstand voltage of the device.

The third NMOS transistor M5 can be replaced by a third PMOS transistor, the grid electrode and the source electrode of the third PMOS transistor are in short circuit, after replacement, the source electrode of the third PMOS transistor is electrically connected with the second alternating current input end AC2, and the drain electrode of the third PMOS transistor is electrically connected with the grid electrode of the first NMOS transistor M1 and the voltage stabilizing diode D1 respectively.

Further, the second driving control circuit 102 includes a resistor R2, a fourth NMOS transistor M6 and a second voltage stabilizing unit 105, a source and a drain of the fourth NMOS transistor M6 are connected in parallel with the resistor R2, a drain of the fourth NMOS transistor M6 is electrically connected to the first AC input terminal AC1, a source of the fourth NMOS transistor M6 is electrically connected to the gate of the second NMOS transistor M2 and the second voltage stabilizing unit 105, and a gate and a source of the fourth NMOS transistor M6 are shorted.

Preferably, the second voltage regulation unit 105 is a voltage regulation diode D2, and the source of the fourth NMOS transistor M6 is grounded through the voltage regulation diode D2. The grid-source voltage of the second NMOS transistor M2 is realized within the controllable range of the withstand voltage of the device.

the fourth NMOS transistor M6 can be replaced by a fourth PMOS transistor, the grid electrode and the source electrode of the fourth PMOS transistor are in short circuit, after replacement, the source electrode of the fourth PMOS transistor is electrically connected with the first alternating current input end AC1, and the drain electrode of the fourth PMOS transistor is electrically connected with the grid electrode of the second NMOS transistor M2 and the voltage stabilizing diode D2 respectively.

Further, a small-power on-chip rectifier bridge circuit and the main chip circuit 101 can be integrally mounted on the same wafer substrate, and the small-power on-chip rectifier bridge circuit provides working voltage for the main chip circuit 101, so that integrated and miniaturized production is realized.

In the first driving circuit 100 and the second driving circuit 102, the gate and the source of the NMOS transistor are short-circuited, and the NMOS transistors of the two driving circuits can realize the fast turn-on and turn-off of the first NMOS transistor M1 and the second NMOS transistor M2, thereby effectively suppressing the occurrence of ringing and realizing the improvement of rectification efficiency.

After the gates and the sources of the first PMOS transistor M3 and the second PMOS transistor M4 are shorted, when a forward voltage is input to the drain, the first PMOS transistor M3 and the second PMOS transistor M4 are turned on, and at this time, the forward voltage outputs a voltage through a parasitic diode of the PMOS transistor itself, and the voltage drop of the parasitic diode is smaller than the conduction voltage drop of the diode.

The working principle of the invention is as follows: when the first alternating current input end AC1 inputs a high level and the second alternating current input end AC2 inputs a low level, the first alternating current input end AC1 raises the grid potential of the second NMOS transistor M2 through the resistor R2, and the second NMOS transistor M2 is turned on; the second alternating current input end AC2 pulls down the grid potential of the first NMOS transistor M1 through the resistor R1, and the first NMOS transistor M1 is closed; at this time, the first AC input terminal AC1 transfers energy to VDC through the parasitic diode of the first PMOS transistor M3.

When the second alternating current input end AC2 inputs a high level and the first alternating current input end AC1 inputs a low level, the second alternating current input end AC2 raises the grid potential of the first NMOS transistor M1 through the resistor R1, and the first NMOS transistor M1 is turned on; the first alternating current input end AC1 pulls down the grid potential of the second NMOS transistor M2 through the resistor R2, and the second NMOS transistor M2 is closed; at this time, the second AC input terminal AC2 transfers energy to VDC through the parasitic diode of the second PMOS transistor M4.

The first PMOS tube M3 and the second PMOS tube M4 realize lower source-drain voltage which is far lower than the inherent voltage drop of the diode (about 0.6V), thereby realizing smaller power loss and improving the output efficiency of the system. The first NMOS transistor M1 and the second NMOS transistor M2 are used, and the potential problem of leakage among the isolation of the components is eliminated.

And a third NMOS transistor M5 connected with R1 in parallel and a fourth NMOS transistor M6 connected with R2 in parallel are in short connection with a grid electrode and a source electrode. The third NMOS transistor M5 and the fourth NMOS transistor M6 have two functions: firstly, when the first NMOS transistor M1 or the second NMOS transistor M2 is turned on, the gate of the first NMOS transistor M1 or the second NMOS transistor M2 is quickly lifted by using the parasitic capacitance between the gate and the drain of the third NMOS transistor M5 and the fourth NMOS transistor M6 and the parasitic capacitance between the source and the drain, so that quick conduction is realized; secondly, when the first NMOS transistor M1 or the second NMOS transistor M2 is turned off, the parasitic diodes of the third NMOS transistor M5 and the fourth NMOS transistor M6 are used to rapidly discharge the gate of the first NMOS transistor M1 or the second NMOS transistor M2, so as to achieve rapid turn-off. The third NMOS transistor M5 and the fourth NMOS transistor M6 achieve fast turn-on and turn-off of the first NMOS transistor M1 or the second NMOS transistor M2, so that occurrence of ringing is suppressed, and rectification efficiency is further improved.

In light of the foregoing, it is to be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.