阅读说明：本技术 化合物半导体晶体管与高密度电容器的集成 (Integration of compound semiconductor transistor and high density capacitor ) 是由 杨斌 李夏 陶耿名 于 2018-02-20 设计创作，主要内容包括：金属-绝缘体-金属(MIM)电容器包括化合物半导体衬底。MIM电容器包括化合物半导体衬底上的集电极接触层、集电极接触层上的第一电介质层、第一电介质层上的导电电极层以及导电电极层上的第二电介质层。MIM电容器包括第二电介质层上的第一导电互连、第一导电互连上的第三电介质层以及第三电介质层上的第二导电互连。第一电容组件包括集电极接触层、导电电极层和第一电介质层。第二电容组件包括第一导电互连、导电电极层和第二电介质层。第三电容组件包括第二导电互连、第一导电互连和第三电介质层。第一电容组件、第二电容组件和第三电容组件彼此并联布置。(A metal-insulator-metal (MIM) capacitor includes a compound semiconductor substrate. The MIM capacitor includes a collector contact layer on a compound semiconductor substrate, a first dielectric layer on the collector contact layer, a conductive electrode layer on the first dielectric layer, and a second dielectric layer on the conductive electrode layer. The MIM capacitor includes a first conductive interconnect on the second dielectric layer, a third dielectric layer on the first conductive interconnect, and a second conductive interconnect on the third dielectric layer. The first capacitive component includes a collector contact layer, a conductive electrode layer, and a first dielectric layer. The second capacitive component includes a first conductive interconnect, a conductive electrode layer, and a second dielectric layer. The third capacitive component includes a second conductive interconnect, a first conductive interconnect, and a third dielectric layer. The first, second and third capacitive components are arranged in parallel with each other.)

1. A metal-insulator-metal (MIM) capacitor, comprising:

A compound semiconductor substrate;

A collector contact layer on the compound semiconductor substrate;

A first dielectric layer on the collector contact layer;

A conductive electrode layer on the first dielectric layer, a first capacitive component comprising the collector contact layer, the conductive electrode layer, and the first dielectric layer;

A second dielectric layer on the conductive electrode layer;

A first conductive interconnect on the second dielectric layer, a second capacitive component comprising the first conductive interconnect, the conductive electrode layer, and the second dielectric layer;

A third dielectric layer on the first conductive interconnect; and

a second conductive interconnect on the third dielectric layer, a third capacitive component comprising the second conductive interconnect, the first conductive interconnect, and the third dielectric layer, and arranged in parallel with the second capacitive component and the first capacitive component.

2. The MIM capacitor of claim 1, wherein the first, second, and/or third dielectric layers comprise a high-K dielectric layer.

3. the MIM capacitor according to claim 1, further comprising:

A fourth dielectric layer; and

A third conductive interconnect, a fourth capacitive component comprising one of the first conductive interconnect and the second conductive interconnect, the fourth dielectric layer, and the third conductive interconnect.

4. The MIM capacitor according to claim 1, wherein the conductive electrode layer comprises tantalum nitride (TaN) or nickel chromium (NiCr).

5. The MIM capacitor according to claim 1 integrated with a resistor fabricated from the material of the conductive electrode layer.

6. The MIM capacitor according to claim 1, wherein the compound semiconductor substrate comprises indium phosphide (InP), gallium nitride (GaN), gallium antimony (GaSb), gallium phosphide (GaP), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), aluminum gallium antimony (algassb), indium gallium antimony (InGaSb), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), indium gallium arsenide phosphide (InGaAsP), indium gallium arsenide antimonide (InGaAsSb), or indium gallium arsenide nitride (InGaAs: N).

7. The MIM capacitor according to claim 1 integrated with a Heterojunction Bipolar Transistor (HBT) on an HBT chip.

8. The MIM capacitor of claim 7, wherein the HBT chip is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a Personal Digital Assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

9. a method of fabricating a high density metal-insulator-metal (MIM) capacitor, comprising:

depositing a first dielectric layer on a collector contact layer on a compound semiconductor substrate;

Depositing a conductive electrode layer on the first dielectric layer to form a first capacitive component;

Depositing a second dielectric layer on the conductive electrode layer;

Forming a first conductive interconnect on the second dielectric layer to form a second capacitive component;

Depositing a third dielectric layer on the first conductive interconnect; and

forming a second conductive interconnect on the third dielectric layer to form a third capacitive component arranged in parallel with the second capacitive component and the first capacitive component.

10. The method of claim 9, wherein depositing the second dielectric layer comprises: a high-K dielectric layer is deposited on the conductive electrode layer.

11. The method of claim 9, further comprising:

Depositing a fourth dielectric layer on the second conductive interconnect; and

Depositing a third conductive interconnect on the fourth dielectric layer to form a fourth capacitive component.

12. The method of claim 9, wherein depositing the conductive electrode layer comprises: tantalum nitride (TaN) or nickel chromium (NiCr) is deposited on the first dielectric layer.

13. The method of claim 9, further comprising: a resistor on the compound semiconductor substrate is fabricated from the material of the conductive electrode layer.

14. The method of claim 9, further comprising:

integrating the MIM capacitor with a Heterojunction Bipolar Transistor (HBT) on an HBT chip; and

The HBT chip is integrated into a wireless transceiver that is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a Personal Digital Assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

15. A metal-insulator-metal (MIM) capacitor, comprising:

Means for supporting a MIM capacitor;

a collector contact layer on the means for supporting;

A first dielectric layer on the collector contact layer;

A conductive electrode layer on the first dielectric layer, a first capacitive component comprising the collector contact layer, the conductive electrode layer, and the first dielectric layer;

A second dielectric layer on the conductive electrode layer;

a first conductive interconnect on the second dielectric layer, a second capacitive component comprising the first conductive interconnect, the conductive electrode layer, and the second dielectric layer;

A third dielectric layer on the first conductive interconnect; and

A second conductive interconnect on the third dielectric layer, a third capacitive component comprising the second conductive interconnect, the first conductive interconnect, and the third dielectric layer, and arranged in parallel with the second capacitive component and the first capacitive component.

16. The MIM capacitor according to claim 15, wherein the first, second, and/or third dielectric layers comprise a high-K dielectric layer.

17. The MIM capacitor according to claim 15, further comprising:

A fourth dielectric layer; and

A third conductive interconnect, a fourth capacitive component comprising one of the first conductive interconnect and the second conductive interconnect, the fourth dielectric layer, and the third conductive interconnect.

18. The MIM capacitor according to claim 15, wherein the conductive electrode layer comprises tantalum nitride (TaN) or nickel chromium (NiCr).

19. The MIM capacitor according to claim 15 integrated with a resistor fabricated from the material of the conductive electrode layer.

20. The MIM capacitor according to claim 15, wherein the means for supporting comprises indium phosphide (InP), gallium nitride (GaN), gallium antimony (GaSb), gallium phosphide (GaP), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), aluminum gallium antimony (algassb), indium gallium antimony (InGaSb), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), indium gallium arsenide phosphide (InGaAsP), indium gallium arsenide antimonide (InGaAsSb), or indium gallium arsenide nitride (InGaAs: N).

21. The MIM capacitor according to claim 15 integrated with a Heterojunction Bipolar Transistor (HBT) on an HBT chip.

22. The MIM capacitor according to claim 21, wherein the HBT chip is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a Personal Digital Assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

Technical Field

The present disclosure relates generally to wireless communication systems and more particularly to compound semiconductor transistors integrated with high density capacitors.

Background

A wireless device (e.g., a cellular telephone or smartphone) in a wireless communication system may include a Radio Frequency (RF) transceiver to transmit and receive data for two-way communication. The mobile RF transceiver may include a transmit section for data transmission and a receive section for data reception. For data transmission, the transmit section may modulate an RF carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal to obtain an amplified RF signal having an appropriate output power level, and transmit the amplified RF signal to a base station via an antenna. For data reception, the receive section may obtain a received RF signal via an antenna, and may amplify and process the received RF signal to recover data transmitted by the base station.

The transmit section of the mobile RF transceiver may amplify and transmit communication signals. The transmit section may include one or more circuits for amplifying and transmitting communication signals. The amplifier circuit may include one or more amplifier stages, which may have one or more driver stages and one or more power amplifier stages. Each amplifier stage includes one or more transistors configured in various ways for amplifying the communication signal. Transistors configured to amplify communication signals are typically selected to operate at substantially higher frequencies for supporting communication enhancements, such as carrier aggregation. These transistors are typically implemented using compound semiconductor transistors, such as Bipolar Junction Transistors (BJTs), Heterojunction Bipolar Transistors (HBTs), and the like.

further design challenges for mobile RF transceivers include analog/RF performance considerations, including mismatch, noise, and other performance considerations. The design of these mobile RF transceivers includes the use of additional passive devices, for example, to suppress resonance and/or perform filtering, bypassing and coupling. Unfortunately, the integration of passive devices and compound semiconductor transistors is problematic.

Disclosure of Invention

A metal-insulator-metal (MIM) capacitor includes a compound semiconductor substrate. The MIM capacitor includes a collector contact layer on a compound semiconductor substrate, a first dielectric layer on the collector contact layer, a conductive electrode layer on the first dielectric layer, and a second dielectric layer on the conductive electrode layer. The MIM capacitor includes a first conductive interconnect on the second dielectric layer, a third dielectric layer on the first conductive interconnect, and a second conductive interconnect on the third dielectric layer. The first capacitive component includes a collector contact layer, a conductive electrode layer, and a first dielectric layer. The second capacitive component includes a first conductive interconnect, a conductive electrode layer, and a second dielectric layer. The third capacitive component includes a second conductive interconnect, a first conductive interconnect, and a third dielectric layer. The first, second and third capacitive components are arranged in parallel with each other.

a method of fabricating a high density metal-insulator-metal (MIM) capacitor may include depositing a first dielectric layer on a collector contact layer on a compound semiconductor substrate and depositing a conductive electrode layer on the first dielectric layer to form a first capacitive component. The method may further include depositing a second dielectric layer on the conductive electrode layer and forming a first conductive interconnect on the second dielectric layer, forming a second capacitive component. The method may also include depositing a third dielectric layer on the first conductive interconnect and forming a second conductive interconnect on the third dielectric layer, forming a third capacitive component. The third capacitive assembly may be arranged in parallel with the second capacitive assembly and the first capacitive assembly.

The MIM capacitor may include a means for supporting the MIM capacitor. The MIM capacitor may further comprise a collector contact layer on the means for supporting, a first dielectric layer on the collector contact layer, a conductive electrode layer on the first dielectric layer. The MIM capacitor may also include a second dielectric layer on the conductive electrode layer, a first conductive interconnect on the second dielectric layer, a third dielectric layer on the first conductive interconnect, and a second conductive interconnect on the third dielectric layer. The first capacitive component may include a collector contact layer, a conductive electrode layer, and a first dielectric layer. The second capacitive component may include a first conductive interconnect, a conductive electrode layer, and a second dielectric layer. The third capacitive component may include a second conductive interconnect, a first conductive interconnect, and a third dielectric layer. The first, second and third capacitive components may be arranged in parallel with each other.

This has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

drawings

Fig. 1 shows a perspective view of a semiconductor wafer.

Fig. 2 shows a cross-sectional view of a die.

Fig. 3 shows a block diagram of an exemplary wireless device.

Fig. 4 shows a Heterojunction Bipolar Transistor (HBT) chip integrating a compound semiconductor transistor, a resistor, and a compound semiconductor capacitor.

Fig. 5A-5C illustrate high density compound semiconductor MIM capacitors in parallel capacitor configurations according to aspects of the present disclosure.

Fig. 6A-6C illustrate high density compound semiconductor MIM capacitors in alternative parallel capacitor configurations according to aspects of the present disclosure.

Fig. 7A-7C illustrate a high density compound semiconductor MIM capacitor in another alternative parallel capacitor configuration according to aspects of the present disclosure.

Fig. 8A-8C illustrate a high density compound semiconductor MIM capacitor in another alternative parallel capacitor configuration according to aspects of the present disclosure.

Fig. 9 is a flow chart illustrating a method of fabricating a high density metal-insulator-metal (MIM) capacitor according to aspects of the present disclosure.

fig. 10 is a block diagram illustrating an example wireless communication system in which aspects of the present disclosure may be advantageously employed.

Detailed Description

the detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details in order to provide a thorough understanding of the various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

As described herein, use of the term "and/or" is intended to mean "inclusive or" and use of the term "or" is intended to mean "exclusive or". As described herein, the term "exemplary" used throughout this specification means "serving as an example, instance, or illustration," and should not be construed as preferred or advantageous over other exemplary configurations. The term "coupled" as used throughout this specification means "connected, directly or indirectly, electrically, mechanically or otherwise through an intermediate connection (e.g., a switch), and is not necessarily limited to physical connections. Additionally, the connection may be such that the object is permanently connected or releasably connected. The connection may be through a switch.

The fabrication of mobile Radio Frequency (RF) chip designs (e.g., mobile RF transceivers) becomes complex at deep sub-micron process nodes due to cost and power consumption considerations. The mobile RF transceiver may include a transmit section for data transmission and a receive section for data reception. For data transmission, the transmit section may modulate an RF carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal to obtain an amplified RF signal having an appropriate output power level, and transmit the amplified RF signal to a base station via an antenna. For data reception, the receive section may obtain a received RF signal via an antenna, and may amplify and process the received RF signal to recover data transmitted by the base station.

The transmit section of the mobile RF transceiver may amplify and transmit communication signals. The transmit section may include one or more circuits for amplifying and transmitting communication signals. The amplifier circuit may include one or more amplifier stages, which may have one or more driver stages and one or more power amplifier stages. Each amplifier stage includes one or more transistors configured in various ways for amplifying the communication signal. Transistors configured to amplify communication signals are typically selected to operate at substantially higher frequencies for supporting communication enhancements, such as carrier aggregation. These transistors are typically implemented using compound semiconductor transistors, such as Bipolar Junction Transistors (BJTs), Heterojunction Bipolar Transistors (HBTs), High Electron Mobility Transistors (HEMTs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), and the like.

Further design challenges for mobile RF transceivers include analog/RF performance considerations such as mismatch, noise, and other performance considerations. The design of these mobile RF transceivers includes the use of additional passive devices, for example, to suppress resonance and/or perform filtering, bypassing and coupling. Unfortunately, the integration of passive devices and compound semiconductor transistors (e.g., bipolar transistors) is problematic.

A bipolar transistor, also known as a Bipolar Junction Transistor (BJT), is a transistor that uses hole charges and electron carriers. Bipolar transistors are fabricated in integrated circuits and are also used as individual components. Bipolar transistors are designed to amplify current. This basic function of the bipolar transistor makes it a reasonable choice for implementing the amplifier and the switch. As a result, bipolar transistors are widely used in electronic equipment such as cellular phones, audio amplifiers, and radio transmitters.

A Heterojunction Bipolar Transistor (HBT) is a bipolar transistor that uses different semiconductor materials for the emitter region and the base region of the device, creating a heterojunction. The heterojunction bipolar transistor may use a III-V compound semiconductor material, a II-VI compound semiconductor material, or other similar compound semiconductor materials. Group III-V (and II-VI) compound semiconductor materials typically exhibit high carrier mobility and direct energy gap. Heterojunction bipolar transistors improve bipolar transistors by supporting substantially higher frequencies, e.g., up to several hundred gigahertz (GHz). Thus, heterojunction bipolar transistors are commonly used in high speed circuits, such as RF chip designs, including RF power amplifiers in mobile RF transceivers.

A relatively small number of silicon-based CMOS transistors are used to fabricate the RF power amplifier. Highly complex and highly integrated baseband and transceiver RF integrated circuits involve advanced, reduced gate length CMOS processes for integrating functions in very small dies. For example, within the RF front end module, CMOS processes are used to fabricate the switches and digital control. In contrast, a compound semiconductor heterojunction bipolar transistor is used to implement a power amplifier.

Successful fabrication of modern semiconductor chip products, such as integrated compound semiconductor transistors and passive devices, involves interactions between the processes and materials employed. A process flow for semiconductor fabrication of integrated circuit structures may include front-end (FEOL) processes, middle-end (MOL) (also known as middle-end (MEOL)) processes, and back-end (BEOL) processes to form interconnects (e.g., M1, M2, M3, M4, etc.). The front-end process may include a set of process steps to form active devices, such as transistors, capacitors, and diodes.

front-end processes include ion implantation, annealing, oxidation, Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), etching, Chemical Mechanical Polishing (CMP), and epitaxy. The intermediate process may include a set of process steps that can connect the transistors to the back-end interconnect. These steps include silicidation and contact formation and stress introduction. The back end process may include a set of process steps that form interconnects that join individual transistors and form a circuit.

A Heterojunction Bipolar Transistor (HBT) is an example of a compound semiconductor transistor. A heterojunction bipolar transistor integrated circuit (HBT chip) may integrate resistors, capacitors, and heterojunction bipolar transistors to provide, for example, a power amplifier. Unfortunately, capacitors (e.g., metal-insulator-metal (MIM) capacitors) can occupy up to twenty percent (20%) of the HBT chip area due to the limited range of dielectric materials available in HBT processes. That is, compound semiconductor (e.g., III-and V-group (III-V) materials) dielectrics are generally not available, making it difficult to fabricate capacitors (e.g., MIM capacitors) in compound semiconductor devices. In contrast, CMOS (complementary metal oxide semiconductor) silicon-based MIM capacitors can exhibit a capacitance density four times (4x) greater than compound semiconductor MIM capacitors.

aspects of the present disclosure may address this problem by integrating a compound semiconductor transistor (e.g., a compound semiconductor field effect transistor, a heterojunction bipolar transistor, a High Electron Mobility Transistor (HEMT), etc.) with a high-density compound semiconductor metal-insulator-metal (MIM) Capacitor (CAP). Replacing the compound semiconductor MIM capacitors of the HBT chip with high density compound semiconductor MIM capacitors increases the capacitance density (e.g., by 300% -600%). High density compound semiconductor MIM capacitors can occupy a significantly reduced capacitor area (e.g., 1/3-1/6 of original size). Such HBT chip area reduction can significantly reduce HBT chip cost (e.g., by 13% -16% (from about 20%)). Furthermore, the integration of the high-density compound semiconductor MIM capacitor in the HBT chip is performed without changing the HBT process and without sacrificing the performance of the HBT. The integration of high-density compound semiconductor MIM capacitors in HBT chips does not involve additional masks either.

fig. 1 shows a perspective view of a semiconductor wafer. The wafer 100 may be a semiconductor wafer or may be a substrate material having one or more layers of semiconductor material on a surface of the wafer 100. When the wafer 100 is a semiconductor material, it may be grown from a seed using a Czochralski (Czochralski) process, in which the seed is immersed in a molten bath of semiconductor material and slowly rotated, and removed from the molten bath. The molten material then crystallizes onto the seed crystals in the crystalline orientation.

The wafer 100 may be composed of the following materials: compound semiconductor materials such as gallium arsenide (GaAs, InP) or gallium nitride (GaN); ternary materials such as indium gallium arsenide (InGaAs, AlGaAs, InGaSb); quaternary material (InGaAsP); or any material that can serve as a substrate material for other compound semiconductor materials. Although many materials may be crystalline in nature, polycrystalline or amorphous materials may also be used for wafer 100.

The wafer 100 or a layer coupled to the wafer 100 may be supplied with a material that makes the wafer 100 more conductive. For example, but not limiting of, the silicon wafer may have phosphorus or boron added to the wafer 100 to allow charge to flow in the wafer 100. These additives are referred to as dopants and provide additional charge carriers (electrons or holes) within wafer 100 or portions of wafer 100. Different types of electronic devices may be formed in or on the wafer 100 by selecting the region in which the additional charge carriers are provided, which type of charge carriers are provided, and the amount (density) of additional charge carriers in the wafer 100.

Wafer 100 has an orientation 102, which indicates the crystal orientation of wafer 100. Orientation 102 may be a flat edge of wafer 100 as shown in fig. 1, or may be a notch or other marking to show the crystal orientation of wafer 100. The orientation 102 may indicate the miller index of the lattice plane in the wafer 100.

after the wafer 100 is processed as necessary, the wafer 100 is divided along the dicing lines 104. Scribe lines 104 indicate locations where the wafer 100 is to be separated or diced. Scribe lines 104 may define the outline of various integrated circuits that have been fabricated on wafer 100.

Once the scribe lines 104 are defined, the wafer 100 may be sawed or otherwise separated into pieces to form the dies 106. Each of the dies 106 may be an integrated circuit having many devices, or may be a single electronic device. The physical size of the die 106 (which may also be referred to as a chip or semiconductor chip) depends, at least in part, on the ability to divide the wafer 100 into particular sizes and the number of individual devices that the die 106 is designed to contain.

after the wafer 100 is separated into one or more dies 106, the dies 106 can be mounted into packages to allow access to devices and/or integrated circuits fabricated on the dies 106. The package may include a single inline package, a dual inline package, a motherboard package, a flip chip package, an indium dot/bump package, or other type of device that provides access to the die 106. The die 106 may also be directly accessed by wire bonds, probes, or other connections without the die 106 being mounted in a separate package.

Fig. 2 shows a cross-sectional view of the die 106. In the die 106, a substrate 200 may be present, the substrate 200 may be a semiconductor material and/or may serve as a mechanical support for the electronic device. The substrate 200 may be a doped semiconductor substrate having electron (designated as N-channel) or hole (designated as P-channel) charge carriers present throughout the substrate 200. Subsequent doping of the substrate 200 with charge carrier ions/atoms may alter the charge carrying capacity of the substrate 200.

The semiconductor substrate may also have a well 206 and a well 208. The well 208 may be entirely within the well 206, and in some cases, a Bipolar Junction Transistor (BJT), a Heterojunction Bipolar Transistor (HBT), or other similar compound semiconductor transistor may be formed. The well 206 may also serve as an isolation well to isolate the well 208 from electric and/or magnetic fields within the die 106.

Layers (e.g., 210-214) may be added to the die 106. Layer 210 may be, for example, an oxide or insulating layer that may isolate wells (e.g., 202-208) from each other or from other devices on die 106. In this case, layer 210 may be silicon dioxide, a polymer, a dielectric, or another electrically insulating layer. Layer 210 may also be an interconnect layer, in which case it may comprise a conductive material, such as copper, tungsten, aluminum, an alloy, or other conductive or metallic material.

Layer 212 may also be a dielectric or conductive layer depending on the desired device characteristics and/or the material of the layer (e.g., 210 and 214). Layer 214 may be an encapsulation layer that may protect the layers (e.g., 210 and 212) as well 202 and 208 and substrate 200 from external forces. For example, but not by way of limitation, layer 214 may be a layer that protects die 106 from mechanical damage, or layer 214 may be a layer of material that protects die 106 from electromagnetic or radiation damage.

The electronic device designed on the die 106 may include a number of features or structural components. For example, the die 106 may be exposed to any number of methods to impart dopants into the substrate 200, the well 202, 208, and, if desired, layers (e.g., 210, 214). For example, but not limited to, the die 106 may be exposed to ion implantation, deposition of dopant atoms driven into the crystal lattice by a diffusion process, chemical vapor deposition, epitaxial growth, or other methods. Many different structures and electronic devices may be formed within the scope of the present disclosure by selective growth, material selection and removal of portions of the layers (e.g., 210-214), and by selective removal, material selection and dopant concentration of the substrate 200 and the wells 202-208.

in addition, the substrate 200, wells 202, 208, and layers (e.g., 210, 214) may be selectively removed or added by various processes. Chemical wet etching, Chemical Mechanical Planarization (CMP), plasma etching, photoresist masking, damascene processes, and other methods may produce the structures and devices of the present disclosure. Aspects of the present disclosure include integration of a high-density compound semiconductor transistor with a compound semiconductor transistor such as a heterojunction bipolar transistor.

A Heterojunction Bipolar Transistor (HBT) is a bipolar transistor that uses different semiconductor materials for the emitter region and the base region of the device, creating a heterojunction. The heterojunction bipolar transistor may use a III-V compound semiconductor material, a II-VI compound semiconductor material, or other similar compound semiconductor materials. Group III-V (and II-VI) compound semiconductor materials typically exhibit high carrier mobility and direct energy gap. Heterojunction bipolar transistors improve bipolar transistors by supporting substantially higher frequencies, e.g., up to several hundred gigahertz (GHz). Thus, heterojunction bipolar transistors are commonly used in high speed circuits, such as the RF chip design of RF power amplifiers in mobile RF transceivers including Radio Frequency (RF) front end modules, for example, as shown in fig. 3.

Fig. 3 shows a block diagram of an exemplary design of a wireless device 300. Fig. 3 shows an example of a transceiver 320, which may be a Wireless Transceiver (WTR). In general, the conditioning of signals in the transmitter 330 and receiver 350 may be performed by one or more stages of amplifiers, filters, upconverters, downconverters, and so forth. These circuit blocks may be arranged differently from the configuration shown in fig. 3. In addition, other circuit blocks not shown in fig. 3 may also be used to condition signals in transmitter 330 and receiver 350. Unless otherwise noted, any of the signals in fig. 3 or any of the other figures may be single ended or differential. Some circuit blocks in fig. 3 may also be omitted.

In the example shown in fig. 3, the wireless device 300 generally includes a transceiver 320 and a data processor 310. The data processor 310 may include a memory (not shown) for storing data and program code, and may typically include analog and digital processing elements. Transceiver 320 may include a transmitter 330 and a receiver 350 that support bi-directional communication. In general, wireless device 300 may include any number of transmitters and/or receivers for any number of communication systems and frequency bands. All or a portion of transceiver 320 may be implemented on one or more analog Integrated Circuits (ICs), Radio Frequency (RF) integrated circuits (RFICs), mixed signal ICs, and so forth.

The transmitter or receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between radio frequency and baseband in multiple stages, e.g., from radio frequency to Intermediate Frequency (IF) in one stage and then from intermediate frequency to baseband in another stage for a receiver. In the direct conversion architecture, the signal is frequency converted between radio frequency and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the example shown in fig. 3, the transmitter 330 and receiver 350 are implemented with a direct conversion architecture.

In the transmit path, data processor 310 processes data to be transmitted. The data processor 310 also provides in-phase (I) and quadrature (Q) analog output signals to the transmitter 330 in the transmit path. In an exemplary aspect, the data processor 310 includes digital-to-analog converters (DACs) 314a and 314b for converting digital signals generated by the data processor 310 into in-phase (I) and quadrature (Q) analog output signals (e.g., I and Q output currents) for further processing.

Within transmitter 330, low pass filters 332a and 332b filter the in-phase (I) and quadrature (Q) analog transmit signals, respectively, to remove unwanted images caused by previous digital-to-analog conversion. Amplifiers (Amp)334a and 334b amplify the signals from lowpass filters 332a and 332b, respectively, and provide in-phase (I) and quadrature (Q) baseband signals. An upconverter 340 upconverts in-phase (I) and quadrature (Q) baseband signals, which are in-phase (I) and quadrature (Q) transmit Local Oscillator (LO) signals from a TX LO signal generator 390, to provide an upconverted signal. The filter 342 filters the up-converted signal to remove an undesired image caused by the up-conversion and noise in a reception frequency band. A Power Amplifier (PA)344 amplifies the signal from the filter 342 to obtain a desired output power level and provides a transmit radio frequency signal. The transmit radio frequency signal is routed through duplexer/switch 346 and transmitted via antenna 348.

In the receive path, antenna 348 receives communication signals and provides a received Radio Frequency (RF) signal, which is routed through duplexer/switch 346 and provided to a Low Noise Amplifier (LNA) 352. Duplexer/switch 346 is designed to operate with a particular Receive (RX) -Transmit (TX) (RX-TX) duplexer frequency separation, so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 352 and filtered by filter 354 to obtain the desired RF input signal. Downconversion mixers 361a and 361b mix the output of filter 354 with in-phase (I) and quadrature (Q) Receive (RX) LO signals (i.e., LO _ I and LO _ Q) from an RX LO signal generator 380 to generate in-phase (I) and quadrature (Q) baseband signals. The in-phase (I) and quadrature (Q) baseband signals are amplified by amplifiers 362a and 362b and further filtered by low pass filters 364a and 364b to obtain in-phase (I) and quadrature (Q) analog input signals, which are provided to data processor 310. In the exemplary configuration shown, data processor 310 includes analog-to-digital converters (ADCs) 316a and 316b to convert analog input signals to digital signals for further processing by data processor 310.

In fig. 3, a transmit local oscillator (TX LO) signal generator 390 generates in-phase (I) and quadrature (Q) TX LO signals that are used for frequency upconversion, while a receive local oscillator (RX LO) signal generator 380 generates in-phase (I) and quadrature (Q) RX LO signals that are used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A phase-locked loop (PLL)392 receives timing information from data processor 310 and generates control signals that are used to adjust the frequency and/or phase of the TX LO signals from TX LO signal generator 390. Similarly, PLL382 receives timing information from data processor 310 and generates a control signal that is used to adjust the frequency and/or phase of the RX LO signals from RX LO signal generator 380.

The wireless device 300 may support carrier aggregation and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers of different frequencies and/or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. For intra-band carrier aggregation, transmissions are sent on different carriers in the same frequency band. For inter-band carrier aggregation, transmissions are sent on multiple carriers of different frequency bands. However, those skilled in the art will appreciate that the aspects described herein may be implemented in systems, devices, and/or architectures that do not support carrier aggregation.

The power amplifier 344 may include one or more stages having, for example, driver stages, power amplifier stages, or other components, which may be configured to amplify communication signals at one or more frequencies, in one or more frequency bands, and at one or more power levels. Transistors configured to amplify communication signals are typically selected to operate at substantially higher frequencies. Heterojunction bipolar transistors improve bipolar transistors by supporting substantially higher frequencies, e.g., up to several hundred gigahertz (GHz). Therefore, heterojunction bipolar transistors are commonly used for high speed circuits, such as RF chip designs that include a specified high power efficiency of the RF power amplifier in mobile RF transceivers.

A heterojunction bipolar transistor integrated circuit (HBT chip) may integrate resistors, capacitors, and heterojunction bipolar transistors to provide, for example, a power amplifier. Unfortunately, capacitors (e.g., metal-insulator-metal (MIM) capacitors) can occupy a substantial portion of HBT chip area due to the limited range of dielectric materials available in HBT processes. That is, compound semiconductor (e.g., III-and V-group (III-V) materials) dielectrics are generally not available, making it difficult to fabricate capacitors (e.g., MIM capacitors) in compound semiconductor devices. In contrast, CMOS (complementary metal oxide semiconductor) silicon-based MIM capacitors can exhibit significantly increased capacitance density relative to compound semiconductor MIM capacitors.

Aspects of the present disclosure may address this problem by integrating a compound semiconductor transistor (e.g., a compound semiconductor field effect transistor, a heterojunction bipolar transistor, a High Electron Mobility Transistor (HEMT), etc.) with a high-density compound semiconductor metal-insulator-metal (MIM) Capacitor (CAP). The integration of high density compound semiconductor MIM capacitors in HBT chips can be performed without changing the HBT process and without sacrificing HBT performance. The integration of high density compound semiconductor MIM capacitors in HBT chips may also involve no additional masks while reducing the footprint (footprint) of the compound semiconductor MIM capacitor.

Fig. 4 shows a heterojunction bipolar transistor die sheet 400 integrating a compound semiconductor transistor (e.g., Heterojunction Bipolar Transistor (HBT)410), a resistor 402 (e.g., a thin film resistor), and a compound semiconductor MIM capacitor 430. Although shown as integrating HBT410 and compound semiconductor MIM capacitor 430, compound semiconductor MIM capacitor 430 may be integrated with a field effect transistor or other similar compound semiconductor device, such as a High Electron Mobility Transistor (HEMT).

HBT chip 400 may provide, for example, an HBT-based power amplifier, such as power amplifier 344 of figure 3. HBT410 includes an emitter 420(EM), a base 414 contacting emitter 420, a collector 412 contacting base 414, and a subcollector 411 contacting collector 412. The emitter 420 includes an emitter contact 422(EC), the base 414 includes a base contact 424(BC), and the subcollector 411 includes a collector contact 426 (CC). HBT410 is supported by a compound semiconductor substrate 428, such as gallium arsenide (GaAs). Additionally, resistor 402 and compound semiconductor MIM capacitor 430 are disposed adjacent HBT 410. The conductive material of the resistor 402 may include, but is not limited to, tantalum nitride (TaN), tungsten silicide (WSi), nickel chromide (NiCr), cobalt nitride (CoN), or other similar conductive materials. The thickness of the resistor 402 may be in the range of ten angstroms (10A) to one thousand angstroms (1000A).

As noted, compound semiconductor MIM capacitor 430 may occupy up to twenty percent (20%) of the die area of HBT die 400. The large size of the compound semiconductor MIM capacitor 430 is due to the HBT process used to form the compound semiconductor MIM capacitor 430. In particular, HBT dielectrics, such as silicon nitride (SiN), used to form compound semiconductor MIM capacitor 430 typically exhibit low dielectric constants (e.g., about 7). Therefore, the capacitance density of the compound semiconductor MIM capacitor 430 is low because the capacitance density is proportional to the dielectric constant of the insulator. In the stacked MIM capacitor configuration shown in figure 4, the capacitance density of the compound semiconductor MIM capacitor 430 is increased.

in this arrangement, three electrodes are used to support two parallel capacitors. A first capacitor (C1) is formed between the first conductive interconnect (M1) electrode, the second dielectric layer 434 (first SiNx), and the second conductive interconnect (M2) electrode. The second capacitor (C2) is formed between the (M1) electrode, the first dielectric layer 432 (second SiNx), and the Collector Contact (CC) metal. The first capacitor C1 (e.g., the first capacitive component) may exhibit a capacitance density of six hundred picofarads per square meter (600pF/mm 2). The second capacitor C2 (e.g., the second capacitive component) may exhibit a capacitance density of three hundred picofarads per square meter (300pF/mm2), with a total stacked capacitance density of 900pF/mm 2. In contrast, silicon-based CMOS capacitors can exhibit a capacitance density of four thousand farads per square meter (4000fF/mm2) while occupying less than five percent (5%) of the chip area.

fig. 5A-5C illustrate high density compound semiconductor MIM capacitors in parallel capacitor configurations according to aspects of the present disclosure. Fig. 5A illustrates a cross-sectional view of a compound semiconductor MIM capacitor 500 according to aspects of the present disclosure. In some embodiments, the term "in. In some embodiments, the term "in. The compound semiconductor MIM capacitor 500 may comprise a collector contact layer (CC metal) supporting a first dielectric layer SiN1 and a via one (V1). A first conductive interconnect M1 is arranged on the first dielectric layer SiN 1. The conductive material of the CC metal may include, but is not limited to, titanium (Ti), platinum (Pt), gold (Au), cobalt (Co), or other similar conductive materials. The thickness of the CC metal may range from ten angstroms (10A) to one thousand angstroms (1000A).

in this arrangement, instead of the second dielectric layer, a high-K dielectric layer (HiK layer) is deposited on the first conductive interconnect M1. In addition, a second conductive interconnect M2 is disposed on the HiK layer to form a first capacitive component (e.g., capacitor C1). The M1 electrode is in electrical contact with the first conductive interconnect M1 through via one (V1), and the M2 electrode is in electrical contact with the second conductive interconnect M2 to access the first capacitor C1. In addition, a Collector Contact (CC) electrode is in electrical contact with the CC metal through via one V1 and via two V2 to access a second capacitive component (e.g., capacitor C2). The material of the first and second conductive interconnects M1 and M2 may include, but is not limited to, tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), or other similar conductive materials. The thickness of the first conductive interconnect M1 and the second conductive interconnect M2 may be in a range between five tenths of a micron (.5 μ M) to four (4) and eight (8) microns.

In one arrangement, the HiK layer is hafnium oxide (HfO2) or other similar high-K dielectric, including but not limited to aluminum oxide (Al2O3), lanthanum oxide (La2O3), yttrium oxide (Y2O3), lanthanum aluminate (LaAlO3), strontium titanate (SrTiO), zirconium oxide (ZrO2), silicon oxynitride (SiON), silicon carbonitride, tantalum pentoxide (Ta2O5), titanium oxide (TiO2), cerium oxide (CeO2), zirconium titanium bromide oxide (BaZrTiO3), (Bz, Ca, Sr) F2, barium strontium titanium oxide (BaSrTiO3), lead lanthanum titanium oxide (PbLaZrTiO3), lead titanium oxide (PbTiO3), lead magnesium niobium oxide (pbnbmgo 3), magnesium oxide (MgO), or zinc oxide (ZnO). The thickness of the HiK layer may be in the range of 2 nanometers (2nm) to 100 nanometers (100 nm). The use of these high-K dielectrics can significantly increase the capacitance density (e.g., 300%) of the compound semiconductor MIM capacitor 500 while causing negligible impact from back-end metal capacitance.

Fig. 5B illustrates a top view 550 and fig. 5C illustrates a simplified terminal view of the compound semiconductor MIM capacitor 500 of fig. 5A in accordance with aspects of the present disclosure. In the arrangement of fig. 5B, the use of the HiK layer enables the size of the M2 pole plate of the first capacitor C1 to be significantly reduced. The reduction of the M2 plate may reduce the capacitor area by twenty percent (20%). The capacitor area reduction can be up to about 7% (7%) of the total chip area, which results in a significant die cost reduction (e.g., 13%).

Fig. 6A-6C illustrate a high density compound semiconductor MIM capacitor 600 in an alternative parallel capacitor configuration according to aspects of the present disclosure. In this arrangement, a conductive electrode layer 640 (e.g., tantalum nitride (TaN) or nickel chromium (NiCr) metal) is deposited on first dielectric layer SiN 1. In addition, a high-K layer (HiK layer) is deposited on the conductive electrode layer 640 to form a second high-density capacitor C2. The HiK layer may be referred to as a third dielectric layer.

based on the simplified terminal view 670 of the compound semiconductor MIM capacitor 600 of fig. 6C, the conductive contact electrode 642 is in electrical contact with the conductive electrode layer 640 through via one V1 and via two V2. Access to the high density second capacitor C2 is provided by electrically conductive contact electrodes 642 and M1 electrodes. In addition, the M1 electrode is in electrical contact with the first conductive interconnect M1 through via two V2, and the M2 electrode is in electrical contact with the second conductive interconnect M2. In this arrangement, access to the low density capacitor C1 is provided by the M1 electrode and the M2 electrode.

As seen in top view 650 (fig. 6B), the use of the HiK layer enables the size of the M2 plate of the first capacitor C1 to be significantly reduced. The reduction of the M2 plate may also result in a significant capacitor area reduction. The capacitor area reduction may correspond to a significant reduction in the total chip area, which reduces die cost. In addition, the material of the conductive electrode layer 640 may be slightly modified from a high-precision metal resistor (e.g., the resistor 402 of fig. 4).

Fig. 7A-7C illustrate a high density compound semiconductor MIM capacitor 700 in another alternative parallel capacitor configuration according to aspects of the present disclosure. In this arrangement, a second high-K layer (HiK layer-2 #) was deposited on the M1 plate of the first high-density capacitor C1 in place of the second dielectric layer SiN2, as shown in fig. 6A. Similar to the configuration in fig. 6A, a first high-K layer (HiK layer-1 #) is deposited on the conductive electrode layer 640 to form a second high-density capacitor C2. In addition, a conductive electrode layer 640 is deposited on the first dielectric layer SiN 1.

Based on the simplified terminal view 770 of the compound semiconductor MIM capacitor 700 of fig. 7C, access to the first high-density capacitor C1 is provided by an M1 electrode and an M2 electrode. In this arrangement, the M1 electrode is in electrical contact with the M1 plate through via two V2, and the M2 electrode is in electrical contact with the M2 plate of the first high-density capacitor. In addition, conductive contact electrode 642 is also in electrical contact with conductive electrode layer 640 through via one V1 and via two V2. Access to the second high-density capacitor C2 is also provided by conductive contact electrodes 642 and M1 electrodes.

In top view 750 of fig. 7B, the use of first HiK layer-1 # and second HiK layer-2 # provides a significant increase in capacitance density (e.g., a 500% improvement). This arrangement also produces a significant capacitor area reduction (e.g., 20%). The capacitor area reduction may amount to a significant reduction in the total chip area (e.g., 4%), thereby reducing die cost (e.g., 16%).

fig. 8A-8C illustrate a high density compound semiconductor MIM capacitor 800 in another alternative parallel capacitor configuration in accordance with aspects of the present disclosure. In this arrangement, a second high-K layer (HiK layer-2 #) is also deposited on the M1 plate of the first high-density capacitor C1, in place of the second dielectric layer SiN2, as shown in fig. 6A. Similar to the configuration in fig. 7A, a first high-K layer (HiK layer-1 #) is deposited on the conductive electrode layer 640 to form a second high-density capacitor C2. In addition, a conductive electrode layer 640 is deposited on the first dielectric layer SiN 1.

In this arrangement, the CC electrode is in electrical contact with the CC metal through via one V1 and via two V2. This arrangement of CC electrodes provides a third capacitive component (e.g., capacitor C3) in parallel with the first high-density capacitor C1 and the second high-density capacitor C2. The third capacitor C3 (e.g., third capacitive component) may include CC metal as a first plate, a first dielectric layer SiN1 as a capacitor dielectric, and a conductive electrode layer 640 as a second plate.

Based on the simplified terminal view 870 of the compound semiconductor MIM capacitor 800 of fig. 8C, the CC electrode electrically contacts the CC metal through via one V1 and via two V2. Access to the third capacitor C3 is provided by conductive contact electrode 642 and the CC electrode. In addition, the M1 electrode is in electrical contact with the first conductive interconnect M1 through via two V2, and the M2 electrode is in electrical contact with the second conductive interconnect M2. In this arrangement, access to the first high-density capacitor C1 is provided by the M1 electrode and the M2 electrode. Access to the second high density capacitor is provided by the M1 electrode and the conductive contact electrode 642.

In the top view 850 of fig. 8B, the addition of the third capacitor C3 provides a further increase in capacitance density (e.g., a 560% improvement). This arrangement also produces a significant capacitor area reduction (e.g., 20%). The capacitor area reduction can amount to a significant reduction in the total chip area (e.g., 3.5%), with a cost savings (e.g., 16.5%). This achieves significant die cost reduction without having to modify the HBT process.

Although shown as including three parallel capacitors (e.g., C1, C2, and C3), it should be appreciated that: aspects in accordance with the present disclosure contemplate the formation of additional parallel or series coupled capacitors using additional interconnect layers (e.g., M3, M4, etc.) and dielectric layers. For example, a fourth capacitor C4 (e.g., a fourth capacitive component) may be formed by the third conductive interconnect M3 and a fourth dielectric layer on the first conductive interconnect M1 or the second conductive interconnect M2.

According to additional aspects of the present disclosure, the compound semiconductor material may include, but is not limited to, gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), gallium antimony (GaSb), gallium phosphide (GaP), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), aluminum gallium antimony (AlGaSb), indium gallium antimony (InGaSb), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), indium gallium arsenide phosphide (InGaAsP), indium gallium arsenide antimonide (InGaAsSb), or indium gallium arsenide nitride (InGaAs: N). These are merely exemplary, and other materials are possible.

Fig. 9 is a flow chart illustrating a method of fabricating a high density metal-insulator-metal (MIM) capacitor according to an aspect of the invention. The blocks in method 900 may or may not be performed in the order shown, and in some aspects may be performed at least partially in parallel.

the method 900 begins at block 902, where a first dielectric layer is deposited on a collector contact layer supported by a compound semiconductor substrate. For example, a first dielectric layer of SiN1 is deposited on the CC metal, as shown in fig. 5A. Alternatively, a high-K dielectric layer may be deposited on the CC metal to increase capacitance density. At block 904, a conductive electrode layer is deposited on the first dielectric layer to form a first capacitive component. For example, a conductive electrode layer 640 is deposited on the first dielectric layer SiN1 to form a third capacitor C3. The third capacitor C3 may be converted into a high-density capacitor by replacing the first dielectric layer SiN1 with a high-K dielectric.

referring again to fig. 9, at block 906, a second dielectric layer is deposited over the conductive electrode layer. For example, as shown in fig. 8A, HiK layer # 1 is deposited on the conductive electrode layer 640. At block 908, a first conductive interconnect is formed on the second dielectric layer to form a second capacitive component. For example, as shown in fig. 8A, the first conductive interconnect M1 is formed on the HiK layer-1 # to form the second high-density capacitor C2. At block 910, a third dielectric layer is deposited over the first conductive interconnect. For example, HiK layer-2 # may be deposited on the first conductive interconnect M1. At block 912, a second conductive interconnect is formed on the third dielectric layer to form a third capacitive component. For example, the second conductive interconnect M2 is formed on the HiK layer-2 # to form the first high-density capacitor C1 (first capacitive component).

The HBT chip may integrate resistors, capacitors, and heterojunction bipolar transistors to provide, for example, a power amplifier. The integration of high density compound semiconductor MIM capacitors in HBT chips is performed without modifying the HBT process and without sacrificing HBT performance. The integration of high density compound semiconductor MIM capacitors in HBT chips also does not involve additional masks, while reducing the footprint of the compound semiconductor MIM capacitor.

According to another aspect of the present disclosure, a metal-insulator-metal capacitor is described. A MIM capacitor may include a means for supporting the MIM capacitor. The support member may, for example, include a compound semiconductor substrate 428 as shown in fig. 4. In another aspect, the aforementioned means may be any layer, module or any device configured to perform the functions recited by the aforementioned means.

Fig. 10 is a block diagram illustrating an exemplary wireless communication system 100 in which an aspect of the present disclosure may be advantageously employed. For purposes of illustration, FIG. 10 shows three remote units 1020, 1030, and 1050 and two base stations 1040. It will be appreciated that a wireless communication system may have many more remote units and base stations. Remote units 1020, 1030, and 1050 include IC devices 1025A, 1025C, and 1025B that include the disclosed compound semiconductor MIM capacitors. It will be appreciated that other devices may also include the disclosed compound semiconductor MIM capacitor, such as base stations, user equipment, and network equipment. Fig. 10 illustrates forward link signals 1080 from the base stations 1040 to the remote units 1020, 1030, and 1050 and reverse link signals 1090 from the remote units 1020, 1030, and 1050 to base stations 1040.

in fig. 10, remote unit 1020 is illustrated as a mobile telephone, remote unit 1030 is illustrated as a portable computer, and remote unit 1050 is illustrated as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, hand-held Personal Communication Systems (PCS) units, portable data units such as Personal Digital Assistants (PDAs), GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or other communication devices that store or retrieve data or computer instructions, or a combination thereof. Although fig. 10 illustrates remote units according to aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the invention are applicable to many devices including the disclosed compound semiconductor MIM capacitor.

The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the protection. For example, the example apparatus, methods, and systems disclosed herein may be applied to multi-SIM wireless devices that subscribe to multiple communication networks and/or communication technologies. The apparatus, methods, and systems disclosed herein may be implemented digitally and variously, among others. The various components shown in the figures may be implemented as, for example, but not limited to, software and/or firmware on a processor, ASIC/FPGA/DSP, or dedicated hardware. Moreover, the features and attributes of the specific example aspects disclosed above may be combined in different ways to form additional aspects, all of which fall within the scope of the present disclosure.

The foregoing method descriptions and process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the operations of the method must be performed in the order presented. Certain operations may be performed in a different order. Words such as "after," "then," "next," etc. are not intended to limit the order of the operations; these words are simply used to guide the reader through the description of the method.

the various illustrative logical blocks, modules, circuits, and operations described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and operations have been described herein generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The hardware used to implement the various illustrative logics, logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of receiver devices (e.g., a combination of a DSP and a microprocessor), a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry that is specific to a given function.

In one or more exemplary aspects, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable storage medium or a non-transitory processor-readable storage medium. The operations of the methods or algorithms disclosed herein may be embodied in processor-executable instructions that may reside on non-transitory computer-readable or processor-readable storage media. A non-transitory computer-readable or processor-readable storage medium may be any storage medium that is accessible by a computer or a processor. By way of example, and not limitation, such non-transitory computer-readable or processor-readable storage media can include Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and/or instructions on a non-transitory processor-readable storage medium and/or computer-readable storage medium, which may be incorporated into a computer program product.

While the present disclosure provides certain example aspects and applications, other aspects that will be apparent to those of ordinary skill in the art, including aspects that do not provide all of the features and advantages set forth herein, are also within the scope of the present disclosure. For example, the apparatus, methods, and systems described herein may be implemented digitally and differently, among others. Accordingly, the scope of the present disclosure is intended to be defined only by reference to the appended claims.