阅读说明：本技术 半导体元件的制作方法 (Method for manufacturing semiconductor element ) 是由 孔祥波 邵红旭 孔德锦 邱云松 黃清俊 谈文毅 于 2021-03-19 设计创作，主要内容包括：本发明公开一种半导体元件的制作方法,包含提供一基底,在该基底上沉积一材料层,对该材料层进行一平坦化步骤,移除部分该材料层,在该平坦化步骤之后,对剩余的该材料层进行一掺杂步骤,以及进行一清洗步骤,同时移除该平坦化步骤后所产生的杂质以及该掺杂步骤后所产生的杂质。(The invention discloses a method for manufacturing a semiconductor element, which comprises the steps of providing a substrate, depositing a material layer on the substrate, carrying out a planarization step on the material layer, removing part of the material layer, carrying out a doping step on the rest material layer after the planarization step, carrying out a cleaning step, and simultaneously removing impurities generated after the planarization step and impurities generated after the doping step.)

1. A method for fabricating a semiconductor device includes:

providing a substrate, and depositing a material layer on the substrate;

carrying out a planarization step on the material layer, and removing part of the material layer;

after the planarization step, performing an ion doping step on the remaining material layer; and

and performing a cleaning step, and removing impurities generated after the planarization step and impurities generated after the ion doping step.

2. The method of claim 1, wherein the material layer comprises a polysilicon layer.

3. The method of claim 1, wherein the cleaning step comprises a standard cleaning Step (SPM), an RCA cleaning step, a high pressure water gun (scrubber) cleaning step, and combinations thereof.

4. The method of claim 3, further comprising: during this cleaning step, a thermal annealing step is performed.

5. The method of claim 4, wherein said thermal annealing step is performed after said RCA cleaning step and before said high pressure water gun cleaning step.

6. The method of claim 3, wherein the standard cleaning step comprises cleaning with a mixed solution of sulfuric acid, hydrogen peroxide and water.

7. The method of claim 3, wherein the standard cleaning step comprises cleaning with a mixture of ammonia, hydrogen peroxide and water, or a mixture of hydrochloric acid, hydrogen peroxide and water.

8. The method of claim 1, wherein no other steps are performed between performing the planarization step and performing the ion doping step.

9. The method of claim 1, further comprising forming a plurality of shallow trench isolations partially within the substrate and partially protruding from the surface of the substrate.

10. The method of claim 1, wherein the planarizing step comprises a Chemical Mechanical Polishing (CMP) step.

11. The method of claim 10, further comprising performing a high pressure water gun cleaning step to remove particulate impurities from the substrate prior to the Chemical Mechanical Polishing (CMP) step.

12. The method of claim 1, wherein after said cleaning step, further comprising an etch back step of said material layer, removing a portion of said material layer, and forming at least one floating gate structure on said substrate with the remaining material layer.

13. The method of claim 1, wherein the material layer has a thickness of less than 1000 angstroms after the planarization step is performed.

Technical Field

The present invention relates to the field of semiconductor manufacturing processes, and in particular, to a method for simplifying a floating gate structure in a semiconductor memory device.

Background

Semiconductor memories are semiconductor devices used for storing data or data in computers or electronic products, and can be roughly classified into volatile memories (vollatile) and nonvolatile memories, wherein the nonvolatile memories are widely used because of their characteristic of preventing data loss due to power supply interruption.

However, as computer microprocessors become more powerful, the need for large capacity and low cost memory increases. To meet this trend and the continuing challenge of high integration in semiconductor technology, memory structures are becoming smaller and more complex. And also the total time of the manufacturing process is lengthened as the manufacturing process becomes more complicated and the number of steps becomes more.

For example, in the conventional fabrication of a material layer (e.g., a polysilicon layer) of a floating gate in a semiconductor device, cleaning steps may be performed after an ion doping step, a planarization step, and an annealing step, respectively, so that although the impurities remaining on the substrate may be cleaned in real time, the fabrication process is increased and the total number of fabrication processes is lengthened.

Disclosure of Invention

In order to solve the above problems, the present invention provides a method for fabricating a semiconductor device, which can shorten the time of the semiconductor fabrication process.

In one embodiment of the present invention, a method for fabricating a semiconductor device includes providing a substrate, depositing a material layer on the substrate, performing a planarization step on the material layer, removing a portion of the material layer, performing a doping step on the remaining material layer after the planarization step, and performing a cleaning step while removing impurities generated after the planarization step and impurities generated after the doping step.

The present invention is characterized in that when manufacturing the material layer (such as the polysilicon layer) of the floating gate, a planarization step is performed to reduce the thickness of the material layer, and then an ion doping step is performed to fully dope ions into the material layer. It is noted that the planarization step and the ion doping step generate unnecessary impurities, respectively, and the cleaning step is performed after the ion doping step, and the impurities generated in the planarization step and the ion doping step are removed, respectively, so as to save the steps.

Drawings

FIG. 1 is a flow chart of a method for fabricating a semiconductor device according to the present invention;

fig. 2 to 5 are schematic cross-sectional views illustrating the fabrication of the semiconductor device of the present invention.

Description of the main elements

100 base

102 element region

103 liner layer

104 logical area

106 shallow trench isolation

108 polycrystalline silicon layer

109 impurities

P1 planarization step

P2 ion doping step

P3 SPM cleaning step

P4 RCA cleaning step

S101. step

S102 step

S103, step

S104 step

S105, step

S105, step

S107 step

S108 step

S109, step

S110. step

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

For convenience of explanation, the drawings are only schematic to facilitate understanding of the present invention, and the detailed proportions thereof may be adjusted according to design requirements. The relative positions of elements in the figures described herein are understood by those skilled in the art to refer to relative positions of objects and thus all parts may be turned over to present the same elements, all falling within the scope of the present disclosure and all described herein.

Referring to fig. 1, fig. 1 is a flow chart illustrating the fabrication of the semiconductor device of the present invention, and fig. 2 to 5 are also included, wherein fig. 2 to 5 are schematic cross-sectional views illustrating the fabrication of the semiconductor device of the present invention. First, as shown in step S101 of fig. 1 and fig. 2, a substrate 100 is provided, a plurality of shallow trench isolations 106 are formed in the substrate, and a liner layer 103 is formed on the substrate 100, as shown in fig. 2, a substrate 100 is provided, and an element region 102 and a logic region 104 are defined on the substrate 100. The device region 102 typically includes subsequently formed bit lines, word lines, and the like, while the logic region 104 typically includes read/write circuits and/or other circuit transistors to support operation of the memory devices. Generally, the devices in the device region 102 have a greater density, i.e., the devices are arranged more closely, and the devices in the logic region 104 have a looser arrangement and a lower density.

Still referring to FIG. 2, a plurality of shallow trench isolations 106 are formed in the substrate 100 within the device region 102 and the logic region 104. Wherein the shallow trench isolations 106 are generally linear and parallel. In this embodiment, the upper surface of the shallow trench isolation 106 is higher than the surface of the substrate 100. The material of the shallow trench isolation 106 is, for example, but not limited to, silicon oxide.

In addition, a liner layer 103, such as silicon oxide or a composite layer of silicon oxide and silicon nitride, is included between the substrate 100 and each of the polysilicon layers 108. The liner layer 103 is formed by, for example, in-situ vapor generation (ISSG) technology, which is a prior art in the field and will not be described herein.

In addition, although not shown in fig. 2, in the present embodiment, a doping step may be performed in the substrate 100 to form a P-type well or an N-type well in the substrate 100 for subsequent fabrication of semiconductor memory devices. These technical features are known to those skilled in the art and will not be described herein.

Next, in step S102 of FIG. 1, a polysilicon material layer is formed. Referring to fig. 3, a polysilicon layer 108 is deposited to cover the shallow trench isolation 106 and the liner layer 103. Polysilicon layer 108 may be used to form a subsequently desired layer of Floating Gate (FG) material. In this embodiment, undoped polysilicon is deposited on the STI 106 and the pad layer 103 by, for example, deposition, and Silane (SiH) may be introduced during the deposition process₄) The thickness of the deposited polysilicon layer 108 may be about 4000 angstroms in this embodiment, but the invention is not limited thereto, and the thickness of the deposited polysilicon layer may be adjusted according to actual requirements, and other manufacturing process parameters may be adjusted according to requirements.

Next, in step S103 of FIG. 1, a scrubbing step (scrubber) is performed to remove impurities from the polysilicon layer. In the process of forming the polysilicon layer 108 by deposition, impurities or particles with larger sizes may fall from the cavity of the machine to the surface of the polysilicon layer 108, and the particles may affect the subsequent manufacturing process, so a cleaning step, such as flushing with a high pressure water gun, is performed before the subsequent steps to remove the particles or impurities on the surface of the polysilicon layer 108. In some embodiments, the high pressure water gun may also be used with a brush to enhance cleaning. The above step may also be referred to as a brushing step (scrubber). It should be noted that, in the present invention, the step S103 is not a necessary procedure, that is, in some embodiments, if the number of particles dropped during the manufacturing process is evaluated to be within a tolerable range (e.g., the deposition time is short), the brushing step of the step S103 may also be omitted.

Next, step S104 of FIG. 1 is performed to perform a planarization step, and step S105 is performed to perform an ion doping step. Referring to fig. 4, a planarization step P1 is performed, such as by a Chemical Mechanical Polishing (CMP) process, to remove a portion of polysilicon layer 108 until the upper surface of sti 106 is exposed, as shown in fig. 4. An ion doping step P2 is then performed to dope the remaining polysilicon layer 108. In the present embodiment, after the planarization step P1 is performed, the thickness of the polysilicon layer 108 is reduced from about 4000 angstroms to about 1000 angstroms, for example, about 950 angstroms, but the above thickness is only an example of the present invention, and the present invention is not limited thereto. The ion doping step P2 is, for example, to dope the desired ions into the polysilicon layer 108 to make it charged (e.g., N-type charge).

It is noted that during the planarization step P1, some impurities may be generated on the surface of the polysilicon layer 108, and then the ion doping step P2 is performed directly without cleaning the impurities. That is, in the present invention, no other steps, especially the cleaning step, are performed between the planarization step P1 and the ion doping step P2. In the prior art, the cleaning step is performed after the planarization step to remove the impurities, but the cleaning step is omitted in the present invention. In addition, some impurities may also be generated during the ion doping step P2. Therefore, after the ion doping step P2, the remaining polysilicon layer 108 has impurities 109 left on the surface, wherein the impurities 109 are generated during the planarization step P1 and the ion doping step P2.

And then, carrying out one or more cleaning steps to remove the impurities remained on the surface of the polycrystalline silicon layer. As shown in step S106 of FIG. 1, an SPM cleaning step is performed; step S107, an RCA cleaning step is performed. Referring also to fig. 5, as shown in fig. 5, an SPM cleaning step P3, which may also be referred to as Caro's cleaning step, is performed, which is to soak the substrate 100 in a mixed solution of sulfuric acid, hydrogen peroxide and water for a certain period of time (e.g., 600 seconds in this embodiment). An RCA cleaning step P4 is performed, wherein the RCA cleaning step P4 may include an SC1 cleaning step and/or an SC2 cleaning step (either or both of them), wherein the solution for SC1 cleaning mainly includes a mixed solution of ammonia, hydrogen peroxide and pure water, and the solution for SC2 cleaning mainly includes a mixed solution of hydrochloric acid, hydrogen peroxide and pure water. In the RCA cleaning step P4, ultrasonic cleaning may be optionally performed simultaneously, but not limited thereto. Through the above cleaning steps, the impurities 109 remaining on the surface of the polysilicon layer 108 can be effectively removed. That is, after the SPM cleaning step P3 and the RCA cleaning step P4, the impurities 109 on the surface of the polysilicon layer 108 are removed.

The difference between the prior art and the prior art is that after the polysilicon layer is completed, since the planarization step is usually performed after the ion doping step, it is not easy to uniformly implant ions into the polysilicon layer in the ion doping step (because the polysilicon layer before planarization is thick), and in the prior art, the cleaning steps (which may include SPM cleaning and/or RCA cleaning) are performed after the ion doping step and after the planarization step, respectively, so that multiple times of cleaning are required. The present invention is characterized in that the planarization step is performed before the ion doping step, so that the ion doping step is easier to uniformly implant ions into the polysilicon layer (because the polysilicon layer becomes thinner after planarization). In addition, after the planarization step is performed, the cleaning step is not performed first, but is performed after the ion doping step is also completed. Therefore, the effect of saving steps can be achieved, and the manufacturing process efficiency is improved.

It should be noted that step S106 and step S107 described above both belong to cleaning steps, and are used for cleaning the impurities remaining on the surface of the polysilicon layer 108. In other embodiments of the present invention, the number and sequence of the cleaning steps may be adjusted according to actual requirements, for example, a part of the cleaning steps may be omitted herein, or other cleaning steps may be additionally added, all of which fall within the scope of the present invention.

The process may continue with other steps to complete a floating gate structure formed from the polysilicon layer, including a step S108 of performing a thermal anneal step on the polysilicon layer to activate (activate) the doped ions, for example by a Rapid Thermal Process (RTP) to a temperature of about 1000 degrees celsius for about 20 seconds. Step S109, optionally cleaning the polysilicon layer, for example, by using the above-mentioned high pressure water gun (scrubber), and step S110, optionally etching back the polysilicon layer. After the etch back step is completed, a floating gate structure (not shown) is formed on the substrate. These steps are prior art in the field and will not be described herein.

In addition, other steps may be subsequently performed to complete the semiconductor memory device. Such as forming other material layers (e.g., ONO structure and control gate, etc.) over the floating gate structure. Since these techniques belong to the prior art in the field, they will not be described in detail herein.

In an embodiment of the present invention, with reference to the above drawings and paragraphs, a method for fabricating a semiconductor device is provided, which includes providing a substrate 100, depositing a material layer (polysilicon layer 108) on the substrate 100, performing a planarization step P1 on the material layer, removing a portion of the material layer, performing an ion doping step P2 on the remaining material layer after the planarization step P1, and performing a cleaning step (SPM cleaning step P3, RCA cleaning step P4, high pressure water gun cleaning step S109), while removing impurities 109 generated after the planarization step P1 and impurities 109 generated after the ion doping step P2.

In one embodiment of the present invention, the material layer comprises a polysilicon layer 108.

In an embodiment of the present invention, the cleaning step includes a standard cleaning Step (SPM) P3, an RCA cleaning step P4, a high pressure water gun cleaning step (S109), and combinations thereof.

In one embodiment of the present invention, during the cleaning step, a thermal annealing step (S108) is performed.

In one embodiment of the present invention, the thermal annealing step (S108) is performed after the RCA cleaning step P4 and before the high pressure water gun cleaning step (S109).

In one embodiment of the present invention, the standard cleaning step P3 includes cleaning with a mixed solution of sulfuric acid, hydrogen peroxide and water.

In an embodiment of the present invention, the standard cleaning step P4 includes cleaning with a mixed solution of ammonia, hydrogen peroxide and water (also called SC1 cleaning), or a mixed solution of hydrochloric acid, hydrogen peroxide and water (also called SC2 cleaning).

In an embodiment of the present invention, no other steps are performed between performing the planarization step P1 and performing the ion doping step P2.

In an embodiment of the present invention, the method further comprises forming a plurality of shallow trench isolations 106 partially within the substrate 100, and a portion of the shallow trench isolations 106 protruding from a surface of the substrate.

In one embodiment of the present invention, the planarization step comprises a Chemical Mechanical Polishing (CMP) step.

In an embodiment of the present invention, before the Chemical Mechanical Polishing (CMP) step, another high pressure water gun cleaning step (S103) is performed to remove a plurality of particle impurities on the substrate.

In an embodiment of the invention, after the cleaning step, an etching back step (S110) is further performed on the material layer to remove a portion of the material layer, and the remaining material layer forms at least one floating gate structure on the substrate.

In one embodiment of the present invention, the material layer has a thickness of less than 1000 angstroms after the planarization step is performed.

The present invention is characterized in that when manufacturing the material layer (such as the polysilicon layer) of the floating gate, a planarization step is performed to reduce the thickness of the material layer, and then an ion doping step is performed to fully dope ions into the material layer. It is noted that the planarization step and the ion doping step generate unnecessary impurities, respectively, and the cleaning step is performed after the ion doping step, and the impurities generated in the planarization step and the ion doping step are removed, respectively, so as to save the steps.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.