阅读说明：本技术 一种大电容预充电路、系统及其控制方法 (Large-capacitor pre-charging circuit, system and control method thereof ) 是由 李丰军 周剑光 汪冬亮 王志伟 王君 于 2021-07-30 设计创作，主要内容包括：本发明涉及汽车技术领域,本发明提供了一种大电容预充电路、系统及其控制方法。该大电容预充电路包括至少一个一级预充电路；该一级预充电路包括第一晶体管、第二晶体管和第一限流电阻；该第一晶体管的基极与控制单元的第一控制端口连接,该第一晶体管的第一端与该第二晶体管的基极连接,该第一晶体管的第二端接地；该第二晶体管的第一端与该第一限流电路的第一端连接,该第二晶体管的第二端与电源连接；该第一限流电阻的第二端与电容集连接,以使该电源通过该一级预充电路对该电容集进行预充。从而使得基于本申请提供的预充电路对电容集充电能够有效降低电流冲击,提高器件的寿命的特点。(The invention relates to the technical field of automobiles, and provides a large-capacitor pre-charging circuit, a large-capacitor pre-charging system and a control method of the large-capacitor pre-charging system. The large-capacitor pre-charging circuit comprises at least one primary pre-charging circuit; the primary pre-charging circuit comprises a first transistor, a second transistor and a first current-limiting resistor; the base electrode of the first transistor is connected with a first control port of a control unit, the first end of the first transistor is connected with the base electrode of the second transistor, and the second end of the first transistor is grounded; the first end of the second transistor is connected with the first end of the first current limiting circuit, and the second end of the second transistor is connected with a power supply; the second end of the first current-limiting resistor is connected with the capacitor set, so that the power supply pre-charges the capacitor set through the primary pre-charging circuit. Therefore, the pre-charging circuit provided by the application can effectively reduce current impact when charging the capacitor set, and the service life of the device is prolonged.)

1. A large-capacitance pre-charging circuit is characterized by comprising at least one primary pre-charging circuit (1);

the primary pre-charging circuit (1) comprises a first transistor, a second transistor and a first current-limiting resistor;

the base electrode of the first transistor is connected with a first control port (2) of a control unit, the first end of the first transistor is connected with the base electrode of the second transistor, and the second end of the first transistor is grounded;

the first end of the second transistor is connected with the first end of the first current limiting circuit, and the second end of the second transistor is connected with a power supply (3);

the second end of the first current-limiting resistor is connected with a capacitor set (4) so that the power supply (3) can pre-charge the capacitor set (4) through the primary pre-charging circuit (1).

2. The large-capacitance pre-charging circuit according to claim 1, characterized in that the primary pre-charging circuit (1) further comprises a first resistor, a second resistor, a third resistor and a fourth resistor;

the first end of the first resistor is connected with the first control port (2), and the second end of the first resistor is connected with the base electrode of the first transistor;

a first end of the second resistor is connected with a second end of the first resistor, and a second end of the second resistor is connected with a second end of the first transistor;

a first end of the third resistor is connected with a first end of the first transistor, and a second end of the third resistor is connected with a base electrode of the second transistor;

a first end of the fourth resistor is connected to a second end of the third resistor, and a second end of the fourth resistor is connected to a second end of the second transistor.

3. The large-capacitance pre-charging circuit according to claim 1, characterized by comprising a first one-stage pre-charging circuit (101) and a second one-stage pre-charging circuit (102) which are connected in parallel;

the circuit structure of the first primary pre-charging circuit (101) is the same as that of the second primary pre-charging circuit (102);

the base electrode of a first transistor of the first primary pre-charging circuit (101) is connected with the first control port (2);

the base electrode of the first transistor of the second-stage pre-charging circuit (102) is connected with the second control port (6) of the control unit;

the resistance value of a first current-limiting resistor of the first primary pre-charging circuit (101) is larger than that of a first current-limiting resistor of the second primary pre-charging circuit (102), so that when the current in the large-capacitor pre-charging circuit is larger than the preset current, the first primary pre-charging circuit (101) is controlled to work through the first control port (2); otherwise, the second-stage pre-charging circuit (102) is controlled to work through the second control port (6).

4. Large capacitor pre-charge circuit according to claim 1, further comprising a secondary pre-charge circuit (5);

a first detection point is arranged on a line close to the second end of the second transistor; a second detection point is arranged on the capacitor set;

the secondary pre-charging circuit (5) comprises a first voltage regulator tube, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a second current-limiting resistor;

the cathode of the first voltage-regulator tube is connected with the first end of the second transistor, and the anode of the first voltage-regulator tube is connected with the first end of the third transistor;

the second end of the third transistor is connected with the base of the fourth transistor, and the base of the third transistor is connected with the capacitor set (4);

the first end of the fourth transistor is connected with the base electrode of the fifth transistor, and the second end of the fourth transistor is grounded;

the first end of the fifth transistor is connected with the first end of the second transistor, and the second end of the fifth transistor is connected with the capacitor set (4) through the second current-limiting resistor;

the base electrode of the sixth transistor is connected with the third control port of the control unit, the first end of the sixth transistor is connected with the base electrode of the fourth transistor, and the second end of the sixth transistor is grounded;

the resistance value of the second current-limiting resistor is smaller than that of the first current-limiting resistor, so that when the difference between the voltage of the first detection point and the voltage of the second detection point is smaller than a first preset threshold value, the first-stage pre-charging circuit (1) is controlled to work through the first control port (2), and the second-stage pre-charging circuit (5) is controlled to work through the third control port.

5. The large-capacitance pre-charging circuit according to claim 4, characterized by comprising a first MOS transistor, a second MOS transistor and an inductor which are connected in series in sequence;

the first MOS tube is connected with the power supply (3);

the inductor is connected with the capacitor set (4);

the first end of the fourth transistor is connected with the grid electrode of the first MOS tube, so that when the secondary pre-charging circuit (5) works, the fourth transistor can provide voltage for cutting off the first MOS tube.

6. The large-capacitance pre-charging circuit according to claim 5, wherein the secondary pre-charging circuit (5) comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor;

the first end of the fifth resistor is connected with the anode of the first voltage regulator tube, and the second end of the fifth resistor is connected with the base electrode of the third transistor;

a first end of the sixth resistor is connected with the base electrode of the third transistor, and a second end of the sixth resistor is connected with the capacitor set (4);

a first end of the seventh resistor is connected with a second end of the third transistor, and a second end of the seventh resistor is connected with a base of the fourth transistor;

a first end of the eighth resistor is connected with the base electrode of the fourth transistor, and a second end of the eighth resistor is grounded;

a first end of the ninth resistor is connected with a first end of the second transistor, and a second end of the ninth resistor is connected with a base electrode of the fifth transistor;

a first end of the tenth resistor is connected with a base electrode of the fifth transistor, and a second end of the tenth resistor is connected with a first end of the fourth transistor;

the third control port is connected to the sixth transistor through the eleventh resistor;

and the first end of the twelfth resistor is connected with the base electrode of the sixth transistor, and the second end of the twelfth resistor is grounded.

7. Large capacitor pre-charge circuit according to claim 5, characterized by comprising a three-stage pre-charge circuit (9);

the three-stage pre-charging circuit (9) comprises a seventh transistor, an eighth transistor, a second voltage regulator tube and a third current-limiting resistor;

the base electrode of the seventh transistor is connected with the first end of the eighth transistor, the first end of the seventh transistor is connected with the first end of the second transistor, and the second end of the seventh transistor is connected with the capacitor set (4) through the third current-limiting resistor;

the base electrode of the eighth transistor is connected with the anode of the second voltage regulator tube, and the second end of the eighth transistor is grounded;

the cathode of the voltage stabilizing tube is connected with the capacitor set (4);

the resistance value of the third current-limiting resistor is smaller than that of the second current-limiting resistor, so that when the difference between the voltage of the first detection point and the voltage of the second detection point is smaller than a second preset threshold value, and when the voltage of the second detection point is larger than a first voltage drop, and the first voltage drop is the difference between the voltage drop of the second voltage regulator tube and the voltage drop of the eighth transistor, the large-capacitor pre-charging circuit pre-charges the capacitor set (4) through the first-stage pre-charging circuit (1) and the third-stage pre-charging circuit (9).

8. The large capacitor pre-charge circuit according to claim 7, wherein the three-stage pre-charge circuit (9) further comprises a thirteenth resistor, a fourteenth resistor, a fifteenth resistor and a sixteenth resistor;

a first end of the thirteenth resistor is connected with the base of the eighth transistor, and a second end of the thirteenth resistor is grounded;

a first end of the fourteenth resistor is connected with a first end of the eighth transistor, and a second end of the fourteenth resistor is connected with a base of the seventh transistor;

a first end of the fifteenth resistor is connected with a first end of the second transistor, and a second end of the fifteenth resistor is connected with a base of the seventh transistor;

and the second voltage stabilizing tube is connected with the capacitor set through a sixteenth resistor.

9. Large capacitor pre-charge circuitry, characterized in that it comprises a power supply (3), a control unit and a large capacitor pre-charge circuit according to any of claims 1-8.

10. The control method of the large-capacitor pre-charging circuit is characterized by being applied to the large-capacitor pre-charging circuit, wherein the large-capacitor pre-charging circuit comprises at least one primary pre-charging circuit (1), and the primary pre-charging circuit (1) comprises a first transistor, a second transistor and a first current-limiting resistor; the base electrode of the first transistor is connected with a first control port (2) of the control unit, the first end of the first transistor is connected with the base electrode of the second transistor, and the second end of the first transistor is grounded; the first end of the second transistor is connected with the first end of the first current limiting circuit, and the second end of the second transistor is connected with a power supply (3); the second end of the first current limiting resistor is connected with a capacitor set (4); the method comprises the following steps:

-receiving a driving voltage of the first port and a voltage of the power supply (3);

controlling the first transistor and the second transistor to conduct based on the driving voltage of the first port and the voltage of the power supply (3) so that the power supply (3) pre-charges the capacitor set (4) through the primary pre-charging circuit (1).

Technical Field

The invention relates to the technical field of automobiles, in particular to a large-capacitor pre-charging circuit, a large-capacitor pre-charging system and a control method of the large-capacitor pre-charging system.

Background

The intelligent electric chassis is a key part of an automobile and is also a key development direction of the future automobile, and comprises three key independent execution parts, namely braking, steering and suspension. For example, the braking system is exemplified, the intelligent braking control system comprises a mechanical hydraulic component, an algorithm control unit and an electronic control unit, functional modules such as a motor drive, a vehicle stability control module, a double-control electronic parking brake module and the like are integrated, and the braking requirement of the whole vehicle above the L3 level can be met, wherein the electronic control unit is a link establishing the connection between the algorithm control module and the mechanical hydraulic component, is provided with key module circuits such as a power supply management module circuit, a motor drive module circuit, a valve drive module circuit and a signal processing module circuit, and aims at the power supply filtering processing of the motor drive, a large capacitor needs to be connected in parallel on a power supply circuit, as shown in figure 1, so that the power supply stability and the reliability of the circuit are improved.

Under the initial condition, the power input is 0, the charge capacity of the capacitor is 0, when the power is connected, due to the charging characteristic of the capacitor, the capacitor is equivalent to an instant short circuit at the moment of power connection, the current impact is large, and the service life of a preceding stage power device of the capacitor is shortened or the power device is damaged.

Disclosure of Invention

The invention aims to solve the technical problem of large current impact in the process of precharging a capacitor in the prior art.

To solve the above technical problem, the present application discloses in one aspect a large capacitor pre-charge circuit, which includes at least one primary pre-charge circuit;

the primary pre-charging circuit comprises a first transistor, a second transistor and a first current-limiting resistor;

the base electrode of the first transistor is connected with a first control port of a control unit, the first end of the first transistor is connected with the base electrode of the second transistor, and the second end of the first transistor is grounded;

the first end of the second transistor is connected with the first end of the first current limiting circuit, and the second end of the second transistor is connected with a power supply;

the second end of the first current-limiting resistor is connected with the capacitor set, so that the power supply pre-charges the capacitor set through the primary pre-charging circuit.

Optionally, the first-stage precharge circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor;

the first end of the first resistor is connected with the first control port, and the second end of the first resistor is connected with the base electrode of the first transistor;

the first end of the second resistor is connected with the second end of the first resistor, and the second end of the second resistor is connected with the second end of the first transistor;

the first end of the third resistor is connected with the first end of the first transistor, and the second end of the third resistor is connected with the base electrode of the second transistor;

the first end of the fourth resistor is connected with the second end of the third resistor, and the second end of the fourth resistor is connected with the second end of the second transistor.

Optionally, the first and second pre-charging circuits are connected in parallel;

the circuit structure of the first primary pre-charging circuit is the same as that of the second primary pre-charging circuit;

the base electrode of a first transistor of the first primary pre-charging circuit is connected with the first control port;

the base electrode of the first transistor of the second-stage pre-charging circuit is connected with the second control port of the control unit;

the resistance value of the first current-limiting resistor of the first primary pre-charging circuit is greater than that of the first current-limiting resistor of the second primary pre-charging circuit, so that when the current in the large-capacitor pre-charging circuit is greater than the preset current, the first primary pre-charging circuit is controlled to work through the first control port; otherwise, the second-stage pre-charging circuit is controlled to work through the second control port.

Optionally, the system further comprises a secondary pre-charging circuit;

a first detection point is arranged on the line close to the second end of the second transistor; a second detection point is arranged on the capacitor set;

the second-stage pre-charging circuit comprises a first voltage-regulator tube, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a second current-limiting resistor;

the cathode of the first voltage-regulator tube is connected with the first end of the second transistor, and the anode of the first voltage-regulator tube is connected with the first end of the third transistor;

the second end of the third transistor is connected with the base electrode of the fourth transistor, and the base electrode of the third transistor is connected with the capacitor set;

the first end of the fourth transistor is connected with the base electrode of the fifth transistor, and the second end of the fourth transistor is grounded;

a first end of the fifth transistor is connected with a first end of the second transistor, and a second end of the fifth transistor is connected with the capacitor set through the second current-limiting resistor;

the base of the sixth transistor is connected with the third control port of the control unit, the first end of the sixth transistor is connected with the base of the fourth transistor, and the second end of the sixth transistor is grounded;

the resistance value of the second current-limiting resistor is smaller than that of the first current-limiting resistor, so that when the difference between the voltage of the first detection point and the voltage of the second detection point is smaller than a first preset threshold value, the first-stage pre-charging circuit is controlled to work through the first control port, and the second-stage pre-charging circuit is controlled to work through the third control port.

Optionally, the MOS transistor comprises a first MOS transistor, a second MOS transistor and an inductor which are sequentially connected in series;

the first MOS tube is connected with the power supply;

the inductor is connected with the capacitor set;

the first end of the fourth transistor is connected with the grid electrode of the first MOS tube, so that when the secondary pre-charging circuit works, the fourth transistor can provide voltage for cutting off the first MOS tube.

Optionally, the second-stage precharge circuit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor;

the first end of the fifth resistor is connected with the anode of the first voltage regulator tube, and the second end of the fifth resistor is connected with the base electrode of the third transistor;

the first end of the sixth resistor is connected with the base electrode of the third transistor, and the second end of the sixth resistor is connected with the capacitor set;

a first end of the seventh resistor is connected with a second end of the third transistor, and a second end of the seventh resistor is connected with a base electrode of the fourth transistor;

the first end of the eighth resistor is connected with the base electrode of the fourth transistor, and the second end of the eighth resistor is grounded;

a first end of the ninth resistor is connected with the first end of the second transistor, and a second end of the ninth resistor is connected with the base of the fifth transistor;

a first end of the tenth resistor is connected with the base electrode of the fifth transistor, and a second end of the tenth resistor is connected with the first end of the fourth transistor;

the third control port is connected with the sixth transistor through the eleventh resistor;

the first end of the twelfth resistor is connected with the base electrode of the sixth transistor, and the second end of the twelfth resistor is grounded.

Optionally, a three-stage pre-charging circuit is included;

the three-stage pre-charging circuit comprises a seventh transistor, an eighth transistor, a second voltage regulator tube and a third current-limiting resistor;

the base of the seventh transistor is connected with the first end of the eighth transistor, the first end of the seventh transistor is connected with the first end of the second transistor, and the second end of the seventh transistor is connected with the capacitor set through the third current-limiting resistor;

the base electrode of the eighth transistor is connected with the anode of the second voltage regulator tube, and the second end of the eighth transistor is grounded;

the cathode of the voltage stabilizing tube is connected with the capacitor set;

the third current-limiting resistor has a resistance value smaller than that of the second current-limiting resistor, so that when the difference between the voltage of the first detection point and the voltage of the second detection point is smaller than a second preset threshold value, and when the voltage of the second detection point is larger than a first voltage drop, and the first voltage drop is the difference between the voltage drop of the second voltage regulator tube and the voltage drop of the eighth transistor, the large-capacitor pre-charging circuit pre-charges the capacitor set through the first-stage pre-charging circuit and the third-stage pre-charging circuit.

Optionally, the three-stage precharge circuit further includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, and a sixteenth resistor;

the first end of the thirteenth resistor is connected with the base of the eighth transistor, and the second end of the thirteenth resistor is grounded;

a first end of the fourteenth resistor is connected with a first end of the eighth transistor, and a second end of the fourteenth resistor is connected with a base of the seventh transistor;

a first end of the fifteenth resistor is connected with the first end of the second transistor, and a second end of the fifteenth resistor is connected with the base of the seventh transistor;

the second voltage stabilizing tube is connected with the capacitor set through a sixteenth resistor.

The application further discloses a large-capacitor pre-charging circuit system which comprises a power supply, a control unit and the large-capacitor pre-charging circuit.

The application also discloses a control method of the large-capacitor pre-charging circuit, which is applied to the large-capacitor pre-charging circuit, wherein the large-capacitor pre-charging circuit comprises at least one primary pre-charging circuit, and the primary pre-charging circuit comprises a first transistor, a second transistor and a first current-limiting resistor; the base electrode of the first transistor is connected with the first control port of the control unit, the first end of the first transistor is connected with the base electrode of the second transistor, and the second end of the first transistor is grounded; the first end of the second transistor is connected with the first end of the first current limiting circuit, and the second end of the second transistor is connected with a power supply; the second end of the first current limiting resistor is connected with the capacitor set; the method comprises the following steps:

receiving a driving voltage of the first port and a voltage of the power supply;

and controlling the first transistor and the second transistor to be conducted based on the driving voltage of the first port and the voltage of the power supply so that the power supply precharges the capacitor set through the primary precharging circuit.

By adopting the technical scheme, the large-capacitor pre-charging circuit provided by the application has the following beneficial effects:

the large-capacitor pre-charging circuit comprises at least one primary pre-charging circuit; the primary pre-charging circuit comprises a first transistor, a second transistor and a first current-limiting resistor; the base electrode of the first transistor is connected with a first control port of a control unit, the first end of the first transistor is connected with the base electrode of the second transistor, and the second end of the first transistor is grounded; the first end of the second transistor is connected with the first end of the first current limiting circuit, and the second end of the second transistor is connected with a power supply; the second end of the first current-limiting resistor is connected with the capacitor set, so that the power supply pre-charges the capacitor set through the primary pre-charging circuit. Compared with the technical scheme that the capacitor set is directly charged in the prior art, the transistor and the current-limiting resistor are arranged in the pre-charging circuit, so that the on and off of the circuit can be stably controlled, the impact of large current on the capacitor set can be effectively buffered under the action of the current-limiting resistor, and the service life of a device is prolonged.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a pre-charge circuit in the prior art;

FIG. 2 is a schematic diagram of a large capacitor pre-charge circuit according to an alternative embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a pre-charge circuit in the prior art;

FIG. 4 is a schematic diagram of a large capacitor pre-charge circuit according to another alternative embodiment of the present application;

FIG. 5 is a schematic diagram of a large capacitor pre-charge circuit according to another alternative embodiment of the present application;

FIG. 6 is a schematic diagram of a large capacitor pre-charge circuit according to another alternative embodiment of the present application;

FIG. 7 is a schematic diagram of a large capacitor pre-charge circuit according to another alternative embodiment of the present application;

fig. 8 is a schematic structural diagram of a large capacitor pre-charge circuit according to another alternative embodiment of the present application.

The following is a supplementary description of the drawings:

1-first stage pre-charge circuit; 101-a first one-stage pre-charge circuit; 102-a second stage precharge circuit; 5-a secondary pre-charge circuit; 6-a second control port; 7-a first fuse; 8-a second fuse; 9-a three-stage pre-charge circuit; 2-a first control port; 3-a power supply; 4-capacitance set.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.

Fig. 2 is a schematic structural diagram of a large capacitor pre-charge circuit according to an alternative embodiment of the present disclosure, as shown in fig. 2. The present application discloses in one aspect a large capacitor pre-charge circuit comprising at least one primary pre-charge circuit 1; the primary pre-charging circuit 1 comprises a first transistor Q1, a second transistor Q2 and a first current-limiting resistor Ra; the base of the first transistor Q1 is connected to the first control port 2 of the control unit, the first terminal of the first transistor Q1 is connected to the base of the second transistor Q2, and the second terminal of the first transistor Q1 is grounded; a first terminal of the second transistor Q2 is connected to a first terminal of the first current limiting circuit, and a second terminal of the second transistor Q2 is connected to a power supply 3; the second end of the first current limiting resistor Ra is connected to the capacitor set 4, so that the power supply 3 pre-charges the capacitor set 4 through the first stage pre-charging circuit 1. Optionally, the first transistor Q1 is an NPN transistor, the second transistor Q2 is a PNP transistor, and other types may be provided as needed, and the precharge circuit of the present application is provided with a plurality of transistors and a current-limiting resistor, so that the circuit can be stably controlled to be turned on and off, and under the effect of the current-limiting resistor, the impact of a large current on the capacitor set 4 can be effectively buffered, and the service life of the device is prolonged.

Although the circuit shown in fig. 3 is also used to precharge a large capacitor in the prior art, the circuit is controlled by a relay, that is, when the precharge is needed, the circuit is implemented by the relay, a resistor R, MOS (FET1 and FET2) and an inductor L1, but because the circuit is controlled by the relay, the circuit has the disadvantages of high cost, large occupied space and large mass, the relay occupies the layout space of the electronic control unit, and may meet the space requirement at the expense of performance.

Optionally, each electrode of each transistor and each electrode of the MOS transistor in the present application may be connected in the drawings, or may be connected in other ways as needed, as long as the effect of the precharge circuit in the present application can be achieved, which is not limited herein.

Optionally, the capacitor set 4 includes 6 capacitors connected in parallel, and certainly, according to needs, the number of capacitors may also be 4, 5, 7, and the like, which is not limited herein.

In an alternative embodiment, referring to fig. 4, fig. 4 is a schematic structural diagram of a large capacitor pre-charge circuit according to another alternative embodiment of the present application. The primary pre-charging circuit 1 further comprises a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; a first terminal of the first resistor R1 is connected to the first control port 2, and a second terminal of the first resistor R1 is connected to the base of the first transistor Q1; a first terminal of the second resistor R2 is connected to a second terminal of the first resistor R1, and a second terminal of the second resistor R2 is connected to a second terminal of the first transistor Q1; a first terminal of the third resistor R3 is connected to the first terminal of the first transistor Q1, and a second terminal of the third resistor R3 is connected to the base of the second transistor Q2; a first terminal of the fourth resistor R4 is connected to a second terminal of the third resistor R3, and a second terminal of the fourth resistor R4 is connected to a second terminal of the second transistor Q2.

Optionally, the circuit may also include only the first resistor R1 and the third resistor R3 for limiting current; the second resistor R2 and the fourth resistor R4 are used to provide a bias voltage for the corresponding parallel connected transistor, for example, the second resistor R2 provides a bias voltage for the first transistor Q1, and the fourth resistor R4 provides a bias voltage for the second transistor Q2.

Optionally, a first detection point AD1 is disposed on a line close to the second end of the second transistor Q2; the capacitor set 4 is provided with a second detection point AD 2.

It should be noted that the first current limiting resistor Ra may be formed by one resistor as shown in fig. 4, or may be formed by two resistors connected in parallel, as long as the resistance power can meet the preset requirement, and the second current limiting resistor Rb and the third current limiting resistor Rc are also referred to hereinafter, and this is not limited herein, and the current limiting resistor can also effectively improve the heat dissipation effect, thereby improving the system reliability. During initial charging, the voltage at the second detecting point AD2 is 0, the detecting voltage at the first detecting point AD1 is V1, and the maximum current during charging of the primary pre-charging circuit 1 is I_maxV1/Ra, where V1 is the voltage of the power supply 3 and Ra is the resistance of the first limiting resistor Ra; optionally, as the charging process continues to advance, the voltage of the AD2 gradually increases, so that the difference between the voltage of the AD2 and the voltage of the AD1 gradually decreases, and then it may be determined whether to start another pre-charging circuit based on the difference between the two voltages, which is described in detail below.

In an alternative embodiment, referring to fig. 5, fig. 5 is a schematic structural diagram of a large capacitor pre-charge circuit according to another alternative embodiment of the present application. The circuit comprises a first primary pre-charging circuit 101 and a second primary pre-charging circuit 102 which are connected in parallel; the circuit structure of the first one-stage pre-charge circuit 101 is the same as that of the second one-stage pre-charge circuit 102; the base of the first transistor Q1 of the first primary precharge circuit 101 is connected to the first control port 2; the base of the first transistor Q1 of the second-stage precharge circuit 102 is connected to the second control port 6 of the control unit; the resistance value of the first current-limiting resistor Ra of the first primary pre-charge circuit 101 is greater than the resistance value of the first current-limiting resistor Ra of the second primary pre-charge circuit 102, so that when the current in the large-capacitance pre-charge circuit is greater than the preset current, the first primary pre-charge circuit 101 is controlled to work through the first control port 2; otherwise, the second-stage precharge circuit 102 is controlled to operate through the second control port 6. Based on the circuit shown in fig. 5 of the present application, the charging current can be limited by flexibly adopting the current-limiting resistors with different resistance values according to different charging currents, so that the charging flexibility can be effectively improved, and the impact of a large current on the capacitor set 4 is avoided.

Optionally, the pre-charge circuit may also determine whether to charge based on the first primary pre-charge circuit 101 or the second primary pre-charge circuit 102 in advance based on the voltage of the power supply 3, and when the voltage of the power supply 3 is greater than a preset voltage, the charging may be based on the first primary pre-charge circuit 101.

If the fixed current-limiting resistor is used for charging control, the charging speed is gradually reduced along with the charging process along with the increase of the charging amount, and the quick charging requirement cannot be met. In order to avoid the above situation, the above circuit of the present application can also implement a segmented control of the current, that is, the charging current can be adjusted as needed, that is, when the charging is just started, the capacitor set 4 can be precharged based on the first primary precharge circuit 101, and when the voltage at the second detection point AD2 reaches the preset threshold value or the current in the circuit is smaller than the preset threshold value or the difference between the voltage at the first detection point AD1 and the voltage at the second detection point AD2 is smaller than a third preset threshold value, the first primary precharge circuit 101 can be turned off, and the second primary precharge circuit 102 is turned on, so that the charging rate can be increased.

Certainly, the number of the first-stage precharge circuits 1 may be two, and the first-stage precharge circuits 1 may further include N first-stage precharge circuits 1 such as a third-stage precharge circuit 1 and a fourth-stage precharge circuit 1, where N is an integer greater than or equal to 5, and the resistances of the first current-limiting resistors Ra in the N first-stage precharge circuits 1 are all different, so as to meet the requirements of different charging rates and charging currents.

In an alternative embodiment, as shown in fig. 6, fig. 6 is a schematic structural diagram of a large capacitor pre-charge circuit in another alternative embodiment of the present application. The circuit also includes a secondary pre-charge circuit 5; the secondary pre-charging circuit 5 comprises a first voltage regulator tube Z1, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6 and a second current-limiting resistor Rb; the cathode of the first regulator tube Z1 is connected to the first end of the second transistor Q2, and the anode of the first regulator tube Z1 is connected to the first end of the third transistor Q3; a second terminal of the third transistor Q3 is connected to the base of the fourth transistor Q4, and the base of the third transistor Q3 is connected to the capacitor set 4; a first terminal of the fourth transistor Q4 is connected to the base of the fifth transistor Q5, and a second terminal of the fourth transistor Q4 is grounded; a first terminal of the fifth transistor Q5 is connected to the first terminal of the second transistor Q2, and a second terminal of the fifth transistor Q5 is connected to the capacitor set 4 through the second current limiting resistor Rb; the base of the sixth transistor Q6 is connected to the third control port of the control unit, the first terminal of the sixth transistor Q6 is connected to the base of the fourth transistor Q4, and the second terminal of the sixth transistor Q6 is connected to ground; the resistance of the second current-limiting resistor Rb is smaller than the resistance of the first current-limiting resistor Ra, so that when the difference between the voltage at the first detection point AD1 and the voltage at the second detection point AD2 is smaller than a first preset threshold, the first control port 2 controls the first-stage pre-charge circuit 1 to operate, and the third control port controls the second-stage pre-charge circuit 5 to operate. Optionally, the circuit shown in fig. 6 may be controlled as needed, and optionally, when the current is large, in order to reduce the impact of the large current, the first control port 2 and the second control port 6 may be simultaneously driven to open the corresponding transistors, that is, the first-stage precharge circuit 1 and the second-stage precharge circuit 5 operate simultaneously; optionally, the voltage output by the second control port 6 may be set to a default level for turning on the sixth transistor Q6, so as to simplify the control process; optionally, according to needs, only when the current in the pre-charge circuit is smaller than the preset threshold, the second control port 6 is enabled to output a low level, and the sixth transistor Q6 is controlled to be turned on, so that the secondary pre-charge circuit 5 operates.

Optionally, the third transistor Q3 is a PNP transistor, the fourth transistor Q4 is an NPN transistor, and the fifth transistor Q4 is an NPN transistorThe transistor Q5 is a PNP transistor, and the sixth transistor Q6 is an NPN transistor, which may be configured in other types as needed. Referring to fig. 6, when the first-stage pre-charge circuit 1 and the second-stage pre-charge circuit 5 operate simultaneously, the maximum current during the charging process in the circuit is I_maxWhere V1 is the voltage of the power supply 3, VAD2 is the voltage of the second detection point, and Rb is the resistance of the second current limiting resistor Rb, (V1-VAD2)/Ra + (V1-VAD 2)/Rb.

In an alternative embodiment, as shown in fig. 7, fig. 7 is a schematic structural diagram of a large capacitor pre-charge circuit in another alternative embodiment of the present application. The large-capacitance pre-charging circuit comprises a first MOS transistor FET1, a second MOS transistor FET2 and an inductor L1 which are sequentially connected in series; the first MOS FET1 is connected to the power supply 3; the inductor L1 is connected to the capacitor set 4; the first terminal of the fourth transistor Q4 is connected to the base of the first mosfet FET1, so that when the secondary precharge circuit 5 is operating, the fourth transistor Q4 can provide a voltage to turn off the first MOS FET1, so that when the voltage difference between VAD2 and VAD3 at capacitor set 4 in the circuit is greater than a preset threshold, where VAD3 is the voltage at AD3, i.e. when the current in the precharge circuit is still large, since the fourth transistor Q4 is connected to the base of the first MOS FET1, it can provide a turn-off level, when the AD4 voltage does not reach the voltage at which the secondary precharge control module stops operating, if there is an unexpected level to open the first MOS FET1, at this time, the V2 will directly charge the capacitors C1-C6 through the first MOS FET1, the second MOS FETs 2, L1, thereby generating a current surge, and since the secondary precharge circuit 5 is operating, the fourth transistor Q4 is turned on, and the control terminal of the first mosfet 1 can be forced to be at a low level by the dashed line in fig. 7, so that when the first mosfet 1 receives an unexpected control level, the first mosfet 1 is forced to be turned off by the second stage precharge control module, and no current surge is generated; the circuit design of the hardware fault tolerance mechanism can effectively improve the stability of the circuit.

Optionally, referring to fig. 7, the large-capacitance precharge circuit further includes a third MOS transistor FET3, a first terminal of the third MOS transistor FET3 is connected to the power supply 3, a second terminal of the third MOS transistor FET3 is connected to a second terminal of the second transistor Q2, and a base of the third MOS transistor FET3 is connected to the driving circuit, so as to improve the application range of the circuit.

Optionally, as shown in fig. 7, the large-capacitance precharge circuit further includes a first fuse 7 and a second fuse 8, where the first fuse 7 is located between the third MOS FET3 and the power supply 3, and the second fuse 8 is located between the power supply 3 and the first MOS FET1, so as to avoid a situation that a large current impacts the precharge circuit due to situations such as instability of the power supply 3, and improve stability of the precharge circuit.

Optionally, the circuit further includes reverse connection prevention diodes, each MOS transistor is connected in parallel with one diode, and the diode may be a body diode or a separate device, and has a reverse connection prevention function.

In an alternative embodiment, referring to fig. 6, the secondary pre-charge circuit 5 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12; a first end of the fifth resistor R5 is connected to the anode of the first regulator tube Z1, and a second end of the fifth resistor R5 is connected to the base of the third transistor Q3; a first end of the sixth resistor R6 is connected to the base of the third transistor Q3, and a second end of the sixth resistor R6 is connected to the capacitor set 4; a first terminal of the seventh resistor R7 is connected to the second terminal of the third transistor Q3, and a second terminal of the seventh resistor R7 is connected to the base of the fourth transistor Q4; a first terminal of the eighth resistor R8 is connected to the base of the fourth transistor Q4, and a second terminal of the eighth resistor R8 is grounded; a first terminal of the ninth resistor R9 is connected to the first terminal of the second transistor Q2, and a second terminal of the ninth resistor R9 is connected to the base of the fifth transistor Q5; a first terminal of the tenth resistor R10 is connected to the base of the fifth transistor Q5, and a second terminal of the tenth resistor R10 is connected to the first terminal of the fourth transistor Q4; the third control port is connected to the sixth transistor Q6 through the eleventh resistor R11; a first end of the twelfth resistor R12 is connected to the base of the sixth transistor Q6, and a second end of the twelfth resistor R12 is grounded. Optionally, the sixth resistor R6, the seventh resistor R7, the tenth resistor R10 and the eleventh resistor R11 function to limit current; the fifth resistor R5, the eighth resistor R8, the ninth resistor R9 and the twelfth resistor R12 are used for providing bias voltage for the corresponding connected triodes in parallel.

It should be noted that, the secondary pre-charge circuit 5 may be provided with a plurality of sub-secondary pre-charge circuits according to needs, the sub-secondary pre-charge circuits are connected in parallel, the basic structure of each circuit of the sub-secondary pre-charge circuit is the same, and the resistance of the resistor in the circuit can be adaptively changed according to needs, but the resistance of the second current resistor of each circuit in the sub-secondary pre-charge circuits connected in parallel is different, so as to be convenient for adapting to the currents of different pre-charge circuits; optionally, each sub-secondary pre-charging circuit does not work at the same time, and the working state of the sub-secondary pre-charging circuit can be controlled by controlling the level of the corresponding second control port 6 according to the requirement.

Optionally, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are a PNP triode, an NPN triode, a PNP triode, and an NPN triode, respectively, and may be set to other types as needed. When the first-stage precharge circuit 1 and the second-stage precharge circuit 5 operate simultaneously (see fig. 6), the maximum current during charging in the circuit is I_max(V1-VAD2)/Ra + (V1-VAD2)/Rb, where V1 is the voltage of the power supply 3, VAD2 is the voltage of the second detection point AD2, Rb is the resistance of the second current limiting resistor Rb, and when the circuit is the circuit shown in fig. 7, the maximum current during charging in the circuit is I_max(V1- Δ V1-VAD2)/Ra + (V1- Δ V1-VAD2)/Rb, where Δ V1 is the voltage drop across the third MOS transistor FET 3.

Optionally, referring to fig. 7, when the difference between the voltage at AD3 and the voltage at AD2 is smaller than the difference between the voltage at the first regulator tube Z1 and the voltage drop at the third transistor Q3, the first regulator tube Z1 is turned off, so that the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 are turned off, that is, the second-stage pre-charge circuit 5 stops operating, at this time, the pre-charge circuit may charge the capacitor set 4 through the first-stage pre-charge circuit 1, for example, the output voltage of the power supply 3 is 12V, and when the difference between the voltage at AD3 and the voltage at AD2 is smaller than 5V, the second-stage pre-charge circuit 5 stops operating.

In an alternative embodiment, as shown in fig. 8, a schematic structural diagram of a large capacitor pre-charge circuit in another alternative embodiment of the present application is shown. In order to further simplify the control of the circuit while ensuring the charging efficiency, the pre-charging circuit comprises a three-stage pre-charging circuit 9; the three-stage precharging circuit 9 comprises a seventh transistor Q7, an eighth transistor Q8, a second voltage regulator tube Z2 and a third current-limiting resistor Rc; the base of the seventh transistor Q7 is connected to the first terminal of the eighth transistor Q8, the first terminal of the seventh transistor Q7 is connected to the first terminal of the second transistor Q2, and the second terminal of the seventh transistor Q7 is connected to the capacitor set 4 through the third current limiting resistor Rc; the base of the eighth transistor Q8 is connected to the anode of the second regulator tube Z2, and the second terminal of the eighth transistor Q8 is grounded; the cathode of the voltage stabilizing tube is connected with the capacitor set 4; the resistance of the third current-limiting resistor Rc is smaller than that of the second current-limiting resistor Rb, so that when the difference between the voltage at the first detection point AD1 and the voltage at the second detection point AD2 is smaller than a second preset threshold, and when the voltage at the second detection point AD2 is larger than a first voltage drop, which is the difference between the voltage drop at the second voltage regulator tube Z2 and the voltage drop at the eighth transistor Q8, the large-capacitance precharging circuit precharges the capacitor set 4 through the first-stage precharging circuit 1 and the third-stage precharging circuit 9, and since the voltage at the second detection point AD2 is larger than the first voltage drop, the eighth transistor Q8 is turned on, so that the seventh transistor Q7 is turned on, and at this time, the V1 output by the precharging circuit can charge the capacitor set 4 through the third MOS transistor 3, the second transistor Q2, the seventh transistor Q7 and the third current-limiting resistor Rc; optionally, in the precharging process, the capacitor set 4 may be charged through the first-stage precharging circuit 1 and the third-stage precharging circuit 9, so that the charging efficiency is improved.

Optionally, when the pre-charge circuit is the circuit shown in fig. 8, the pre-charge circuit includes a first-stage pre-charge circuit, a second-stage pre-charge circuit and a third-stage pre-charge circuit; when the current in the circuit is I1, the pre-charging circuit can charge the capacitor set based on the primary pre-charging circuit and the secondary pre-charging circuit; when the current in the circuit is I2, the pre-charging circuit can charge the capacitor set based on the first-stage pre-charging circuit and the third-stage pre-charging circuit; of course, since the three-stage precharge circuit may include N sub-precharge circuits connected In parallel, when the current In the circuit is In, the precharge circuit may charge the capacitor set based on the one-stage precharge circuit and the nth sub-precharge circuit, where I1< I2< … … < In; n is an integer of 3 or more; n is an integer greater than or equal to 2; the pre-charging circuit realizes multi-section controllability of pre-charging current by combining devices such as a voltage stabilizing tube, a current limiting resistor, a triode and the like, and meets the requirements of different charging speeds; and the voltage difference between the voltage V1 of the input power supply and the VAD2 of the capacitor collector voltage is used as the input of the pre-charging circuit, so that the voltage fluctuation can be automatically adapted, and the sensitivity of the pre-charging device is improved.

In an alternative embodiment, the three-stage precharge circuit 9 further includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a sixteenth resistor R16; a first end of the thirteenth resistor R13 is connected to the base of the eighth transistor Q8, and a second end of the thirteenth resistor R13 is grounded; a first terminal of the fourteenth resistor R14 is connected to the first terminal of the eighth transistor Q8, and a second terminal of the fourteenth resistor R14 is connected to the base of the seventh transistor Q7; a first end of the fifteenth resistor R15 is connected to the first end of the second transistor Q2, and a second end of the fifteenth resistor R15 is connected to the base of the seventh transistor Q7; the second zener diode Z2 is connected to the capacitor set 4 through a sixteenth resistor R16. Optionally, the fourteenth resistor R14 and the sixteenth resistor R16 function to limit current; the thirteenth resistor R13 and the fifteenth resistor R15 are used to provide bias voltage for the corresponding parallel connected transistor.

It should be noted that, the three-stage pre-charge circuit 9 may be provided with a plurality of sub-three-stage pre-charge circuits according to needs, the sub-three-stage pre-charge circuits are connected in parallel, the basic structure of the circuit of each sub-three-stage pre-charge circuit is the same, and the resistance value of the resistor in the circuit can be adaptively changed according to needs, but the resistance values of the third current-limiting resistors of each circuit in the sub-three-stage pre-charge circuits connected in parallel are different, so as to be convenient for adapting to the currents of different pre-charge circuits; optionally, each sub-three-stage precharge circuit does not operate at the same time, and according to needs, the operating state of the sub-three-stage precharge circuit may be controlled by configuring different performances of the transistor, the voltage regulator and the resistor in the three-stage precharge circuit, for example, the resistance values of the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15 and the sixteenth resistor R16, or the voltage drop of the voltage regulator and the voltage drop of the transistor are changed.

Optionally, the seventh transistor Q7 and the eighth transistor Q8 are a PNP transistor and an NPN transistor, respectively, and may be set to other types as needed. When the first-stage precharge circuit 1 and the third-stage precharge circuit 9 operate simultaneously (see fig. 8), the maximum current during charging in the circuit is I_max(V1- Δ V1-VAD2)/Ra + (V1- Δ V1-VAD2)/Rc, wherein Rc is the resistance of the third current limiting resistor Rc.

It should be noted that, when the pre-charging circuit according to any of the above embodiments is adopted, when the voltage at the AD2 reaches a certain limit, the pre-charging process is completed, and at this time, the output of the first control port 2 turns off the level of the first transistor Q1, which may be a low level, so as to turn off the one-stage pre-charging circuit 1. Optionally, the above-mentioned determining the type of starting the precharge circuit by monitoring the voltages of the first detection point AD1 and the second detection point AD2 may be adopted in the present application, that is, the first-stage precharge circuit 1 and the second-stage precharge circuit 5, the first-stage precharge circuit 1 and the third-stage precharge circuit 9, and the like, and of course, the present application may also determine the type of starting the precharge circuit by monitoring the current value in the large-capacitance precharge circuit; optionally, when the current in the pre-charge circuit is greater than the first preset current, the capacitor set may be pre-charged based on the first-stage pre-charge circuit 1 and the second-stage pre-charge circuit 5, and when the current in the pre-charge circuit is greater than the second pre-charge current and is less than the first preset current, the capacitor set may be pre-charged based on the first-stage pre-charge circuit 1 and the first sub-third-stage pre-charge circuit; when the current in the pre-charging circuit is greater than the third pre-charging current and less than the second preset current, the capacitor set can be pre-charged based on the first-stage pre-charging circuit 1 and the second sub-third pre-charging circuit, and so on, and when the current in the pre-charging circuit is greater than the mth pre-charging current and less than the mth-1 preset current, the capacitor set can be pre-charged based on the first-stage pre-charging circuit 1 and the M-1 sub-third pre-charging circuit, where M is an integer greater than or equal to 4; the first predetermined current is greater than the second predetermined current, and so on, the M-1 th predetermined current is greater than the M-th predetermined charging current.

The application also discloses a large-capacitor pre-charging circuit system which comprises a power supply 3, a control unit and the large-capacitor pre-charging circuit; the pre-charging circuit system can effectively reduce the impact of large current on the capacitor set 4, improves the stability of the circuit and reduces the cost.

The application also discloses a control method of the large-capacitor pre-charging circuit, which is applied to the large-capacitor pre-charging circuit, wherein the large-capacitor pre-charging circuit comprises at least one primary pre-charging circuit 1, and the primary pre-charging circuit 1 comprises a first transistor Q1, a second transistor Q2 and a first current-limiting resistor Ra; the base of the first transistor Q1 is connected to the first control port 2 of the control unit, the first terminal of the first transistor Q1 is connected to the base of the second transistor Q2, and the second terminal of the first transistor Q1 is grounded; a first terminal of the second transistor Q2 is connected to a first terminal of the first current limiting circuit, and a second terminal of the second transistor Q2 is connected to a power supply 3; the second end of the first current limiting resistor Ra is connected with the capacitor set 4; the method comprises the following steps: receiving a driving voltage of the first port and a voltage of the power supply 3; the first transistor Q1 and the second transistor Q2 are controlled to be turned on based on the driving voltage of the first port and the voltage of the power source 3, so that the power source 3 precharges the capacitor set 4 through the first stage precharge circuit 1.

Optionally, the control method may also be based on the precharge circuit shown in fig. 4 to 8, and the specific control process refers to the description of the embodiment of the large-capacitance precharge circuit, which is not described herein again.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.