阅读说明：本技术 图像感测设备 (Image sensing apparatus ) 是由 黄元锡 于 2021-01-18 设计创作，主要内容包括：一种图像感测设备包括第一在前比较器和第二在前比较器以及第一在后比较器和第二在后比较器。第一在前比较器基于第一像素信号和斜坡信号生成第一在前比较信号。第一在后比较器在第一比较前提下执行将第一在前比较信号与第一参考信号进行比较的第一比较,并且生成与第一比较的结果对应的第一在后比较信号。第二在前比较器基于第二像素信号和斜坡信号生成第二在前比较信号。第二在后比较器在不同于第一比较前提的第二比较前提下,执行将第二在前比较信号与第二参考信号进行比较的第二比较。第二在后比较器生成与第二比较的结果对应的第二在后比较信号。(An image sensing apparatus includes first and second preceding comparators and first and second following comparators. The first previous comparator generates a first previous comparison signal based on the first pixel signal and the ramp signal. The first post comparator performs a first comparison comparing the first preceding comparison signal with the first reference signal on the first comparison premise, and generates a first post comparison signal corresponding to a result of the first comparison. The second previous comparator generates a second previous comparison signal based on the second pixel signal and the ramp signal. The second post comparator performs a second comparison comparing the second prior comparison signal with a second reference signal on a second comparison premise different from the first comparison premise. The second subsequent comparator generates a second subsequent comparison signal corresponding to a result of the second comparison.)

1. An image sensing apparatus, comprising:

a first previous comparator adapted to generate a first previous comparison signal based on the first pixel signal and the ramp signal;

a first subsequent comparator adapted to perform a first comparison comparing the first previous comparison signal with a first reference signal on a first comparison premise and to generate a first subsequent comparison signal corresponding to a result of the first comparison;

a second previous comparator adapted to generate a second previous comparison signal based on a second pixel signal and the ramp signal; and

a second post comparator adapted to perform a second comparison comparing the second preceding comparison signal with a second reference signal on a second comparison premise different from the first comparison premise, and adapted to generate a second post comparison signal corresponding to a result of the second comparison.

2. The image sensing device of claim 1, wherein:

the first comparison precondition includes a condition for initializing an input terminal to which the first previous comparison signal is input to a first voltage level,

the second comparison precondition includes a condition for initializing the input terminal to which the second previous comparison signal is input to a second voltage level, which is different from the first voltage level.

3. The image sensing device of claim 2, wherein

The first voltage level corresponds to a voltage level of the first reference signal that is adjusted during an initialization time, an

The second voltage level corresponds to a voltage level of the second reference signal that is adjusted during the initialization time.

4. The image sensing device of claim 1, wherein

The first comparison precondition comprises a condition for adjusting a voltage level of the first reference signal to a first voltage level,

the second comparison precondition comprises a condition for adjusting a voltage level of the second reference signal to a second voltage level, the second voltage level being different from the first voltage level.

5. The image sensing device of claim 1, wherein the first and second prior comparators operate on the same comparison premise.

6. The image sensing device of claim 1, further comprising:

a first sampling circuit coupled to the first subsequent comparator and adapted to sample the first reference signal; and

a second sampling circuit coupled to the second subsequent comparator and adapted to sample the second reference signal.

7. The image sensing device of claim 1, wherein the first subsequent comparator generates and adjusts the first reference signal by self-generation based on a first control code signal.

8. The image sensing device of claim 1, wherein the first subsequent comparator comprises:

an input circuit adapted to receive the first pixel signal and the first reference signal;

a loading circuit coupled between the input circuit and a first voltage terminal;

a first current source coupled between the input circuit and a second voltage terminal and adapted to generate a first current corresponding to a voltage level of the first reference signal; and

a second current source coupled between the input circuit and the second voltage terminal and adapted to generate a first adjustment current based on a first control code signal, the first adjustment current for adjusting the voltage level of the first reference signal.

9. The image sensing device of claim 1, wherein the second subsequent comparator generates and adjusts the second reference signal by self-generation based on a second control code signal.

10. The image sensing device of claim 1, wherein the second post comparator comprises:

an input circuit adapted to receive the second pixel signal and the second reference signal;

a loading circuit coupled between the input circuit and a first voltage terminal;

a first current source coupled between the input circuit and a second voltage terminal and adapted to generate a second current corresponding to a voltage level of the second reference signal; and

a second current source coupled between the input circuit and the second voltage terminal and adapted to generate a second regulation current based on a second control code signal, the second regulation current for regulating the voltage level of the second reference signal.

11. An image sensing apparatus, comprising:

a first previous comparator configured to be initialized during an initialization time and adapted to generate a first previous comparison signal based on the first pixel signal and the ramp signal during a row time;

a first post comparator adapted to initialize a first input terminal to a first voltage level and a first sub input terminal to a default voltage level during the initialization time, and adapted to generate a first post comparison signal based on the first previous comparison signal input through the first input terminal and a first reference signal input through the first sub input terminal during the line time;

a second previous comparator configured to be initialized during the initialization time and adapted to generate a second previous comparison signal based on a second pixel signal and the ramp signal during the line time; and

a second post comparator adapted to initialize a second input terminal to a second voltage level different from the first voltage level and a second sub input terminal to the default voltage level during the initialization time, and adapted to generate a second post comparison signal based on the second previous comparison signal input through the second input terminal and a second reference signal input through the second sub input terminal during the line time.

12. The image sensing device of claim 11, further comprising:

a first sampling circuit coupled to the first subsequent comparator and adapted to sample the first reference signal; and

a second sampling circuit coupled to the second subsequent comparator and adapted to sample the second reference signal.

13. The image sensing device of claim 11, wherein

The first subsequent comparator generates and adjusts the first reference signal by self-generation based on a first control code signal, an

The second subsequent comparator generates and adjusts the second reference signal by self-generation based on a second control code signal.

14. The image sensing device of claim 11, wherein the first subsequent comparator comprises:

an input circuit adapted to receive the first pixel signal and the first reference signal;

a loading circuit coupled between the input circuit and a first voltage terminal;

a first current source coupled between the input circuit and a second voltage terminal and adapted to generate a first current corresponding to a voltage level of the first reference signal; and

a second current source coupled between the input circuit and the second voltage terminal and adapted to generate a first adjustment current based on a first control code signal, the first adjustment current for adjusting the voltage level of the first reference signal.

15. The image sensing device of claim 11, wherein the second post comparator comprises:

an input circuit adapted to receive the second pixel signal and the second reference signal;

a loading circuit coupled between the input circuit and a first voltage terminal;

a first current source coupled between the input circuit and a second voltage terminal and adapted to generate a second current corresponding to a voltage level of the second reference signal; and

a second current source coupled between the input circuit and the second voltage terminal and adapted to generate a second regulation current based on a second control code signal, the second regulation current for regulating the voltage level of the second reference signal.

16. An image sensing apparatus, comprising:

a first previous comparator initialized during an initialization time and adapted to generate a first previous comparison signal based on the first pixel signal and the ramp signal during a row time;

a first post comparator adapted to adjust a voltage level of a first reference signal to a first voltage level during the initialization time and to generate a first post comparison signal based on the first prior comparison signal and the first reference signal during the line time;

a second previous comparator initialized during the initialization time and adapted to generate a second previous comparison signal based on a second pixel signal and the ramp signal during the line time; and

a second post comparator adapted to adjust a voltage level of a second reference signal to a second voltage level different from the first voltage level during the initialization time, and adapted to generate a second post comparison signal based on the second prior comparison signal and the second reference signal during the line time.

17. The image sensing device of claim 16, further comprising:

a first sampling circuit coupled to the first subsequent comparator and adapted to sample the first reference signal; and

a second sampling circuit coupled to the second subsequent comparator and adapted to sample the second reference signal.

18. The image sensing device of claim 16, wherein

The first subsequent comparator generates and adjusts the first reference signal by self-generation based on a first control code signal, an

The second subsequent comparator generates and adjusts the second reference signal by self-generation based on a second control code signal.

19. The image sensing device of claim 16, wherein the first subsequent comparator comprises:

an input circuit adapted to receive the first pixel signal and the first reference signal;

a loading circuit coupled between the input circuit and a first voltage terminal;

a first current source coupled between the input circuit and a second voltage terminal and adapted to generate a first current corresponding to a voltage level of the first reference signal; and

a second current source coupled between the input circuit and the second voltage terminal and adapted to generate a first adjustment current based on a first control code signal, the first adjustment current for adjusting the voltage level of the first reference signal.

20. The image sensing device of claim 16, wherein the second post comparator comprises:

an input circuit adapted to receive the second pixel signal and the second reference signal;

a loading circuit coupled between the input circuit and a first voltage terminal;

a first current source coupled between the input circuit and a second voltage terminal and adapted to generate a second current corresponding to a voltage level of the second reference signal; and

a second current source coupled between the input circuit and the second voltage terminal and adapted to generate a second regulation current based on a second control code signal, the second regulation current for regulating the voltage level of the second reference signal.

21. A method for controlling an image sensing device, the method comprising:

generating a first previous comparison signal based on the first pixel signal and the ramp signal;

on a first comparison premise, performing a first comparison comparing the first prior comparison signal with a first reference signal;

generating a first subsequent comparison signal corresponding to a result of the first comparison;

generating a second previous comparison signal based on a second pixel signal and the ramp signal;

performing a second comparison comparing the second prior comparison signal with a second reference signal on a second comparison premise different from the first comparison premise; and

generating a second subsequent comparison signal corresponding to a result of the second comparison.

Technical Field

One or more embodiments described herein relate to an image sensing apparatus.

Background

The image sensing device may capture an image based on semiconductor characteristics that react to light. Image sensing devices may be broadly classified into a Charge Coupled Device (CCD) image sensing device and a Complementary Metal Oxide Semiconductor (CMOS) image sensing device. CMOS image sensing devices are widely used because they can allow both analog and digital control circuits to be implemented directly on a single Integrated Circuit (IC).

Disclosure of Invention

Various embodiments of the present disclosure relate to an image sensing apparatus that minimizes the influence of a dropped source power.

According to one embodiment, an image sensing apparatus may include: a first previous comparator adapted to generate a first previous comparison signal based on the first pixel signal and the ramp signal; a first post comparator adapted to compare the first pre-comparison signal with the first reference signal on a first comparison premise and to generate a first post-comparison signal corresponding to a comparison result; a second previous comparator adapted to generate a second previous comparison signal based on the second pixel signal and the ramp signal; and a second post comparator adapted to compare the second previous comparison signal with a second reference signal on a second comparison premise different from the first comparison premise, and adapted to generate a second post comparison signal corresponding to a comparison result.

The first comparison precondition may include a condition for initializing an input terminal to which a first previous comparison signal is input to a first voltage level, and the second comparison precondition may include a condition for initializing an input terminal to which a second previous comparison signal is input to a second voltage level, the second voltage level being different from the first voltage level.

The first comparison precondition may include a condition for adjusting a voltage level of the first reference signal to a first voltage level, and the second comparison precondition may include a condition for adjusting a voltage level of the second reference signal to a second voltage level, the second voltage level being different from the first voltage level.

The first preceding comparator and the second preceding comparator may operate on the same comparison premise.

According to one embodiment, an image sensing apparatus may include: a first previous comparator initialized during an initialization time and adapted to generate a first previous comparison signal based on the first pixel signal and the ramp signal during a row time; a first post comparator adapted to initialize the first input terminal to a first voltage level and the first sub input terminal to a default voltage level during an initialization time, and adapted to generate a first post comparison signal based on a first previous comparison signal input through the first input terminal and a first reference signal input through the first sub input terminal during a row time; a second previous comparator initialized during an initialization time and adapted to generate a second previous comparison signal based on the second pixel signal and the ramp signal during the row time; and a second post comparator adapted to initialize the second input terminal to a second voltage level different from the first voltage level and the second sub input terminal to a default voltage level during the initialization time, and adapted to generate a second post comparison signal based on a second previous comparison signal input through the second input terminal and a second reference signal input through the second sub input terminal during the line time.

The image sensing apparatus may further include: a first sampling circuit coupled to the first following comparator and adapted to sample a first reference signal; and a second sampling circuit coupled to the second subsequent comparator and adapted to sample a second reference signal.

The first subsequent comparator may generate and adjust the first reference signal by self-generation based on the first control code signal, and the second subsequent comparator may generate and adjust the second reference signal by self-generation based on the second control code signal.

According to one embodiment, an image sensing apparatus may include: a first previous comparator initialized during an initialization time and adapted to generate a first previous comparison signal based on the first pixel signal and the ramp signal during a row time; a first post comparator adapted to adjust a voltage level of the first reference signal to a first voltage level during an initialization time and to generate a first post comparison signal based on a first preceding comparison signal and the first reference signal during a line time; a second previous comparator initialized during an initialization time and adapted to generate a second previous comparison signal based on the second pixel signal and the ramp signal during the row time; and a second subsequent comparator adapted to adjust a voltage level of the second reference signal to a second voltage level different from the first voltage level during the initialization time, and adapted to generate a second subsequent comparison signal based on a second previous comparison signal and the second reference signal during the row time.

The image sensing apparatus may further include: a first sampling circuit coupled to the first following comparator and adapted to sample a first reference signal; and a second sampling circuit coupled to the second subsequent comparator and adapted to sample a second reference signal.

The first subsequent comparator may generate and adjust the first reference signal by self-generation based on the first control code signal, and the second subsequent comparator may generate and adjust the second reference signal by self-generation based on the second control code signal.

Drawings

FIG. 1 illustrates one embodiment of an image sensing device.

Fig. 2 shows an embodiment of a signal converter.

Fig. 3 shows one embodiment of a first comparison circuit in the first signal converter.

FIG. 4 illustrates one embodiment of a first late comparator.

Fig. 5 shows an embodiment of a first comparison circuit in the second signal converter.

FIG. 6 illustrates one embodiment of a first late comparator.

Fig. 7 shows an embodiment of a first comparison circuit in a third signal converter.

FIG. 8 illustrates one embodiment of a first late comparator.

FIG. 9 illustrates one embodiment of a memory.

FIG. 10 illustrates one embodiment of a first control circuit of the first group.

FIG. 11 illustrates one embodiment of a first control circuit of the second group.

Fig. 12 shows an embodiment of the first control circuit of the third group.

FIG. 13 illustrates one embodiment of a timing diagram for an image sensing device.

Fig. 14 and 15 show additional timing diagrams for the image sensing apparatus.

Detailed Description

Various embodiments are described below in order to describe the present disclosure in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily realize the technical spirit of the present disclosure.

It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or electrically connected or coupled to the other element with one or more elements interposed therebetween. In addition, it will be further understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of stated elements, and do not preclude the presence or addition of one or more other elements. In the description throughout the specification, some components are described in the singular, but the present disclosure is not limited thereto, and it will be understood that components may be formed in the plural.

Fig. 1 is a block diagram illustrating an image sensing apparatus 100 according to an embodiment.

Referring to fig. 1, the image sensing apparatus 100 may include a row controller 110, a pixel array 120, a ramp signal generator 130, a signal converter 140, a global counter 150, and a memory 160.

The row controller 110 may generate a plurality of row control signals CTRLs for controlling the pixel array 120 of each row. For example, the row controller 110 may generate a first row control signal for controlling pixels arranged in a first row of the pixel array 120 during a first row time, and may generate a second row control signal for controlling pixels arranged in a second row of the pixel array 120 during a second row time.

The pixel array 120 may include a plurality of pixels PX arranged in rows and columns. The pixel array 120 may output a plurality of pixel signals VPs for each row to the signal converter 140 under the control of the row controller 110. For example, the pixel array 120 may generate a plurality of pixel signals VPs from pixels arranged in a first row during a first row time and may generate a plurality of pixel signals VPs from pixels arranged in a second row during a second row time. The plurality of pixel signals VPs may be referred to as a plurality of first pixel signals VP1s, a plurality of second pixel signals VP2s, and a plurality of third pixel signals VP3 s. For convenience of description, the plurality of pixel signals VPs are described as being divided into three groups, but may be divided into a different number of groups in another embodiment.

The ramp signal generator 130 may generate a ramp signal VR having a set mode for each line time based on the ramp control signal RP.

The signal converter 140 may generate a plurality of comparison signals VXs based on the plurality of first pixel signals VP1s, the plurality of second pixel signals VP2s, the plurality of third pixel signals VP3s, the ramp signal VR, and the first to third control code signals CC1s, CC2s, and CC3 s. The plurality of comparison signals VXs may be referred to as a plurality of post-comparison signals VXs, or the plurality of comparison signals VXs may be referred to as a plurality of first post-comparison signals VX1s, a plurality of second post-comparison signals VX2s, and a plurality of third post-comparison signals VX3 s.

For example, the signal converter 140 may include a first signal converter a1, a second signal converter a2, and a third signal converter A3. The first signal converter a1 may generate a plurality of first following comparison signals VX1s based on the plurality of first pixel signals VP1s, the ramp signal VR, and the first control code signal CC1 s. The second signal converter a2 may generate a plurality of second post-comparison signals VX2s based on the plurality of second pixel signals VP2s, the ramp signal VR, and the second control code signal CC2 s. The third signal converter a3 may generate a plurality of third post-comparison signals VX3s based on the plurality of third pixel signals VP3s, the ramp signal VR, and the third control code signal CC3 s.

Global counter 150 may generate one or more count signals CNTs for each line time.

The memory 160 may store the count signal CNTs for each column based on the plurality of first after comparison signals VX1s, the plurality of second after comparison signals VX2s, and the plurality of third after comparison signals VX3s for each line time, and may generate the plurality of digital signals DOUTs for each line time. The plurality of digital signals DOUTs may be referred to as a plurality of first digital signals DOUT1s, a plurality of second digital signals DOUT2s, and a plurality of third digital signals DOUT3 s.

For example, memory 160 may include a first memory B1, a second memory B2, and a third memory B3. The first memory B1 may store the count signal CNTs based on each of the plurality of first after-comparison signals VX1s, and may output the stored count signal as the plurality of first digital signals DOUT1 s. The second memory B2 may store the count signal CNTs based on each of the plurality of second post-comparison signals VX2s, and may output the stored count signal as the plurality of second digital signals DOUT2 s. The third memory B3 may store the count signal CNTs based on each of the plurality of third following comparison signals VX3s, and may output the stored count signal as the plurality of third digital signals DOUT3 s.

Fig. 2 is a block diagram illustrating one embodiment of a signal converter 140, which signal converter 140 may include a first signal converter a1, a second signal converter a2, and a third signal converter A3.

The first signal converter a1 may generate a plurality of first following comparison signals VX1s based on the plurality of first pixel signals VP1s, the ramp signal VR, and the first control code signal CC1 s. For example, the first signal converter A1 may include a plurality of comparison circuits a11 to A1 n. The plurality of comparison circuits a11 through A1n may commonly receive the ramp signal VR and the first control code signal CC1s, may receive corresponding pixel signals among the plurality of first pixel signals VP1s, and may respectively generate a plurality of first following comparison signals VX1 s.

For example, the first comparison circuit a11 of the plurality of comparison circuits a11 through A1n may generate the first following comparison signal VOUT11 of the first following comparison signals VX1s based on the first pixel signal VP11, the first control code signal CC1s, and the ramp signal VR among the plurality of first pixel signals VP1 s. The nth comparison circuit A1n among the plurality of comparison circuits a11 through A1n may generate an nth post-comparison signal VOUT1n among the first post-comparison signals VX1s based on the nth pixel signal VP1n, the first control code signal CC1s, and the ramp signal VR among the plurality of first pixel signals VP1 s.

The second signal converter a2 may generate a plurality of second post-comparison signals VX2s based on the plurality of second pixel signals VP2s, the ramp signal VR, and the second control code signal CC2 s. For example, the second signal converter A2 may include a plurality of comparison circuits a21 to A2 n. The plurality of comparison circuits a21 through A2n may commonly receive the ramp signal VR and the second control code signal CC2s, may receive corresponding pixel signals among the plurality of second pixel signals VP2s, and may generate a plurality of second post-comparison signals VX2s, respectively.

For example, the first comparison circuit a21 among the plurality of comparison circuits a21 through A2n may generate the first following comparison signal VOUT21 among the plurality of second following comparison signals VX2s based on the first pixel signal VP21, the second control code signal CC2s, and the ramp signal VR among the plurality of second pixel signals VP2 s. The nth comparison circuit A2n among the plurality of comparison circuits a21 through A2n may generate an nth post-comparison signal VOUT2n among the plurality of second post-comparison signals VX2s based on the nth pixel signal VP2n, the second control code signal CC2s, and the ramp signal VR among the plurality of second pixel signals VP2 s.

The third signal converter a3 may generate a plurality of third post-comparison signals VX3s based on the plurality of third pixel signals VP3s, the ramp signal VR, and the third control code signal CC3 s. For example, the third signal converter A3 may include a plurality of comparison circuits a31 to A3 n. The plurality of comparison circuits a31 through A3n may commonly receive the ramp signal VR and the third control code signal CC3s, may receive corresponding pixel signals among the plurality of third pixel signals VP3s, and may generate a plurality of third following comparison signals VX3s, respectively.

For example, the first comparison circuit a31 among the plurality of comparison circuits a31 through A3n may generate the first following comparison signal VOUT31 among the plurality of third following comparison signals VX3s based on the first pixel signal VP31, the third control code signal CC3s, and the ramp signal VR among the plurality of third pixel signals VP3 s. The nth comparison circuit A3n among the plurality of comparison circuits a31 through A3n may generate the nth post-comparison signal VOUT3n among the plurality of third post-comparison signals VX3s based on the nth pixel signal VP3n, the third control code signal CC3s, and the ramp signal VR among the plurality of third pixel signals VP3 s.

The first comparison circuit a11 may represent the structures of the comparison circuits a11 to A1n in the first signal converter A1, the first comparison circuit a21 may represent the structures of the comparison circuits a21 to A2n in the second signal converter A2, and the first comparison circuit a31 may represent the structures of the comparison circuits a31 to A3n in the third signal converter A3.

Fig. 3 is a block diagram illustrating one embodiment of a first comparison circuit a11 in the first signal converter a 1. Referring to fig. 3, the first comparison circuit a11 may include a first sampling circuit CA11, a second sampling circuit CA12, a first preceding comparator AA11, a first switch SWA11, a second switch SWA12, a third sampling circuit CA13, a fourth sampling circuit CA14, a first following comparator AA12, a third switch SWA13, and a fourth switch SWA 14.

The first sampling circuit CA11 may sample the first pixel signal VP11 during a row time and output the sampled first pixel signal to a first input terminal of the first preceding comparator AA 11. The first input terminal may be an inverting (-) input terminal.

The second sampling circuit CA12 may sample the ramp signal VR during the row time and output the sampled ramp signal to the second input terminal of the first previous comparator AA 11. The second input terminal may be a non-inverting (+) input terminal.

The first previous comparator AA11 may generate a first previous comparison signal VAOUT1 based on the sampled first pixel signal and the sampled ramp signal. For example, the first previous comparator AA11 may compare the sampled first pixel signal with the sampled ramp signal during the line time, and may allow the first previous comparison signal VAOUT1 to transition when the comparison result indicates that the voltage level of the sampled first pixel signal becomes lower than the voltage level of the sampled ramp signal. The first previous comparator AA11 may be initialized by the first switch SWA11 and the second switch SWA12 during an initialization time prior to the row time.

The first switch SWA11 may be coupled between the first input terminal and the first output terminal of the first preceding comparator AA 11. The first output terminal may be a non-inverting (+) output terminal, and may be an output terminal through which the first previous comparison signal VAOUT1 is output. The first switch SWA11 may selectively couple the first input terminal to the first output terminal based on a first switch control signal S1. For example, first switch SWA11 may electrically couple the first input terminal to the first output terminal during an initialization time, and may electrically decouple the first input terminal from the first output terminal during a row time.

The second switch SWA12 may be coupled between the second input terminal and the second output terminal of the first preceding comparator AA 11. The second output terminal may be an inverting (-) output terminal. The second switch SWA12 may selectively couple the second input terminal to the second output terminal based on the first switch control signal S1. For example, the second switch SWA12 may electrically couple the second input terminal to the second output terminal during the initialization time, and may electrically decouple the second input terminal from the second output terminal during the row time.

The third sampling circuit CA13 may sample the first previous comparison signal VAOUT1 during the row time and may output the sampled first previous comparison signal to the first input terminal N11 of the first following comparator AA 12. The first input terminal N11 may be an inverting (-) input terminal. The third sampling circuit CA13 may sample the voltage level of the first input terminal N11 of the first following comparator AA12 during the initialization time.

The fourth sampling circuit CA14 may sample the first reference signal VREF1 (e.g., the first reference signal VREF1 generated at the second input terminal N12) input to the second input terminal N12 of the first following comparator AA12 during the initialization time. The second input terminal N12 may be a non-inverting (+) input terminal. The fourth sampling circuit CA14 may be coupled between the second input terminal N12 of the first following comparator AA12 and a low voltage terminal (e.g., a ground voltage terminal).

The first post comparator AA12 may generate a first post comparison signal VOUT11 based on the sampled first prior comparison signal and the first reference signal VREFl during the line time. For example, the first post comparator AA12 may compare the sampled first pre-comparison signal with the first reference signal VREF1 on the first comparison premise, and may allow the first post-comparison signal VOUT11 to transition when the comparison result indicates that the voltage level of the sampled first pre-comparison signal becomes lower than the voltage level of the first reference signal VREF 1.

For example, the first comparison precondition may include the following conditions: during the initialization time, the first input terminal N11 of the first following comparator AA12 is initialized to a first voltage level. In one embodiment, the first comparison premise may include the following conditions: during the initialization time, the voltage level of the first reference signal VREF1 is adjusted to a first voltage level.

The first post comparator AA12 may be initialized during an initialization time, and when initialized, the first post comparator AA12 may initialize the first input terminal N11 to a first voltage level or adjust the voltage level of the first reference signal VREF1 to the first voltage level through self-generation based on the first control code signal CC1 s. The self-generation is related to the current generated in the first post comparator AA 12. An example of a self-generating operation is described in more detail below, for example, with reference to fig. 4.

The third switch SWA13 may be coupled between the first input terminal N11 and the first output terminal of the first following comparator AA 12. The first output terminal may be a non-inverting (+) output terminal through which the first post-comparison signal VOUT11 is output. The third switch SWA13 may selectively couple the first input terminal N11 to the first output terminal based on the second switch control signal S2. For example, the third switch SWA13 may electrically couple the first input terminal N11 to the first output terminal during the initialization time, and may electrically decouple the first input terminal N11 from the first output terminal during the row time.

The fourth switch SWA14 may be coupled between the second input terminal N12 and the second output terminal of the first following comparator AA 12. The second output terminal may be an inverting (-) output terminal. The fourth switch SWA14 may selectively couple the second input terminal N12 to the second output terminal based on the second switch control signal S2. For example, the fourth switch SWA14 may electrically couple the second input terminal N12 to the second output terminal during the initialization time, and may electrically decouple the second input terminal N12 from the second output terminal during the row time.

Fig. 4 is a circuit diagram showing an embodiment of the first late comparator AA12, together with the third switch SWA13 and the fourth switch SWA 14.

Referring to fig. 4, the first subsequent comparator AA12 may include input circuits AN11 and AN12, load circuits AP11 and AP12, a first current source AS11, and a second current source AS 12. The input circuits AN11 and AN12 may be coupled between the load circuits AP11 and AP12 and the current sources AS11 and AS12, respectively. The input circuits AN11 and AN12 may receive the sampled first prior comparison signal and the first reference signal VREF 1. For example, the input circuits AN11 and AN12 may include a first NMOS transistor AN11 and a second NMOS transistor AN12, respectively. The first NMOS transistor AN11 may include a gate terminal coupled to the second input terminal N12, and source and drain terminals coupled between the second output terminal and a first node. The second NMOS transistor AN12 may include a gate terminal coupled to the first input terminal N11, and source and drain terminals coupled between the first output terminal and a first node.

The load circuits AP11 and AP12 may be coupled between the respective input circuits AN11 and AN12 and a high voltage terminal (e.g., a supply voltage terminal). For example, the loading circuits AP11 and AP12 may include a first PMOS transistor AP11 and a second PMOS transistor AP12, respectively. The first PMOS transistor AP11 may include a gate terminal coupled to the first common coupling node, and source and drain terminals coupled between a high voltage terminal and a second output terminal. The first common coupling node and the second output terminal may be electrically coupled to each other. The second PMOS transistor AP12 may include a gate terminal coupled to the first common coupling node, and source and drain terminals coupled between the high voltage terminal and the first output terminal.

The first current source AS11 and the second current source AS12 may be coupled in parallel between the first node and the low voltage terminal. The first current source AS11 may generate a first current corresponding to a default voltage level of the first reference signal VREF 1. The second current source AS12 may generate a first regulation current based on the first control code signal CC1 s. The first regulation current may be used to regulate the voltage level of the first reference signal VREF 1.

The first post comparator AA12 having the above-described configuration may substantially use the first current during the initialization time, and may selectively use the first regulation current based on the first control code signal CC1s during the initialization time. Accordingly, a first reference current obtained from the first current may be supplied to the first input terminal N11 through the third switch SWA13, and supplied to the second input terminal N12 through the fourth switch SWA 14.

In one embodiment, a first reference current obtained from a sum current of the first current and the first regulation current (hereinafter, referred to as "first sum current") may be supplied to the first input terminal N11 through the third switch SWA13, and supplied to the second input terminal N12 through the fourth switch SWA 14. For example, when the first sum current is generated during an initial period of the initialization time and the first current is generated during a final period of the initialization time, the first input terminal N11 may be initialized to the first voltage level during the initial period based on the first reference current obtained from the first sum current. Also, the first reference signal VREF1 may have a default voltage level during the last period based on a first reference current obtained from the first current. For example, the third sampling circuit CA13 may sample the first voltage level of the first input terminal N11 during an initial period, and the fourth sampling circuit CA14 may sample the default voltage level of the first reference signal VREF1 during a final period.

As another example, when the first current is generated during an initial period of the initialization time and the first sum current is generated during a final period of the initialization time, the first input terminal N11 may be initialized to a default voltage level during the initial period based on a first reference current obtained from the first current. Also, the first reference signal VREF1 may have a first voltage level during the last period based on a first reference current obtained from the first sum current. For example, the third sampling circuit CA13 may sample a default voltage level of the first input terminal N11 during an initial period, and the fourth sampling circuit CA14 may sample a first voltage level of the first reference signal VREF1 during a final period. As such, the first reference signal VREF1 may not be provided from an external device or circuit, but may be generated based on the current generated in the first subsequent comparator AA12 (e.g., may be self-generating).

Fig. 5 is a block diagram illustrating one embodiment of a first comparison circuit a21 in the second signal converter a 2. Referring to fig. 5, the first comparison circuit a21 may include a first sampling circuit CB11, a second sampling circuit CB12, a first preceding comparator AB11, a first switch SWB11, a second switch SWB12, a third sampling circuit CB13, a fourth sampling circuit CB14, a first following comparator AB12, a third switch SWB13, and a fourth switch SWB 14.

The first sampling circuit CB11 may sample the first pixel signal VP21 during a row time and may output the sampled first pixel signal to a first input terminal of the first preceding comparator AB 11. The first input terminal may be an inverting (-) input terminal.

The second sampling circuit CB12 may sample the ramp signal VR during the row time and may output the sampled ramp signal to the second input terminal of the first preceding comparator AB 11. The second input terminal may be a non-inverting (+) input terminal.

The first previous comparator AB11 may generate a first previous comparison signal VBOUT1 based on the sampled first pixel signal and the sampled ramp signal. For example, the first previous comparator AB11 may compare the sampled first pixel signal with the sampled ramp signal during the line time, and may allow the first previous comparison signal VBOUT1 to transition when the comparison result indicates that the voltage level of the sampled first pixel signal becomes lower than the voltage level of the sampled ramp signal. The first previous comparator AB11 may be initialized by the first switch SWB11 and the second switch SWB12 during an initialization time prior to the row time. The first preceding comparator AB11 may be initialized according to the same comparison precondition as the first preceding comparator AA11 included in the first signal converter a 1. For example, the input and output terminals of the first preceding comparators AA11 and AB11 may be initialized to the same level.

The first switch SWB11 may be coupled between the first input terminal and the first output terminal of the first preceding comparator AB 11. The first output terminal may be a non-inverting (+) output terminal, and may be an output terminal through which the first previous comparison signal VBOUT1 is output. The first switch SWB11 may selectively couple the first input terminal to the first output terminal based on a first switch control signal S1. For example, first switch SWB11 may electrically couple the first input terminal to the first output terminal during an initialization time and may electrically decouple the first input terminal from the first output terminal during a row time.

The second switch SWB12 may be coupled between the second input terminal and the second output terminal of the first preceding comparator AB 11. The second output terminal may be an inverting (-) output terminal. The second switch SWB12 may selectively couple the second input terminal to the second output terminal based on the first switch control signal S1. For example, second switch SWB12 may electrically couple the second input terminal to the second output terminal during an initialization time and may electrically decouple the second input terminal from the second output terminal during a row time.

The third sampling circuit CB13 may sample the first previous comparison signal VBOUT1 during the row time and may output the sampled first previous comparison signal to the first input terminal N21 of the first following comparator AB 12. The first input terminal N21 may be an inverting (-) input terminal. The third sampling circuit CB13 may sample the voltage level of the first input terminal N21 of the first following comparator AB12 during the initialization time.

The fourth sampling circuit CB14 may sample the second reference signal VREF2 (e.g., the second reference signal VREF2 generated at the second input terminal N22) input to the second input terminal N22 of the first post-comparator AB12 during the initialization time. The second input terminal N22 may be a non-inverting (+) input terminal. The fourth sampling circuit CB14 may be coupled between the second input terminal N22 of the first following comparator AB12 and the low voltage terminal.

The first post comparator AB12 may generate a first post comparison signal VOUT21 based on the sampled first pre-comparison signal and the second reference signal VREF2 during the row time. For example, the first post comparator AB12 may compare the sampled first pre-comparison signal with the second reference signal VREF2 on a second comparison premise different from the first comparison premise, and may allow the first post-comparison signal VOUT21 to transition when the comparison result indicates that the voltage level of the sampled first pre-comparison signal becomes lower than the voltage level of the second reference signal VREF 2. For example, the second comparison precondition may include the following conditions: during the initialization time, the first input terminal N21 of the first following comparator AB12 is initialized to a second voltage level different from the first voltage level. In one embodiment, the second comparison precondition may include the following condition: during the initialization time, the voltage level of the second reference signal VREF2 is adjusted to a second voltage level.

The first post-comparator AB12 may be initialized during the initialization time, and when initialized, the first post-comparator AB12 may initialize the first input terminal N21 to the second voltage level or adjust the voltage level of the second reference signal VREF2 to the second voltage level by self-generation based on the second control code signal CC2 s. The self-generating operation may be related to the current generated in the first following comparator AB 12. One example of a self-generating operation is described in more detail below, for example, with reference to FIG. 6.

The third switch SWB13 may be coupled between the first input terminal N21 and the first output terminal of the first following comparator AB 12. The first output terminal may be a non-inverting (+) output terminal, and may be an output terminal through which the first post-comparison signal VOUT21 is output. The third switch SWB13 may selectively couple the first input terminal N21 to the first output terminal based on the second switch control signal S2. For example, the third switch SWB13 may electrically couple the first input terminal N21 to the first output terminal during the initialization time, and may electrically decouple the first input terminal N21 from the first output terminal during the row time.

The fourth switch SWB14 may be coupled between the second input terminal N22 and the second output terminal of the first following comparator AB 12. The second output terminal may be an inverting (-) output terminal. The fourth switch SWB14 may selectively couple the second input terminal N22 to the second output terminal based on the second switch control signal S2. For example, the fourth switch SWB14 may electrically couple the second input terminal N22 to the second output terminal during the initialization time, and may electrically decouple the second input terminal N22 from the second output terminal during the row time.

Fig. 6 is a circuit diagram showing one embodiment of the first late comparator AB12, together with the third switch SWB13 and the fourth switch SWB 14. Referring to fig. 6, the first post comparator AB12 may include input circuits BN11 and BN12, loading circuits BP11 and BP12, a first current source BS11, and a second current source BS 12.

The input circuits BN11 and BN12 may be coupled between the loading circuits BP11 and BP12 and the current sources BS11 and BS12, respectively. The input circuits BN11 and BN12 may receive the sampled first prior comparison signal and the second reference signal VREF 2. For example, the input circuits BN11 and BN12 may include a first NMOS transistor BN11 and a second NMOS transistor BN12, respectively. The first NMOS transistor BN11 may include a gate terminal coupled to the second input terminal N22, and source and drain terminals coupled between the second output terminal and a second node. The second NMOS transistor BN12 may include a gate terminal coupled to the first input terminal N21, and source and drain terminals coupled between the first output terminal and a second node.

The loading circuits BP11 and BP12 may be coupled between the respective input circuits BN11 and BN12 and the high voltage terminals. For example, the loading circuits BP11 and BP12 may include a first PMOS transistor BP11 and a second PMOS transistor BP12, respectively. The first PMOS transistor BP11 may include a gate terminal coupled to the second common coupling node, and source and drain terminals coupled between the high voltage terminal and the second output terminal. The second common coupling node and the second output terminal may be electrically coupled to each other. The second PMOS transistor BP12 may include a gate terminal coupled to the second common coupling node, and source and drain terminals coupled between the high voltage terminal and the first output terminal.

The first current source BS11 and the second current source BS12 may be coupled in parallel between the second node and the low voltage terminal. The first current source BS11 may generate a second current corresponding to the default voltage level of the second reference signal VREF 2. The second current source BS12 may generate a second adjustment current based on the second control code signal CC2 s. The second regulation current may regulate the voltage level of the second reference signal VREF 2.

The first post comparator AB12 having the above-described configuration may substantially use the second current during the initialization time, and may selectively use the second regulation current based on the second control code signal CC2s during the initialization time. Accordingly, a second reference current obtained from the second current may be supplied to the first input terminal N21 through the third switch SWB13, and supplied to the second input terminal N22 through the fourth switch SWB 14.

In one embodiment, a second reference current obtained from a sum current of the second current and the second regulation current (hereinafter, referred to as "second sum current") may be supplied to the first input terminal N21 through the third switch SWB13, and supplied to the second input terminal N22 through the fourth switch SWB 14. For example, when the second sum current is generated during an initial period of the initialization time and the second current is generated during a final period of the initialization time, the first input terminal N21 may be initialized to the second voltage level during the initial period based on the second reference current obtained from the second sum current. Also, the second reference signal VREF2 may have a default voltage level during the last period based on a second reference current obtained from the second current.

For example, the third sampling circuit CB13 may sample the second voltage level of the first input terminal N21 during the initial period. The fourth sampling circuit CB14 may sample the default voltage level of the second reference signal VREF2 during the last period. As another example, when the second current is generated during an initial period of the initialization time and the second sum current is generated during a final period of the initialization time, the first input terminal N21 may be initialized to a default voltage level during the initial period based on a second reference current obtained from the second current. The second reference signal VREF2 may have a second voltage level during the last period based on a second reference current obtained from the second sum current.

For example, the third sampling circuit CB13 may sample a default voltage level of the first input terminal N21 during an initial period. The fourth sampling circuit CB14 may sample the second voltage level of the second reference signal VREF2 during the last period. As such, the second reference signal VREF2 may not be provided from an external device or circuit, but may be generated (e.g., self-generated) based on the current generated in the first subsequent comparator AB 12.

Fig. 7 is a block diagram illustrating one embodiment of a first comparison circuit a31 included in the third signal converter A3. Referring to fig. 7, the first comparison circuit a31 may include a first sampling circuit CC11, a second sampling circuit CC12, a first preceding comparator AC11, a first switch SWC11, a second switch SWC12, a third sampling circuit CC13, a fourth sampling circuit CC14, a first following comparator AC12, a third switch SWC13, and a fourth switch SWC 14.

The first sampling circuit CC11 may sample the first pixel signal VP31 during a row time and may output the sampled first pixel signal to a first input terminal of the first preceding comparator AC 11. The first input terminal may be an inverting (-) input terminal.

The second sampling circuit CC12 may sample the ramp signal VR during the row time and may output the sampled ramp signal to the second input terminal of the first preceding comparator AC 11. The second input terminal may be a non-inverting (+) input terminal.

The first preceding comparator AC11 may generate a first preceding comparison signal VCOUT1 based on the sampled first pixel signal and the sampled ramp signal. For example, the first preceding comparator AC11 may compare the sampled first pixel signal with the sampled ramp signal during the line time, and may allow the first preceding comparison signal VCOUT1 to transition when the comparison result indicates that the voltage level of the sampled first pixel signal becomes lower than the voltage level of the sampled ramp signal. The first previous comparator AC11 may be initialized by the first switch SWC11 and the second switch SWC12 during an initialization time prior to the row time. The first preceding comparator AC11 may be initialized according to the same comparison preconditions as the first preceding comparator AA11 in the first signal converter a 1. For example, the input and output terminals of the first preceding comparators AA11, AB11, and AC11 may be initialized to the same level.

The first switch SWC11 may be coupled between the first input terminal and the first output terminal of the first preceding comparator AC 11. The first output terminal may be a non-inverting (+) output terminal, and may be an output terminal through which the first previous comparison signal VCOUT1 is output. The first switch SWC11 may selectively couple the first input terminal to the first output terminal based on a first switch control signal S1. For example, first switch SWC11 may electrically couple the first input terminal to the first output terminal during an initialization time and may electrically decouple the first input terminal from the first output terminal during a row time.

The second switch SWC12 may be coupled between the second input terminal and the second output terminal of the first preceding comparator AC 11. The second output terminal may be an inverting (-) output terminal. The second switch SWC12 may selectively couple the second input terminal to the second output terminal based on the first switch control signal S1. For example, second switch SWC12 may electrically couple the second input terminal to the second output terminal during an initialization time and may electrically decouple the second input terminal from the second output terminal during a row time.

The third sampling circuit CC13 may sample the first previous comparison signal VCOUT1 during a row time and may output the sampled first previous comparison signal to the first input terminal N31 of the first following comparator AC 12. The first input terminal N31 may be an inverting (-) input terminal. The third sampling circuit CC13 may sample the voltage level of the first input terminal N31 of the first following comparator AC12 during the initialization time.

The fourth sampling circuit CC14 may sample the third reference signal VREF3 (e.g., the third reference signal VREF3 generated at the second input terminal N32) input to the second input terminal N32 of the first post-comparator AC12 during the initialization time. The second input terminal N32 may be a non-inverting (+) input terminal. The fourth sampling circuit CC14 may be coupled between the second input terminal N32 of the first following comparator AC12 and the low voltage terminal.

The first post comparator AC12 may generate a first post comparison signal VOUT31 based on the sampled first pre-comparison signal and the third reference signal VREF3 during the line time. For example, the first post comparator AC12 may compare the sampled first pre-comparison signal with the third reference signal VREF3 on a third comparison premise different from the first and second comparison premises, and may allow the first post-comparison signal VOUT31 to transition when the comparison result indicates that the voltage level of the sampled first pre-comparison signal becomes lower than the voltage level of the third reference signal VREF 3. For example, the third comparison precondition may include the following conditions: during the initialization time, the first input terminal N31 of the first post comparator AC12 is initialized to a third voltage level different from the first voltage level and the second voltage level. In one embodiment, the third comparison premise may include the following condition: during the initialization time, the voltage level of the third reference signal VREF3 is adjusted to a third voltage level.

The first post-comparator AC12 may be initialized during the initialization time, and when initialized, the first post-comparator AC12 may initialize the first input terminal N31 to the third voltage level or adjust the voltage level of the third reference signal VREF3 to the third voltage level by self-generation based on the third control code signal CC3 s. The self-generating operation is related to the current generated in the first post comparator AC 12. One example of a self-generating operation is described in more detail below, for example, with reference to FIG. 8.

The third switch SWC13 may be coupled between the first input terminal N31 and the first output terminal of the first trailing comparator AC 12. The first output terminal may be a non-inverting (+) output terminal, and may be an output terminal through which the first post-comparison signal VOUT31 is output. The third switch SWC13 may selectively couple the first input terminal N31 to the first output terminal based on the second switch control signal S2. For example, the third switch SWC13 may electrically couple the first input terminal N31 to the first output terminal during the initialization time, and may electrically decouple the first input terminal N31 from the first output terminal during the row time.

The fourth switch SWC14 may be coupled between the second input terminal N32 and the second output terminal of the first following comparator AC 12. The second output terminal may be an inverting (-) output terminal. The fourth switch SWC14 may selectively couple the second input terminal N32 to the second output terminal based on the second switch control signal S2. For example, the fourth switch SWC14 may electrically couple the second input terminal N32 to the second output terminal during the initialization time, and may electrically decouple the second input terminal N32 from the second output terminal during the row time.

Fig. 8 is a circuit diagram illustrating one embodiment of the first rear comparator AC12 shown in fig. 7, together with the third switch SWC13 and the fourth switch SWC 14.

Referring to fig. 8, the first post comparator AC12 may include input circuits CN11 and CN12, load circuits CP11 and CP12, a first current source CS11, and a second current source CS 12. Input circuits CN11 and CN12 may be coupled between load circuits CP11 and CP12 and current sources CS11 and CS12, respectively. The input circuits CN11 and CN12 may receive the sampled first prior comparison signal and the third reference signal VREF 3. For example, the input circuits CN11 and CN12 may include a first NMOS transistor CN11 and a second NMOS transistor CN12, respectively. The first NMOS transistor CN11 may include a gate terminal coupled to the second input terminal N32, and source and drain terminals coupled between the second output terminal and a third node. The second NMOS transistor CN12 may include a gate terminal coupled to the first input terminal N31, and source and drain terminals coupled between the first output terminal and a third node.

The load circuits CP11 and CP12 may be coupled between the respective input circuits CN11 and CN12 and the high voltage terminals. For example, the loading circuits CP11 and CP12 may include first and second PMOS transistors CP11 and CP12, respectively. The first PMOS transistor CP11 may include a gate terminal coupled to the third common coupling node, and source and drain terminals coupled between the high voltage terminal and the second output terminal. The third common coupling node and the second output terminal may be electrically coupled to each other. The second PMOS transistor CP12 may include a gate terminal coupled to the third common coupling node, and source and drain terminals coupled between the high voltage terminal and the first output terminal.

The first current source CS11 and the second current source CS12 may be coupled in parallel between the third node and the low voltage terminal. The first current source CS11 may generate a third current corresponding to a default voltage level of the third reference signal VREF 3. The second current source CS12 may generate a third adjustment current for adjusting the voltage level of the third reference signal VREF3 based on the third control code signal CC3 s.

The first post comparator AC12 having the above-described configuration may substantially use the third current during the initialization time, and may selectively use the third regulation current based on the third control signal CC3s during the initialization time. Accordingly, a third reference current obtained from the third current may be supplied to the first input terminal N31 through the third switch SWC13, and supplied to the second input terminal N32 through the fourth switch SWC 14.

In one embodiment, a third reference current obtained from a sum current of the third current and the third regulation current (hereinafter, referred to as a "third sum current") may be supplied to the first input terminal N31 through the third switch SWC13, and supplied to the second input terminal N32 through the fourth switch SWC 14. For example, when the third sum current is generated during an initial period of the initialization time and the third current is generated during a final period of the initialization time, the first input terminal N31 may be initialized to the third voltage level during the initial period based on the third reference current obtained from the third sum current. Based on a third reference current obtained from the third current, the third reference signal VREF3 may have a default voltage level during the last period. For example, the third sampling circuit CC13 may sample the third voltage level of the first input terminal N31 during the initial period. The fourth sampling circuit CC14 may sample a default voltage level of the third reference signal VREF3 during the last period.

As another example, when the third current is generated during an initial period of the initialization time and the third sum current is generated during a final period of the initialization time, the first input terminal N31 may be initialized to the default voltage level during the initial period based on a third reference current obtained from the third current. The third reference signal VREF3 may have a third voltage level during the last period based on a third reference current obtained from the third sum current. For example, the third sampling circuit CC13 may sample a default voltage level of the first input terminal N31 during an initial period, and the fourth sampling circuit CC14 may sample a third voltage level of the third reference signal VREF3 during a final period. As such, the third reference signal VREF3 may not be provided from an external device or circuit, but may be generated (e.g., self-generated) based on the current generated in the first subsequent comparator AC 12.

FIG. 9 is a block diagram illustrating one embodiment of memory 160. Referring to fig. 9, the memory 160 may include a first memory B1, a second memory B2, and a third memory B3.

As described above, the first memory B1 may store the count signal CNTs based on each of the plurality of first subsequent comparison signals VX1s, and may output the stored count signal CNTs as the plurality of first digital signals DOUT1 s. For example, the first memory B1 may include a plurality of first control circuits BA11 through BA1n and a plurality of first memory circuits BA21 through BA2 n.

The plurality of first control circuits BA11 to BA1n may generate a plurality of first storage control signals ASHOT1 to ASHOTn, respectively, based on the plurality of first after comparison signals VX1S and the input control signal S3. For example, the first control circuit BA11 among the plurality of first control circuits BA11 through BA1n may generate the first storage control signal ASHOT1 among the plurality of first storage control signals ASHOT1 through ASHOTn based on the first post-comparison signal VOUT11 among the first post-comparison signals VX1S and the input control signal S3. The nth control circuit BA1n (among the plurality of first control circuits BA11 through BA1 n) may generate the nth storage control signal ASHOTn (among the plurality of first storage control signals ASHOT1 through ASHOTn) based on the nth post-comparison signal VOUT1n among the first post-comparison signals VX1S and the input control signal S3.

The plurality of first memory circuits BA21 through BA2n may store the plurality of first digital signals DOUT1s based on the plurality of first memory control signals ASHOT1 through ASHOTn and the count signal CNTs, respectively. For example, when the first storage control signal ASHOT1 (among the plurality of first storage control signals ASHOT1 through ASHOTn) is enabled, the first storage circuit BA21 (among the plurality of first storage circuits BA21 through BA2 n) may store the count signal CNTs as the first digital signal D11s among the first digital signals DOUT1 s. When the nth memory control signal ASHOTn (among the plurality of first memory control signals ASHOT1 through ASHOTn) is enabled, the nth memory circuit BA2n (among the plurality of first memory circuits BA21 through BA2 n) may store the count signal CNTs as the nth digital signal D1ns among the first digital signals DOUT1 s.

As described above, the second memory B2 may store the count signal CNTs based on each of the plurality of second post-comparison signals VX2s, and may output the stored count signal CNTs as the plurality of second digital signals DOUT2 s. For example, the second memory B2 may include a plurality of second control circuits BB11 to BB1n and a plurality of second memory circuits BB21 to BB2 n.

The plurality of second control circuits BB11 to BB1n may generate a plurality of second store control signals BSHOT1 to BSHOT, respectively, based on the plurality of second post-compare signals VX2S and the input control signal S3. For example, the first control circuit BB11 (among the plurality of second control circuits BB11 to BB1 n) may generate the first storage control signal BSHOT1 (among the plurality of second storage control signals BSHOT1 to BSHOT) based on the first post-comparison signal VOUT21 and the input control signal S3 among the second post-comparison signals VX 2S. The nth control circuit BB1n (among the plurality of second control circuits BB11 through BB1 n) may generate the nth storage control signal BSHOT (among the plurality of second storage control signals BSHOT1 through BSHOT) based on the nth post-comparison signal VOUT2n and the input control signal S3 among the second post-comparison signals VX 2S.

The plurality of second memory circuits BB21 to BB2n may store the plurality of second digital signals DOUT2s based on the plurality of second memory control signals BSHOT1 to BSHOT and the count signal CNTs, respectively. For example, when the first memory control signal BSHOT1 (among the plurality of second memory control signals BSHOT1 through BSHOT) is enabled, the first memory circuit BB21 (among the plurality of second memory circuits BB21 through BB2 n) may store the count signal CNTs as the first digital signal D21s among the second digital signals DOUT2 s. When the nth memory control signal BSHOT (among the plurality of second memory control signals BSHOT1 through BSHOT) is enabled, the nth memory circuit BB2n among the plurality of second memory circuits BB21 through BB2n may store the count signal CNTs as the nth digital signal D2ns among the second digital signals DOUT2 s.

As described above, the third memory B3 may store the count signal CNTs based on each of the plurality of third post-comparison signals VX3s, and may output the stored count signal CNTs as the plurality of third digital signals DOUT3 s. For example, the third memory B3 may include a plurality of third control circuits BC11 to BC1n and a plurality of third memory circuits BC21 to BC2 n.

The plurality of third control circuits BC11 to BC1n may generate a plurality of third memory control signals CSHOT1 to CSHOT n, respectively, based on the plurality of third post-comparison signals VX3S and the input control signal S3. For example, the first control circuit BC11 among the plurality of third control circuits BC11 through BC1n may generate the first storage control signal CSHOT1 (among the plurality of third storage control signals CSHOT1 through CSHOT) based on the first post-comparison signal VOUT31 among the third post-comparison signals VX3S and the input control signal S3. The nth control circuit BC1n (among the plurality of third control circuits BC11 through BC1 n) may generate the nth memory control signal CSHOT (among the plurality of third memory control signals CSHOT1 through CSHOT) based on the nth post-comparison signal VOUT3n among the third post-comparison signals VX3S and the input control signal S3.

The plurality of third memory circuits BC21 through BC2n may store the plurality of third digital signals DOUT3s based on the plurality of third memory control signals CSHOT1 through CSHOT and the count signal CNTs, respectively. For example, when the first memory control signal CSHOT1 (among the plurality of third memory control signals CSHOT1 through CSHOT) is enabled, the first memory circuit BC21 (among the plurality of third memory circuits BC21 through BC2 n) may store the count signal CNTs as the first digital signal D31s among the third digital signals DOUT3 s. When the nth memory control signal CSHOT (among the plurality of third memory control signals CSHOT1 through CSHOT) is enabled, the nth memory circuit BC2n (among the plurality of third memory circuits BC21 through BC2 n) may store the count signal CNTs as the nth digital signal D3ns among the third digital signals DOUT3 s.

The plurality of first control circuits BA11 to BA1n, the plurality of second control circuits BB11 to BB1n, the plurality of third control circuits BC11 to BC1n, the plurality of first memory circuits BA21 to BA2n, the plurality of second memory circuits BB21 to BB2n, and the plurality of third memory circuits BC21 to BC2n may use the same voltage (e.g., power supply voltage VDD) as a source power supply. The plurality of first memory circuits BA21 to BA2n, the plurality of second memory circuits BB21 to BB2n, and the plurality of third memory circuits BC21 to BC2n may be referred to as "line memories".

Fig. 10 is a circuit diagram illustrating one embodiment of the first control circuit BA11 among the first control circuits BA11 through BA1n shown in fig. 9. Since the first control circuits BA11 to BA1n may be designed to be all the same, the first control circuit BA11 is representatively described hereinafter.

Referring to fig. 10, the first control circuit BA11 may include an input circuit IN11, a delay circuit DLY11, and an output circuit OUT 11. The input circuit IN11 may receive a first post comparison signal VOUT11 and an input control signal S3 among the plurality of first post comparison signals VX 1S. For example, the input circuit IN11 may include a nand gate and a not gate. The nand gate may perform a nand operation on the first last comparison signal VOUT11 and the input control signal S3, and the nand gate may invert an output signal of the nand gate.

The delay circuit DLY11 may delay the output signal of the input circuit IN11 by a set delay time. For example, delay circuit DLY11 may include an inverter chain in which a plurality of not gates are coupled in series with each other.

The output circuit OUT11 may receive the output signal of the input circuit IN11 and the output signal of the delay circuit DLY11, and may generate the first storage control signal ASHOT1 among the plurality of first storage control signals ASHOT1 through ASHOTn. For example, the output circuit OUT11 may include an or gate. The or gate may perform an or operation on the output signal of the input circuit IN11 and the output signal of the delay circuit DLY11 to generate the first storage control signal ASHOT1, and the first storage control signal ASHOT1 is generated for a set time (e.g., a relatively short time). The pulse width (e.g., enable width) of the first storage control signal ASHOT1 may correspond to a delay time.

Fig. 11 is a circuit diagram illustrating one embodiment of the first control circuit BB11 among the second control circuits BB11 to BB1n shown in fig. 9. Since the second control circuits BB11 to BB1n may be designed to be all the same, the first control circuit BB11 is described representatively hereinafter.

Referring to fig. 11, the first control circuit BB11 may include an input circuit IN21, a delay circuit DLY21, and an output circuit OUT 21. The input circuit IN21 may receive the first post comparison signal VOUT21 and the input control signal S3 among the plurality of second post comparison signals VX 2S. For example, the input circuit IN21 may include a nand gate and a not gate. The nand gate may perform a nand operation on the first last comparison signal VOUT21 and the input control signal S3, and the nand gate may invert an output signal of the nand gate.

The delay circuit DLY21 may delay the output signal of the input circuit IN21 by a delay time. For example, delay circuit DLY21 may include an inverter chain in which a plurality of not gates are coupled in series with each other.

The output circuit OUT21 may receive the output signal of the input circuit IN21 and the output signal of the delay circuit DLY21, and may generate the first storage control signal BSHOT1 among the plurality of second storage control signals BSHOT1 through BSHOT. For example, the output circuit OUT21 may include an or gate. The or gate may perform an or operation on the output signal of the input circuit IN21 and the output signal of the delay circuit DLY21 to generate the first storage control signal BSHOT1, and the first storage control signal BSHOT1 may be generated for a set time (e.g., a relatively short time). A pulse width (e.g., an enable width) of the first storage control signal BSHOT1 may correspond to a delay time.

Fig. 12 is a circuit diagram showing one embodiment of the first control circuit BC11 among the third control circuits BC11 through BC1n shown in fig. 9. Since the third control circuits BC11 to BC1n may be designed to be all the same, the first control circuit BC11 is representatively described hereinafter.

Referring to fig. 12, the first control circuit BC11 may include an input circuit IN31, a delay circuit DLY31, and an output circuit OUT 31. The input circuit IN31 may receive the first post comparison signal VOUT31 and the input control signal S3 among the plurality of third post comparison signals VX 3S. For example, the input circuit IN31 may include a nand gate and a not gate. The nand gate may perform a nand operation on the first last comparison signal VOUT31 and the input control signal S3, and the nand gate may invert an output signal of the nand gate.

The delay circuit DLY31 may delay the output signal of the input circuit IN31 by a delay time. For example, delay circuit DLY31 may include an inverter chain in which a plurality of not gates are coupled in series with each other.

The output circuit OUT31 may receive the output signal of the input circuit IN31 and the output signal of the delay circuit DLY31, and may generate the first storage control signal CSHOT1 among the plurality of third storage control signals CSHOT1 through CSHOT. For example, the output circuit OUT31 may include an or gate. The or gate may perform an or operation on the output signal of the input circuit IN31 and the output signal of the delay circuit DLY31, thereby generating the first storage control signal CSHOT1, the first storage control signal CSHOT1 being generated for a set time (e.g., a relatively short time). A pulse width (e.g., an enable width) of the first storage control signal CSHOT1 may correspond to a delay time.

FIG. 13 illustrates one embodiment of a timing diagram for operating the image sensing device 100. Fig. 13 shows an operation related to one pixel signal (for example, the first pixel signal VP11) as a representative example.

Referring to fig. 13, the image sensing apparatus 100 may be initialized during an initialization time RST. For example, a plurality of post comparators in the first signal converter a1 may be initialized according to a first comparison precondition, a plurality of post comparators included in the second signal converter a2 may be initialized according to a second comparison precondition, and a plurality of post comparators included in the third signal converter A3 may be initialized according to a third comparison precondition (e.g., refer to fig. 14 and 15).

The image sensing device 100 may generate and store the first pixel signal VP11 during the line time SRT. Which is described in more detail below.

Pixel array 120 may generate first pixel signal VP11 during row time SRT. For example, during the reset time RT of the row time SRT, the pixel array 120 may generate the reset signal VR11 corresponding to a noise component in the first pixel signal VP11 as the first pixel signal VP 11. Then, during the data time DT of the row time SRT, the pixel array may generate a data signal VD11 corresponding to the incident light as a first pixel signal VP 11.

The ramp signal generator 130 may generate the ramp signal VR having the set mode during the row time SRT based on the ramp control signal RP. For example, the ramp signal generator 130 may generate the following ramp signal VR: the ramp signal VR ramps in a reset voltage range during the reset time RT and ramps in a data voltage range during the data time DT.

The first previous comparator AA11 may compare the first pixel signal VP11 with the ramp signal VR, and may generate a first previous comparison signal VAOUT1 corresponding to the comparison result. For example, during the reset time RT and the data time DT, when the voltage level of the ramp signal VR is higher than the voltage level of the first pixel signal VP11, the first previous comparator AA11 may generate the first previous comparison signal VAOUT1 having a logic high level. When the voltage level of the ramp signal VR is lower than the voltage level of the first pixel signal VP11, the first previous comparator AA11 may generate the first previous comparison signal VAOUT1 having a logic low level. The first previous comparison signal VAOUT1 may be sampled by the third sampling circuit CA 13.

The first post comparator AA12 may compare the sampled first pre-compare signal with the first reference signal VREF1 on a first comparison premise. The first post comparator AA12 may generate a first post comparison signal VOUT11 corresponding to the comparison result. For example, during the reset time RT and the data time DT, the first following comparator AA12 may generate the first following comparison signal VOUT11 having a logic low level when the voltage level of the sampled preceding comparison signal is higher than the voltage level of the first reference signal VREF 1. The first following comparator AA12 may generate the first following comparison signal VOUT11 having a logic high level when the voltage level of the sampled preceding comparison signal is lower than the voltage level of the first reference signal VREF 1.

At this time, since the first post comparison signal VOUT11 is generated on the first comparison premise, the transition time of the first post comparison signal VOUT11 and the transition time of the first preceding comparison signal VAOUT11 may be different from each other. For example, the transition time of the first late comparison signal VOUT11 may be less than the transition time of the first early comparison signal VAOUT1 by a set time. The set time may be determined according to the voltage difference Δ V, an example of which is described below with reference to fig. 14 and 15.

The global counter 150 may generate a count signal CNTs that is counted in a set manner during the line time SRT. For example, the global counter 150 may generate a count signal CNTs that is counted during the reset time RT and counted during the data time DT.

The first control circuit BA11 may generate the first storage control signal ASHOT1 based on the first post-comparison signal VOUT11 and the input control signal S3. For example, the first control circuit BA11 may allow the first storage control signal ASHOT1 to be generated for a set time (e.g., a relatively short time) according to a transition time of the first subsequent comparison signal VOUT11 during the reset time RT and the data time DT. For example, the first control circuit BA11 may enable the first storage control signal ASHOT1 for a set time (e.g., a relatively short time).

The first memory circuit BA21 may store the count signal CNTs based on the first memory control signal ASHOT 1. For example, the first storage circuit BA21 may latch the count signal CNTs when the first storage control signal ASHOT1 is pulsed during the reset time RT, and may output the latched count signal (hereinafter, referred to as "reset count signal") as the first digital signal D11 s. In addition, the first storage circuit BA21 may latch the count signal CNTs when the first storage control signal ASHOT1 is pulsed during the data time DT, and may output the latched count signal (hereinafter, referred to as "data count signal") as the first digital signal D11 s.

The reset count signal may further include a count code "α" corresponding to the set time, and the data count signal may further include a count code "α" corresponding to the set time. For example, an unnecessary count code "α" may be reflected in the reset count signal and the data count signal. In one embodiment, the count code "α" may be shifted by a subsequent operation. For example, the subsequent operation may include a Digital Double Sampling (DDS) operation.

Pixel array 120 may simultaneously generate a plurality of pixel signals VPs including first pixel signal VP11 during row time SRT. At this time, a pixel signal having the same voltage level as that of the first pixel signal VP11 (hereinafter, referred to as "same pixel signal") may exist among the plurality of pixel signals VPs. In this case, the transition time of the first post-comparison signal VOUT11 corresponding to the first pixel signal VP11 may be equal to the transition time of the post-comparison signal corresponding to the same pixel signal. The description thereof will be described in more detail with reference to fig. 14 and 15. Hereinafter, for convenience of description, the first pixel signal VP21 among the plurality of second pixel signals VP2s and the first pixel signal VP31 among the plurality of third pixel signals VP3s will be taken as an example of the same pixel signal, and description will be made.

Fig. 14 illustrates one embodiment of a timing diagram for operating the first pixel signals VP11, VP21, and VP31, according to one example.

Referring to fig. 14, during the initialization time RST, the first input terminals N11, N21, and N31 may be initialized to first to third voltage levels, respectively. For example, during an initial period of the initialization time RST, the first subsequent comparator AA12 may initialize the first input terminal N11 to a first voltage level corresponding to a first sum current based on the first control code signal CC1 s. The initial period corresponds to a period in which the first switch control signal S1 is enabled. The first voltage level may be higher than the default voltage level by a voltage difference av.

During an initial period of the initialization time RST, the first subsequent comparator AB12 may initialize the first input terminal N21 to a second voltage level corresponding to the second sum current based on the second control code signal CC2 s. The second voltage level may be equal to the default voltage level. During an initial period of the initialization time RST, the first subsequent comparator AC12 may initialize the first input terminal N31 to a third voltage level corresponding to a third sum current based on the third control code signal CC3 s. The third voltage level may be lower than the default voltage level by a voltage difference av.

During the initialization time RST, the first to third reference signals VREF1, VREF2, and VREF3 having default voltage levels may be generated at the second input terminals N12, N22, and N32. The first to third reference signals VREF1, VREF2, and VREF3 may have default voltage levels that are adjusted during the last period of the initialization time RST. The last period corresponds to a period in which the first switch control signal S1 is deactivated and the second switch control signal S2 is activated.

In this state, during the row time SRT, a sampled first previous comparison signal corresponding to the first pixel signal VP11 may be input through the first input terminal N11, a sampled first previous comparison signal corresponding to the first pixel signal VP21 may be input through the first input terminal N21, and a sampled first previous comparison signal corresponding to the first pixel signal VP31 may be input through the first input terminal N31. At this time, the voltage difference Δ V may be maintained between the sampled first previous comparison signals input through the first input terminals N11, N21, and N31.

Accordingly, during the row time SRT, a delay difference corresponding to the voltage difference Δ V may occur between the first late comparison signals VOUT11, VOUT21, and VOUT 31. For example, during the reset time RT of the row time SRT, the crossing time points between the sampled first previous comparison signal and the first to third reference signals VREF1, VREF2, and VREF3 are slightly changed. Therefore, the first post-comparison signals VOUT11, VOUT21, and VOUT31 may sequentially transition. In addition, during the data time DT of the row time SRT, the crossing time points between the sampled first previous comparison signal and the first to third reference signals VREF1, VREF2, and VREF3 are slightly changed. Therefore, the first post-comparison signals VOUT11, VOUT21, and VOUT31 may sequentially transition.

According to a delay difference occurring between the first subsequent comparison signals VOUT11, VOUT21, and VOUT31, during the row time SRT, the first control circuits BA11, BB11, and BC11 may sequentially enable the first storage control signals ASHOT1, BSHOT1, and CSHOT1, and the first storage circuits BA21, BB21, and BC21 may sequentially store the count signal CNTs based on the first storage control signals ASHOT1, BSHOT1, and CSHOT 1. Accordingly, the points of time at which the first control circuits BA11, BB11, and BC11 and the first memory circuits BA21, BB21, and BC21 use the source power supply (e.g., power supply voltage VDD) can be dispersed. As a result, the amount of drop in the source power supply can also be dispersed.

Fig. 15 illustrates one embodiment of a timing diagram for operating the first pixel signals VP11, VP21, and VP31, according to another example.

Referring to fig. 15, during the initialization time RST, the first input terminals N11, N21, and N31 may be initialized to a default voltage level. For example, during an initial period of the initialization time RST, the first subsequent comparator AA12 may initialize the first input terminal N11 to a default voltage level corresponding to the first current. The initial period corresponds to a period in which the first switch control signal S1 is enabled. During an initial period of the initialization time RST, the first following comparator AB12 may initialize the first input terminal N21 to a default voltage level corresponding to the second current. During an initial period of the initialization time RST, the first subsequent comparator AC12 may initialize the first input terminal N31 to a default voltage level corresponding to the third current.

During the initialization time RST, the first to third reference signals VREF1, VREF2, and VREF3 having first to third voltage levels, respectively, may be generated at the second input terminals N12, N22, and N32. For example, during the last period of the initialization time RST, the first following comparator AA12 may adjust the voltage level of the first reference signal VREF1 to a first voltage level, which corresponds to a first sum current, based on the first control code signal CC1 s. The last period corresponds to a period in which the first switch control signal S1 is deactivated and the second switch control signal S2 is activated. The first voltage level may be higher than the default voltage level by a voltage difference av.

During the last period of the initialization time RST, the first subsequent comparator AB12 may adjust the voltage level of the second reference signal VREF2 to a second voltage level, which corresponds to a second sum current, based on the second control code signal CC2 s. The second voltage level may be equal to the default voltage level.

During the last period of the initialization time RST, the first following comparator AC12 may initialize the voltage level of the third reference signal VREF3 to a third voltage level, which corresponds to a third sum current, based on the third control code signal CC3 s. The third voltage level may be lower than the default voltage level by a voltage difference av.

In this state, during the row time SRT, a sampled first previous comparison signal corresponding to the first pixel signal VP11 may be input through the first input terminal N11, a sampled first previous comparison signal corresponding to the first pixel signal VP21 may be input through the first input terminal N21, and a sampled first previous comparison signal corresponding to the first pixel signal VP31 may be input through the first input terminal N31. At this time, the sampled first previous comparison signals input through the first input terminals N11, N21, and N31 may have the same voltage level.

Accordingly, during the row time SRT, a delay difference corresponding to the voltage difference Δ V may occur between the first late comparison signals VOUT11, VOUT21, and VOUT 31. For example, during the reset time RT of the row time SRT, the crossing time points between the sampled first previous comparison signal and the first to third reference signals VREF1, VREF2, and VREF3 are slightly changed. Therefore, the first post-comparison signals VOUT11, VOUT21, and VOUT31 may sequentially transition. In addition, during the data time DT of the row time SRT, the crossing time points between the sampled first previous comparison signal and the first to third reference signals VREF1, VREF2, and VREF3 are slightly changed. Therefore, the first post-comparison signals VOUT11, VOUT21, and VOUT31 may sequentially transition.

According to a delay difference occurring between the first subsequent comparison signals VOUT11, VOUT21, and VOUT31, during the row time SRT, the first control circuits BA11, BB11, and BC11 may sequentially enable the first storage control signals ASHOT1, BSHOT1, and CSHOT1, and the first storage circuits BA21, BB21, and BC21 may sequentially store the count signal CNTs based on the first storage control signals ASHOT1, BSHOT1, and CSHOT1, respectively. Accordingly, the points of time at which the first control circuits BA11, BB11, and BC11 and the first memory circuits BA21, BB21, and BC21 use the source power supply (e.g., power supply voltage VDD) can be dispersed. Therefore, the amount of drop in the source power supply can also be dispersed.

According to one or more of the foregoing embodiments of the present disclosure, different comparison preconditions for each of a plurality of groups may be applied to pixel signals generated for each corresponding row, thereby dispersing the amount of drop in source power supply. According to these and other embodiments of the present disclosure, the operational reliability of the image sensing apparatus may be improved by reducing or minimizing the influence of a dropped power supply.

While the present disclosure has been shown and described with respect to particular embodiments, the disclosed embodiments are provided for description and are not intended to be limiting. Further, it is noted that the present disclosure may be implemented in various ways by means of substitutions, changes and modifications falling within the scope of the appended claims, as will be recognized by those skilled in the art in light of the present disclosure.