阅读说明：本技术 具有双阱隔离的延伸漏极mos (Extended drain MOS with double well isolation ) 是由 C·特塞 G·马图尔 于 2020-03-30 设计创作，主要内容包括：集成电路(100)包括延伸漏极MOS晶体管(105)。集成电路(100)的衬底(101)具有第一导电类型的下层(103)。延伸漏极MOS晶体管(105)的漏极阱(106)具有第一导电类型。漏极阱(106)通过具有相反的第二导电类型的漏极隔离阱(112)与下层(103)分开。延伸漏极MOS晶体管(105)的源极区(108)通过具有第二导电类型的体阱(113)与下层(103)分开。漏极隔离阱(112)和体阱(113)都接触下层(103)。漏极隔离阱(112)中的第二导电类型的平均掺杂剂密度小于体阱(113)中的第二导电类型的平均掺杂剂密度。(An integrated circuit (100) includes an extended drain MOS transistor (105). A substrate (101) of an integrated circuit (100) has an underlayer (103) of a first conductivity type. The drain well (106) of the extended drain MOS transistor (105) has a first conductivity type. The drain well (106) is separated from the lower layer (103) by a drain isolation well (112) of an opposite second conductivity type. The source region (108) of the extended drain MOS transistor (105) is separated from the lower layer (103) by a body well (113) having the second conductivity type. Both the drain isolation well (112) and the body well (113) contact the lower layer (103). The average dopant density of the second conductivity type in the drain isolation well (112) is less than the average dopant density of the second conductivity type in the bulk well (113).)

1. An integrated circuit, comprising:

a substrate;

a lower layer of semiconductor material in the substrate, the lower layer having a first conductivity type;

an extended drain Metal Oxide Semiconductor (MOS) transistor, comprising:

a drain well in the substrate, the drain well having the first conductivity type;

a source region in the substrate, the source region having the first conductivity type;

a drain isolation well in the substrate, the drain isolation well having a second conductivity type opposite the first conductivity type, wherein the drain isolation well separates the drain well from the lower layer, and the drain isolation well contacts the drain well and contacts the lower layer; and

a body well in the substrate, the body well having the second conductivity type, wherein the body well separates the source region from the underlying layer and contacts the source region and contacts the underlying layer, and wherein an average dopant density of the dopant of the second conductivity type in the drain isolation well is less than an average dopant density of the dopant of the second conductivity type in the body well.

2. The integrated circuit of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

3. The integrated circuit of claim 1, further comprising a MOS transistor in a well in the substrate, the well having the second conductivity type, wherein an average dopant density of dopants of the second conductivity type in the well is substantially equal to an average dopant density of dopants of the second conductivity type in the bulk well.

4. The integrated circuit of claim 1, further comprising a MOS transistor in a well in the substrate, the well having the second conductivity type, wherein an average dopant density of dopants of the second conductivity type in the well is substantially equal to an average dopant density of dopants of the second conductivity type in the drain isolation well.

5. The integrated circuit of claim 1, wherein the drain isolation well has a plurality of regions of higher dopant density of dopants of the second conductivity type laterally adjacent to one another, the drain isolation well between the regions of higher dopant density having a lower dopant density of dopants of the second conductivity type than the regions of higher dopant density, wherein lateral refers to a direction parallel to a top surface of the substrate.

6. The integrated circuit of claim 1, wherein the drain isolation well has a plurality of regions of higher dopant density of the dopant of the second conductivity type vertically adjacent to one another separated by a region of lower dopant density of the dopant of the second conductivity type, wherein vertical refers to a direction perpendicular to a top surface of the substrate.

7. The integrated circuit of claim 1, wherein the drain well extends under an element of a field oxide layer.

8. The integrated circuit of claim 1, further comprising a metal silicide on the source and drain contact regions, the drain contact region contacting the drain well, wherein a top surface of the substrate between a gate of the extended drain MOS transistor and the drain contact region is free of the metal silicide.

9. The integrated circuit of claim 1, wherein the drain well contacts the body well below a gate of the extended drain MOS transistor.

10. The integrated circuit of claim 1, wherein the drain well is separated from the body well by the drain isolation well below a gate of the extended drain MOS transistor.

11. The integrated circuit of claim 1, further comprising a MOS transistor in a well in the substrate, the well having the first conductivity type, wherein an average dopant density of dopants of the first conductivity type in the well is substantially equal to an average dopant density of dopants of the first conductivity type in the drain well.

12. A method of forming an integrated circuit, comprising:

obtaining a substrate comprising a lower layer of semiconductor material, the lower layer having a first conductivity type;

forming a drain isolation well in the substrate, the drain isolation well having a second conductivity type opposite the first conductivity type, wherein the drain isolation well contacts the lower layer;

forming a body well in the substrate, the body well having the second conductivity type, wherein the body well contacts the underlying layer, and wherein an average dopant density of the dopant of the second conductivity type in the drain isolation well is less than an average dopant density of the dopant of the second conductivity type in the body well;

forming a drain well in the substrate, the drain well having the first conductivity type, wherein the drain well contacts the drain isolation well and is separated from the lower layer by the drain isolation well; and

forming a source region in the substrate, the source region having the first conductivity type, wherein the source region contacts the body well and the source region is separated from the underlying layer by the body well.

13. The method of claim 12, wherein forming the drain isolation well comprises:

forming an implantation mask that exposes a region having a lateral dimension in one direction that is less than half a lateral dimension of the drain isolation well in the same direction, wherein lateral refers to a direction parallel to a top surface of the substrate;

implanting dopants of the second conductivity type into the substrate where exposed by the implantation mask;

removing the implantation mask; and

heating the substrate to diffuse and activate the dopant in the substrate.

14. The method of claim 12, wherein forming the drain isolation well comprises:

forming an implantation mask exposing a plurality of sub-regions in a region for the extended drain MOS transistor;

implanting dopants of said second conductivity type into said substrate where exposed by said implantation mask to form drain isolation implant regions, said drain isolation implant regions corresponding to said sub-regions;

removing the implantation mask; and

heating the substrate to diffuse and activate the dopant in the substrate such that the drain isolation well is continuous across the drain isolation implant region.

15. The method of claim 12, wherein forming the drain isolation well comprises:

implanting dopants of the second conductivity type into the substrate at a plurality of doses at different energies; and

heating the substrate to diffuse and activate the dopant in the substrate.

16. The method of claim 12, wherein the first conductivity type is p-type and the second conductivity type is n-type.

17. The method of claim 12, wherein forming the drain isolation well comprises:

forming an implantation mask that exposes a region for the extended drain MOS transistor and exposes a region for a well in the region for the MOS transistor;

implanting dopants of said second conductivity type into said substrate where exposed by said implant mask to form drain isolation implant regions in said region for said extended drain MOS transistor and well implant regions in said region for said MOS transistor;

removing the implantation mask; and

heating the substrate to diffuse and activate the dopants in the substrate to simultaneously form the drain isolation implant region and the well.

18. The method of claim 12, wherein forming the bulk well comprises:

implanting dopants of the second conductivity type into the substrate in the region for the extended drain MOS transistor and in the region for the well in the region for the MOS transistor; and

heating the substrate to diffuse and activate the dopants in the substrate to simultaneously form the body implant region and the well.

19. The method of claim 12, comprising forming elements of a field oxide layer in the substrate, wherein the drain well extends under the elements of the field oxide layer.

20. The method of claim 12, comprising:

forming a drain contact region in the substrate in the drain well;

forming a silicide blocking layer over the substrate between the gate of the extended drain MOS transistor and the drain contact region; and

forming a metal silicide on the drain contact region, the substrate between the gate and the drain contact region being free of the metal silicide.

Technical Field

The present disclosure relates to the field of integrated circuits. More particularly, the present disclosure relates to extended drain Metal Oxide Semiconductor (MOS) transistors in integrated circuits.

Background

Some integrated circuits include extended drain Metal Oxide Semiconductor (MOS) transistors in which the drain has the same conductivity type as the underlying substrate. The drain must be isolated from the substrate, which involves more process complexity or increased component area, or both. Providing isolation without degrading transistor performance and reliability parameters, such as on-current, off-current, threshold, and hot carrier reliability, has proven challenging.

Disclosure of Invention

The present disclosure introduces an integrated circuit that includes an extended drain Metal Oxide Semiconductor (MOS) transistor located above a lower layer in a substrate of the integrated circuit. The drain well and the underlying layer of the extended drain MOS transistor are of the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second conductivity type opposite to the first conductivity type. The source region of the extended drain MOS transistor is separated from the underlying layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. The average dopant density of the second conductivity type in the drain isolation well is less than the average dopant density of the second conductivity type in the bulk well.

Drawings

Fig. 1 is a cross section of an example integrated circuit including an extended drain MOS transistor with double well isolation.

Fig. 2A-2D are cross-sections of an integrated circuit including extended drain MOS transistors with double well isolation depicted in various stages of an example method of formation.

Fig. 3 is a cross section of another example integrated circuit including an extended drain MOS transistor with double well isolation.

Fig. 4A-4D are cross-sections of an integrated circuit including an extended drain MOS transistor with dual well isolation depicted in various stages of another example method of formation.

Fig. 5 is a cross section of yet another example integrated circuit including an extended drain MOS transistor with double well isolation.

Fig. 6A-6D are cross-sections of an integrated circuit including an extended drain MOS transistor with dual well isolation depicted in various stages of yet another example method of formation.

Detailed Description

The present disclosure is described with reference to the accompanying drawings. The drawings are not to scale and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Moreover, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure.

Furthermore, while some of the embodiments described herein are shown in two-dimensional views of various regions having depths and widths, it should be clearly understood that these regions are merely illustrative of what is actually part of a device having a three-dimensional structure. Thus, when fabricated on an actual device, these regions will have three dimensions, including length, width, and depth. The active devices of the present invention are not intended to be limited to the physical structures shown. These structures are included to demonstrate the utility and application of the present invention to the presently preferred embodiments.

The integrated circuit has a substrate with an underlying layer of semiconductor material having a first conductivity type. The integrated circuit includes an extended drain Metal Oxide Semiconductor (MOS) transistor located over a lower layer. The drain well of the extended drain MOS transistor has a first conductivity type. The drain well is separated from the lower layer by a drain isolation well that contacts the drain well and contacts the lower layer. The drain isolation well has a second conductivity type opposite the first conductivity type. The source region of the extended drain MOS transistor is separated from the underlying layer by a body well. The body well contacts the source region and the lower layer. The body well has a second conductivity type. The average dopant density of the second conductivity type in the drain isolation well is less than the average dopant density of the second conductivity type in the bulk well.

Terms such as top, above … …, above … …, below … …, and below … … may be used in this disclosure. These terms should not be construed as limiting the position or orientation of structures or elements, but rather should be used to provide a spatial relationship between structures or elements.

The term "substantially equal" as used in this disclosure refers in one aspect to equal amounts, such as average dopant density, within manufacturing tolerances encountered during integrated circuit fabrication. In another aspect, the term "substantially equal" as used in this disclosure refers to measurements of equal quantities (such as average dopant density) within measurement tolerances encountered during measurement of the quantities.

Fig. 1 is a cross section of an example integrated circuit including an extended drain MOS transistor with double well isolation. The integrated circuit 100 has a substrate 101, the substrate 101 having a top surface 102 and comprising an underlying layer 103 of semiconductor material having a first conductivity type. In this example, the first conductivity type is p-type, as shown in fig. 1. The substrate 101 may also include a field oxide layer 104 extending to the top surface 102. The field oxide layer 104 may laterally separate components and elements in the integrated circuit 100. For purposes of this disclosure, the terms "lateral" and "transversely" are understood to refer to a direction parallel to the plane of top surface 102. Similarly, the terms "vertical" and "vertically" are understood to refer to a direction perpendicular to the plane of the top surface 102. The terms lateral, transverse, vertical and vertical are similarly understood in the examples that follow. The field oxide layer 104 may have a Shallow Trench Isolation (STI) structure, wherein the field oxide layer 104 extends below the top surface 102 to a depth of 250 nanometers to 750 nanometers, has substantially straight sidewalls, and does not extend over more than 100 nanometers above the top surface 102, as depicted in fig. 1.

The integrated circuit 100 includes an extended drain MOS transistor 105 having a first polarity. In this example, the first polarity is p-channel. The extended drain MOS transistor 105 includes a drain well 106 having a first conductivity type in the substrate 101; in this example, the drain well 106 is p-type. For example, the drain well 106 may have a 10¹⁶cm^-3To 10¹⁸cm^-3To enable the extended drain MOS transistor 105 to operate at a desired voltage. For the purposes of this disclosure, the terms "dopant concentration of a first conductivity type" and "dopant of the first conductivity type" refer to providing a dopant of the first conductivity type. For the case where the first conductivity type is p-type, as in this example, boron, gallium and indium are dopants of the first conductivity type because they provide p-type conductivity. For the case where the first conductivity type is n-type, phosphorus, arsenic and antimony are dopants of the first conductivity type because they provide n-type conductivity. The extended drain MOS transistor 105 may optionally include a drain contact region 107 contacting the drain well 106 and extending to the top surface 102. The drain contact region 107 has a first conductivity type with an average dopant density of, for example, 10¹⁹cm^-3To 10²¹cm^-3To provide the desired low resistance connection to the drain well 106.

The extended drain MOS transistor 105 includes a source region 108 having a first conductivity type in the substrate 101; in this example, the source region 108 is p-type. The source region 108 and the drain contact region 107 may have substantially equal average densities of dopants of the first conductivity type. The extended drain MOS transistor 105 includes a gate dielectric layer 109 on the top surface 102 of the substrate 101 and a gate 110 on the gate dielectric layer 109. The gate dielectric layer 109 may comprise silicon dioxide, nitrided silicon dioxide, hafnium oxide, zirconium oxide or other dielectric materials suitable for MOS transistors. The gate dielectric layer 109 may have a thickness suitable for the desired gate-drain potential during operation of the integrated circuit 100. For example, the extended drain MOS transistor 105 may operate at a gate-drain potential of 8 volts to 100 volts. For example, the gate dielectric layer 109 may have a thickness of 3 to 10 nanometers. The gate 110 may comprise, for example, polysilicon, titanium nitride, tantalum nitride, or a metal silicide. The gate 110 extends from the source region 108 to the drain well 106, overlapping a portion of the drain well 106. In this example, the extended drain MOS transistor 105 may include an element of a field oxide layer 104a located between a drain contact region 107 and a portion of the drain well 106 that overlaps the gate 110. The drain well 106 extends under the elements of the field oxide layer 104a, as depicted in fig. 1. This drain configuration may advantageously allow the area (area) of the extended drain MOS transistor 105 to be reduced by providing a voltage drop across the portion of the drain well 106 under the element of the field oxide layer 104 a. The extended drain MOS transistor 105 may include gate sidewall spacers 111 on side surfaces of the gate 110. The gate sidewall spacers 111 may comprise, for example, silicon nitride, silicon dioxide, or silicon oxynitride.

The drain well 106 is vertically separated from the lower layer 103 by a drain isolation well 112, the drain isolation well 112 being located in the substrate 101 and having a second conductivity type opposite to the first conductivity type. Drain isolation well 112 contacts lower layer 103 and drain well 106. In this example, the drain isolation well 112 is n-type, as shown in fig. 1. The drain isolation well 112 may have, for example, 10¹⁵cm^-3To 10¹⁷cm^-3To provide a desired junction capacitance at the junction between drain isolation well 112 and drain well 106 and to provide a desired breakdown potential between drain isolation well 112 and drain well 106. For the purposes of this disclosure, the terms "dopant concentration of the second conductivity type" and "dopant of the second conductivity type" refer to providing a dopant of the second conductivity type. The dopant concentration of the second conductivity type in the drain isolation well 112 may decrease with vertical distance below the top surface 102 and may decrease with lateral distance from the drain contact region 107, which may achieve a desired junction capacitance and a desired breakdown potential by appropriate placement of the junction between the drain isolation well 112 and the drain well 106.

The source region 108 is vertically separated from the lower layer 103 by a body well 113, the body well 113 being located in the substrate 101 and having the second conductivity type. The body well 113 contacts the lower layer 103 and the source region 108. In this example, the bulk well 113 is n-type, as shown in FIG. 1. The bulk well 113 may have, for example, 10¹⁶cm^-3To 10¹⁸cm^-3To provide a desired threshold potential for the extended drain MOS transistor 105. Drain isolation wellThe average dopant density of the second conductivity type of 112 is less than the average dopant density of the second conductivity type of the bulk well 113. In this example, the body well 113 may contact the drain well 106 under the gate 110, as shown in fig. 1, which may advantageously reduce the area of the extended drain MOS transistor 105. The body well 113 may optionally extend laterally around the drain well 106, as depicted in fig. 1. The construction of the extended drain MOS transistor 105 (with the drain well 106 isolated from the underlying layer 103 by the drain isolation well 112, and with the source region 108 isolated from the underlying layer 103 by the body well 113, wherein both the drain isolation well 112 and the body well 113 contact the underlying layer 103) may advantageously reduce the area of the extended drain MOS transistor 105 by eliminating the need for a single isolation structure that extends completely under the extended drain MOS transistor 105. The extended drain MOS transistor 105 may optionally include a body contact region 114 that contacts the well 113 and extends to the top surface 102. The body contact regions 114 have a second conductivity type with an average dopant density of, for example, 10¹⁹cm^-3To 10²¹cm^-3To provide the desired low resistance connection to the body well 113.

The extended drain MOS transistor 105 is depicted in fig. 1 as having an asymmetric configuration, with the source region 108 located on one side of the drain well 106. In an alternative version of this example, the extended drain MOS transistor 105 may have a symmetric configuration, with the source regions 108 located on opposite sides of the drain well 106.

The integrated circuit 100 may optionally include a first low voltage MOS transistor 115 having a first polarity and a second low voltage MOS transistor 116 having a second polarity opposite the first polarity. In this example, the first low voltage MOS transistor 115 is a p-channel, and the second low voltage MOS transistor 116 is an n-channel. For the purposes of this disclosure, the term "low voltage" as applied to a MOS transistor refers to a MOS transistor that operates at a drain-source potential of less than 3 volts. Such transistors are commonly used in logic circuits and Static Random Access Memory (SRAM) circuits. The first low voltage MOS transistor 115 has a first low voltage gate structure 117 on the top surface 102 of the substrate 101, a first source 118 in the substrate 101, and a first drain 119 in the substrate 101. The first low voltage MOS transistor 115 is disposed in the first well 120. The first well 120 has a second conductivity type, in this example n-type, as shown in fig. 1. The first well 120 may have an average dopant density of the second conductivity type substantially equal to the bulk well 113.

The second low voltage MOS transistor 116 has a second low voltage gate structure 121 on the top surface 102 of the substrate 101, a second source 122 in the substrate 101, and a second drain 123 in the substrate 101. The second low voltage MOS transistor 116 is disposed in the second well 124. The second well 124 has a first conductivity type, in this example p-type, as shown in fig. 1. The second well 124 may have an average dopant density of the first conductivity type substantially equal to the drain well 106. In the semiconductor industry, a well having the same conductivity type as the substrate is sometimes referred to simply as the substrate, and not the well at all. However, as used herein, the term "well" is intended to mean either an n-type well or a p-type well, and includes wells that may have the same conductivity type as the substrate.

The integrated circuit 100 may optionally include a first high voltage MOS transistor 125 having a first polarity (in this example, a p-channel) and a second high voltage MOS transistor 126 having a second polarity (in this example, an n-channel). For the purposes of this disclosure, the term "high voltage" as applied to a MOS transistor refers to a MOS transistor operating at a drain-source potential of 3 to 6 volts. Such transistors are commonly used in input/output circuits and analog circuits. The first high voltage MOS transistor 125 has a first high voltage gate structure 127 on the top surface 102 of the substrate 101, a third source 128 in the substrate 101, and a third drain 129 in the substrate 101. The first high voltage MOS transistor 125 is disposed in the third well 130. The third well 130 has a second conductivity type, which in this example is n-type, as shown in fig. 1. The third well 130 may have an average dopant density of the second conductivity type substantially equal to the drain isolation well 112.

The second high voltage MOS transistor 126 has a second high voltage gate structure 131 on the top surface 102 of the substrate 101, a fourth source 132 in the substrate 101, and a fourth drain 133 in the substrate 101. The second high voltage MOS transistor 126 is disposed in the fourth well 134. The fourth well 134 has the first conductivity type, in this example p-type, as shown in fig. 1.

The integrated circuit 100 may include a dielectric layer 135 over the top surface 102 of the substrate 101. The dielectric layer 135 may represent a pre-metal dielectric (PMD) layer having one or more sublayers, such as a PMD liner of silicon nitride on the top surface 102, a layer of silicon dioxide, phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG), and a capping layer of silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride. The integrated circuit 100 may also include contacts 136 extending through the dielectric layer 135 to provide electrical connections to the extended drain MOS transistor 105, the first low voltage MOS transistor 115, the second low voltage MOS transistor 116, the first high voltage MOS transistor 125, and the second high voltage MOS transistor 126. The contact 136 may include a liner of titanium and titanium nitride or tantalum nitride with a tungsten core. The integrated circuit 100 may also include interconnects 137 on the dielectric layer 135 to make electrical connections to the contacts 136. For example, the interconnect may comprise aluminum or copper.

Fig. 2A-2D are cross-sections of an integrated circuit including extended drain MOS transistors with double well isolation depicted in various stages of an example method of formation. Referring to fig. 2A, forming an integrated circuit 200 includes obtaining a substrate 201. The substrate 201 may be implemented as a bulk semiconductor wafer, a semiconductor wafer with an epitaxial layer, a silicon-on-insulator (SOI) wafer, or other structure suitable for forming the integrated circuit 200. The substrate 201 has a top surface 202 and includes an underlying layer 203 of semiconductor material having a first conductivity type below the top surface 202. In this example, the first conductivity type is p-type, as shown in fig. 2A.

The substrate 201 includes a region for the extended drain MOS transistor 205, a region for the first low voltage MOS transistor 215, a region for the second low voltage MOS transistor 216, a region for the first high voltage MOS transistor 225, and a region for the second high voltage MOS transistor 226. The terms "low voltage" and "high voltage" are used as described with reference to fig. 1.

A protective layer 238 may be formed on the top surface 202. The protective layer 238 may include silicon dioxide formed by a thermal oxidation process. For example, the protective layer 238 may have a thickness of 5 nanometers to 25 nanometers. The protective layer 238 is sometimes referred to as a pad layer or pad oxide layer. The protective layer 238 may advantageously reduce contamination of the substrate 201 during subsequent manufacturing operations. Other compositions and methods of formation of the protective layer 238 are within the scope of this example.

A first implantation mask 239 is formed over the protection layer 238. The first implantation mask 239 exposes the protection layer 238 in a region 240 for the subsequently formed drain isolation well 212 (shown in fig. 2B) in the region for extending the drain MOS transistor 205. In this example, the region 240 may have a lateral dimension in a direction parallel to the plane of fig. 2A that is less than half the lateral dimension of the subsequently formed drain isolation well 212 in the same direction. The first implant mask 239 may optionally expose a region for a subsequently formed third well 230 (as shown in fig. 2B) in the region for the first high voltage MOS transistor 225. The first implant mask 239 may be formed of photoresist using a photolithography process. Alternatively, first implant mask 239 may be formed of a hard mask material (such as silicon oxynitride). Other materials and processes for forming first implant mask 239 are within the scope of this example.

In the region exposed by the first implantation mask 239, a first dopant 241 is implanted into the substrate 201 to form a drain isolation implant region 243 in the region for the extended drain MOS transistor 205 and a well implant region 244 in the region for the first high voltage MOS transistor 225. The first dopants 241 are dopants of the second conductivity type, which in this example are n-type dopants, such as phosphorus. May be as 10¹²cm^-2To 10¹⁴cm^-2The first dopant 241 is implanted at a dose to provide a desired average dopant density of the second conductivity type in the subsequently formed drain isolation well 212 and the subsequently formed third well 230. The first dopants 241 may be implanted at an energy sufficient to pass a substantial portion of the first dopants 241 through the protective layer 238 and into the substrate 201. For example, the first dopant 241 may be implanted at an energy of 20 kilo electron volts (keV) to 100 keV.

The first implantation mask 239 is removed after the implantation of the first dopants 241. First implant mask 239 may be removed by a plasma etch process followed by a wet etch clean process.

Referring to fig. 2B, the substrate 201 is heated by a thermal process 245 to diffuse and activate the first dopant 241 of fig. 2A in the drain isolation implant region 243 and the well implant region 244 of fig. 2A to form the drain isolation well 212 and the third well 230, respectively. The thermal process 245 may have a thermal profile sufficient to diffuse the first dopant 241 such that the lateral dimension of the drain isolation well 212 in a direction parallel to the plane of fig. 2B is more than twice the lateral dimension of the region 240 exposed by the first implantation mask 230 of fig. 2A in the same direction. For example, the thermal process 245 may heat the substrate 201 to 1080 ℃ to 1120 ℃ for 300 minutes to 400 minutes. The thermal process 245 may be implemented as a furnace process using an ambient environment including some oxygen to grow additional silicon dioxide on the top surface 202 of the substrate 201. As a result of the thermal process 245, the density of the first dopant 241 in the drain isolation well 212 at the junction between the drain isolation well 212 and the lower layer 203 may be less than the density in the region surrounding the drain isolation implant region 243.

Referring to fig. 2C, a field oxide layer 204 is formed extending into the substrate 201. The field oxide layer 204 may be formed by an STI process such that the field oxide layer 204 has an STI structure as depicted in fig. 2C. An example STI process includes forming a Chemical Mechanical Polishing (CMP) stop layer of silicon nitride over the substrate 201, etching an isolation trench through the CMP stop layer and into the substrate 201, and filling the isolation trench with silicon dioxide using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process using Tetraethylorthosilicate (TEOS), a High Density Plasma (HDP) process, a High Aspect Ratio Process (HARP) using TEOS and ozone, an atmospheric chemical vapor deposition (APCVD) process using silane, or a sub-atmospheric pressure chemical vapor deposition (SACVD) process using dichlorosilane. Excess silicon dioxide is removed from over the CMP stop layer by an oxide CMP process, and the CMP stop layer is subsequently removed, leaving the field oxide layer 204. In this example, elements of the field oxide layer 204a may be formed in the drain isolation well 212.

The fourth well 234 may be formed in a region for the second high voltage MOS transistor 226. The fourth well 234 has the first conductivity type, in this example, p-type, as shown in fig. 2C.

A second implant mask 246 is formed over the protective layer 238. The second implantation mask 246 exposes the protection layer 238 in a region for the subsequently formed body well 213 in a region for extending the drain MOS transistor 205. The second implantation mask 246 may optionally expose a region for the subsequently formed first well 220 in a region for the first low voltage MOS transistor 215. For example, the second implant mask 246 may comprise a photoresist or hard mask material and may be formed by a similar process as the first implant mask 239 of fig. 2A.

In the regions exposed by the second implantation mask 246, a second dopant 247 is implanted into the substrate 201. The second dopants 247 are dopants of the second conductivity type, in this example, n-type dopants such as phosphorus and arsenic. The second dopant 247 may be implanted in more than one implantation step, where the main step has a dose of 10¹²cm-²To 10¹⁴cm-²Is implanted at an energy of 400keV to 600 keV. The additional implantation step of the second dopant 247 may have a lower dose and lower energy to set the threshold potential for the extended drain MOS transistor 205 and the first low voltage MOS transistor 215.

The second implantation mask 246 is removed after the second dopant 247 implantation. The second implant mask 246 may be removed by a process similar to the process used to remove the first implant mask 239 of fig. 2A.

The substrate 201 is then heated to activate the second dopants 247 implanted into the substrate 201 to form the body well 213 and the first well 220. The substrate 201 may be heated by a rapid thermal process to reduce unwanted diffusion of the second dopants 247 and the first dopants 241 of fig. 2A in the drain isolation well 212. For example, the substrate 201 may be heated to 1000 ℃ to 1100 ℃ for 20 seconds to 60 seconds. The body well 213 has a higher average dopant density of the second conductivity type than the drain isolation well 212.

Referring to fig. 2D, in the region for extending the drain MOS transistor 205, a drain well 206 is formed in the substrate 201 such that the drain well 206 is vertically separated from the lower layer 203 by a drain isolation well 212. The drain well 206 of this example is formed so as to extend under the elements of the field oxide layer 204 a. Drain well 206 has a first conductivity type; in this example, the drain well 206 is p-type. In the region for the second low voltage MOS transistor 216, a second well 224 may be formed in the substrate 201. The second well 224 has the first conductivity type and may be formed to have a similar distribution of dopants of the first conductivity type as the drain well 206.

Drain well 206 and second well 224 may be formed simultaneously by implanting a dopant of the first conductivity type, such as boron, into substrate 201 using an appropriate implantation mask (not shown in fig. 2D). The dopant of the first conductivity type may be implanted in more than one implantation step, the main step having a dose of 10¹²cm^-2To 10¹⁴cm^-2Is implanted at an energy of 200keV to 400 keV. The additional implantation step of dopants of the first conductivity type may have a lower dose and lower energy to set the threshold potential for the second low voltage MOS transistor 216. The substrate 201 is then heated to activate the dopants of the first conductivity type implanted into the substrate 201 to form the drain well 206 and the second well 224. The substrate 201 may be heated by a process similar to that described with reference to fig. 2C. Forming drain well 206 and second well 224 may reduce the manufacturing cost of integrated circuit 200 as compared to forming drain well 206 and second well 224 separately. In some versions of the example, activating the dopants of the first conductivity type may be performed simultaneously with activating the second dopants 247 of fig. 2C.

The protective layer 238 of fig. 2C is then removed. For example, the protective layer 238 may be removed by a wet etching process using a buffered dilute aqueous solution of hydrofluoric acid.

In the region for the extended drain MOS transistor 205, a gate dielectric layer 209 is formed on the top surface 202 of the substrate 201. The gate dielectric layer 209 may be formed by a thermal oxidation process, or by depositing an oxide material via, for example, an Atomic Layer Deposition (ALD) process. The gate 210 of the extended drain MOS transistor 205 is formed on the gate dielectric layer 209. The gate 210 may be formed, for example, by: a polysilicon layer is formed on the gate dielectric layer 209 and then patterned using an etch mask and a Reactive Ion Etch (RIE) process. Gate sidewall spacers 211 may be formed on the side surfaces of the gate 210. The gate sidewall spacers 211 may be formed by: one or more conformal layers of silicon nitride, silicon dioxide, or silicon oxynitride are formed over the gate 210 and removed from horizontal surfaces of the gate 210 and the substrate 201 using an anisotropic etch process, leaving the one or more conformal layers on side surfaces of the gate 210 to provide gate sidewall spacers 211.

In the region for the first low voltage MOS transistor 215, a first low voltage gate structure 217 is formed on the top surface 202 of the substrate 201. In the region for the second low voltage MOS transistor 216, a second low voltage gate structure 221 is formed on the top surface 202 of the substrate 201. In the region for the first high voltage MOS transistor 225, a first high voltage gate structure 227 is formed on the top surface 202 of the substrate 201. In the region for the second high voltage MOS transistor 226, a second high voltage gate structure 231 is formed on the top surface 202 of the substrate 201. Part or all of the first low voltage gate structure 217, the second low voltage gate structure 221, the first high voltage gate structure 227, and the second high voltage gate structure 231 may be formed simultaneously with the gate dielectric layer 209, the gate 210, and the gate sidewall spacer 211 of the extended drain MOS transistor 205.

A source region 208 is formed in the substrate 201 in contact with the body well 213 adjacent to the gate 210 and positioned opposite the drain well 206. Source region 208 has a first conductivity type; in this example, source region 208 is p-type. The source region 208 may be formed by implanting a dopant of the first conductivity type, such as boron, in two or more implantation steps. A first portion of the source region 208 may be formed by implanting a first portion of the dopant of the first conductivity type prior to forming the gate sidewall spacers 211, and a second portion of the source region 208 may be formed by implanting a second portion of the dopant of the first conductivity type after forming the gate sidewall spacers 211. For example, the total dose of dopants of the first conductivity type may be 1 × 10¹⁴cm^-2To 1X 10¹⁶cm^-2. The substrate 201 is then heated to activate the dopants of the first conductivity type implanted into the substrate 201 to form the source regions 208. The substrate 201 may be heated by a spike annealing process to reduce unwanted diffusion of the already activated dopants into the substrate 201. For example, the substrate 201 may be heated to 950 ℃ to 1100 ℃ for 1 second to 10 seconds.

A drain contact region 207 may optionally be formed in the substrate 201, contacting the drain well 206. The drain contact region 207 has a first conductivity type; in this example, the drain contact region 207 is p-type. The drain contact region 207 may be formed simultaneously with the source region 208.

In the region for the first low voltage MOS transistor 215, a first source 218 and a first drain 219 are formed in the substrate 201 on opposite sides of the first low voltage gate structure 217. A third source 228 and a third drain 229 are formed in the substrate 201 on opposite sides of the first high voltage gate structure 227 in the region for the first high voltage MOS transistor 225. The first source 218, the first drain 219, the third source 228, and the third drain 229 have the first conductivity type; in this example, the first source 218, the first drain 219, the third source 228, and the third drain 229 are p-type. The first source 218, the first drain 219, the third source 228, and the third drain 229 may be formed simultaneously with the source region 208.

Body contact regions 214 may optionally be formed in the substrate 201, contacting the body wells 213. The body contact regions 214 have a second conductivity type; in this example, the body contact regions 214 are n-type. Body contact regions 214 may be formed by implanting dopants of the second conductivity type, such as phosphorus, arsenic and antimony, into substrate 201, optionally in two or more implantation steps. For example, the total dose of the dopant of the second conductivity type may be 1 × 10¹⁴cm^-2To 1X 10¹⁶cm^-2. The substrate 201 is then heated to activate the dopants of the second conductivity type implanted into the substrate 201 to form the body contact regions 214. The substrate 201 may be heated by a spike annealing process to reduce unwanted diffusion of the already activated dopants in the substrate 201. For example, the substrate 201 may be heated to 950 ℃ to 1100 ℃ for 1 second to 10 seconds.

In the region for the second low voltage MOS transistor 216, a second source 222 and a second drain 223 are formed in the substrate 201 on opposite sides of the second low voltage gate structure 221. In the region for the second high voltage MOS transistor 226, a fourth source 232 and a fourth drain 233 are formed in the substrate 201 on opposite sides of the second high voltage gate structure 231. The second source electrode 222, the second drain electrode 223, the fourth source electrode 232, and the fourth drain electrode 233 have the second conductive type; in this example, the second source 222, the second drain 223, the fourth source 232, and the fourth drain 233 are n-type. The second source electrode 222, the second drain electrode 223, the fourth source electrode 232, and the fourth drain electrode 233 may be formed simultaneously with the body contact region 214.

Formation of the integrated circuit 200 may continue by forming a dielectric layer (not shown in fig. 2D) over the top surface 202 of the substrate 201, which is similar to the dielectric layer 135 of fig. 1. Contacts (not shown in fig. 2D) may be formed through the dielectric layer, similar to contacts 136 of fig. 1. An interconnect (not shown in fig. 2D) may be formed over the dielectric layer to make an electrical connection to the contact, similar to interconnect 137 of fig. 1.

Fig. 3 is a cross section of another example integrated circuit including an extended drain MOS transistor with double well isolation. The integrated circuit 300 has a substrate 301, the substrate 301 having a top surface 302 and comprising an underlying layer 303 of semiconductor material having a first conductivity type. In this example, the first conductivity type is p-type, as shown in fig. 3. The substrate 301 may also include a field oxide layer 304 extending to the top surface 302. The field oxide layer 304 may have STI structures, as depicted in fig. 3.

The integrated circuit 300 includes an extended drain MOS transistor 305 having a first polarity (in this example, a p-channel). The extended drain MOS transistor 305 includes a drain well 306 having a first conductivity type in the substrate 301; in this example, the drain well 306 is p-type. The drain well 306 may have an average dopant density of the first conductivity type as disclosed with reference to the drain well 106 of fig. 1. The extended drain MOS transistor 305 may optionally include a drain contact region 307 that contacts the drain well 306 and extends to the top surface 302. The drain contact region 307 has a first conductivity type with an average dopant density of the first conductivity type as disclosed with reference to the drain contact region 107 of fig. 1.

The extended drain MOS transistor 305 includes a source region 308 having a first conductivity type in the substrate 301; in this example, the source region 308 is p-type. In this example, the source regions 308 are symmetrically arranged on opposite sides of the drain well 306, as depicted in fig. 3. The source region 308 and the drain contact region 307 may have a similar average density of dopants of the first conductivity type. Extended drain MOS transistor 305 includes a gate dielectric layer 309 on top surface 302 of substrate 301 and a gate 310 on gate dielectric layer 309. In this example, the gate 310 and the gate dielectric layer 309 are symmetrically arranged on opposite sides of the drain well 306, as depicted in fig. 3. Gate 310 and gate dielectric layer 309 may comprise the materials disclosed with reference to gate 110 and gate dielectric layer 109 of fig. 1. Gate 310 extends from source region 308 toward drain well 306; in this example, the gate 310 does not overlap a portion of the drain well 306. The extended drain MOS transistor 305 may include gate sidewall spacers 311 on the side surfaces of the gate 310. A silicide block layer 348 is disposed over the top surface 302 of the substrate 301 extending from the gate 310 to the drain contact region 307. Silicide block layer 348 may comprise one or more layers of silicon dioxide, silicon nitride, silicon oxynitride, or other material suitable for preventing the formation of a metal silicide on top surface 302. In some versions of this example, the silicide block layer 348 may appear as an extension of the gate sidewall spacer 311.

The drain well 306 is vertically separated from the lower layer 303 by a drain isolation well 312, the drain isolation well 312 being located in the substrate 301 and having a second conductivity type opposite the first conductivity type. In this example, the drain isolation well 312 is n-type, as shown in fig. 3. Drain isolation well 312 contacts lower layer 303 and drain well 306. The drain isolation well 312 may have, for example, 10¹⁵cm^-3To 10¹⁷cm^-3Of the second conductivity type. As depicted in fig. 3, the drain isolation well 312 may laterally surround the drain well 306 and extend completely below the drain well 306. In this example, the drain isolation well 312 may have a higher second conductivity typeThe dopant densities of the types are laterally adjacent to each other such that two or more regions 312a, wherein the drain isolation well between the regions 312a has a lower dopant density of the second conductivity type than the regions 312 a. The higher dopant density region 312a may provide a more uniform distribution of dopants of the second conductivity type, which may advantageously achieve a desired junction capacitance and a desired breakdown potential of the drain well 306 around the lateral perimeter of the drain well 306, as compared to the laterally reduced dopant concentration of the drain isolation well 112 of fig. 1.

The source region 308 is vertically separated from the lower layer 303 by a body well 313, the body well 313 being located in the substrate 301 and having the second conductivity type. In this example, the bulk well 313 is n-type, as shown in FIG. 3. The body well 313 contacts the lower layer 303 and the source region 308. The bulk well 313 may have, for example, 10¹⁶cm^-3To 10¹⁸cm^-3Of the second conductivity type. The average dopant density of the second conductivity type of the drain isolation well 312 is less than the average dopant density of the second conductivity type of the bulk well 313. In this example, the bulk well 313 may be separated from the drain well 306 under the gate 310 by a drain isolation well 312, which may advantageously enable the extended drain MOS transistor 305 to operate at a higher potential than a similar transistor in which the bulk well contacts the drain well, as depicted in fig. 3. The construction of the extended drain MOS transistor 305 (with the drain well 306 isolated from the lower layer 303 by the drain isolation well 312 and with the source region 308 isolated from the lower layer 303 by the body well 313, wherein both the drain isolation well 312 and the body well 313 contact the lower layer 303) may advantageously reduce the area of the extended drain MOS transistor 305 by eliminating the need for a single isolation structure that extends completely under the extended drain MOS transistor 305. Extended drain MOS transistor 305 may optionally include a body contact region 314 that contacts well 313 and extends to top surface 302. The body contact regions 314 have a second conductivity type with an average dopant density of, for example, 10¹⁹cm^-3To 10²¹cm^-3To provide the desired low resistance connection to the body well 313.

The extended drain MOS transistor 305 is depicted in fig. 3 as having a symmetric configuration, with source regions 308 located on both sides of the drain well 306. In an alternate version of this example, the extended drain MOS transistor 305 may have an asymmetric configuration, with the source region 308 located on one side of the drain well 306.

In this example, a metal silicide 349 is disposed on the drain contact region 307, on the source region 308, and on the body contact region 314. Metal suicide 349 may advantageously provide reduced resistance connections to drain contact region 307, source region 308, and body contact regions 314. The top surface 302 between the drain contact region 307 and the gate 310 is free of metal silicide 349 due to the presence of the silicide block 348. The metal silicide 349 may include, for example, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, or tungsten silicide.

The integrated circuit 300 may optionally include a first low voltage MOS transistor 315 having a first polarity (in this example, a p-channel). The first low voltage MOS transistor 315 has a first low voltage gate structure 317 on the top surface 302 of the substrate 301, a first source 318 in the substrate 301, and a first drain 319 in the substrate 301 with a metal silicide 349 on the first source 318 and the first drain 319. The first low voltage MOS transistor 315 is disposed in a first well 320, the first well 320 having a second conductivity type, in this example n-type, as shown in fig. 3. The first well 320 may have an average dopant density of the second conductivity type substantially equal to that of the body well 313.

The integrated circuit 300 may also optionally include a second low voltage MOS transistor 316 having a second polarity (in this example, an n-channel). The second low voltage MOS transistor 316 has a second low voltage gate structure 321 on the top surface 302 of the substrate 301, a second source 322 in the substrate 301, and a second drain 323 in the substrate 301, with a metal silicide 349 on the second source 322 and the second drain 323. The second low voltage MOS transistor 316 is disposed in a second well 324, the second well 324 having the first conductivity type, in this example, p-type, as shown in fig. 3. The second well 324 may have an average dopant density of the first conductivity type substantially equal to the drain well 306.

The integrated circuit 300 may optionally include a first high voltage MOS transistor 325 having a first polarity (in this example, a p-channel). The first high voltage MOS transistor 325 has a first high voltage gate structure 327 on the top surface 302 of the substrate 301, a third source 328 in the substrate 301, and a third drain 329 in the substrate 301, with a metal silicide 349 on the third source 328 and the third drain 329. The first high voltage MOS transistor 325 is disposed in a third well 330, the third well 330 having a second conductivity type, in this example n-type, as shown in fig. 3. The third well 330 may have an average dopant density of the second conductivity type substantially equal to the drain isolation well 312.

The integrated circuit 300 may also optionally include a second high voltage MOS transistor 326 having a second polarity (in this example, an n-channel). The second high voltage MOS transistor 326 has a second high voltage gate structure 331 on the top surface 302 of the substrate 301, a fourth source 332 in the substrate 301, and a fourth drain 333 in the substrate 301, with a metal silicide 349 on the fourth source 332 and the fourth drain 333. The second high voltage MOS transistor 326 is disposed in a fourth well 334, the fourth well 334 having the first conductivity type, in this example, p-type, as shown in fig. 3.

Integrated circuit 300 may include a dielectric layer 335 over top surface 302 of substrate 301. The dielectric layer 335 may represent a PMD layer similar to the PMD layer disclosed with reference to fig. 1. Integrated circuit 300 may also include contacts 336 extending through dielectric layer 335 to metal silicide 349 to provide electrical connections to extended drain MOS transistor 305, first low voltage MOS transistor 315, second low voltage MOS transistor 316, first high voltage MOS transistor 325, and second high voltage MOS transistor 326. Contact 336 may have the structure disclosed with reference to contact 136 of fig. 1. Integrated circuit 300 may also include interconnects 337 on dielectric layer 335 to make electrical connections to contacts 336.

Fig. 4A-4D are cross-sections of an integrated circuit including an extended drain MOS transistor with dual well isolation depicted in various stages of another example method of formation. Referring to fig. 4A, formation of integrated circuit 400 includes obtaining a substrate 401, which may be implemented as disclosed with reference to substrate 201 of fig. 2A. The substrate 401 has a top surface 402 and includes an underlying layer 403 of semiconductor material below the top surface 402. The lower layer 403 has a first conductivity type, in this example p-type, as shown in fig. 4A.

The substrate 401 includes a region for the extended drain MOS transistor 405, a region for the first low voltage MOS transistor 415, a region for the second low voltage MOS transistor 416, a region for the first high voltage MOS transistor 425, and a region for the second high voltage MOS transistor 426. The terms "low voltage" and "high voltage" are used as described with reference to fig. 1.

A protective layer 438 may be formed on the top surface 402. The protective layer 438 may have a composition and structure as described with reference to the protective layer 238 of fig. 2A. A first implant mask 439 is formed over the protective layer 438. The first implantation mask 439 exposes the protective layer 438 in a region for the subsequently formed drain isolation well 412 (shown in fig. 4B) in a region for extending the drain MOS transistor 405. In this example, the first implantation mask 439 exposes the protection layer 438 in a plurality of sub-regions 450 in the region for extending the drain MOS transistor 405. The sub-regions 450 may be separate from each other or may be connected out of the plane of fig. 2A. The first implantation mask 439 may optionally expose a region for a subsequently formed third well 430 (shown in fig. 4B) in the region for the first high voltage MOS transistor 425. First implant mask 439 may be formed as disclosed with reference to first implant mask 239 of figure 2A.

A first dopant 441 is implanted into the substrate 401 in the region exposed by the first implant mask 439 to form a plurality of drain isolation implant regions 443 in the region for the extended drain MOS transistor 405 and to form a well implant region 444 in the region for the first high voltage MOS transistor 425. In this example, the drain isolation implant region 443 corresponds to the sub-region 450 exposed by the first implant mask 439, as depicted in fig. 4A. The first dopant 441 is a dopant of the second conductivity type, in this example an n-type dopant such as phosphorus. May be as 10¹²cm^-2To 10¹⁴cm^-2Is implanted with a first dopant 441 to be raised in the subsequently formed drain isolation well 412 and the subsequently formed third well 430Providing a desired average dopant density of the second conductivity type. Having a plurality of drain isolation implant regions 443 may provide a first average dose of first dopants 441 in drain isolation implant regions 443 and may provide a second average dose of first dopants 441 in well implant regions 444 in the area for first high voltage MOS transistor 425, where the first desired average dose of first dopants 441 in drain isolation implant regions 443 is lower than the second average dose of first dopants 441 in well implant regions 444. The first dopants 441 may be implanted at an energy sufficient to drive a substantial portion of the first dopants 441 through the protective layer 438 and into the substrate 401. The first implantation mask 439 is removed after the first dopants 441 are implanted.

Referring to fig. 4B, the substrate 401 is heated by a thermal process 445 to diffuse and activate the first dopant 441 of fig. 4A in the drain isolation implant region 443 and the well implant region 444 of fig. 4A to form the drain isolation well 412 and the third well 430, respectively. The thermal process 445 may have a thermal profile sufficient to diffuse the first dopant 441 sufficient to form a drain isolation well 412 that is continuous across the drain isolation implant region. Having a plurality of drain isolation implant regions 443 may result in a plurality of regions 412a laterally adjacent to each other of a higher dopant density of the second conductivity type in the drain isolation well 412, where each region 412a corresponds to a drain isolation implant region 443. For example, the thermal process 445 may heat the substrate 401 to 1080 ℃ to 1120 ℃ for 300 minutes to 400 minutes. The thermal process 445 may be performed as disclosed with reference to fig. 22B. The average density of the first dopants 441 in the drain isolation well 412 may be lower than the average density of the first dopants 441 in the third well 430.

Referring to fig. 4C, a field oxide layer 404 is formed extending into the substrate 401. The field oxide layer 404 may be formed by an STI process such that the field oxide layer 404 has an STI structure as depicted in fig. 4C. The fourth well 434 may be formed in a region for the second high voltage MOS transistor 426. The fourth well 434 has the first conductivity type, in this example, p-type, as shown in fig. 4C.

A second implantation mask 446 is formed over the protective layer 438. A second implantation mask 446 is used for extending the drain MOS transistor 405The protective layer 438 is exposed in a region of the region for the subsequently formed body well 413. The second implantation mask 446 may optionally expose a region for the subsequently formed first well 420 in a region for the first low voltage MOS transistor 415. The second implant mask 446 may be formed by a process similar to the first implant mask 439 of fig. 4A. A second dopant 447 is implanted into the substrate 401 in the areas exposed by the second implant mask 446. In this example, the second dopants 447 are dopants of a second conductivity type, n-type dopants such as phosphorus and arsenic. The second dopant 447 may be implanted in more than one implant step, with the main step having a dose of 10¹²cm^-2To 10¹⁴cm^-2Is implanted at an energy of 400keV to 600 keV. The additional implantation step of the second dopant 447 may have a lower dose and lower energy to set the threshold potential for the extended drain MOS transistor 405 and the first low voltage MOS transistor 415. The second implantation mask 446 is removed after the implantation of the second dopants 447. The second implant mask 446 may be removed by a process similar to that used to remove the first implant mask 439 of figure 4A.

The substrate 401 is then heated to activate the second dopant 447 implanted into the substrate 401 to form the body well 413 and the first well 420. The substrate 401 may be heated by a rapid thermal process to reduce unwanted diffusion of the second dopant 447 and the first dopant 441 of fig. 4A in the drain isolation well 412. The body well 413 has a higher average dopant density of the second conductivity type than the drain isolation well 412.

Referring to fig. 4D, a drain well 406 is formed in the substrate 401 in the region for the extended drain MOS transistor 405 such that the drain well 406 is vertically separated from the lower layer 403 by a drain isolation well 412. The drain well 406 has a first conductivity type; in this example p-type. In the region for the second low voltage MOS transistor 416, a second well 424 may be formed in the substrate 401. The second well 424 has the first conductivity type and may be formed with a similar distribution of dopants of the first conductivity type as the drain well 406. Drain well 406 and second well 424 may be formed simultaneously as disclosed with reference to drain well 206 and second well 224 of fig. 2D, thereby obtaining similar advantages of reduced manufacturing costs. The protective layer 438 of fig. 4C is then removed.

A gate dielectric layer 409 is formed on the top surface 402 of the substrate 401 in the region for the extended drain MOS transistor 405. A gate 410 of the extended drain MOS transistor 405 is formed on the gate dielectric layer 409. Gate 410 and gate dielectric layer 409 may be formed as disclosed with reference to gate 210 and gate dielectric layer 209 of fig. 2D. Gate sidewall spacers 411 may be formed on the side surfaces of the gate 410. The gate sidewall spacers 411 may be formed as disclosed with reference to the gate sidewall spacers 211 of fig. 2D. A silicide block 448 is formed over the top surface 402 of the substrate 401 extending from the gate 410 to the drain contact region 407. Silicide block layer 448 may be formed by: one or more layers of silicon dioxide, silicon nitride, or silicon nitride are formed over gate 410 and over top surface 402 of substrate 401, and then one or more layers are patterned using a plasma etch process to remove one or more layers l where exposed by an etch mask (not shown in fig. 4D). Alternatively, silicide-block layer 448 may be formed by patterning a conformal layer used to form gate sidewall spacers 411, such that silicide-block layer 448 is implemented as an extension of gate sidewall spacers 411.

In the region for the first low voltage MOS transistor 415, a first low voltage gate structure 417 is formed on the top surface 402 of the substrate 401. In the region for the second low voltage MOS transistor 416, a second low voltage gate structure 421 is formed on the top surface 402 of the substrate 401. In the region for first high voltage MOS transistor 425, a first high voltage gate structure 427 is formed on top surface 402 of substrate 401. In the region for the second high voltage MOS transistor 426, a second high voltage gate structure 431 is formed on the top surface 402 of the substrate 401. Part or all of the first low voltage gate structure 417, the second low voltage gate structure 421, the first high voltage gate structure 427, and the second high voltage gate structure 431 may be formed simultaneously with the gate dielectric layer 409, the gate 410, and the gate sidewall spacer 411 of the extended drain MOS transistor 405.

A source region 408 is formed in the substrate 401 in contact with the body well 413 adjacent to the gate 410 and positioned opposite the drain well 406. Source region 408 has a first conductivity type; in this example, source region 408 is p-type. Source region 408 may be formed as disclosed with reference to source region 208 of fig. 2D. A drain contact region 407 may optionally be formed in the substrate 401 contacting the drain well 406. The drain contact region 407 has a first conductivity type; in this example, the drain contact region 407 is p-type. The drain contact region 407 may be formed simultaneously with the source region 408. A first source 418 and a first drain 419 are formed in the substrate 401 on opposite sides of a first low voltage gate structure 417 in the region for the first low voltage MOS transistor 415. A third source 428 and a third drain 429 are formed in the substrate 401 on opposite sides of the first high voltage gate structure 427 in the region for the first high voltage MOS transistor 425. The first source 418, the first drain 419, the third source 428, and the third drain 429 have the first conductivity type; in this example, the first source 418, the first drain 419, the third source 428, and the third drain 429 are p-type. The first source 418, the first drain 419, the third source 428, and the third drain 429 may be formed simultaneously with the source region 408.

Body contact regions 414 may optionally be formed in substrate 401, contacting body wells 413. The body contact region 414 has a second conductivity type; in this example, the body contact regions 414 are n-type. The body contact regions 414 may be formed as disclosed with reference to the body contact regions 214 of fig. 2D. In the region for the second low voltage MOS transistor 416, a second source 422 and a second drain 423 are formed in the substrate 401 on opposite sides of the second low voltage gate structure 421. In the region for the second high voltage MOS transistor 426, a fourth source 432 and a fourth drain 433 are formed in the substrate 401 on opposite sides of the second high voltage gate structure 431. The second source 422, the second drain 423, the fourth source 432, and the fourth drain 433 have the second conductive type; in this example, the second source 422, the second drain 423, the fourth source 432, and the fourth drain 433 are n-type. The second source electrode 422, the second drain electrode 423, the fourth source electrode 432, and the fourth drain electrode 433 may be formed simultaneously with the body contact region 414.

A metal silicide 449 is formed over the drain contact region 407, the source region 408, the body contact region 414, the first source 418, the first drain 419, the second source 422, the second drain 423, the third source 428, the third drain 429, the fourth source 432 and the fourth drain 433. An example process for forming the metal suicide 449 may include forming a metal layer (not shown in fig. 4D) comprising titanium, nickel, and a few percent of platinum, cobalt, or platinum on the top surface 402 of the substrate 401 such that the metal contacts the exposed silicon on the drain contact region 407, the source region 408, the body contact region 414, the first source 418, the first drain 419, the second source 422, the second drain 423, the third source 428, the third drain 429, the fourth source 432, and the fourth drain 433. A capping layer of titanium nitride may be formed over the metal layer to provide a diffusion barrier. The metal layer is then heated, for example in a rapid thermal processor, to react the metal layer with the exposed silicon to form a metal silicide 449. The unreacted metal of the metal layer is removed, for example, by wet etching using an aqueous solution of an acidic or basic reagent. The metal silicide 449 may then be annealed to provide the desired crystalline phase.

Formation of integrated circuit 400 may continue by forming a dielectric layer (not shown in fig. 4) over top surface 402 of substrate 401, which is similar to dielectric layer 335 of fig. 3. Contacts (not shown in fig. 4D) may be formed through the dielectric layer, similar to contacts 336 of fig. 4D. An interconnect (not shown in fig. 4D) can be formed over the dielectric layer to make an electrical connection to the contact, similar to interconnect 337 of fig. 3.

Fig. 5 is a cross section of yet another example integrated circuit including an extended drain MOS transistor with double well isolation. The integrated circuit 500 has a substrate 501, the substrate 501 having a top surface 502 and comprising an underlying layer 503 of semiconductor material having a first conductivity type. In this example, the first conductivity type is n-type, as shown in fig. 5. Substrate 501 may also include a field oxide layer 504 extending to top surface 502. The field oxide layer 504 may have a local oxidation of silicon (LOCOS) structure in which the field oxide layer 504 extends below the top surface 502 to a depth of 250 nanometers to 750 nanometers and above the top surface 502 to a height of 150 nanometers to 500 nanometers, with tapered ends, sometimes referred to as bird's beaks, as depicted in fig. 5.

The integrated circuit 500 includes an extended drain MOS transistor 505 having a first polarity (in this example, an n-channel). The extended drain MOS transistor 505 comprises a drain well 506 in the substrate 501 having a first conductivity type, in this example n-type. The drain well 506 may have an average dopant density of the first conductivity type as disclosed with reference to the drain well 106 of fig. 1. The extended drain MOS transistor 505 may optionally include a drain contact region 507 that contacts the drain well 506 and extends to the top surface 502 of the substrate 501. The drain contact region 507 has the first conductivity type and may have an average dopant density of the first conductivity type as disclosed with reference to the drain contact region 107 of fig. 1.

The extended drain MOS transistor 505 includes a source region 508 having a first conductivity type in the substrate 501; in this example, the source region 508 is n-type. The source region 508 and the drain contact region 507 may have a similar average density of dopants of the first conductivity type. The extended drain MOS transistor 505 includes a gate dielectric layer 509 on the top surface 502 of the substrate 501 and a gate 510 on the gate dielectric layer 509. The gate 510 and gate dielectric 509 may be the materials disclosed with reference to the gate 110 and gate dielectric 109 of fig. 1. Gate 510 extends from source region 508 toward drain well 506; in this example, the gate 510 overlaps a portion of the drain well 506. In this example, the extended drain MOS transistor 505 may include an element of field oxide layer 504a between the drain contact region 507 and the portion of the drain well 506 that overlaps the gate 510. Drain well 506 extends under elements of field oxide layer 504a, as depicted in fig. 5. The extended drain MOS transistor 505 may include gate sidewall spacers 511 on side surfaces of the gate 510.

The drain well 506 is vertically separated from the lower layer 503 by a drain isolation well 512, the drain isolation well 512 being located in the substrate 501 and having a second conductivity type opposite the first conductivity type. In this example, the drain isolation well 512 is p-type, as shown in fig. 5. Drain isolation well 512 contacts lower layer 503 and drain well 506. The drain isolation well 512 may have, for example, 10¹⁵cm^-3To 10¹⁷cm^-3Of the second conductivity typeDensity. As shown in fig. 5, drain isolation well 512 may laterally surround drain well 506 and extend completely below drain well 506. In this example, the drain isolation well 512 may have two or more regions 512a vertically adjacent to each other with a higher dopant density of the second conductivity type. The higher dopant density region 512a may provide a more uniform vertical distribution of dopants of the second conductivity type, which may advantageously achieve a desired junction capacitance and a desired breakdown potential of the drain well 506 around the lateral perimeter of the drain well 506, as compared to the vertically reduced dopant concentration of the drain isolation well 112 of fig. 1.

The source region 508 is vertically separated from the lower layer 503 by a body well 513, the body well 513 being located in the substrate 501 and having the second conductivity type. In this example, the body well 513 is p-type, as shown in FIG. 5. A body well 513 contacts the lower layer 503 and the source region 508. The bulk well 513 may have, for example, 10¹⁶cm^-3To 10¹⁸cm^-3Of the second conductivity type. The average dopant density of the second conductivity type of the drain isolation well 512 is less than the average dopant density of the second conductivity type of the body well 513. In this example, the bulk well 513 may be separated from the drain well 506 by a drain isolation well 512 under the gate 510, as depicted in fig. 5. The construction of the extended drain MOS transistor 505 (with the drain well 506 isolated from the lower layer 503 by the drain isolation well 512, and with the source region 508 isolated from the lower layer 503 by the body well 513, wherein both the drain isolation well 512 and the body well 513 contact the lower layer 503) may advantageously reduce the area of the extended drain MOS transistor 505 by eliminating the need for a single isolation structure that extends completely under the extended drain MOS transistor 505. The extended drain MOS transistor 505 may optionally include a body contact region 514 that contacts the body well 513 and extends to the top surface 502 of the substrate 501. Body contact regions 514 have a second conductivity type with an average dopant density of, for example, 10¹⁹cm^-3To 10²¹cm^-3To provide the desired low resistance connection to the body well 513.

The extended drain MOS transistor 505 is depicted in fig. 5 as having an asymmetric configuration, with a source region 508 located on one side of a drain well 506. In an alternative version of this example, the extended drain MOS transistor 505 may have a symmetric configuration, with source regions 508 located on opposite sides of the drain well 506.

The integrated circuit 500 may optionally include a first low voltage MOS transistor 515 having a first polarity (in this example, an n-channel). The first low voltage MOS transistor 515 has a first low voltage gate structure 517 on the top surface 502 of the substrate 501, a first source 518 in the substrate 501, and a first drain 519 in the substrate 501. A first low voltage MOS transistor 515 is disposed in the first well 520, which has a second conductivity type, in this example p-type, as shown in fig. 5. The first well 520 may have an average dopant density of the second conductivity type substantially equal to that of the body well 513.

The integrated circuit 500 may also optionally include a second low voltage MOS transistor 516 having a second polarity (in this example, a p-channel). The second low voltage MOS transistor 516 has a second low voltage gate structure 521 on the top surface 502 of the substrate 501, a second source 522 in the substrate 501, and a second drain 523 in the substrate 501. The second low voltage MOS transistor 516 is disposed in a second well 524, which has the first conductivity type, in this example n-type, as shown in fig. 5. The second well 524 may have an average dopant density of the first conductivity type substantially equal to the drain well 506.

The integrated circuit 500 may optionally include a first high voltage MOS transistor 525 having a first polarity (in this example, an n-channel). The first high voltage MOS transistor 525 has a first high voltage gate structure 527 on the top surface 502 of the substrate 501, a third source 528 in the substrate 501, and a third drain 529 in the substrate 501. A first high voltage MOS transistor 525 is disposed in the third well 530, which has a second conductivity type, in this example, p-type, as shown in fig. 5. The third well 530 may have an average dopant density of the second conductivity type substantially equal to the drain isolation well 512, and may have two or more regions 530a vertically adjacent to each other having a higher dopant density of the second conductivity type substantially equal to the drain isolation well 512.

The integrated circuit 500 may also optionally include a second high voltage MOS transistor 526 having a second polarity (in this example, a p-channel). The second high voltage MOS transistor 526 has a second high voltage gate structure 531 on the top surface 502 of the substrate 501, a fourth source 532 in the substrate 501, and a fourth drain 533 in the substrate 501. A second high voltage MOS transistor 526 is disposed in the fourth well 534 and has the first conductivity type, in this example n-type, as shown in fig. 5.

The integrated circuit 500 may include a dielectric layer 535 over the top surface 502 of the substrate 501. The dielectric layer 535 may represent a PMD layer that is substantially equal to the PMD layer disclosed with reference to fig. 1. The integrated circuit 500 may also include contacts 536 extending through the dielectric layer 535 to provide electrical connections to the extended drain MOS transistor 505, the first low voltage MOS transistor 515, the second low voltage MOS transistor 516, the first high voltage MOS transistor 525, and the second high voltage MOS transistor 526. The contact 536 may have the structure disclosed with reference to the contact 136 of fig. 1. The integrated circuit 500 may also include interconnects 537 on the dielectric layer 535 to make electrical connections to the contacts 536.

Fig. 6A-6D are cross-sections of an integrated circuit including an extended drain MOS transistor with dual well isolation depicted in various stages of yet another example method of formation. Referring to fig. 6A, the formation of integrated circuit 600 includes obtaining a substrate 601, which may be implemented as disclosed with reference to substrate 201 of fig. 2A. The substrate 601 has a top surface 602 and includes an underlying layer 603 of semiconductor material below the top surface 602. The lower layer 603 has a first conductivity type, in this example n-type, as shown in fig. 6A. The substrate 601 includes a region for the extended drain MOS transistor 605, a region for the first low-voltage MOS transistor 615, a region for the second low-voltage MOS transistor 616, a region for the first high-voltage MOS transistor 625, and a region for the second high-voltage MOS transistor 626. The terms "low voltage" and "high voltage" are used as described with reference to fig. 1.

The protective layer 638 may be formed on the top surface 602. The protective layer 638 may have a composition and structure as described with reference to the protective layer 238 of fig. 2A. A first implantation mask 639 is formed over the protective layer 638. The first implantation mask 639 exposes the protection layer 638 in a region for the subsequently formed drain isolation well 612 (shown in fig. 6B) in a region for extending the drain MOS transistor 605. The first implantation mask 639 may optionally expose a region for a subsequently formed third well 630 (shown in fig. 6B) in the region for the first high voltage MOS transistor 625. First implant mask 639 may be formed as disclosed with reference to first implant mask 239 of fig. 2A.

A first dopant 641 is implanted into the substrate 601 in the region exposed by the first implantation mask 639 to form a plurality of drain isolation implant regions 643 vertically arranged in the region for the extended drain MOS transistor 605 and to form well implant regions 644 vertically arranged in the region for the first high voltage MOS transistor 625. In this example, the drain isolation implant region 643 corresponds to an implant of a first dopant 641 implanted at a different implant energy. The first dopant 641 is a dopant of the second conductivity type, in this example a p-type dopant such as boron. Can be 10¹²cm^-2To 10¹⁴cm^-2The first dopant 641 is implanted at an implantation energy of 100keV to 1000keV to form the well implant region 644 in a vertically aligned configuration. Having a plurality of drain isolation implant regions 643 in the region for the extended drain MOS transistor 605 and well implant regions 644 in the region for the first high voltage MOS transistor 625 may provide a more uniform vertical dopant profile in the subsequently formed drain isolation well 612 (as shown in fig. 6B) and in the subsequently formed third well 630 (as shown in fig. 6B). The first implantation mask 639 is removed after implanting the first dopant 641.

Referring to fig. 6B, the substrate 601 is heated by a thermal process 645 to diffuse and activate the first dopants 641 of fig. 6A in the drain isolation implant region 643 and the well implant region 644 of fig. 6A to form the drain isolation well 612 and the third well 630, respectively. The thermal process 645 may have a thermal profile sufficient to diffuse the first dopant 641 sufficiently to form a continuous drain isolation well 612 from the drain isolation implant region 643 and a continuous third well 630 from the well implant region 644, as shown in fig. 6B. Having a plurality of drain isolation implant regions 643 may result in a plurality of regions 612a of higher second conductivity type dopant density vertically adjacent to each other in drain isolation well 612, where each region 612a corresponds to a drain isolation implant region 643. Similarly, having a plurality of well implant regions 644 may result in a plurality of regions 630a of higher dopant density of the second conductivity type vertically adjacent to each other in the third well 630, wherein each region 630a corresponds to a drain isolation implant region 643. For example, the thermal process 645 may heat the substrate 601 to 1080 ℃ to 1120 ℃ for 100 minutes to 300 minutes. The thermal process 645 may be implemented as disclosed with reference to fig. 2B.

Referring to fig. 6C, a field oxide layer 604 is formed that extends into the substrate 601. The field oxide layer 604 may be formed by a LOCOS process such that the field oxide layer 604 has a LOCOS structure depicted in fig. 6C. An exemplary LOCOS process includes forming a silicon nitride layer over the protection layer 638, patterning the silicon nitride layer to expose the protection layer 638 in the area for the field oxide layer 604, growing the field oxide layer 604 by a thermal oxidation process, and removing the silicon nitride layer. After the field oxide layer 604 is formed, the protection layer 638 may be added by a new layer of protection material (such as a new layer of silicon dioxide) formed by a thermal oxidation process.

The fourth well 634 may be formed in a region for the second high voltage MOS transistor 626. Fourth well 634 has the first conductivity type, in this example n-type, as shown in fig. 6C.

A second implant mask 646 is formed over the protective layer 638. The second implantation mask 646 exposes the protection layer 638 in a region for the subsequently formed body well 613 in a region for extending the drain MOS transistor 605. The second implantation mask 646 may optionally expose a region for the subsequently formed first well 620 in a region for the first low voltage MOS transistor 615. Second implantation mask 646 may be formed by a process similar to first implantation mask 639 of fig. 6A. A second dopant 647 is implanted into the substrate 601 in areas exposed by the second implant mask 646. The second dopant 647 is a dopant of the second conductivity type, in this example a p-type dopant such as boron. The second dopant 647 may be implanted in more than one implantation step, with the main step having a dose of 10¹²cm^-2To 10¹⁴cm^-2Is implanted at an energy of 400keV to 600 keV. The additional implant step of the second dopants 647 may have a lower dose and lower energy to set the threshold potential for the extended drain MOS transistor 605 and the first low voltage MOS transistor 615. Second implantation mask 646 is removed after the second dopant 647 implantation. The second implantation mask 646 may be removed by a process similar to that used to remove the first implantation mask 639 of fig. 6A.

Substrate 601 is then heated to activate second dopants 647 implanted into substrate 601 to form body well 613 and first well 620. The substrate 601 may be heated by a rapid thermal process to reduce unwanted diffusion of the second dopant 647 and the first dopant 641 of fig. 6A in the drain isolation well 612. The body well 613 has a higher average dopant density of the second conductivity type than the drain isolation well 612.

Referring to fig. 6D, in a region for extending the drain MOS transistor 605, a drain well 606 is formed in the substrate 601 such that the drain well 606 is vertically separated from the lower layer 603 by a drain isolation well 612. The drain well 606 may extend partially under the gate 610, as depicted in fig. 6, such that the drain well 606 is laterally separated from the bulk well 613 under the gate 610 by a drain isolation well 612. The drain well 606 of this example is formed so as to extend under the elements of the field oxide layer 604 a. The drain well 606 has a first conductivity type; in this example n-type.

In the region for the second low voltage MOS transistor 616, a second well 624 may be formed in the substrate 601. The second well 624 has the first conductivity type and may be formed to have a similar distribution of dopants of the first conductivity type as the drain well 606. Drain well 606 and second well 624 may be formed simultaneously as disclosed with reference to drain well 206 and second well 224 of fig. 2D, thereby obtaining similar advantages of reduced manufacturing costs. The protective layer 638 of fig. 6C is then removed.

In the region for extending the drain MOS transistor 605, a gate dielectric layer 609 is formed on the top surface 602 of the substrate 601. The gate 610 of the extended drain MOS transistor 605 is formed on a gate dielectric layer 609. The gate 610 and gate dielectric 609 may be formed as disclosed with reference to the gate 210 and gate dielectric 209 of fig. 2D. In this example, the gate 610 may extend from the source region 608 to the elements of the field oxide layer 604a in the drain well 606. Gate sidewall spacers 611 may be formed on the side surfaces of the gate 610. The gate sidewall spacers 611 may be formed as disclosed with reference to the gate sidewall spacers 211 of fig. 2D.

In the region for the first low voltage MOS transistor 615, a first low voltage gate structure 617 is formed on the top surface 602 of the substrate 601. In the region for the second low-voltage MOS transistor 616, a second low-voltage gate structure 621 is formed on the top surface 602 of the substrate 601. In the region for the first high voltage MOS transistor 625, a first high voltage gate structure 627 is formed on the top surface 602 of the substrate 601. In the region for the second high voltage MOS transistor 626, a second high voltage gate structure 631 is formed on the top surface 602 of the substrate 601. Part or all of the first low-voltage gate structure 617, the second low-voltage gate structure 621, the first high-voltage gate structure 627 and the second high-voltage gate structure 631 may be formed simultaneously with the gate dielectric layer 609, the gate 610 and the gate sidewall spacer 611 of the extended drain MOS transistor 605.

A source region 608 is formed in the substrate 601 in contact with the body well 613 adjacent the gate 610 and positioned opposite the drain well 606. Source region 608 has a first conductivity type; in this example, source region 608 is n-type. Source region 608 may be formed as disclosed with reference to source region 208 of fig. 2D. A drain contact region 607 may optionally be formed in the substrate 601 contacting the drain well 606. The drain contact region 607 has a first conductivity type; in this example, the drain contact region 607 is n-type. The drain contact region 607 may be formed simultaneously with the source region 608. In the region for the first low voltage MOS transistor 615, on opposite sides of the first low voltage gate structure 617, a first source 618 and a first drain 619 are formed in the substrate 601. In the region for the first high voltage MOS transistor 625, a third source 628 and a third drain 629 are formed in the substrate 601 on opposite sides of the first high voltage gate structure 627. The first source 618, the first drain 619, the third source 628, and the third drain 629 have the first conductivity type; in this example, the first source 618, the first drain 619, the third source 628, and the third drain 629 are n-type. The first source 618, the first drain 619, the third source 628, and the third drain 629 may be formed simultaneously with the source region 608.

Body contact regions 614 may optionally be formed in substrate 601, contact wells 613. Body contact regions 614 have a second conductivity type; in this example, the body contact regions 614 are p-type. The body contact regions 614 may be formed as disclosed with reference to body contact regions 214 of fig. 2D. In the region for the second low voltage MOS transistor 616, a second source 622 and a second drain 623 are formed in the substrate 601 on opposite sides of the second low voltage gate structure 621. In the region for the second high-voltage MOS transistor 626, a fourth source 632 and a fourth drain 633 are formed in the substrate 601 on opposite sides of the second high-voltage gate structure 631. The second source electrode 622, the second drain electrode 623, the fourth source electrode 632, and the fourth drain electrode 633 have a second conductivity type; in this example, the second source 622, the second drain 623, the fourth source 632, and the fourth drain 633 are p-type. The second source electrode 622, the second drain electrode 623, the fourth source electrode 632, and the fourth drain electrode 633 may be formed simultaneously with the body contact region 614.

Formation of integrated circuit 600 may continue by forming a dielectric layer (not shown in fig. 6D) over top surface 602 of substrate 601, similar to dielectric layer 535 of fig. 5. Contacts (not shown in fig. 6D) may be formed through the dielectric layer, similar to contacts 536 of fig. 5. An interconnect (not shown in fig. 6D) can be formed over the dielectric layer to make an electrical connection to the contact, similar to interconnect 537 of fig. 5.

Various features of the examples disclosed herein may be combined in other manifestations of example integrated circuits. Any one of the extended drain MOS transistors 105, 305, and 505 may have a symmetrical or asymmetrical configuration, and any one of the extended drain MOS transistors 105, 305, and 505 may have a p-channel polarity or an n-channel polarity, with appropriate changes made to the first conductivity type and the second conductivity type. Any of the extended drain MOS transistors 105, 305, and 505 may have elements of field oxide in the corresponding drain wells 106, 306, and 506. Any of the extended drain MOS transistors 105, 305, and 505 may have STI or LOCOS field oxide. Any of the extended drain MOS transistors 105, 305, and 505 may have a metal silicide, and may have a silicide blocking layer. Any of the drain isolation wells 112, 312, and 512 may be formed according to the example methods disclosed with reference to fig. 2A and 2B, fig. 4A and 4B, and fig. 6A and 6B.

While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Many variations may be made to the disclosed embodiments in light of the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.