阅读说明：本技术 电子装置 (Electronic device ) 是由 何宇胜 陈怡欣 于 2020-05-06 设计创作，主要内容包括：本发明提供一种电子装置,包含第一相位延迟元件、第二相位延迟元件以及液晶层,第二相位延迟元件设置于第一相位延迟元件上,液晶层设置于第一相位延迟元件与第二相位延迟元件之间,且液晶层包含手性剂,手性剂的节距介于7微米至25微米之间。第一相位延迟元件具有第一平面内光延迟值及第一平面外光延迟值,第二相位延迟元件具有第二平面内光延迟值及第二平面外光延迟值,第一平面内光延迟值及第二平面内光延迟值介于20纳米至70纳米之间,且第一平面外光延迟值及第二平面外光延迟值介于170纳米至210纳米之间。(The invention provides an electronic device, which comprises a first phase delay element, a second phase delay element and a liquid crystal layer, wherein the second phase delay element is arranged on the first phase delay element, the liquid crystal layer is arranged between the first phase delay element and the second phase delay element, the liquid crystal layer comprises a chiral agent, and the pitch of the chiral agent is between 7 micrometers and 25 micrometers. The first phase retardation element has a first in-plane optical retardation value and a first out-of-plane optical retardation value, the second phase retardation element has a second in-plane optical retardation value and a second out-of-plane optical retardation value, the first in-plane optical retardation value and the second in-plane optical retardation value are between 20 nanometers and 70 nanometers, and the first out-of-plane optical retardation value and the second out-of-plane optical retardation value are between 170 nanometers and 210 nanometers.)

1. An electronic device, comprising:

a first phase delay element;

a second phase delay element disposed on the first phase delay element; and

a liquid crystal layer disposed between the first phase retardation element and the second phase retardation element, wherein the liquid crystal layer comprises a chiral agent, and the pitch of the chiral agent is between 7 microns and 25 microns;

wherein the first phase retardation element has a first in-plane optical retardation value and a first out-of-plane optical retardation value, the second phase retardation element has a second in-plane optical retardation value and a second out-of-plane optical retardation value, the first in-plane optical retardation value and the second in-plane optical retardation value are between 20 nanometers and 70 nanometers, and the first out-of-plane optical retardation value and the second out-of-plane optical retardation value are between 170 nanometers and 210 nanometers.

2. The electronic device of claim 1, wherein the first in-plane optical retardation value and the second in-plane optical retardation value are between 30 nanometers and 60 nanometers, and the first out-of-plane optical retardation value and the second out-of-plane optical retardation value are between 180 nanometers and 200 nanometers.

3. The electronic device of claim 1, wherein the first in-plane optical retardation value is the same as the second in-plane optical retardation value and the first out-of-plane optical retardation value is the same as the second out-of-plane optical retardation value.

4. The electronic device of claim 1, further comprising:

a first polarizing layer adjacent to the first phase delay element; and

a second polarizing layer adjacent to the second phase delay element;

wherein the first phase retardation element comprises a first phase retardation layer and a second phase retardation layer, the second phase retardation element comprises a third phase retardation layer and a fourth phase retardation layer, the first phase retardation layer is located between the second phase retardation layer and the first polarizing layer, and the third phase retardation layer is located between the fourth phase retardation layer and the second polarizing layer.

5. The electronic device of claim 4, wherein the first phase retardation layer is the same material as the third phase retardation layer, and the second phase retardation layer is the same material as the fourth phase retardation layer.

6. The electronic device of claim 1, further comprising:

a first polarizing layer, the first phase retardation element being disposed between the first polarizing layer and the liquid crystal layer,

the first phase retardation element comprises a first substrate, a first phase retardation layer and a second phase retardation layer, wherein the first phase retardation layer is arranged between the first substrate and the liquid crystal layer, and the second phase retardation layer is arranged between the first phase retardation layer and the liquid crystal layer.

7. The electronic device of claim 6, further comprising:

a second polarizing layer, the second phase delay element disposed between the second polarizing layer and the liquid crystal layer,

the second phase retardation element comprises a second substrate, a third phase retardation layer and a fourth phase retardation layer, wherein the third phase retardation layer is arranged between the second substrate and the liquid crystal layer, and the fourth phase retardation layer is arranged between the third phase retardation layer and the liquid crystal layer.

8. The electronic device according to claim 1, comprising a panel having a sub-pixel region, wherein the panel comprises a first substrate, a second substrate, a first electrode layer and the liquid crystal layer, wherein the second substrate is opposite to the first substrate, the first electrode layer is located between the first substrate and the liquid crystal layer, and the first electrode layer is correspondingly disposed in the sub-pixel region, wherein the first electrode layer has a main portion and a plurality of branch portions, the main portion divides the first electrode layer into a first portion, a second portion, a third portion and a fourth portion, and an included angle between one of the plurality of branch portions corresponding to the first portion and the main portion is 40-50 degrees.

9. The electronic device according to claim 1, comprising a panel having a sub-pixel region, wherein the panel comprises a first substrate, a second substrate, a first electrode layer and the liquid crystal layer, wherein the second substrate is opposite to the first substrate, the first electrode layer is located between the first substrate and the liquid crystal layer, and the first electrode layer is correspondingly disposed in the sub-pixel region, wherein the first electrode layer has a main portion and a plurality of branch portions, the main portion divides the first electrode layer into a first portion, a second portion, a third portion, and fourth portions, corresponding to a first angle between one of the plurality of branch portions in the first portion and the main portion, and corresponding to a second angle between one of the plurality of branch portions in the second portion and the main portion, and the first included angle is not equal to the second included angle.

10. The electronic device of claim 9, wherein a sum of the first angle and the second angle is between 80 degrees and 100 degrees.

Technical Field

The present invention relates to an electronic device, and more particularly, to an electronic device having a phase delay element.

Background

With the rapid development of electronic products, consumers have great expectations for the quality, function and price of electronic products, such as development towards high-resolution electronic products. However, the electronic device still has not been satisfactory in all aspects, such as significant light leakage in dark state or uneven brightness of the panel under different viewing angles. Therefore, developing a structure design capable of further improving the quality or performance of the electronic device is still one of the issues of research in the industry.

Disclosure of Invention

According to some embodiments of the present invention, an electronic device is provided, which includes a first phase retardation element, a second phase retardation element disposed on the first phase retardation element, and a liquid crystal layer disposed between the first phase retardation element and the second phase retardation element, wherein the liquid crystal layer includes a chiral agent, and a pitch of the chiral agent is between 7 microns and 25 microns. The first phase retardation element has a first in-plane optical retardation value and a first out-of-plane optical retardation value, the second phase retardation element has a second in-plane optical retardation value and a second out-of-plane optical retardation value, the first in-plane optical retardation value and the second in-plane optical retardation value are between 20 nanometers and 70 nanometers, and the first out-of-plane optical retardation value and the second out-of-plane optical retardation value are between 170 nanometers and 210 nanometers.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 2 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 3 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 4 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 5 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 6 is a graph showing results of optical analysis performed by an electronic device according to some embodiments of the invention;

FIG. 7 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 8 is a schematic top view of a sub-pixel region of an electronic device according to some embodiments of the invention;

FIG. 9 is a schematic diagram illustrating a top view of a sub-pixel region of an electronic device according to some embodiments of the invention;

FIG. 10 is a cross-sectional view of an electronic device according to some embodiments of the invention.

Description of the symbols

10. 20, 30, 40, 50, 60, 70 electronic devices;

100 a first phase delay element;

101 a first substrate;

101s a first substrate;

101x circuit layers;

103a phase retardation layer;

103a first phase retardation layer;

103b a second phase retardation layer;

111a first electrode layer;

a 111A main portion;

a 111B branch part;

113 a first alignment layer;

200 a second phase delay element;

201 a second substrate;

201s a second substrate;

201x color filter layer;

203 phase retardation layer;

203a third phase delay layer;

203b a fourth phase delay layer;

211 a second electrode layer;

213 a second alignment layer;

300 a liquid crystal layer;

402a first polarizing layer;

402b a second polarizing layer;

A-A' section line;

O₁a first opening;

O₂a second opening;

a PN panel;

a P1 first part;

a second part P2;

part three of P3;

fourth part P4;

an SP sub-pixel region;

an included angle theta;

an azimuth angle;

θ₁a first included angle;

θ₂a second included angle;

θ₃a third included angle;

θ₄a third included angle;

θ_tand (4) an included angle.

Detailed Description

The electronic device according to the embodiment of the present invention will be described in detail below. It is to be understood that the following description provides many different embodiments, which can be used to implement different aspects of some embodiments of the invention. The specific elements and arrangements described below are merely illustrative of some embodiments of the invention for simplicity and clarity. These are, of course, merely examples and are not intended to be limiting. Moreover, similar and/or corresponding reference numerals may be used to identify similar and/or corresponding elements in different embodiments to clearly describe the present invention. However, the use of such similar and/or corresponding reference numerals is merely for simplicity and clarity in describing some embodiments of the invention and does not represent any correlation between the various embodiments and/or structures discussed.

The present invention may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, in which it is noted that, for the sake of clarity, the various drawings depict only some of the electronic devices and that certain elements of the drawings are not necessarily drawn to scale. In addition, the number and size of the elements in the drawings are merely illustrative and are not intended to limit the scope of the present invention.

It should be understood that the elements of the drawings or devices may exist in various forms well known to those skilled in the art. In addition, relative terms, such as "lower" or "bottom" or "upper" or "top," may be used in relation to one element of the figures to describe the relative relationship of one element to another. It will be understood that if the device of the drawings is turned over with its top and bottom portions reversed, the elements described as being on the "lower" side will be turned over to those on the "higher" side. The embodiments of the present invention can be understood together with the accompanying drawings, which are also to be considered part of the description of the invention. Further, when a first material layer is referred to as being on or over a second material layer, the first material layer may be directly in contact with the second material layer, or one or more other material layers may be interposed therebetween, in which case the first material layer may not be directly in contact with the second material layer.

Certain terms are used throughout the description and following claims to refer to particular elements. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that differ in function but not name. In the following description and claims, the terms "including", "comprising", "having", "with", and the like are open-ended terms, and thus should be construed to mean "including, but not limited to …". Thus, when the terms "comprises," "comprising," and/or "having" are used in the description of the present invention, they specify the presence of stated features, regions, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, and/or components.

Directional phrases used herein include, for example: the upper, lower, front, rear, left, right, etc. are only referred to the direction of the drawing. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting. In the drawings, which illustrate general features of methods, structures, and/or materials used in certain embodiments. These drawings, however, should not be construed as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses, and locations of various film layers, regions, and/or structures may be reduced or exaggerated for clarity.

When a corresponding element (e.g., layer or region) is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. On the other hand, when an element is referred to as being "directly on" another element, there is no element present therebetween. In addition, when a component is referred to as being "on" another component, the two components may be located above or below the other component in a top-down relationship, depending on the orientation of the device.

Further, it should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, or sections, these elements, components, or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

As used herein, the term "about" or "substantially" generally means within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantities given herein are approximate quantities, that is, the meanings of "about" and "substantially" are implied unless otherwise indicated. Moreover, the term "range between a first value and a second value" means that the range includes the first value, the second value, and other values therebetween.

It is to be understood that the embodiments described below may be combined, rearranged or mixed in order to achieve additional embodiments without departing from the spirit of the invention. Features of the various embodiments may be combined and matched as desired, without departing from the spirit or ambit of the invention.

In the present invention, the thickness, length and width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but not limited thereto. In addition, there may be some error in any two values or directions for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

According to some embodiments of the present invention, an electronic device including a phase retardation element is provided, and an in-plane retardation (Ro) and an out-plane retardation (Rth) of the phase retardation element are designed within a range, so as to improve the quality of the electronic device, for example, improve the dark state light leakage problem or the panel brightness non-uniformity problem at different viewing angles. According to some embodiments of the present invention, the electronic device may include a display device, a light emitting device, a touch device, a sensing device, a splicing device, or a combination thereof, but not limited thereto. The electronic device may include a bendable or flexible electronic device. The electronic device may include, for example, a liquid crystal (liquid-crystal) device, but is not limited thereto. In some embodiments, the electronic device may include a backlight module (backlight module). The backlight module may include light emitting diodes, such as inorganic light emitting diodes (inorganic light emitting diodes), Organic Light Emitting Diodes (OLEDs), sub-millimeter light emitting diodes (mini LEDs), micro LEDs, Quantum Dot (QD) light emitting diodes (which may be, for example, QLEDs or QDLEDs), fluorescent light (fluorescent), phosphorescent light (phosphor), other suitable materials, or combinations thereof, but not limited thereto. The electronic device will be described below by taking the display device as an example, but the invention is not limited thereto.

Referring to fig. 1, fig. 1 is a schematic cross-sectional view illustrating an electronic device 10 according to some embodiments of the invention. It should be understood that some elements of the electronic device 10 are omitted from the figures for clarity of illustration, and only some elements are schematically shown. According to some embodiments, additional features may be added to the electronic device 10 described below. In other embodiments, some of the features of electronic device 10 described below may be replaced or omitted.

As shown in fig. 1, the electronic device 10 may include a first phase retardation element 100, a second phase retardation element 200, and a liquid crystal layer 300, wherein the second phase retardation element 200 may be disposed on the first phase retardation element 100, and the liquid crystal layer 300 may be disposed between the first phase retardation element 100 and the second phase retardation element 200.

In some embodiments, the first phase retardation element 100 and the second phase retardation element 200 may be used, for example, to change the polarization state of the light source, including changing the direction of the long axis of the polarization of the light and/or the polarization pattern of the light (e.g., circular polarization, elliptical polarization, or linear polarization), but not limited thereto. Further, the first phase retardation element 100 has a first in-plane optical retardation value (Ro-1) and a first out-of-plane optical retardation value (Rth-1), and the second phase retardation element 200 has a second in-plane optical retardation value (Ro-2) and a second out-of-plane optical retardation value (Rth-2). In some embodiments, the first in-plane optical retardation value and/or the second in-plane optical retardation value is between 20 nanometers (nm) and 70 nanometers (i.e., 20 nanometers ≦ Ro-1 ≦ 70 nanometers, 20 nanometers ≦ Ro-2 ≦ 70 nanometers), or between 30 nanometers and 60 nanometers (i.e., 30 nanometers ≦ Ro-1 ≦ 60 nanometers, 30 nanometers ≦ Ro-2 ≦ 60 nanometers), such as, but not limited to, 35 nanometers, 40 nanometers, 45 nanometers, 50 nanometers, or 55 nanometers. In some embodiments, the first out-of-plane optical retardation value and/or the second out-of-plane optical retardation value is between 170 nanometers and 210 nanometers (i.e., 170 nanometers ≦ Rth-1 ≦ 210 nanometers, 170 nanometers ≦ Rth-2 ≦ 210 nanometers), or between 180 nanometers and 200 nanometers (i.e., 180 nanometers ≦ Rth-1 ≦ 200 nanometers, 180 nanometers ≦ Rth-2 ≦ 200 nanometers), such as, but not limited to, 185 nanometers, 190 nanometers, or 195 nanometers.

It should be noted that if the in-plane retardation value is too small or too large (e.g., less than 20 nm or more than 70 nm), the first phase retardation element 100 or the second phase retardation element 200 may not achieve the proper light compensation effect, and the dark-state light leakage of the image is easily generated at some viewing angles. Similarly, if the first out-of-plane retardation value and/or the second out-of-plane retardation value is too small or too large (e.g., less than 170nm or more than 210nm), the first phase retardation element 100 or the second phase retardation element 200 may not achieve a proper light compensation effect, and in some viewing angles, dark-state light leakage of the image is easily caused.

In some embodiments, the first in-plane optical retardation value of the first phase retardation element 100 and the second in-plane optical retardation value of the second phase retardation element 200 may be substantially the same, and the first out-of-plane optical retardation value of the first phase retardation element 100 and the second out-of-plane optical retardation value of the second phase retardation element 200 may be substantially the same, but is not limited thereto.

According to some embodiments, the first phase retardation element 100 may be defined as all elements or layers between the liquid crystal layer 300 and the first polarizing layer 402a, and the second phase retardation element 200 may be defined as all elements or layers between the liquid crystal layer 300 and the second polarizing layer 402 b. Further, the in-plane optical retardation value and the out-of-plane optical retardation value of the first phase retardation element 100 and the second phase retardation element 200 can be measured by a known phase difference measuring instrument, for example, a polarimeter (axiometrics) and/or a phase difference measuring device KOBRA series.

Referring to fig. 1, in some embodiments, the first phase retardation device 100 may include a first substrate 101 and a phase retardation layer 103, the first substrate 101 is adjacent to the phase retardation layer 103, and the second phase retardation device 200 may include a second substrate 201 and a phase retardation layer 203, the second substrate 201 is adjacent to the phase retardation layer 203, but not limited thereto.

In some embodiments, the panel PN may include a first substrate 101, a second substrate 201, and elements (including a liquid crystal layer 300) disposed between the first substrate 101 and the second substrate 201. In some embodiments, the first substrate 101 may serve as a driving substrate, and the second substrate 201 may serve as a color filter substrate, but not limited thereto. The detailed arrangement of the first substrate 101 and the second substrate 201 will be further described below.

In some embodiments, the phase retardation layer 103 and/or the phase retardation layer 203 may include, but is not limited to, triacetyl cellulose (TAC), Cyclic Olefin Polymer (COP), liquid-crystal polymer (LCP), polymethyl methacrylate (PMMA), other suitable materials, or a combination thereof. Furthermore, the retardation layers 103 and 203 may have a single-layer structure or a multi-layer structure (as shown in fig. 2 to 5).

In some embodiments, the liquid crystal layer 300 may include liquid crystal materials, other suitable modulating materials, or combinations thereof. In some embodiments, the liquid crystal material may include nematic (nematic) liquid crystal, smectic (cholesteric) liquid crystal, cholesteric (cholesteric) liquid crystal, blue phase (blue phase) liquid crystal, other suitable liquid crystal material, or a combination of the foregoing, but is not limited thereto. The electronic device 10 may include a Twisted Nematic (TN) type liquid crystal device, a Super Twisted Nematic (STN) type liquid crystal device, a double layer super twisted nematic (DSTN) type liquid crystal device, a Vertical Alignment (VA) type liquid crystal device, an in-plane switching (IPS) type liquid crystal device, a cholesteric liquid crystal device, a blue phase type liquid crystal device, a Fringe Field Switching (FFS) type liquid crystal device, a nano-protrusion vertical alignment (NPVA) type liquid crystal device, other suitable liquid crystal devices, or a combination thereof.

Furthermore, the liquid crystal layer 300 may include a chiral agent (chiral dopant) which can adjust the alignment and/or rotation characteristics of the liquid crystal molecules, so that the liquid crystal molecules in a partial region (e.g., a dark fringe region) can be rotated by an electric field, thereby providing a retardation in the partial region (e.g., the dark fringe region) and improving the transmittance of the entire electronic device. The dark fringe region can be defined as a region where the liquid crystal molecules are less rotated (i.e., a region providing less retardation) when the electric field is formed by applying a voltage to the electronic device, for example, as shown in the following fig. 8, the dark fringe region can substantially correspond to or overlap with a region of the first electrode layer 111, but is not limited thereto, and the detailed arrangement position and pattern of the first electrode layer 111 will be described later. In some embodiments, the pitch P (pitch) of the chiral agent, which may also be referred to as chiral molecules (chiral molecules), is between 7 microns (μm) and 25 microns (i.e., 7 μm. ltoreq. pitch p. ltoreq.25 μm), or between 10 μm and 20 μm (i.e., 10 μm. ltoreq. pitch p. ltoreq.20 μm), such as, but not limited to, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, or 19 μm. When the pitch P of the chiral agent is designed within the above range, the liquid crystal molecules can have proper handedness, thereby providing a better phase retardation and improving the transmittance of the electronic device 10 as a whole. In some embodiments, the product of the birefringence (Δ n, birefringency) of the liquid crystal layer 300 and the thickness d of the liquid crystal layer 300 may be between 300 nm and 550 nm (300 nm ≦ Δ n.d ≦ 550 nm), or may be between 320 nm and 380 nm (320 nm ≦ Δ n.d ≦ 380 nm), or may be between 440 nm and 500 nm (440 nm ≦ Δ n.d ≦ 550 nm), but is not limited thereto. In some embodiments, the ratio of thickness d to pitch P can be between 0.15 and 0.35 (0.15 ≦ d/P ≦ 0.35), between 0.2 and 0.3 (0.2 ≦ d/P ≦ 0.3), or between 0.23 and 0.28(0.23 ≦ d/P ≦ 0.28), but is not limited thereto, such as 0.24 or 025.

In some embodiments, the pitch P (pitch) can be measured by, but is not limited to, the Grandjean-Cano wedge groove method.

According to some embodiments, the thickness d refers to a maximum thickness of the liquid crystal layer 300 in a normal direction (e.g., a Z direction shown in the figure) of the first substrate 101.

According to embodiments of the present invention, the thickness, width, or distance between elements may be measured using an Optical Microscope (OM), a Scanning Electron Microscope (SEM), a thin film thickness profile gauge (α -step), an ellipsometer, or other suitable means. In detail, in some embodiments, after removing the liquid crystal layer 300, any cross-sectional image of the structure may be obtained by using a scanning electron microscope, and the height, thickness or distance between the elements in the image may be measured.

As shown in fig. 1, according to some embodiments, the electronic device 10 may further include a first polarizing layer 402a and a second polarizing layer 402b, the first polarizing layer 402a is adjacent to the first phase retardation element 100, and the second polarizing layer 402b is adjacent to the second phase retardation element 200. In some embodiments, the first phase retardation element 100, the second phase retardation element 200, and the liquid crystal layer 300 are disposed between the first polarizing layer 402a and the second polarizing layer 402 b.

In some embodiments, the first and/or second polarizing layers 402a and 402b may include a polyvinyl alcohol (PVA) film, a tri-acetate cellulose (TAC), a pressure sensitive adhesive (pressure sensitive adhesive film), a protective film (protective film), and/or a release film, other suitable polarizing materials, or a combination thereof, but is not limited thereto.

In some embodiments, the aforementioned components can be selectively bonded by an adhesion process, such as bonding the phase retardation layer 103 to the first substrate 101, bonding the phase retardation layer 203 to the second substrate 201, bonding the phase retardation layer 103 to the first polarizing layer 402, or bonding the phase retardation layer 203 to the second polarizing layer 402 b. In other words, an adhesive layer (not shown) may be optionally provided between the above components. In other embodiments, the stacked structure of the devices may be formed sequentially by a coating process, a chemical deposition process, a printing process, other suitable processes, or a combination thereof.

Referring to fig. 2, fig. 2 is a schematic cross-sectional view illustrating an electronic device 20 according to another embodiment of the invention. It should be understood that the same or similar components or elements are denoted by the same or similar reference numerals, and the same or similar materials, manufacturing methods and functions are the same or similar to those described above, so that the detailed description thereof will not be repeated.

In some embodiments, as shown in FIG. 2, the first phase retardation element 100 and the second phase retardation element 200 may be composite layers, for example, may have multiple phase retardation layers. In detail, in some embodiments, the first phase retardation element 100 may include a first phase retardation layer 103a and/or a second phase retardation layer 103b, the second phase retardation element 200 may include a third phase retardation layer 203a and/or a fourth phase retardation layer 203b, the first phase retardation layer 103a is located between the second phase retardation layer 103b and the first polarizing layer 402a, and the third phase retardation layer 203a is located between the fourth phase retardation layer 203b and the second polarizing layer 402 b.

As shown in fig. 2, according to some embodiments, the retardation layer may be disposed outside the first substrate 101 and/or the second substrate 201, that is, the retardation layer may be disposed outside the panel PN, which is an out-cell retardation layer. In some embodiments, the panel PN includes a first substrate 101, a second substrate 201, and a liquid crystal layer 300 disposed therebetween.

In some embodiments, the first phase retardation element 100 may be disposed between the first polarizing layer 402a and the liquid crystal layer 300. In some embodiments, the second phase retardation element 200 may be disposed between the second polarizing layer 402b and the liquid crystal layer 300. In some embodiments, the first phase retardation element 100 may include a first substrate 101, a first phase retardation layer 103a and/or a second phase retardation layer 103b, and the first phase retardation layer 103a is disposed between the first substrate 101 and the liquid crystal layer 300, and the second phase retardation layer 103b is disposed between the first phase retardation layer 103a and the liquid crystal layer 300. In some embodiments, the second phase retardation element 200 may include a second substrate 201, a third phase retardation layer 203a and/or a fourth phase retardation layer 203b, the third phase retardation layer 203a being disposed between the second substrate 201 and the liquid crystal layer 300, the fourth phase retardation layer 203b being disposed between the third phase retardation layer 203a and the liquid crystal layer 300.

In some embodiments, the materials of the first phase retardation layer 103a, the second phase retardation layer 103b, the third phase retardation layer 203a and/or the fourth phase retardation layer 203b may be similar to the materials of the phase retardation layer 103 and the phase retardation layer 203, which are not repeated here. In some embodiments, the materials of the first phase retardation layer 103a and the third phase retardation layer 203a are the same, the materials of the second phase retardation layer 103b and the fourth phase retardation layer 203b are the same, and the materials of the first phase retardation layer 103a and the second phase retardation layer 103b are different, i.e., the electronic device 20 may have a substantially symmetrical (based on the liquid crystal layer 300) stacked structure, but is not limited thereto. In some embodiments (not shown), the first phase retardation layer 103a and the fourth phase retardation layer 203b are the same material, the second phase retardation layer 103b and the third phase retardation layer 203a are the same material, and the first phase retardation layer 103a and the second phase retardation layer 103b are different materials, but not limited thereto. In some embodiments, the materials of the first, second, third, and fourth phase retardation layers 103a, 103b, 203a, and 203b may be partially the same or partially different, or all the same or all the different.

It should be understood that the number and/or arrangement of the phase retardation layers are not limited to those shown in the drawings, and according to some embodiments, the first and second phase retardation elements 100 and 200 may have other suitable numbers of phase retardation layers (e.g., two, three, four, but not limited thereto), and the number of phase retardation layers that the first and second phase retardation elements 100 and 200 have may be the same or different, as long as the first and second phase retardation elements 100 and 200 may have the in-plane optical retardation value and the out-of-plane optical retardation value as described above, e.g., the first and/or second in-plane optical retardation value is between 20 nm and 70nm (20 nm. ltoreq. Ro-1. ltoreq.70 nm, 20 nm. ltoreq. Ro-2. ltoreq.70 nm), and the first and/or second out-plane optical retardation value is between 170nm and 210nm (170 nm. ltoreq. Ro-70 nm) Rth-1 is less than or equal to 210 nanometers, and Rth-2 is less than or equal to 170 nanometers and less than or equal to 210 nanometers).

Referring to fig. 3, fig. 3 is a schematic cross-sectional view illustrating an electronic device 30 according to another embodiment of the invention. As shown in fig. 3, in some embodiments, the first phase retardation element 100 and/or the second phase retardation element 200 may include a composite layer, for example, may have a plurality of phase retardation layers, and the phase retardation layers may be disposed on the inner sides of the first substrate 101 and the second substrate 201, i.e., may be disposed on the inner side of the panel PN, i.e., an in-cell phase retardation layer. In the embodiment shown in fig. 3, the panel PN includes a first substrate 101, a second substrate 201, and a first phase retardation layer 103a, a second phase retardation layer 103b, a liquid crystal layer 300, a third phase retardation layer 203a and/or a fourth phase retardation layer 203b disposed between the first substrate 101 and the second substrate 201, but is not limited thereto.

In some embodiments, the first phase retardation layer 103a and the second phase retardation layer 103b may be disposed between the first substrate 101 and the liquid crystal layer 300. In some embodiments, the third phase retardation layer 203a and the fourth phase retardation layer 203b may be disposed between the second substrate 201 and the liquid crystal layer 300. In some embodiments, the material of the first retardation layer 103a, the second retardation layer 103b, the third retardation layer 203a and/or the fourth retardation layer 203b may include liquid-crystal polymer (LCP), and the above retardation layer composed of LCP may be disposed between the liquid crystal layer 300 and the first substrate 101 or between the liquid crystal layer 300 and the second substrate 201. In some embodiments, the retardation layers composed of liquid crystal polymer may have different thicknesses corresponding to different colors (for example, but not limited to, red, blue and/or green) of the sub-pixels, respectively, and the thickness of the retardation layer is measured by, for example, a scanning electron microscope to obtain the maximum thickness of the film in the SEM image.

Referring to fig. 4, fig. 4 is a schematic cross-sectional view illustrating an electronic device 40 according to another embodiment of the invention. As shown in fig. 4, according to some embodiments, the first retardation element 100, the second retardation element 200, the first polarizing layer 402a and/or the second polarizing layer 402b may be disposed inside the first substrate 101 and the second substrate 201, and the polarizing layer may also be disposed inside the panel PN, which is an in-cell retardation layer. In the embodiment shown in fig. 4, the panel PN includes a first substrate 101, a second substrate 201, and a first polarizing layer 402a, a first phase retardation layer 103a, a second phase retardation layer 103b, a liquid crystal layer 300, a second polarizing layer 402b, a third phase retardation layer 203a, and/or a fourth phase retardation layer 203b disposed between the first substrate 101 and the second substrate 201, but is not limited thereto.

In some embodiments, the first phase retardation element 100 may be disposed between the liquid crystal layer 300 and the first polarizing layer 402 a. In some embodiments, the second phase retardation element 200 may be disposed between the liquid crystal layer 300 and the second polarizing layer 402 b. In some embodiments, the first polarizing layer 402a may be disposed between the first phase retardation element 100 and the first substrate 101. In some embodiments, the second polarizing layer 402b may be disposed between the second phase retardation element 200 and the second substrate 201. The first and/or second polarizing layers 402a and 402b in the embodiment of fig. 4 include, for example, but not limited to, a metal (nano) Wire Grid Plate (WGP).

Referring to fig. 5, fig. 5 is a schematic cross-sectional view illustrating an electronic device 50 according to another embodiment of the invention. As shown in fig. 5, in some embodiments, the first phase delay element 100 and the second phase delay element 200 may be partially disposed inside the panel PN and may be partially disposed outside the panel PN. For example, the second phase retardation layer 103b of the first phase retardation element 100 and the fourth phase retardation layer 203b of the second phase retardation element 200 may be disposed on the inner side of the panel PN (i.e., the inner side of the first substrate 101 and the second substrate 201). In some embodiments, the first phase retardation layer 103a of the first phase retardation element 100 and the third phase retardation layer 203a of the second phase retardation element 200 may be disposed outside the panel PN (i.e., outside the first substrate 101 and the second substrate 201, respectively). In other words, the first retardation layer 103a and the second retardation layer 103b of the first retardation element 100 can be disposed on two sides of the first substrate 101, respectively. In some embodiments, the third phase retardation layer 203a and the fourth phase retardation layer 203b of the second phase retardation element 200 may be respectively disposed on both sides of the second substrate 201. In the embodiment shown in fig. 5, the panel PN includes a first substrate 101, a second substrate 201, and a second phase retardation layer 103b, a liquid crystal layer 300 and/or a fourth phase retardation layer 203b disposed between the first substrate 101 and the second substrate 201.

In some embodiments (not shown), the first phase delay element 100 may be partially disposed within the panel PN and partially disposed outside the panel PN, and the second phase delay element 200 may be disposed entirely within the panel PN, but is not limited thereto. In other words, one of the first retardation layer 103a and the second retardation layer 103b may be disposed between the first substrate 101 and the liquid crystal layer 300, and the third retardation layer 203a and the fourth retardation layer 203b are disposed between the second substrate 201 and the liquid crystal layer 300. In summary, the first phase delay element 100 and/or the second phase delay element 200 may be selectively disposed completely outside the panel PN, completely inside the panel PN, or partially inside the panel PN and partially outside the panel PN.

Referring to fig. 6, fig. 6 is a graph showing an optical analysis result of the electronic device according to some embodiments of the present invention, for example, the optical analysis result is measured when the electronic device is in a dark state. The optical analysis result can be measured or analyzed by, for example, a conoscopic (conoscopic) lens measurement or other suitable instrument, but is not limited thereto. Specifically, in FIG. 6, the right-hand color level represents the luminance (cd/m) per unit area differently²) The results on the left show the corresponding to different angles theta and azimuthLuminance per unit area (cd/m)²) The case (1). Wherein the angle theta is, for example, the angle between the measuring direction and the normal direction Z of the panel PN, and the azimuth angleFor example the angle of the measuring direction in a direction parallel to the upper surface of the panel PN. In FIG. 6, it can be seen that the angle θ ranges from 0 degree (i.e. including the center point) to 20 degrees, and the azimuth angleLuminance per unit area (cd/m) in the range of 0 to 360 degrees²) About approximately between 0cd/m²To 4E-006cd/m²The range of (1). At an angle theta in the range of 20 degrees to 40 degrees, and an azimuth angleLuminance per unit area (cd/m) in the range of 0 to 360 degrees²) About between 4E-006cd/m²To 1.2E-004cd/m²The range of (1). In the range of 40 to 80 degrees of the angle theta, and in most azimuthal anglesRange (e.g. azimuth angle)Brightness per unit area (cd/m) of approximately 0 to 22.5 degrees, 67.5 to 112.5 degrees, 172.5 to 202.5 degrees, and/or 247.5 to 292.5 degrees²) About 1.2E-004cd/m²Within. In the range of 40 to 80 degrees in the angle theta and in the azimuth angle of the other partRange (azimuth angle other than the above)Range of (d), luminance per unit area (cd/m)²) About 1.6E-004cd/m²To 2.0E-004cd/m²Without being limited thereto. Therefore, the problem of dark state light leakage of the electronic device under different viewing angles is not obvious. It is understood that the luminance value per unit area (cd/m) of the aforementioned electronic device²) The range is only to illustrate the result of one embodiment, but not limited to this, the brightness value per unit area may vary according to the design of the panel PN and the material of the liquid crystal layer 300.

Referring to fig. 7, fig. 7 is a schematic cross-sectional view illustrating an electronic device 60 according to another embodiment of the invention. Fig. 7 shows a detailed structure of the panel PN according to some embodiments. It should be understood that, in fig. 7, the panel PN includes the first substrate 101, the second substrate 201 and the liquid crystal layer 300 as an example, and in the embodiment where the panel PN further includes other elements, the arrangement of the structural arrangement may be appropriately adjusted.

Referring to fig. 7, in some embodiments, the second substrate 201 is opposite to the first substrate 101, and the liquid crystal layer 300 is disposed between the first substrate 101 and the second substrate 201. As mentioned above, the first substrate 101 may be used as a driving substrate, the first substrate 101 may include a first base 101s and a circuit layer 101x, the circuit layer 101x may be disposed on the first base 101s, and the circuit layer 101x may be located between the first base 101s and the liquid crystal layer 300.

In some embodiments, the first base 101s may include a flexible substrate, a rigid substrate, or a combination thereof. In some embodiments, the material of the first substrate 101s may include glass, quartz, sapphire (sapphire), ceramic, Polyimide (PI), liquid-crystal polymer (LCP) material, Polycarbonate (PC), photosensitive polyimide (PSPI), polyethylene terephthalate (PET), other suitable materials, or a combination thereof, but is not limited thereto.

In some embodiments, the circuit layer 101x may include driving circuits, which may include, for example, active driving circuits and/or passive driving circuits. In some embodiments, the driving circuit may include a transistor (e.g., a switching transistor or a driving transistor, etc.), a data line, a scan line, a conductive pad, a dielectric layer, or other lines, etc., but is not limited thereto.

In some embodiments, the first electrode layer 111 and the first alignment layer 113 may be sequentially disposed on the circuit layer 101x, the first electrode layer 111 and the first alignment layer 113 may be located between the first substrate 101 and the liquid crystal layer 300, and the first electrode layer 111 may be electrically connected to the circuit layer 101 x. In some embodiments, the first electrode layer 111 may be patterned to have a plurality of first openings O₁. In some embodiments, the first alignment layer 113 may be conformally (conformally) formed on the first electrode layer 111 and the first openings O₁In (1).

In some embodiments, the material of the first electrode layer 111 may include a metallic conductive material, a transparent conductive material, other suitable materials, or a combination of the foregoing, but is not limited thereto. The metal conductive material may include, but is not limited to, copper (Cu), silver (Ag), tin (Sn), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), any one of the above metal alloys, other suitable materials, or a combination of the above. The transparent conductive material may include Indium Tin Oxide (ITO), tin oxide (SnO), zinc oxide (ZnO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Antimony Tin Oxide (ATO), Antimony Zinc Oxide (AZO), other suitable materials, or a combination thereof, but is not limited thereto.

As mentioned above, the second substrate 201 can be used as a color filter substrate. In some embodiments, the second substrate 201 may include a second substrate 201s and a color filter layer 201x, and the color filter layer 201x may be disposed on the second substrate 201s between the second substrate 201s and the liquid crystal layer 300. In some embodiments, the second substrate 201 also includes a light shielding layer (not shown), which may be disposed between the color filter units (not shown) of the color filter layer 201 x. The material of the second substrate 201s may be similar to that of the first substrate 101s, and is not repeated here. The material of the second substrate 201s may be the same as or different from that of the first substrate 101 s. In some embodiments, the second electrode layer 211 and the second alignment layer 213 may be sequentially disposed on the color filter layer 201x, and the second electrode layer 211 and the second alignment layer 213 may be disposed between the second substrate 201 and the liquid crystal layer 300.

In some embodiments, the second electrode layer 211 may not be patterned, i.e., the second electrode layer 211 may not have openings. Moreover, the material of the second electrode layer 211 can be similar to the material of the first electrode layer 111, and is not repeated here. Also, the material of the second electrode layer 211 may be the same as or different from the material of the first electrode layer 111.

Referring to fig. 8, fig. 8 is a schematic top view of a sub-pixel region SP of an electronic device 60 according to some embodiments of the present invention, where a sectional line a-a' in fig. 8 may correspond to the sectional structure shown in fig. 7. It should be understood that fig. 8 only shows the first electrode layer 111 for clarity of illustration, and other elements are omitted, and the electronic device 60 may actually have a plurality of sub-pixel regions SP, only one of which is shown in fig. 8.

As shown in fig. 8, the first electrode layer 111 is correspondingly disposed in the sub-pixel region SP of the electronic device 60. In light of the foregoing, the first electrode layer 111 may be patterned to have a plurality of first openings O₁. In some embodiments, the patterned first electrode layer 111 may have a main portion 111A and a plurality of branch portions 111B, the main portion 111A may divide the first electrode layer 111 into a first portion P1, a second portion P2, a third portion P3 and a fourth portion P4, wherein the first portion P1, the second portion P2, the third portion P3 and the fourth portion P4 may be arranged in a clockwise manner, for example. As shown in FIG. 8, the second and fourth portions P2 and P4 are adjacent to the first portion P1, and the third portion P3 is substantially diagonally aligned with the first portion P1. In some embodiments, there may be selectively more or fewer portions. In some embodiments, the main portion 111A may have a cross shape, but is not limited thereto. In some embodiments, the plurality of branch portions 111B may be connected to the main portion 111A and extend away from the main portion 111A, but is not limited thereto.

In some embodiments, one of the branch portions 111B corresponding to the first portion P1 has a first included angle θ with the main portion 111A₁Corresponding to a second angle θ between one of the branch portions 111B in the second portion P2 and the main portion 111A₂. In some embodiments, first included angle θ₁At a second angle theta₂Are approximately equal. In some embodiments, first included angle θ₁And/or second included angle theta₂Can be between 40 and 50 degrees (40 ≦ first angle θ)₁≦ 50 degrees; 40 DEG ≦ second angle θ₂50 degrees) or between 42 and 48 degrees (42 degrees ≦ first angle θ₁≦ 48 degrees; 42 DEG ≦ second angle θ₂≦ 48 degrees), for example, 45 degrees. It should be noted that the first included angle θ₁And a second angle theta₂The finger corresponds to an angle formed between the branch portion 111B (e.g., an extension plane thereof) and a long axis of the main portion 111A (e.g., a portion extending in the Y direction in the figure).In some embodiments, one of branches 111B corresponding to first portion P1 and one of branches 111B corresponding to adjacent second portion P2 have an included angle θ therebetween_t(i.e., can be viewed as approximately the first included angle θ)₁At a second angle theta₂The sum of (a) and (b). In some embodiments, the included angle θ_tCan be between 80 and 100 degrees (80 ≦ angle θ)_t100 degrees) or between 85 and 95 degrees (angle θ between 85 and 95 degrees ≦ 85 degrees_t95 degrees), for example, 90 degrees.

It is noted that, as shown in FIG. 8, the angle θ is_tRefers to an angle formed by the intersection of the extension plane of the first portion P1 and the extension plane of the branch 111B of the second portion P2.

Referring to fig. 8, in some embodiments, the branch 111B of the first portion P1 and the branch 111B of the second portion P2 are substantially symmetrical with respect to the long axis (i.e., the portion extending in the Y direction in the figure) of the main portion 111A. In some embodiments, the branch 111B of the third portion P3 and the branch 111B of the fourth portion P4 are substantially symmetrical with respect to the major axis of the main portion 111A. In some embodiments, the branch portion 111B of the first portion P1 and the branch portion 111B of the fourth portion P4 are substantially symmetrical with respect to the short axis of the main portion 111A (a portion extending in the X direction in the drawing). In some embodiments, branch 111B of second portion P2 and branch 111B of third portion P3 are substantially symmetrical with respect to the minor axis of main portion 111A. The term "symmetrical" includes, for example, that the included angle between the branch portion 111B and the main portion 111A is substantially the same, and the width of the branch portion 111B and/or the pitch of the adjacent branch portions 111B is substantially the same, but is not limited thereto.

Referring to fig. 9, fig. 9 is a schematic top view illustrating a sub-pixel region SP of an electronic device 60 according to another embodiment of the invention. The embodiment shown in fig. 9 is similar to the embodiment shown in fig. 8, and one of the differences is that the extension direction of the branch portion 111B of the first electrode layer 111 in fig. 9 is different from that in fig. 8.

As shown in fig. 9, in some embodiments, one of the branch portions 111B corresponding to the first portion P1 has a first included angle θ with the main portion 111A₁Corresponding to a second angle θ between one of the branch portions 111B in the second portion P2 and the main portion 111A₂Corresponding to a third angle θ between one of the branch portions 111B in the third portion P3 and the main portion 111A₃Corresponding to a fourth angle θ between one of the branch portions 111B and the main portion 111A in the fourth portion P4₄. Furthermore, the third angle θ₃And a fourth angle theta₄Is defined to form a first included angle theta with the first₁And a second angle theta₂The definition of (a) is similar and will not be repeated here. In some embodiments, first included angle θ₁At a second angle theta₂Not equal. In some embodiments, third included angle θ₃And a fourth angle theta₄Not equal. In some embodiments, one of the branches 111B (e.g., an extension plane thereof) corresponding to the first portion P1 and one of the branches 111B (e.g., an extension plane thereof) corresponding to the adjacent second portion P2 have an included angle θ therebetween_t(i.e., can be roughly regarded as the first included angle theta)₁At a second angle theta₂The sum of (a) and (b). In some embodiments, the included angle θ_tCan be between 80 and 100 degrees (80 ≦ angle θ)_t100 degrees) or between 85 and 95 degrees (angle θ between 85 and 95 degrees ≦ 85 degrees_t95 degrees), for example, 90 degrees. In some embodiments, one of the branches 111B (e.g., an extension surface thereof) corresponding to the third portion P3 and one of the branches 111B (e.g., an extension surface thereof) corresponding to the adjacent fourth portion P4 have an included angle therebetween (not shown, i.e., can be generally regarded as a third included angle θ)₃And a fourth angle theta₄Total of) the angle range of the angle is, for example, close to the angle θ described above_tThe angular range of (c). In some embodiments, first included angle θ₁Can be between 45 and 75 degrees (45 ≦ first angle θ)₁≦ 75 degrees), second angle θ₂Between 15 and 45 degrees (15 ≦ first angle θ)₁≦ 45 degrees).

As shown in FIG. 9, in some embodiments, third included angle θ₃At a first angle theta₁Are approximately equal. In some embodiments, second included angle θ₂And a fourth angle theta₄Are approximately equal. In some casesIn the embodiment, based on the long axis (a portion extending in the Y direction in the figure) of the main portion 111A, the branch portion 111B of the first portion P1 and the branch portion 111B of the second portion P2 are in an asymmetric relationship. In some embodiments, the branch 111B of the third portion P3 and the branch 111B of the fourth portion P4 have an asymmetric relationship with respect to the major axis of the main portion 111A. In some embodiments, the branch 111B of the first portion P1 and the branch 111B of the fourth portion P4 have an asymmetric relationship with respect to the short axis of the main portion 111A. In some embodiments, branch 111B of second portion P2 and branch 111B of third portion P3 are in an asymmetric relationship with respect to the minor axis of main portion 111A (the portion extending in the X direction in the figure).

Compared to the first electrode layer 111 shown in fig. 8, the extending direction of the branch 111B of the first electrode layer 111 shown in fig. 9 is adjusted in a counterclockwise manner, that is, the extending direction of the branch 111B under different portions (e.g., the first portion P1, the second portion P2, the third portion P3 and the fourth portion P4) is adjusted by about 5 degrees to 45 degrees or 5 degrees to 30 degrees in the counterclockwise direction, but not limited thereto. In some embodiments, when the chiral agent can rotate the liquid crystal molecules clockwise, the first electrode layer 111 can be adjusted, for example, in a manner that the extending direction of the branch portion 111B of the first electrode layer 111 is counterclockwise as shown in fig. 9, so as to achieve a better transmittance, but not limited thereto. In other embodiments (not shown), compared to the first electrode layer 111 shown in fig. 8, the extending direction of the branch 111B of the first electrode layer 111 may be adjusted in a clockwise manner, that is, the extending directions of the branch 111B under different portions (e.g., the first portion P1, the second portion P2, the third portion P3, and the fourth portion P4) are all adjusted by about 5 degrees to 45 degrees or 5 degrees to 30 degrees in the clockwise direction, but not limited thereto. In some embodiments, when the chiral agent can rotate the liquid crystal molecules clockwise, the design of the first electrode layer 111 can be adjusted, for example, the extending direction of the branch portion 111B can be selected to be counterclockwise, so as to achieve a better transmittance, but is not limited thereto.

Referring to FIG. 10, FIG. 10 shows an electronic device according to other embodiments of the present inventionThe device 70 is schematically illustrated in cross-sectional configuration. The embodiment shown in FIG. 10 is similar to the embodiment shown in FIG. 7, one of the differences is that in FIG. 10, the second electrode layer 211 of the electronic device 70 may be patterned to have a plurality of second openings O₂. In some embodiments, the second alignment layer 213 may be conformally (conformally) formed on the second electrode layer 211 and the second openings O₂In (1). In some embodiments, the second electrode layer 211 and the first opening O may be formed in a normal direction (e.g., a Z direction) of the first substrate 101₁The first electrode layer 111 may overlap or be in contact with the second opening O₂And (4) overlapping. In some embodiments, the second opening O₂And the first opening O₁May be the same or different.

In summary, according to some embodiments of the present invention, an electronic device includes a first phase retardation element and a second phase retardation element, and an in-plane retardation value (Ro) and an out-of-plane retardation value (Rth) of the first phase retardation element and the second phase retardation element are within the design range of the present disclosure, so as to improve the display quality of the electronic device, for example, reduce the dark state light leakage problem or the uneven panel brightness problem at different viewing angles.

Although the embodiments of the present invention and their advantages have been disclosed, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the invention. Features of the embodiments of the invention may be combined and matched as desired without departing from the spirit or conflict of the invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but it is to be understood that any process, machine, manufacture, composition of matter, means, method and steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present application. Accordingly, the scope of the present application includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described above. The protection scope of the present invention is subject to the claims. It is not necessary for any embodiment or claim of the invention to achieve all of the objects, advantages, and features disclosed herein.