阅读说明：本技术 半导体装置的形成方法 (Method for forming semiconductor device ) 是由 颜晨恩 康金玮 詹凯钧 吕文雄 林政仁 郑明达 李明机 于 2021-04-08 设计创作，主要内容包括：一种半导体装置的形成方法,包括：提供基板；形成掩膜层于基板的表面之上,掩膜层具有开口位于表面的部分之上；沉积导电层于表面的部分及掩膜层之上；移除掩膜层及掩膜层之上的导电层,在移除掩膜层及掩膜层之上的导电层之后,在表面的部分之上余留的导电层形成导电垫,且导电垫的宽度朝着基板增加；以及通过焊料层接合装置至导电垫,导电垫埋藏于焊料层中。(A method of forming a semiconductor device, comprising: providing a substrate; forming a mask layer on the surface of the substrate, the mask layer having an opening on a portion of the surface; depositing a conductive layer on the surface part and the mask layer; removing the mask layer and the conductive layer over the mask layer, after removing the mask layer and the conductive layer over the mask layer, forming a conductive pad on the conductive layer remaining over the portion of the surface, and the width of the conductive pad increasing toward the substrate; and bonding the device to the conductive pad through the solder layer, the conductive pad being buried in the solder layer.)

1. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a mask layer on a surface of the substrate, wherein the mask layer has an opening on a portion of the surface;

depositing a conductive layer over the portion of the surface and the mask layer;

removing the mask layer and the conductive layer over the mask layer, wherein after removing the mask layer and the conductive layer over the mask layer, the conductive layer remaining over the portion of the surface forms a conductive pad, and a width of the conductive pad increases toward the substrate; and

a device is coupled to the conductive pad through a solder layer, wherein the conductive pad is buried in the solder layer.

Technical Field

Embodiments of the present invention relate to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a package structure.

Background

The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have resulted in several generations of integrated circuits. Each generation has smaller and more complex circuitry than the previous generation. However, these advances have increased the complexity of processing and manufacturing integrated circuits.

As integrated circuits evolve, the functional density (i.e., the number of interconnected devices per chip area) increases as the geometry size (i.e., the minimum elements (or lines) that can be created using a manufacturing process) decreases.

However, as feature sizes continue to decrease, manufacturing processes become more difficult to perform. Therefore, it is a challenge to form smaller and smaller reliable semiconductor devices. Bonding semiconductor devices to other devices is also challenging.

Disclosure of Invention

An embodiment of the invention includes a method for forming a semiconductor device, including: providing a substrate; forming a mask layer on the surface of the substrate, wherein the mask layer has an opening on a portion of the surface; depositing a conductive layer on the surface part and the mask layer; removing the mask layer and the conductive layer over the mask layer, wherein after removing the mask layer and the conductive layer over the mask layer, the conductive layer remaining over the portion of the surface forms a conductive pad, and a width of the conductive pad increases toward the substrate; and bonding the device to the conductive pad through the solder layer, the conductive pad being buried in the solder layer.

Drawings

The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are merely illustrative examples. In fact, the dimensions of the elements may be exaggerated or minimized to clearly illustrate the technical features of the embodiments of the present invention.

FIGS. 1A-1G are cross-sectional views illustrating stages in a process for forming a semiconductor device, in accordance with certain embodiments.

Fig. 1A-1 illustrate top views of the substrate, insulating layer, and conductive lines of fig. 1A, according to some embodiments.

Fig. 1A-2 illustrate top views of the substrate, insulating layer, and conductive lines of fig. 1A, according to some embodiments.

FIG. 1B-1 depicts a top view of FIG. 1B, according to some embodiments.

Fig. 1E-1 depicts a top view of fig. 1E, according to some embodiments.

Fig. 1E-2 depicts a top view of fig. 1E, according to some embodiments.

FIG. 1F-1 depicts a bottom view of FIG. 1F, according to some embodiments.

Fig. 1F-2 depicts a bottom view of fig. 1F, according to some embodiments.

Fig. 1G-1 depicts a top view of fig. 1G, according to some embodiments.

Fig. 1G-2 depicts a top view of fig. 1G, according to some embodiments.

FIG. 2 is a cross-sectional view illustrating a semiconductor device, according to some embodiments.

FIGS. 3A-3F are cross-sectional views depicting stages in a process for forming a semiconductor device, in accordance with certain embodiments.

FIGS. 4A-4F are cross-sectional views depicting stages in a process for forming a semiconductor device, in accordance with certain embodiments.

FIG. 5 is a top view depicting variations of a substrate, an insulating layer, and conductive line protrusions, in accordance with some embodiments.

FIG. 6 is a top view depicting variations of a substrate, an insulating layer, and conductive line protrusions, according to some embodiments.

FIG. 7 is a top view depicting variations of a substrate, insulating layer, and conductive line protrusions, in accordance with some embodiments.

FIG. 8 is a top view depicting variations of a substrate, insulating layer, and conductive line protrusions, in accordance with some embodiments.

FIG. 9 is a top view depicting variations of a substrate, insulating layer, and conductive line protrusions, in accordance with some embodiments.

FIG. 10 is a top view depicting variations of a substrate, an insulating layer, and conductive line protrusions, in accordance with some embodiments.

FIG. 11 is a top view depicting variations of a substrate, insulating layer, and conductive line protrusions, in accordance with some embodiments.

FIG. 12 is a top view depicting variations of a substrate, insulating layer, and conductive line protrusions, in accordance with some embodiments.

FIG. 13 is a top view depicting variations of a substrate, insulating layer, and conductive line protrusions, in accordance with some embodiments.

FIG. 14 is a top view depicting variations of a substrate, insulating layer, and conductive line protrusions, in accordance with some embodiments.

Wherein the reference numerals are as follows:

100, 200, 300, 400: semiconductor device with a plurality of semiconductor chips

110: substrate

112: surface of

112 a: in part

114: projecting part

114 a: columnar structure

116: groove

116 a: bottom surface

117: base seat

118: pedestal

118 a: top surface

118 b: side wall

118 p: peripheral part

120: conductive wire

124: side wall

126: side wall

128: side wall

129a, 129b, 129c, 129 d: corner

130: mask layer

132: opening of the container

132 a: inner wall

132 u: upper part

132 w: lower part

134: groove

136: top surface

140: conductive layer

141a, 141 b: top surface

142: conducting pad

142 a: top surface

142 b: side wall

150: device for measuring the position of a moving object

152: bottom surface

154: projecting part

154 a: columnar structure

160: conducting pad

170: solder layer

310: conductive structure

A: insulating layer

B: boundary of

D1, D2: distance between two adjacent plates

E1: end point part

W1, W2: width of

G: edge portion

T1, T2, T3, T3', T4, T5, T6, T7: thickness of

θ 1: angle of rotation

I-I': section line

R1, R2: region(s)

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. The following disclosure describes specific examples of components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if embodiments of the present invention describe a first feature formed on or above a second feature, that is, embodiments that may include the first feature in direct contact with the second feature, embodiments may also include additional features formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein to facilitate describing the relationship of element(s) or feature(s) to one another in the drawings and include different orientations of the device in use or operation and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation. It should be understood that additional operations may be provided before, during, and/or after the stages described in these embodiments, and other embodiments of this method may replace or eliminate some operations.

Some embodiments of the invention are described. Additional operations may be provided before, during, and/or after the stages described in these embodiments. Some of the stages described may be substituted or eliminated in different embodiments. Additional features may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated in various embodiments. Even though some embodiments may operate in a particular order, these operations may be performed in another logical order.

FIGS. 1A-1G are cross-sectional views illustrating stages in a process for forming a semiconductor device, in accordance with certain embodiments. 1A-1 are top views of the substrate, insulating layer, and conductive lines of FIG. 1A, according to some embodiments. FIG. 1A is a cross-sectional view of a semiconductor device, taken along section line I-I' in FIG. 1A-1, according to some embodiments. According to some embodiments, as illustrated in fig. 1A and 1A-1, a substrate 110 is provided. According to some embodiments, the substrate 110 has a surface 112 and a protruding portion 114. According to some embodiments, the protruding portion 114 protrudes from the surface 112. According to some embodiments, the protruding portion 114 is adjacent to the portion 112a of the surface 112. According to some embodiments, the protruding portion 114 surrounds a portion 112a of the surface 112.

According to some embodiments, as illustrated in fig. 1A and 1A-1, the protrusion 114 includes pillar structures 114a spaced apart from each other. According to some embodiments, the pillar structures 114a are spaced apart from each other by the same distance D1.

The substrate 110 includes, for example, a semiconductor substrate. In some embodiments, the substrate 110 comprises silicon or germanium in a single crystal, polycrystalline, or amorphous structure in an elemental semiconductor material. In some other embodiments, the substrate 110 is made of a compound semiconductor, such as silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), an alloy semiconductor such as SiGe, or GaAsP, or a combination thereof. The substrate 110 may also include multiple layers of semiconductors, Semiconductor On Insulator (SOI), such as silicon on insulator or germanium on insulator, or combinations thereof.

In some embodiments, the substrate 110 includes various device features. In some embodiments, various device components are formed in and/or on the substrate 110. For purposes of brevity and clarity, various device components are not shown in the figures. Examples of various device components include active devices, passive devices, other suitable components, or combinations thereof. The active components may include transistors or diodes (not shown). Passive components include resistors, capacitors, or other suitable passive components.

For example, the transistors may be Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), and the like. Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form various device components. The front end of line semiconductor fabrication process may include deposition, etching, implantation, lithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in the substrate 110. The isolation features are used to define active regions and to electrically isolate device components in and/or on the substrate 110 in the active regions. In some embodiments, the isolation features include Shallow Trench Isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

According to some embodiments, as illustrated in fig. 1A and 1A-1, an insulating layer a is formed over a substrate 110. According to some embodiments, the insulating layer a is made of an oxide (e.g., silicon oxide), fluorine-doped silicate glass (FSG), a low-k dielectric material, polyimide (polyimide), silicon nitride (silicon nitride), Undoped Silicate Glass (USG), and/or other suitable insulating materials. The insulating layer a may be formed by an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, a thermal oxidation process, or other suitable processes.

According to some embodiments, as illustrated in fig. 1A and 1A-1, a conductive line 120 is formed over an insulating layer a (or substrate 110). According to some embodiments, protruding portion 114 surrounds end portion E1 of conductive line 120. According to some embodiments, conductive line 120 is made of a conductive material, such as a metal (e.g., tungsten, copper, or aluminum), an alloy thereof. According to some embodiments, the conductive lines 120 are formed using an electroplating plating process and an etching process.

The projections 114 can have different variations, such as the projections 114 of fig. 1A-2. 1A-2 are top views of the substrate, insulating layer, and conductive lines of FIG. 1A, according to some embodiments. Fig. 1A is a cross-sectional view of a semiconductor device, according to some embodiments, as illustrated along section line I-I' in fig. 1A-2. According to some embodiments, as illustrated in fig. 1A and 1A-2, the protruding portion 114 is a continuous stripe structure. According to some embodiments, protruding portion 114 continuously surrounds end portion E1 of conductive line 120.

Fig. 1B-1 is a top view of the semiconductor device of fig. 1B, according to some embodiments. FIG. 1B is a cross-sectional view of the semiconductor device, according to some embodiments, as illustrated along section line I-I' in FIG. 1B-1.

According to some embodiments, as illustrated in fig. 1B and 1B-1, a mask layer 130 is formed over the insulating layer a (or the surface 112 of the substrate 110) and a portion of the conductive line 120. According to some embodiments, the mask layer 130 covers the entire protruding portion 114. According to some embodiments, masking layer 130 has opening 132 over portion 112a of surface 112.

According to some embodiments, opening 132 exposes end portion E1 of conductive line 120 and insulating layer a over portion 112 a. According to some embodiments, opening 132 has an inner wall 132 a. In some embodiments, the width W1 of the opening 132 increases toward the substrate 110. According to some embodiments, the width W1 of the upper portion 132u of the opening 132 continuously increases toward the substrate 110.

According to some embodiments, the mask layer 130 adjacent to the substrate 110 has a recess 134. According to some embodiments, the groove 134 is recessed from the inner wall 132a of the opening 132. According to some embodiments, recess 134 continuously surrounds end portion E1 of conductive line 120 exposed by opening 132.

According to some embodiments, the width W1 of the lower portion 132W of the opening 132 continuously increases toward the substrate 110. According to some embodiments, the mask layer 130 has an edge portion G between the inner wall 132a of the opening 132 and the groove 134. According to some embodiments, edge portion G surrounds the portion of conductive line 120 exposed by opening 132.

According to some embodiments, the mask layer 130 is a photoresist layer. According to some embodiments, the mask layer 130 is made of a negative photoresist material. Negative photoresists are capable of polymerization and become insoluble upon exposure to radiation, such as ultraviolet radiation.

Forming the mask layer 130 includes forming a negative photoresist layer on the insulating layer a; selectively exposing the negative photoresist layer to radiation causes polymerization to occur on areas of the substrate 110 that are intended to be protected in subsequent processing, and removing the unexposed portions of the negative photoresist layer with a solvent that has minimal effect on the polymerized portions of the negative photoresist layer.

Since the mask layer 130 is made of a negative photoresist material, which is capable of polymerizing and becomes insoluble when exposed to radiation, the mask layer 130 that is further from the substrate 110 (i.e., the mask layer 130 that is closer to the radiation) is wider than the mask layer 130 that is closer to the substrate 110 (i.e., the mask layer 130 that is further from the radiation) after the photolithography process is performed.

In some embodiments, the negative photoresist material adds an additive to increase the light absorption coefficient of the upper half of the mask layer 130. Therefore, according to some embodiments, the optical absorption coefficient of the upper half of the mask layer 130 is greater than the optical absorption coefficient of the lower half of the mask layer 130. Thus, according to some embodiments, the additive aids in forming the recess 134. The recess 134 may be formed using a suitable additive added to the negative photoresist, an exposure process with suitable exposure energy, and a suitable development process.

According to some embodiments, as illustrated in fig. 1C, a conductive layer 140 is formed over the surface 112, the conductive line 120, and the mask layer 130. According to some embodiments, the conductive layer 140 covers the top surface 136 of the mask layer 130, the inner wall 132a of the opening 132, and the inner wall 134a of the recess 134.

According to some embodiments, the conductive layer 140 is a single layer structure. In some other embodiments, conductive layer 140 is a multilayer structure. According to some embodiments, the conductive layer 140 is made of a metal (e.g., gold, tin, copper, or silver), or an alloy thereof.

According to some embodiments, the conductive layer 140 is formed using a deposition process, such as an anisotropic deposition process. According to some embodiments, the deposition rate of the conductive layer 140 on substantially vertical surfaces, such as the inner walls 132a of the opening 132, is less than the deposition rate of the conductive layer 140 on substantially horizontal surfaces, such as the top surfaces 122 and 136 of the conductive lines 120 and the masking layer 130. According to some embodiments, since the recess 134 is recessed from the inner wall 132a, the deposition rate of the conductive layer 140 in the recess 134 is less than the deposition rate of the conductive layer 140 on the inner wall 132 a.

According to some embodiments, the conductive layer 140 on the inner wall 134a of the recess 134 is thinner than the conductive layer 140 on the inner wall 132a of the opening 132. According to some embodiments, the conductive layer 140 on the inner wall 132a is thinner than the conductive layer 140 on the conductive line 120 (or the portion 112a of the surface 112). According to some embodiments, the conductive layer 140 on the conductive line 120 (or the portion 112a of the surface 112) is thinner than the conductive layer 140 on the top surface 136 of the masking layer 130.

According to some embodiments, the deposition process comprises a physical vapor deposition process. According to some embodiments, the conductive layer 140 on the conductive line 120 has a curved top surface 141a due to the conductive layer 140 on the conductive line 120 being formed using a physical deposition process and surrounded by the mask layer 130.

According to some embodiments, the physical vapor deposition generates heat in the mask layer 130, the mask layer 130 deforms, and the top surface 136 of the mask layer 130 becomes a curved top surface. According to some embodiments, the conductive layer 140 on the curved top surface 136 also has a curved top surface 141 b.

According to some embodiments, as illustrated in fig. 1D, the inner wall 132a, the groove 134, and the conductive layer 140 on the insulating layer a are removed. According to some embodiments, the conductive layer 140 remaining on the conductive line 120 after the removal process forms a conductive pad 142.

According to some embodiments, the conductive pad 142 has a curved top surface 142 a. In some embodiments, the width W2 of the conductive pad 142 increases toward the substrate 110. According to some embodiments, the width W2 continues to increase toward the substrate 110. According to some embodiments, the removal process comprises an etching process, such as a wet etching process.

Fig. 1E-1 is a top view of the semiconductor device of fig. 1E, according to some embodiments. FIG. 1E is a cross-sectional view of the semiconductor device of FIG. 1E-1 along section line I-I', according to some embodiments. As illustrated in fig. 1E and 1E-1, the mask layer 130 and the conductive layer 140 on the mask layer 130 are removed. According to some embodiments, as illustrated in FIG. 1E-1, the pillar structure 114a surrounds the conductive pad 142.

According to some embodiments, since the conductive layer 140 on the inner wall 134a of the recess 134 is thinner than the conductive layer 140 on the inner wall 132a of the opening 132 (as illustrated in fig. 1C), the conductive layer 140 on the inner wall 134a tends to be completely removed when the conductive layer 140 on the inner wall 132a is removed (as illustrated in fig. 1D), which facilitates complete removal of the mask layer 130. Thus, according to some embodiments, forming the recess 134 improves the yield of the removal process of the mask layer 130.

According to some embodiments, since the conductive pad 142 is formed by a lift-off process (i.e., the steps of fig. 1B-1E), the conductive pad 142 is not formed by the protrusion 114 surrounding the conductive pad 142. In contrast, if the conductive pad 142 is formed by an electroplating process, the step coverage of the seed layer for conducting current on the protrusion 114 during the electroplating process is less uniform, resulting in high resistance of the seed layer and plating failure, according to some embodiments.

Further, according to some embodiments, if forming the conductive pad 142 includes: forming a stop layer on the substrate 110; depositing a conductive layer on the stop layer; performing a photolithography process and an etching process on the conductive layer; and etching the remaining conductive layer to expose the stop layer, which may damage the protrusion 114.

According to some embodiments, as depicted in fig. 1E, thickness T1 of protruding portion 114 is greater than thickness T2 of conductive line 120. According to some embodiments, the thickness T1 of the protruding portion 114 is greater than the maximum thickness T3 of the conductive pad 142. According to some embodiments, the maximum thickness T3 is in the range of about 2500nm to about 5500 nm. According to some embodiments, the angle θ 1 between the sidewall 142b of the conductive pad 142 and the top surface 122 of the conductive line 120 ranges from about 45 ° to about 75 °.

According to some embodiments, the side wall 142b is beveled. According to some embodiments, a boundary B is between the sidewall 142B and the curved top surface 142 a. According to some embodiments, the conductive pad 142 below the boundary B has a thickness T3'. In some embodiments, the ratio of the thickness T3' to the maximum thickness T3 is in the range of about 0.1 to about 0.7.

Fig. 1E-2 are top views of the semiconductor device of fig. 1E, according to some other embodiments. FIG. 1E is a cross-sectional view of the semiconductor device depicted in FIGS. 1E-2 along section line I-I', according to some embodiments. In some other embodiments, as depicted in fig. 1E and 1E-2, the protruding portion 114 continuously surrounds the conductive pad 142.

According to some embodiments, as depicted in fig. 1F, a device 150 is provided. The device 150 includes a chip, package, active device, passive device, light emitting device, or other suitable device. According to some embodiments, the light emitting device comprises a laser diode (not shown) emitting a laser beam. According to some embodiments, the device 150 has a bottom surface 152 and a protruding portion 154. According to some embodiments, the projections 154 protrude from the bottom surface 152.

According to some embodiments, FIG. 1F-1 is a bottom view of the device 150 of FIG. 1F. FIG. 1F is a cross-sectional view of the device 150 depicted in FIG. 1F-1, along section line I-I', according to some embodiments. In some embodiments, as depicted in fig. 1F and 1F-1, the protruding portion 154 includes a pillar structure 154 a.

According to some embodiments, the pillar structures 154a are spaced apart from one another. According to some embodiments, the pillar structures 154a are spaced apart from each other by the same distance D2. According to some embodiments, the distance D1 between the pillar structures 114a of FIGS. 1A-1 is substantially equal to the distance D2.

According to some embodiments, the term "substantially equal" in embodiments of the present invention refers to "within 10%". For example, according to some embodiments, the term "substantially equal" refers to the difference between the distances D1 and D2 being within 10% of the average of the distances D1 and D2. The differences may result from the manufacturing process.

According to some embodiments, as depicted in fig. 1F, a conductive pad 160 is formed on the bottom surface 152 of the device 150. According to some embodiments, the conductive pad 160 is electrically connected to the laser diode of the device 150. According to some embodiments, the conductive pad 160 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, or silver), or an alloy thereof.

According to some embodiments, as illustrated in fig. 1F and 1F-1, a solder layer 170 is formed over the conductive pad 160. According to some embodiments, the conductive pad 160 is located between the device 150 and the solder layer 170. According to some embodiments, the solder layer 170 is made of a conductive material, such as an alloy material including tin, copper, silver, antimony, indium, zinc, and/or lead. According to some embodiments, as depicted in fig. 1F-1, the protruding portion 154 (or the pillar structure 154a) surrounds the conductive pad 160 and the solder layer 170.

1F-2 are bottom views of the device 150 of FIG. 1F, according to some embodiments. FIG. 1F is a cross-sectional view of the device 150 depicted in FIGS. 1F-2, taken along section line I-I', according to some embodiments. In some embodiments, as illustrated in fig. 1F and 1F-2, the protruding portion 154 is a continuous strip structure. According to some embodiments, the protruding portion 154 continuously surrounds the conductive pad 160 and the solder layer 170.

According to some embodiments, the device 150 is bonded to the conductive pad 142 through the conductive pad 160 and the solder layer 170, as depicted in fig. 1G. In this step, the semiconductor device 100 is formed, according to some embodiments. According to some embodiments, when the device 150 is bonded to the conductive pad 142, the protruding portion 154 is bonded to the protruding portion 114 (or insulating layer a).

According to some embodiments, the protrusions 114 and 154 are configured to support the device 150 to maintain the device 150 level and to prevent the device 150 from being affected by the solder layer 170. In some other embodiments, insulating layer a is not formed over protruding portion 114, and protruding portion 154 is in direct contact with protruding portion 114.

According to some embodiments, the projections 154 are aligned with the projections 114. According to some embodiments, if the protrusion 154 includes a pillar structure 154a (as shown in fig. 1F-1), the protrusion 114 includes a pillar structure 114a (as shown in fig. 1A-1). According to some embodiments, if the protruding portion 154 includes a continuous stripe structure (as illustrated in fig. 1F-2), the protruding portion 114 includes a continuous stripe structure (as illustrated in fig. 1A-2).

According to some embodiments, the protruding portion 154 surrounds the conductive pad 142. According to some embodiments, the solder layer 170 covers the curved top surface 142 a. According to some embodiments, the conductive pad 142 extends partially into the solder layer 170. In some embodiments, an upper portion of the conductive pad 142 is buried in the solder layer 170. Thus, according to some embodiments, the adhesion between the conductive pad 142 and the solder layer 170 is improved.

According to some embodiments, as depicted in fig. 1G-1, the protruding portions 114 and 154 have the same shape. According to some embodiments, as illustrated in fig. 1G-1, the protruding portion 154 includes a pillar structure 154a, and the protruding portion 114 includes a pillar structure 114 a. According to some embodiments, the pillar structures 154a are respectively aligned with the corresponding pillar structures 114a thereunder.

According to some embodiments, as illustrated in fig. 1G-1, the pillar structure 154a and the corresponding pillar structure 114a thereunder have the same shape, such as a rectangle, a circle, an ellipse, a triangle, or another polygon.

Fig. 1G-2 are top views of the semiconductor device of fig. 1G, according to some embodiments. Fig. 1G is a cross-sectional view of the semiconductor device depicted in fig. 1G-2 along section line I-I', according to some embodiments. In some embodiments, as illustrated in fig. 1G and 1G-2, the protruding portion 154 comprises a continuous stripe structure, and the protruding portion 114 comprises a continuous stripe structure.

According to some embodiments, the continuous strip-like structure of the protruding portion 154 is aligned with the continuous strip-like structure of the protruding portion 114. According to some embodiments, as illustrated in fig. 1G-2, the continuous stripe structure of the protruding portion 154 has the same shape as the continuous stripe structure of the protruding portion 114, such as a U-shape.

Fig. 2 is a cross-sectional view of a semiconductor device 200, according to some embodiments. According to some embodiments, as depicted in fig. 2, the semiconductor device 200 is similar to the semiconductor device 100 in fig. 1G, except that the semiconductor device 200 does not have the protruding portions 114 and 154 of the semiconductor device 100. According to some embodiments, the semiconductor device 200 may be formed in a process similar to or the same as the process used to form the semiconductor device 100.

Fig. 3A-3F are cross-sectional views of various stages in a process for forming a semiconductor device, according to some embodiments. According to some embodiments, as illustrated in fig. 3A, a substrate 110 is provided. According to some embodiments, the substrate 110 has regions R1 and R2.

According to some embodiments, the thickness T4 of the substrate 110 in the region R1 is different from the thickness T5 of the substrate 110 in the region R2. According to some embodiments, the thickness T4 is less than the thickness T5.

According to some embodiments, the substrate 110 has a surface 112. According to some embodiments, the surface 112 has grooves 116. According to some embodiments, the groove 116 is in the region R1. According to some embodiments, as illustrated in fig. 3A, an insulating layer a is formed on the surface 112 and in the recess 116.

According to some embodiments, as illustrated in fig. 3A, a conductive structure 310 is formed on the insulating layer a on the bottom surface 116a of the recess 116. Conductive structure 310 includes a conductive line that is similar or identical to conductive line 120 of fig. 1G or other suitable conductive structure.

According to some embodiments, the conductive structure 310 is made of a conductive material, such as a metal (e.g., tungsten, copper, or aluminum) or an alloy thereof. According to some embodiments, the conductive structure 310 is formed using an electroplating plating process and an etching process.

According to some embodiments, as illustrated in fig. 3B, a mask layer 130 is formed over the insulating layer a. According to some embodiments, the mask layer 130 has an opening 132. According to some embodiments, the opening 132 is located over the conductive structure 310. According to some embodiments, the mask layer 130 covers the inner wall 116b of the recess 116.

According to some embodiments, the inner wall 116b may also be referred to as a boundary between the regions R1 and R2. According to some embodiments, the mask layer 130 extends across the boundary between the regions R1 and R2.

In some embodiments, the width W1 of the opening 132 increases toward the substrate 110. According to some embodiments, the width W1 of the upper portion 132u of the opening 132 continuously increases toward the substrate 110.

According to some embodiments, the mask layer 130 covering the inner wall 116b has a recess 134. According to some embodiments, the groove 134 is recessed from the inner wall 132a of the opening 132. According to some embodiments, the groove 134 is in the groove 116. According to some embodiments, the recess 134 is proximate the bottom surface 116a of the recess 116.

According to some embodiments, the width W1 of the lower portion 132W of the opening 132 continues to increase toward the substrate 110. According to some embodiments, the mask layer 130 has an edge portion G between the inner wall 132a of the opening 132 and the groove 134. According to some embodiments, the edge portion G surrounds the conductive structure 310 exposed by the opening 132.

According to some embodiments, as illustrated in fig. 3C, a conductive layer 140 is deposited over the conductive structure 310, the bottom surface 116a, and the mask layer 130. According to some embodiments, the conductive layer 140 covers the top surface 136 of the mask layer 130, the inner wall 132a of the opening 132, and the inner wall 134a of the recess 134.

According to some embodiments, conductive layer 140 on inner wall 134 is thinner than conductive layer 140 on inner wall 132a of opening 132. According to some embodiments, the conductive layer 140 on the inner wall 132a is thinner than the conductive layer 140 on the conductive structure 310. According to some embodiments, the conductive layer 140 on the conductive structure 310 is thinner than the conductive layer 140 on the top surface 136 of the masking layer 130.

According to some embodiments, the deposition process of the conductive layer 140 includes a physical vapor deposition process. According to some embodiments, since the conductive layer 140 is formed on the conductive structure 310 by using a physical vapor deposition process, and the conductive layer 140 is surrounded by the mask layer 130, the conductive layer 140 on the conductive structure 310 has a curved top surface 141 a.

According to some embodiments, the mask layer 130 is deformed due to heat generated in the mask layer 130 by the physical vapor deposition process, and the top surface 136 of the mask layer 130 becomes a curved top surface. According to some embodiments, the conductive layer 140 on the curved top surface 136 also has a curved top surface 141 b.

According to some embodiments, as illustrated in fig. 3D, the inner wall 132a, the groove 134, and the conductive layer 140 on the insulating layer a are removed. According to some embodiments, the conductive layer 140 remaining on the conductive structure 310 after the removal process forms the conductive pad 142.

According to some embodiments, the conductive pad 142 has a curved top surface 142 a. In some embodiments, the width W2 of the conductive pad 142 increases toward the substrate 110. According to some embodiments, the width W2 continues to increase toward the substrate 110. According to some embodiments, the removal process comprises an etching process, such as a wet etching process.

According to some embodiments, as depicted in fig. 3E, a device 150 is provided. The device 150 includes a chip, package, active device, passive device, light emitting device, or other suitable device. According to some embodiments, the light emitting device comprises a laser diode (not shown) emitting a laser beam. According to some embodiments, the device 150 has a bottom surface 152.

According to some embodiments, as depicted in fig. 3E, a conductive pad 160 is formed on the bottom surface 152 of the device 150. According to some embodiments, the conductive pad 160 is electrically connected to the device 150. According to some embodiments, as illustrated in fig. 3E, a solder layer 170 is formed over the conductive pad 160. According to some embodiments, the conductive pad 160 is located between the device 150 and the solder layer 170.

According to some embodiments, the device 150 is bonded to the conductive pad 142 through the conductive pad 160 and the solder layer 170, as depicted in fig. 3F. According to some embodiments, the conductive pad 142 extends partially into the solder layer 170. According to some embodiments, the solder layer 170 is partially located in the recess 116. At this step, the semiconductor device 300 is formed, according to some embodiments.

Fig. 4A-4F are cross-sectional views of various stages in a process for forming a semiconductor device, according to some embodiments. According to some embodiments, as illustrated in fig. 4A, a substrate 110 is provided. According to some embodiments, the substrate 110 has regions R1 and R2.

According to some embodiments, the thickness T6 of the substrate 110 in the region R1 is different from the thickness T7 of the substrate 110 in the region R2. According to some embodiments, the thickness T6 is greater than the thickness T7.

According to some embodiments, the substrate 110 has a base 117 and a pedestal 118. According to some embodiments, a pedestal 118 is positioned above the base 117. According to some embodiments, the base 117 is wider than the pedestal 118. According to some embodiments, the pedestal 117 is located in the regions R1 and R2. According to some embodiments, the pedestal 118 is located in the region R1.

According to some embodiments, as illustrated in fig. 4A, an insulating layer a is formed over the substrate 110. According to some embodiments, as illustrated in FIG. 4A, a conductive structure 310 is formed over the insulating layer A on the top surface 118a of the pedestal 118. Conductive structure 310 includes a conductive line that is similar or identical to conductive line 120 of fig. 1G or other suitable conductive structure.

According to some embodiments, as illustrated in FIG. 4B, a mask layer 130 is formed over the pedestal 117 and pedestal 118. According to some embodiments, the mask layer 130 has an opening 132. According to some embodiments, the opening 132 is located on the top surface 118a of the pedestal 118. According to some embodiments, the mask layer 130 covers a peripheral portion 118p of the top surface 118a of the pedestal 118.

According to some embodiments, the masking layer 130 covering the pedestal 118 is thinner than the masking layer 130 covering the pedestal 117. According to some embodiments, the mask layer 130 covers the sidewalls 118b of the pedestal 118. According to some embodiments, sidewall 118b is also referred to as a boundary between regions R1 and R2.

According to some embodiments, as illustrated in fig. 4C, a conductive layer 140 is deposited over the conductive structure 310, the top surface 118a, and the mask layer 130. According to some embodiments, the conductive layer 140 covers the top surface 136 of the mask layer 130, the inner wall 132a of the opening 132, and the inner wall 134a of the recess 134.

According to some embodiments, the conductive layer 140 on the inner wall 134a is thinner than the conductive layer 140 on the inner wall 132a of the opening 132. According to some embodiments, the conductive layer 140 on the inner wall 132a is thinner than the conductive layer 140 on the conductive structure 310. According to some embodiments, the conductive layer 140 on the conductive structure 310 is thinner than the conductive layer 140 on the top surface 136 of the masking layer 130.

According to some embodiments, the deposition process of the conductive layer 140 includes a physical vapor deposition process. According to some embodiments, since the conductive layer 140 is formed on the conductive structure 310 by using a physical vapor deposition process, and the conductive layer 140 is surrounded by the mask layer 130, the conductive layer 140 on the conductive structure 310 has a curved top surface 141 a.

According to some embodiments, the mask layer 130 is deformed due to heat generated in the mask layer 130 by the physical vapor deposition process, and the top surface 136 of the mask layer 130 becomes a curved top surface. According to some embodiments, the conductive layer 140 on the curved top surface 136 also has a curved top surface 141 b.

According to some embodiments, as illustrated in fig. 4D, the inner wall 132a, the groove 134, and the conductive layer 140 on the insulating layer a are removed. According to some embodiments, the conductive layer 140 remaining on the conductive structure 310 after the removal process forms the conductive pad 142.

According to some embodiments, the conductive pad 142 has a curved top surface 142 a. In some embodiments, the width W2 of the conductive pad 142 increases toward the substrate 110. According to some embodiments, the width W2 continues to increase toward the substrate 110. According to some embodiments, the removal process comprises an etching process, such as a wet etching process.

According to some embodiments, as depicted in fig. 4E, a device 150 is provided. The device 150 includes a chip, package, active device, passive device, light emitting device, or other suitable device. According to some embodiments, the light emitting device comprises a laser diode (not shown) emitting a laser beam. According to some embodiments, the device 150 has a bottom surface 152.

According to some embodiments, as depicted in fig. 4E, a conductive pad 160 is formed on the bottom surface 152 of the device 150. According to some embodiments, the conductive pad 160 is electrically connected to the device 150. According to some embodiments, as illustrated in fig. 4E, a solder layer 170 is formed over the conductive pad 160. According to some embodiments, the conductive pad 160 is located between the device 150 and the solder layer 170.

According to some embodiments, the device 150 is bonded to the conductive pad 142 through the conductive pad 160 and the solder layer 170, as depicted in fig. 4F. According to some embodiments, the conductive pad 142 extends partially into the solder layer 170. At this step, semiconductor device 400 is formed, according to some embodiments.

Many variations and/or modifications may be made to the embodiments of the present invention. For example, the shape, profile, and/or distribution of the projections 114 of FIGS. 1A, 1A-1, and 1A-2 may be different in different embodiments. Fig. 5-14 are top views of different variations of the projection 114, according to some embodiments.

According to some embodiments, as depicted in fig. 5, the protruding portion 114 of fig. 5 is similar to the protruding portion 114 of fig. 1A-1, except that the protruding portion 114 of fig. 5 surrounds the entire conductive line 120. According to some embodiments, the protruding portion 114 includes pillar structures 114a spaced apart from each other.

According to some embodiments, as depicted in fig. 6, the projection 114 of fig. 6 is similar to the projection 114 of fig. 1A-1, except that the projection 114 of fig. 6 has an L-shape. According to some embodiments, protruding portion 114 is adjacent to sidewalls 124 and 126 of conductive line 120. According to some embodiments, the protruding portion 114 includes pillar structures 114a spaced apart from each other. According to some embodiments, the pillar structures 114a are arranged along the sidewalls 124 and 126.

According to some embodiments, as depicted in fig. 7, the ledge 114 of fig. 7 is similar to the ledge 114 of fig. 1A-1, except that the ledge 114 of fig. 7 is adjacent only to two sidewalls 124 and 128 of the conductive line 120. According to some embodiments, the protruding portion 114 includes pillar structures 114a spaced apart from each other. According to some embodiments, the pillar structures 114a are disposed along the sidewalls 124 and 128.

According to some embodiments, as depicted in fig. 8, the protruding portion 114 of fig. 8 is similar to the protruding portion 114 of fig. 1A-1, except that the protruding portion 114 of fig. 8 is adjacent only to a sidewall 124 of the conductive line 120. According to some embodiments, the protruding portion 114 includes pillar structures 114a spaced apart from each other. According to some embodiments, the pillar structures 114a are disposed along the sidewalls 124.

According to some embodiments, as depicted in fig. 9, the ledge 114 of fig. 9 is similar to the ledge 114 of fig. 1A-1, except that the ledge 114 of fig. 9 is adjacent to corners 129a, 129b, 129c, and 129d of the conductive line 120. According to some embodiments, the protruding portion 114 includes pillar structures 114a spaced apart from each other.

According to some embodiments, as depicted in fig. 10, the protruding portion 114 of fig. 10 is similar to the protruding portion 114 of fig. 1A-2, except that the protruding portion 114 of fig. 10 continuously surrounds the entire conductive line 120.

According to some embodiments, as depicted in fig. 11, the projection 114 of fig. 11 is similar to the projection 114 of fig. 1A-2, except that the projection 114 of fig. 11 has an L-shape. According to some embodiments, protruding portion 114 is adjacent to sidewalls 124 and 126 of conductive line 120.

According to some embodiments, as depicted in fig. 12, the ledge 114 of fig. 12 is similar to the ledge 114 of fig. 1A-2, except that the ledge 114 of fig. 12 is adjacent to corners 129a and 129c of the conductive line 120. According to some embodiments, the protruding portion 114 of fig. 12 surrounds the corners 129a and 129 c.

According to some embodiments, as depicted in fig. 13, the ledge 114 of fig. 13 is similar to the ledge 114 of fig. 1A-2, except that the ledge 114 of fig. 13 is adjacent only to two sidewalls 124 and 128 of the conductive line 120.

According to some embodiments, as depicted in fig. 14, the protruding portion 114 of fig. 14 is similar to the protruding portion 114 of fig. 1A-2, except that the protruding portion 114 of fig. 14 is adjacent only to a sidewall 124 of the conductive line 120.

It should be noted that elements of fig. 2-14 that are named or identified as such in fig. 1A-1G have similar or identical materials, structures (including relative dimensions, angles, shapes, thicknesses, widths, etc.), and methods of formation. Therefore, the detailed description will not be repeated here.

According to some embodiments, semiconductor devices and methods of forming the same are provided. The method (for forming a semiconductor device) uses a lift-off process to form a conductive pad surrounded by a ledge to prevent the formation of the conductive pad from being affected by the ledge.

According to some embodiments, a method of forming a semiconductor device is provided. The method includes providing a substrate. The method includes forming a mask layer over a surface of a substrate. The mask layer has an opening over a portion of the surface. The method includes depositing a conductive layer over the surface and the mask layer. The method includes removing the mask layer and the conductive layer over the mask layer. After removing the mask layer and the conductive layer over the mask layer, the remaining conductive layer forms a conductive pad. The width of the conductive pad increases toward the substrate. The method includes bonding a device to a conductive pad through a solder layer. The conductive pad is buried in the solder layer. In one embodiment, the conductive layer covers a top surface of the masking layer and an inner wall of the opening, and the method further includes removing the conductive layer on the inner wall after depositing the conductive layer on the portion of the surface and over the masking layer and before removing the masking layer and the conductive layer on the masking layer. In an embodiment, the conductive layer on the inner wall is thinner than the conductive layer on the portion of the surface, and the conductive layer on the portion of the surface is thinner than the conductive layer on the top surface of the masking layer. In one embodiment, the mask layer is made of a negative photoresist material. In one embodiment, the width of the opening increases toward the substrate. In one embodiment, the conductive pad has a curved top surface. In one embodiment, the substrate has a first protruding portion protruding from the surface, the first protruding portion is adjacent to a portion of the surface, and the mask layer covers the entire first protruding portion. In an embodiment, the first protruding portion surrounds a portion of the surface. In one embodiment, the first protruding portion includes pillar structures spaced apart from each other. In one embodiment, the device has a bottom surface and a second protruding portion protruding from the bottom surface. In one embodiment, the method further includes bonding the second protrusion to the first protrusion while bonding the device to the conductive pad.

According to some embodiments, a method of forming a semiconductor device is provided. The method includes providing a substrate having a first region and a second region. The substrate in the first region and the substrate in the second region have different thicknesses. The method includes forming a mask layer on a surface of a substrate. The mask layer extends across a boundary between the first region and the second region, and the mask layer has an opening over a surface in the first region. The method includes depositing a conductive layer on the surface above the mask layer and below the opening. The method includes removing the mask layer and the conductive layer over the mask layer, wherein after removing the mask layer and the conductive layer over the mask layer, the conductive layer remaining on the surface forms a first conductive pad. The method includes bonding a device to a first conductive pad. In one embodiment, the method further includes forming a second conductive pad on the bottom surface of the device prior to bonding the device to the first conductive pad, and forming a solder layer on the second conductive pad, the device being bonded to the first conductive pad through the second conductive pad and the solder layer, and the first conductive pad extending partially into the solder layer. In one embodiment, the first conductive pad has a curved top surface, and the solder layer covers the curved top surface. In one embodiment, the first region has a first recess on a surface thereof, the opening is located on a bottom surface of the first recess, the mask layer covers a first inner wall of the first recess, the conductive layer is located on the bottom surface and the mask layer, and the first conductive pad is formed on the bottom surface. In one embodiment, the mask layer covering the first inner wall of the first groove has a second groove that is recessed from the second inner wall of the opening of the mask layer, the conductive layer is further deposited on the third inner wall of the second groove, and the conductive layer on the third inner wall of the second groove is thinner than the conductive layer on the second inner wall of the opening. In one embodiment, a substrate has a pedestal and a pedestal on the pedestal, the pedestal being in a first region and a second region, the pedestal being in the first region, a mask layer on the pedestal and the pedestal, the mask layer covering sidewalls of the pedestal, an opening on the pedestal, a conductive layer deposited on the pedestal and the mask layer, and a conductive pad on the pedestal. In one embodiment, the mask layer on the pedestal is thinner than the mask layer on the pedestal.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a first conductive pad located over a portion of the surface. The first conductive pad has a curved top surface, and a width of the first conductive pad increases toward the substrate. The semiconductor device includes a device disposed above the first conductive pad. The semiconductor device includes a solder layer between the device and the first conductive pad. The solder layer covers the curved top surface, and the first conductive pad is buried in the solder layer. In one embodiment, the substrate has a first region and a second region, the substrate in the first region and the substrate in the second region have different thicknesses, and the conductive pad is in the first region.

The foregoing outlines features of various embodiments so that those skilled in the art may better understand the embodiments of the present disclosure in various aspects. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments of the invention as defined by the appended claims. In addition, while the present invention has been described in terms of several preferred embodiments, it is not intended to be limited to the embodiments disclosed herein, and not all advantages will be apparent to those skilled in the art from this detailed description.