阅读说明：本技术 埋入式字线结构的制作方法及其半导体存储器 (Manufacturing method of embedded word line structure and semiconductor memory thereof ) 是由 杨健 于 2020-05-12 设计创作，主要内容包括：本公开关于一种埋入式字线结构的制作方法及相关设备,属于半导体技术领域。该方法包括：提供半导体衬底；向所述半导体衬底中注入目标离子,以在所述半导体衬底中形成注入区域；对包括所述注入区域的所述半导体衬底退火,以将所述注入区域转换成绝缘区域；在所述绝缘区域内形成字线沟槽；填充字线金属于所述字线沟槽中,以形成埋入式字线结构。通过本公开实施例提供的方案,能够避免对半导体衬底的损伤,且可以简化埋入式字线结构的制造工艺。(The disclosure relates to a manufacturing method of an embedded word line structure and related equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate; implanting target ions into the semiconductor substrate to form an implanted region in the semiconductor substrate; annealing the semiconductor substrate including the implanted region to convert the implanted region into an insulating region; forming a word line trench in the insulating region; and filling the word line metal into the word line groove to form a buried word line structure. By the scheme provided by the embodiment of the disclosure, damage to the semiconductor substrate can be avoided, and the manufacturing process of the embedded word line structure can be simplified.)

1. A method for fabricating a buried word line structure, comprising:

providing a semiconductor substrate;

implanting target ions into the semiconductor substrate to form an implanted region in the semiconductor substrate;

annealing the semiconductor substrate including the implanted region to convert the implanted region into an insulating region;

forming a word line trench in the insulating region;

and filling the word line metal into the word line groove to form a buried word line structure.

2. The method of fabricating a buried word line structure of claim 1, wherein prior to implanting target ions into the semiconductor substrate, the method further comprises:

forming a first mask layer on the upper surface of the semiconductor substrate, wherein the first mask layer comprises a first opening for partially exposing the upper surface of the semiconductor substrate.

3. The method of claim 2, wherein before forming the word line trench in the insulating region, the method further comprises:

and forming a second mask layer on the upper surface of the semiconductor substrate, wherein the second mask layer comprises a second opening used for partially exposing the upper surface of the insulation region, and the second opening is smaller than the first opening.

4. The method of claim 1, further comprising, prior to filling the word line trench with word line metal:

and additionally depositing a gate dielectric layer at the bottom and the side wall of the word line groove.

5. The method of claim 1, wherein the target ions comprise oxygen-containing ions.

6. The method as claimed in claim 1, wherein the concentration of the implanted target ions is 1E 16-5E 16cm^-2In the meantime.

7. The method of claim 1, wherein the target ions are implanted with an energy of 50 to 1000 KeV.

8. The method as claimed in claim 1, wherein the target ions are implanted to a depth of 30nm to 300 nm.

9. The method as claimed in claim 1, wherein the annealing temperature is 850-1300 ℃ and the annealing time is 5-60 seconds.

10. A semiconductor memory device comprising a buried word line structure fabricated by the method of any one of claims 1 to 9.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing an embedded word line structure and a semiconductor memory using the same.

Background

DRAM (Dynamic Random Access Memory) is a common system Memory, wherein each Memory cell (cell) includes a transistor and a corresponding capacitor, and the number of charges stored in the capacitor is used to represent 0 and 1, so that the capacitor needs to be refreshed periodically to avoid data errors caused by insufficient charges.

In order to increase the integration of the DRAM to accelerate the operation speed of each memory cell and to cope with the strong demand of the DRAM from the markets of a PC (Personal Computer), a smart phone, a tablet, and the like, the DRAM with an embedded word line (buried word line) has been developed in recent years to meet the demand.

In the DRAM having the buried word line structure, the buried word line structure is formed in a semiconductor substrate and intersects an active region in the semiconductor substrate, so that a portion of the word line may serve as a gate of a transistor of a memory cell, and source and drain regions of the transistor are formed in the substrate at both sides of the gate.

However, in the related art, the buried word line in the DRAM is grooved by dry etching, and by using this method, a silicon surface of a semiconductor substrate is greatly damaged, thereby causing leakage current in the DRAM.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to overcome the above-mentioned deficiencies in the prior art, and provides a method for fabricating an embedded word line structure and a semiconductor memory thereof, which can avoid damage to a semiconductor substrate and simplify a process for fabricating the embedded word line structure.

According to an aspect of the present disclosure, a method for fabricating a buried word line structure is provided, the method comprising: providing a semiconductor substrate; implanting target ions into the semiconductor substrate to form an implanted region in the semiconductor substrate; annealing the semiconductor substrate including the implanted region to convert the implanted region into an insulating region; forming a word line trench in the insulating region; and filling the word line metal into the word line groove to form a buried word line structure.

In some exemplary embodiments of the present disclosure, before implanting target ions into the semiconductor substrate, the method further comprises: forming a first mask layer on the upper surface of the semiconductor substrate, wherein the first mask layer comprises a first opening for partially exposing the upper surface of the semiconductor substrate.

In some exemplary embodiments of the present disclosure, before forming the word line trench within the insulating region, the method further comprises: and forming a second mask layer on the upper surface of the semiconductor substrate, wherein the second mask layer comprises a second opening used for partially exposing the upper surface of the insulation region, and the second opening is smaller than the first opening.

In some exemplary embodiments of the present disclosure, before filling the word line metal in the word line trench, the method further comprises: and additionally depositing a gate dielectric layer at the bottom and the side wall of the word line groove.

In some exemplary embodiments of the present disclosure, the target ion includes an oxygen-containing ion.

In some exemplary embodiments of the present disclosure, the concentration of the target ions implanted is 1E16 to 5E16cm^-2In the meantime.

In some exemplary embodiments of the present disclosure, the target ions are implanted using an energy of 50 to 1000 KeV.

In some exemplary embodiments of the present disclosure, the target ion is implanted to a depth of 30nm to 300 nm.

In some exemplary embodiments of the present disclosure, the annealing temperature is between 850 and 1300 degrees celsius and the annealing time is between 5 and 60 seconds.

According to an aspect of the present disclosure, there is provided a semiconductor memory including: the embedded word line structure manufactured by the method of any of the above embodiments.

In the method for manufacturing the embedded word line structure and the semiconductor memory thereof according to some embodiments of the present disclosure, on one hand, in the process of manufacturing the embedded word line structure, the word line trench is formed by using an ion implantation method, that is, target ions are implanted into the semiconductor substrate, an implantation region is formed in the semiconductor substrate, the semiconductor substrate including the implantation region is annealed, the implantation region is converted into an insulation region, and then the word line trench is formed in the insulation region, so that damage to the semiconductor substrate can be avoided; on the other hand, word line metal can be directly filled in the word line groove, a gate dielectric layer can not be formed any more, and the manufacturing process of the embedded word line structure is simplified. Meanwhile, when the embedded word line structure is applied to manufacturing a semiconductor memory, the generation of leakage current in the semiconductor memory can be avoided, so that the performance of the semiconductor memory can be improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

FIGS. 1-3 are schematic diagrams illustrating a method for fabricating a buried word line structure according to the related art;

fig. 4 schematically illustrates a flow chart of a method of fabricating a buried word line structure according to an embodiment of the present disclosure;

fig. 5-12 schematically illustrate a method of fabricating a buried word line structure according to an embodiment of the present disclosure;

fig. 13-16 schematically illustrate a method of fabricating a buried word line structure according to an embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the disclosure.

The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second" are used merely as labels, and are not limiting on the number of their objects.

The advantages and features of the present disclosure will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure. It should be understood that in the following description, references to "on" and "under" layers may be made based on the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "at … …" can also include "at … …" and other orientational relationships. When a layer, region, pattern, or structure is "on" a substrate, layer, region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. Similarly, when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present.

Fig. 1-3 are schematic diagrams illustrating a method for fabricating a buried word line structure in the related art.

A buried word line in a DRAM is a kind of gate (gate) which is buried deeply. In the related art, as shown in fig. 1, a mask layer 102 is first formed on an upper surface of a semiconductor substrate 101, and then a trench is opened in the semiconductor substrate 101 by dry etching to form a word line trench 103. As shown in fig. 2, the mask layer 102 is then removed, and an oxide layer 104 is grown on the sidewalls and bottom walls of the word line trench 103. As shown in fig. 3, a wordline metal 106 is then filled into the wordline trench 103 to act as the gate of the transistor in the DRAM.

However, in the related art, when the trench is opened in the semiconductor substrate by dry etching in fig. 1, a large loss occurs on the silicon surface of the semiconductor substrate, which results in generation of a leakage current.

The embodiments of the present disclosure provide a method for solving the technical problems in the related art. Fig. 4 schematically illustrates a flow chart of a method of fabricating a buried word line structure according to an embodiment of the present disclosure.

As shown in fig. 4, the method provided by the embodiment of the present disclosure may include the following steps.

In step S410, a semiconductor substrate is provided.

For example, as shown in fig. 5, a semiconductor substrate 1 is provided.

In the embodiment of the present disclosure, the semiconductor substrate may be any one of semiconductor substrate materials including, but not limited to, Silicon (Si), germanium (Ge), Silicon germanium (SiGe), Silicon carbide (SiC), SiCGe, Silicon-On-Insulator (SOI), and the like. In the following embodiments, the semiconductor substrate is exemplified by a Si-containing material.

In step S420, target ions are implanted into the semiconductor substrate to form an implanted region in the semiconductor substrate.

In an exemplary embodiment, before implanting target ions into the semiconductor substrate, the method may further include: forming a first mask layer on the upper surface of the semiconductor substrate, wherein the first mask layer comprises a first opening for partially exposing the upper surface of the semiconductor substrate.

In the embodiment of the disclosure, a layer of photoresist may be spin-coated on the upper surface of the semiconductor substrate, and then an exposure and development process is performed with the aid of a mask plate to open the photoresist on the semiconductor substrate corresponding to the implantation region, thereby forming a first mask layer having a first opening. The material of the first mask layer may be, for example, silicon nitride, but is not limited thereto, and the material of the first mask layer may also be any one or a combination of two or more of oxide USG (undoped-silicate glass), BPSG (boro-phosphate glass), BSG (boro-silicate glass), PSG (phospho-silicate glass), TEOS (tetraethyl orthosilicate), and the like.

Specifically, the first mask layer may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), high-density Plasma CVD (HDPCVD), Metal-organic CVD (MOCVD), Plasma-Enhanced CVD (PECVD), or other suitable Deposition processes. The second mask layer, the gate dielectric layer and other film layers described below may also be fabricated by using similar deposition methods, and thus the deposition methods of the film layers will not be described in the following description of the fabrication method of the embedded word line structure.

For example, as shown in fig. 6, a first mask layer 2 is formed on the upper surface of the semiconductor substrate 1, and the first mask layer 2 may include a first opening 3, through which the upper surface of the semiconductor substrate 1 may be partially exposed for forming the implantation region later.

The size and the position of the first opening 3 are related to the specific requirements of the embedded word line structure to be currently fabricated, which is not limited in the present disclosure. It is assumed that the size of the first opening 3 is L1, a specific value of L1 may be set according to a specific requirement of the currently fabricated embedded word line structure, and optionally, a value of L1 may be 20nm to 80nm, which is not limited in this disclosure.

For example, as shown in fig. 7, target ions 4 are implanted into the semiconductor substrate 1, thereby forming an implantation region 5 in the semiconductor substrate 1 at a portion corresponding to the first opening 3. The implantation region herein refers to a region into which target ions are implanted.

In the embodiment of the present disclosure, when the target ions 4 are implanted, a continuous or pulsed ion implantation process may be adopted, which is not limited by the present disclosure.

In an exemplary embodiment, the target ions may include oxygen-containing ions.

In an exemplary embodiment, the concentration of the target ions implanted may be 1E16 to 5E16cm^-2In the meantime.

In an exemplary embodiment, the target ions may be implanted using an energy of 50 to 1000 KeV.

In an exemplary embodiment, the implantation depth H of the target ions may be 30nm to 300 nm. Optionally, the implantation depth of the target ions may be 60nm, 100nm, 160nm, 200nm, 260 nm. However, the present disclosure is not limited thereto, and the implantation depth of the target ions may be changed by adjusting parameters such as the type, concentration, and energy of the implanted target ions according to actual needs.

In step S430, the semiconductor substrate including the implantation region is annealed to convert the implantation region into an insulation region.

In an exemplary embodiment, the annealing temperature may be between 850 and 1300 degrees celsius and the annealing time may be between 5 and 60 seconds. However, the present disclosure is not limited thereto, and the annealing parameters may be adjusted according to a specific application scenario.

In the embodiment of the present disclosure, as shown in fig. 8, the first mask layer 2 on the upper surface of the semiconductor substrate 1 may be removed before annealing. Thereafter, the semiconductor substrate 1 is subjected to a high temperature anneal, so that the implanted regions 5 in fig. 7 are transformed into the insulating regions 6 in fig. 8.

In step S440, a word line trench is formed within the insulating region.

In an exemplary embodiment, before forming the word line trench in the insulating region, the method may further include: forming a second mask layer (for example, the second mask layer 71 in fig. 9 or the second mask layer 72 in fig. 13) on the upper surface of the semiconductor substrate, where the second mask layer includes a second opening (for example, the second opening 81 in fig. 9 or the second opening 82 in fig. 13) for partially exposing the upper surface of the insulating region, and it is assumed that the size of the second opening 81 is L2, 82, and the size of the second opening is L3, and the second opening is smaller than the first opening (L2 in fig. 9 is smaller than L1, or L3 in fig. 13 is smaller than L1), and a specific value of L2 may be set according to a specific requirement of the embedded word line structure to be currently manufactured, and optionally, a value of L2 or L3 may be 10nm to 70nm, which the disclosure does not limit this.

The method of etching and forming the word line trench may employ a wet etching process and/or a dry etching process. For the wet etching process, the adopted etching solution can be an acidic etching solution or an alkaline etching solution. The word line trench may also be formed by a multiple etching process. It is understood that whether a dry etching process or a wet etching process is used, it should have etching parameters that can be adjusted, such as the etching liquid (or etching gas) used, the etching temperature, the etching liquid (or etching gas) concentration, the etching pressure, the power supply, the etching liquid (or etching gas) flow rate, and other suitable parameters, so as to obtain the size and shape of the word line trench described in the embodiments of the present disclosure.

In the embodiment of the present disclosure, the second mask layer having the second opening pattern may be used as a mask to be etched downward, and the etching method may be, for example, plasma dry etching to etch the semiconductor substrate, so as to form the word line trench in the semiconductor substrate.

In step S450, a word line metal is filled in the word line trench to form a buried word line structure.

In the embodiments of the present disclosure, the material of the word line metal may be selected from one or more of metals (e.g., tungsten, tantalum, titanium, molybdenum, aluminum, hafnium, ruthenium), metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), metal nitrides (e.g., titanium nitride, tantalum nitride), conductive polysilicon, and the like.

In the embodiment of the present disclosure, a word line trench is formed in a semiconductor substrate, a word line is formed in the word line trench, the word line extends along a surface parallel to the semiconductor substrate, and when used as a semiconductor memory, the semiconductor substrate may further have an active region (not shown) therein and an isolation structure for defining an extent of the active region.

In the embodiment of the disclosure, the size and shape of the formed insulating region and the word line trench can be controlled by adjusting the process parameters in the manufacturing process, so that the formed insulating region can be used as an oxide layer and a gate dielectric layer on the side wall and the bottom wall of the word line metal filled in the word line trench.

The above steps S440 and S450 are illustrated below by fig. 9-12 and 13-16, respectively.

In the method for manufacturing the embedded word line structure provided by the embodiment of the disclosure, on one hand, in the process of manufacturing the embedded word line structure, the word line trench is formed by adopting an ion implantation method, that is, target ions are implanted into a semiconductor substrate such as silicon, the target ions may include high-concentration oxygen ions, an implantation region is formed in the semiconductor substrate, then the semiconductor substrate including the implantation region is subjected to high-temperature annealing, the target ions in the implantation region are activated to convert the implantation region into an insulation region, and then the word line trench is formed in the insulation region, so that the damage to the semiconductor substrate can be avoided; on the other hand, word line metal can be directly filled in the word line groove, namely the insulating area is used as an oxide layer, the oxide layer required by the buried word line can be formed in a non-hole opening mode, a gate dielectric layer can not be formed, and the manufacturing process of the embedded word line structure is simplified. Meanwhile, when the embedded word line structure is applied to manufacturing a semiconductor memory, the generation of leakage current in the semiconductor memory can be avoided, so that the performance of the semiconductor memory can be improved.

Fig. 5-12 schematically illustrate a method of fabricating a buried word line structure according to an embodiment of the present disclosure.

The description of fig. 5-8 may refer to the embodiments described above. As shown in fig. 9, a second mask layer 71 is formed on the upper surface of the semiconductor substrate 1, the second mask layer 71 has a second opening 81, the size of the second opening 81 is assumed to be L2, and L2 is smaller than the size L1 of the first opening 3 in the above-described embodiment, so that the upper surface of the insulating region 6 is partially exposed through the second opening 81.

As shown in fig. 10, a portion of the insulating region 6 corresponding to the second opening 81 is etched, and a word line trench 91 is formed in the insulating region 6, wherein the height of the word line trench 91 is smaller than the height H of the insulating region 6, so that the semiconductor substrate 1 can be prevented from being damaged, and the generation of leakage current can be prevented. In fig. 10, the remaining portion after etching the insulating region 6 may be used as the gate oxide layer 61 of the embedded word line structure, where the thickness of the gate oxide layer 61 may be 3-8nm, and may be adjusted according to actual needs, which is not limited by the present disclosure, as long as the thickness of the insulating region 6 left after etching can meet the requirement of the gate oxide layer of the embedded word line structure.

As shown in fig. 11, the second mask layer 71 may be removed.

As shown in fig. 12, a word line metal 111 may be filled into the word line trench for forming a buried word line structure.

In an embodiment of the present disclosure, the word line trench has a bottom wall and a sidewall connected to each other.

Alternatively, a metal barrier layer 101 may be formed on the sidewall and the bottom wall of the word line trench before filling the word line metal 111 in the word line trench, and the metal barrier layer 101 may be made of, for example, titanium nitride or conductive polysilicon.

Compared with the related technology, on one hand, the silicon surface of the semiconductor substrate cannot be lost, so that leakage current cannot be generated, and the reliability of the semiconductor memory is improved; on the other hand, the manufacturing process of a layer of gate dielectric layer is omitted, namely the manufacturing process of the embedded word line structure is simplified, and the cost is reduced.

Fig. 13-16 schematically illustrate a method of fabricating a buried word line structure according to an embodiment of the present disclosure.

Other fabrication steps in embodiments of the present disclosure may be described with reference to fig. 5-8 above. As shown in fig. 13, a second mask layer 72 is formed on the upper surface of the semiconductor substrate 1, the second mask layer 72 having a second opening 82, the size of the second opening 82 is assumed to be L3, and L3 is smaller than the size L1 of the first opening 3 in the above-described embodiment, so that the upper surface of the insulating region 6 is partially exposed through the second opening 82.

For fabricating the embedded word line structure of the same specification, the size L3 of the second opening 82 in the embodiment of fig. 13 is larger than the size L2 of the second opening 81 in the embodiment of fig. 9, i.e., the embodiment of fig. 13 can expose more upper surfaces of the insulating regions 6 than the embodiment of fig. 9.

As shown in fig. 14, a portion of the insulating region 6 corresponding to the second opening 82 is etched, and a word line trench 92 is formed in the insulating region 6, wherein the height of the word line trench 92 is smaller than the height H of the insulating region 6, so that the semiconductor substrate 1 can be prevented from being damaged, and the generation of leakage current can be prevented. In fig. 14, the remaining portion after etching the insulating region 6 may serve as a gate oxide layer 62 of the buried word line structure, where the thickness of the gate oxide layer 62 may be smaller than the thickness of the gate oxide layer 61 in the embodiment of fig. 10.

Correspondingly, since L3 is greater than L2, the width of the word line trench 92 formed in the embodiment of fig. 14 is greater than the width of the word line trench 91 in the embodiment of fig. 10.

As shown in fig. 15, the second mask layer 72 may be removed, and a gate dielectric layer 12 may be additionally deposited on the sidewalls and bottom wall of the word line trench 92, wherein the gate dielectric layer 12 covers the surface of the gate oxide layer 62. The gate dielectric layer 12 can repair the gate oxide layer 62, so that the surface of the gate oxide layer 62 is smoother and does not damage the semiconductor substrate 1. The material of the gate dielectric layer 12 may be, for example, silicon oxide, but the disclosure is not limited thereto.

As shown in fig. 16, a word line metal 112 may be filled into the word line trench 92 for forming a buried word line structure.

Optionally, a metal barrier layer 102 may be formed on the gate dielectric layer 12 before filling the word line metal 112.

In the embodiment of the disclosure, the word line groove which is columnar and has a radian on the bottom wall can be formed, so that the word line metal filled in the word line groove automatically forms the word line which is columnar and has a radian on the bottom wall, and the consistency of the shapes of the word line and the word line is ensured.

In the embodiment of the disclosure, laser annealing can be adopted, so that rapid annealing can be realized, and the implantation region implanted by target ions keeps a columnar shape, and the bottom wall of the implantation region has a certain radian, thereby finally forming a word line structure consistent with the shape of the gate.

According to the manufacturing method of the embedded word line structure provided by the embodiment of the disclosure, the insulating region in the embedded word line structure is formed by adopting an ion implantation method, and the insulating region is directly used as the gate dielectric layer of the embedded word line structure.

Further, the embodiment of the present disclosure also provides a semiconductor memory, which may include the embedded word line structure manufactured by the method of any of the above embodiments.

In the embodiment of the present disclosure, the semiconductor Memory may be any semiconductor Memory, for example, a Dynamic Random Access Memory (DRAM), but the present disclosure is not limited thereto, and the semiconductor Memory may be any Memory.

The semiconductor memory provided by the embodiment of the disclosure includes the embedded word line structure, and thus has the same or similar advantages as the embedded word line structure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.