阅读说明：本技术 半导体器件的制备方法及半导体器件 (Preparation method of semiconductor device and semiconductor device ) 是由 叶长福 蔡亚萤 吕佐文 陈旋旋 上官明沁 于 2021-08-17 设计创作，主要内容包括：本申请提供一种半导体器件的制备方法及半导体器件,该制备方法包括将所述反应腔室加热至第二预设温度,在所述硅晶种层上方形成第一磷掺杂硅层；将所述反应腔室加热至第三预设温度,在所述第一磷掺杂硅层上方形成第二磷掺杂硅层；其中,所述第二磷掺杂硅层的磷掺杂量不同于所述第一磷掺杂硅层的磷掺杂量,所述硅晶种层、所述第一磷掺杂硅层和所述第二磷掺杂硅层的总厚度大于或等于所述接触孔的深度。位线插塞的半导体层的应力变化和尺寸收缩得到控制,半导体层的平坦度大大提升,这样形成的空洞尺寸较小,且沿靠近基板的方向移动,即使在半导体层平坦化减薄之后,空洞也不会对上面的膜层产生影响。(The application provides a preparation method of a semiconductor device and the semiconductor device, the preparation method comprises the steps of heating a reaction chamber to a second preset temperature, and forming a first phosphorus doped silicon layer above a silicon seed layer; heating the reaction chamber to a third preset temperature, and forming a second phosphorus-doped silicon layer above the first phosphorus-doped silicon layer; the phosphorus doping amount of the second phosphorus-doped silicon layer is different from that of the first phosphorus-doped silicon layer, and the total thickness of the silicon seed layer, the first phosphorus-doped silicon layer and the second phosphorus-doped silicon layer is larger than or equal to the depth of the contact hole. The stress change and the size shrinkage of the semiconductor layer of the bit line plug are controlled, the flatness of the semiconductor layer is greatly improved, the size of the formed cavity is small, the cavity moves along the direction close to the substrate, and even after the semiconductor layer is flattened and thinned, the cavity cannot influence the film layer on the cavity.)

1. A method of manufacturing a semiconductor device, comprising:

step S110: providing a semiconductor substrate, and forming a contact hole extending into the substrate on the upper surface of the substrate;

step S120: placing the substrate in a reaction chamber, and heating the reaction chamber to a first preset temperature to form a silicon seed layer covering the inner wall of the contact hole and the upper surface of the substrate;

step S130: heating the reaction chamber to a second preset temperature to form a first phosphorus-doped silicon layer covering the surface, far away from the substrate, of the silicon seed layer;

step S140: heating the reaction chamber to a third preset temperature to form a second phosphorus-doped silicon layer covering the surface, far away from the silicon seed layer, of the first phosphorus-doped silicon layer; the phosphorus doping amount of the second phosphorus-doped silicon layer is different from that of the first phosphorus-doped silicon layer, and the total thickness of the silicon seed layer, the first phosphorus-doped silicon layer and the second phosphorus-doped silicon layer is larger than or equal to the depth of the contact hole.

2. The method of claim 1, wherein the second phosphorus doped silicon layer has a phosphorus doping level that is less than a phosphorus doping level of the first phosphorus doped silicon layer.

3. The method of claim 1, wherein the first phosphorus doped silicon layer has a thickness less than a thickness of the second phosphorus doped silicon layer.

4. The method of claim 1, wherein step S130 comprises the steps of:

step S132: heating the reaction chamber to a second preset temperature, introducing a first reaction gas into the reaction chamber until the pressure in the reaction chamber is a first preset pressure, and keeping the pressure in the reaction chamber for a first preset time period to form a first phosphorus-doped silicon layer covering the surface, far away from the substrate, of the silicon seed layer;

step S134: introducing a second reaction gas into the reaction chamber until the pressure in the reaction chamber is a second preset pressure, and keeping the second preset pressure for a second preset time to thicken the first phosphorus-doped silicon layer; wherein the second preset pressure is different from the first preset pressure.

5. The method of claim 4, wherein the second predetermined pressure is greater than the first predetermined pressure.

6. The method of claim 5, wherein the second predetermined duration is greater than the first predetermined duration.

7. The method of claim 4, wherein the first reactive gas and the second reactive gas each comprise silane and phosphane.

8. The method of claim 4, wherein the pressure in the reaction chamber in step S140 is less than an average of the first predetermined pressure and the second predetermined pressure.

9. The method of claim 4, wherein step S130 further comprises the steps of:

step S136: repeating the steps S132 to S134 for at least 5 times until the thickness of the first phosphorus doped silicon layer covering the surface of the silicon seed layer away from the substrate reaches a preset thickness.

10. The method according to claim 1, wherein the first preset temperature is lower than the second preset temperature, and the second preset temperature is lower than the third preset temperature.

11. The method of claim 1, further comprising:

step S150: and heating the reaction chamber to a fourth preset temperature to form an undoped silicon contact layer covering the surface of the second phosphorus-doped silicon layer far away from the first phosphorus-doped silicon layer.

12. The method of claim 11, wherein after step S150, the method further comprises:

step S160: performing planarization treatment on the lamination of the silicon seed layer, the first phosphorus-doped silicon layer, the second phosphorus-doped silicon layer and the silicon contact layer;

step S170: forming a bit line stack over the stack of the silicon seed layer, the first phosphorus doped silicon layer, the second phosphorus doped silicon layer, and the silicon contact layer after planarization;

step S180: patterning the flattened silicon seed layer, the first phosphorus-doped silicon layer, the second phosphorus-doped silicon layer and the laminated silicon contact layer and the bit line laminated layer to respectively obtain a bit line contact plug and a bit line structure; wherein the bit line structure is electrically connected with the substrate through the bit line contact plug.

13. The method of claim 12, wherein the bitline stack comprises a barrier layer and a metal layer stacked in sequence over the silicon contact layer.

14. The method of claim 1, wherein before the step of forming the contact hole extending into the substrate on the upper surface of the substrate in step S110, the method further comprises:

forming a plurality of active patterns arranged at intervals along a first direction in the upper surface of the substrate; wherein each active pattern is isolated by an isolation pattern;

forming a plurality of trench gate structures arranged at intervals along a second direction in the upper surface of the substrate; wherein each of the trench gate structures intersects at least one of the active patterns.

15. A semiconductor device, comprising:

a semiconductor substrate;

a contact hole disposed in the surface of the substrate and extending into the substrate;

a silicon seed layer covering at least a part of an inner wall of the contact hole and a part of an upper surface of the substrate;

the first phosphorus-doped silicon layer covers the surface, far away from the substrate, of the silicon seed layer;

a second phosphorus doped silicon layer covering the surface of the first phosphorus doped silicon layer far away from the silicon seed layer;

wherein the second phosphorus doped silicon layer has a phosphorus doping amount different from the phosphorus doping amount of the first phosphorus doped silicon layer; the total thickness of the silicon seed layer, the first phosphorus-doped silicon layer and the second phosphorus-doped silicon layer is greater than or equal to the depth of the contact hole; at least one void is formed at the interface of the first phosphorus doped silicon layer and the second phosphorus doped silicon layer at the position of the contact hole.

16. The semiconductor device of claim 15, wherein the second phosphorus doped silicon layer has a phosphorus doping amount that is less than a phosphorus doping amount of the first phosphorus doped silicon layer.

17. The semiconductor device of claim 15, wherein a bottom of the void extends into the first phosphorus doped silicon layer;

the top of the void extends into the second phosphorus doped silicon layer.

18. The semiconductor device of claim 15, wherein a surface of the first phosphorus doped silicon layer proximate to the silicon seed layer is in contact with a surface of the silicon seed layer distal to the substrate;

the surface of the second phosphorus-doped silicon layer close to the first phosphorus-doped silicon layer is in contact with the surface of the first phosphorus-doped silicon layer far away from the silicon seed layer.

19. The semiconductor device of claim 18, wherein the first phosphorus doped silicon layer is concave at the contact hole location.

20. The semiconductor device of claim 15, wherein the first phosphorus doped silicon layer is isolated from the upper surface of the substrate by the silicon seed layer.

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a preparation method of a semiconductor device and the semiconductor device.

Background

With the trend of miniaturization of various electronic products, the design of Dynamic Random Access Memory (DRAM) must meet the requirements of high integration and high density. For the dram with the recessed gate structure, it has gradually replaced the dram with only the planar gate structure because it can obtain a longer carrier channel length in the same semiconductor substrate.

Generally, a DRAM having a recessed gate structure is formed by a large number of memory cells (memory cells 11) grouped together to form an array region for storing data, and each memory cell may be composed of a transistor device connected in series with a charge storage device to receive voltage signals from a Word Line (WL) and a Bit Line (BL). As shown in fig. 1 and 2, the conventional DRAM semiconductor device includes a substrate 101, an active pattern 1011, an isolation pattern 102, a trench gate structure 103 (including a gate insulating layer 1031, a gate electrode 1032, and a second interlayer insulating layer 1033), a first interlayer insulating layer 104, a contact hole 105, a bit line plug (including a seed layer 1061 and a semiconductor layer 1062), and a bit line structure (including a barrier layer 1071 and a metal layer 1072). The bit line structure is electrically connected with the gate structure and the active pattern on the substrate through the bit line plug, the bit line plug is disposed in the contact hole on the substrate surface, the semiconductor layer in the bit line plug is prepared by a one-step method, due to the limitation of the deposition process, a large hollow 1063 is formed on the semiconductor layer 1062, after the semiconductor layer 1062 is planarized, the hollow 1063 may even be located on the surface of the semiconductor layer 1062, which causes the change of the surface energy, as shown in fig. 3 and 4, after the barrier layer 1071 and the metal layer 1072 are deposited, the metal ions in the metal layer 1072 may penetrate through the barrier layer 1071 into the hollow 1063, the diffusion of the metal ions may cause the collapse of the metal ions, which may affect the surface topography of the formed bit line structure BL during the patterning process of the barrier layer 1071 and the metal layer 1072, and ultimately affect the electrical performance of the device.

Disclosure of Invention

In view of the above problems, the present application provides a method for manufacturing a semiconductor device and a semiconductor device, which solve the technical problems in the prior art that the size of a cavity formed in a bit line plug is large, and the position of the cavity is closer to a bit line structure, thereby affecting the surface morphology of the bit line structure.

In a first aspect, the present application provides a method for manufacturing a semiconductor device, including:

step S110: providing a semiconductor substrate, and forming a contact hole extending into the substrate on the upper surface of the substrate;

step S120: placing the substrate in a reaction chamber, and heating the reaction chamber to a first preset temperature to form a silicon seed layer covering the inner wall of the contact hole and the upper surface of the substrate;

step S130: heating the reaction chamber to a second preset temperature to form a first phosphorus-doped silicon layer covering the surface, far away from the substrate, of the silicon seed layer;

step S140: heating the reaction chamber to a third preset temperature to form a second phosphorus-doped silicon layer covering the surface, far away from the silicon seed layer, of the first phosphorus-doped silicon layer; the phosphorus doping amount of the second phosphorus-doped silicon layer is different from that of the first phosphorus-doped silicon layer, and the total thickness of the silicon seed layer, the first phosphorus-doped silicon layer and the second phosphorus-doped silicon layer is larger than or equal to the depth of the contact hole.

According to an embodiment of the application, optionally, in the above method for manufacturing a semiconductor device, the phosphorus doping amount of the second phosphorus doped silicon layer is less than the phosphorus doping amount of the first phosphorus doped silicon layer.

According to an embodiment of the application, optionally, in the above method for manufacturing a semiconductor device, a thickness of the first phosphorus doped silicon layer is smaller than a thickness of the second phosphorus doped silicon layer.

According to an embodiment of the present application, optionally, in the method for manufacturing a semiconductor device, step S130 includes the following steps:

step S132: heating the reaction chamber to a second preset temperature, introducing a first reaction gas into the reaction chamber until the pressure in the reaction chamber is a first preset pressure, and keeping the pressure in the reaction chamber for a first preset time period to form a first phosphorus-doped silicon layer covering the surface, far away from the substrate, of the silicon seed layer;

step S134: introducing a second reaction gas into the reaction chamber until the pressure in the reaction chamber is a second preset pressure, and keeping the second preset pressure for a second preset time to thicken the first phosphorus-doped silicon layer; wherein the second preset pressure is different from the first preset pressure.

According to an embodiment of the application, optionally, in the manufacturing method of the semiconductor device, the second preset pressure is greater than the first preset pressure.

According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, the second preset duration is longer than the first preset duration.

According to an embodiment of the application, optionally, in the above method for manufacturing a semiconductor device, the first reaction gas and the second reaction gas each include silane and phosphane.

According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, in step S140, the pressure in the reaction chamber is smaller than an average value of the first preset pressure and the second preset pressure.

According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, the step S130 further includes the following steps:

step S136: repeating the steps S132 to S134 for at least 5 times until the thickness of the first phosphorus doped silicon layer covering the surface of the silicon seed layer away from the substrate reaches a preset thickness.

According to an embodiment of the application, optionally, in the above method for manufacturing a semiconductor device, the first preset temperature is lower than the second preset temperature, and the second preset temperature is lower than the third preset temperature.

According to an embodiment of the present application, optionally, in the method for manufacturing a semiconductor device, the method further includes:

step S150: and heating the reaction chamber to a fourth preset temperature to form an undoped silicon contact layer covering the surface of the second phosphorus-doped silicon layer far away from the first phosphorus-doped silicon layer.

According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, after step S150, the method further includes:

step S160: performing planarization treatment on the lamination of the silicon seed layer, the first phosphorus-doped silicon layer, the second phosphorus-doped silicon layer and the silicon contact layer;

step S170: forming a bit line stack over the stack of the silicon seed layer, the first phosphorus doped silicon layer, the second phosphorus doped silicon layer, and the silicon contact layer after planarization;

step S180: patterning the flattened silicon seed layer, the first phosphorus-doped silicon layer, the second phosphorus-doped silicon layer and the laminated silicon contact layer and the bit line laminated layer to respectively obtain a bit line contact plug and a bit line structure; wherein the bit line structure is electrically connected with the substrate through the bit line contact plug.

According to an embodiment of the application, optionally, in the above method for manufacturing a semiconductor device, the bit line stack includes a barrier layer and a metal layer sequentially stacked above the silicon contact layer.

According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, before the step of forming the contact hole extending into the substrate on the upper surface of the substrate in step S110, the method further includes:

forming a plurality of active patterns arranged at intervals along a first direction in the upper surface of the substrate; wherein each active pattern is isolated by an isolation pattern;

forming a plurality of trench gate structures arranged at intervals along a second direction in the upper surface of the substrate; wherein each of the trench gate structures intersects at least one of the active patterns.

In a second aspect, the present application provides a semiconductor device comprising:

a semiconductor substrate;

a contact hole disposed in the surface of the substrate and extending into the substrate;

a silicon seed layer covering at least a part of an inner wall of the contact hole and a part of an upper surface of the substrate;

the first phosphorus-doped silicon layer covers the surface, far away from the substrate, of the silicon seed layer;

a second phosphorus doped silicon layer covering the surface of the first phosphorus doped silicon layer far away from the silicon seed layer;

wherein the second phosphorus doped silicon layer has a phosphorus doping amount different from the phosphorus doping amount of the first phosphorus doped silicon layer; the total thickness of the silicon seed layer, the first phosphorus-doped silicon layer and the second phosphorus-doped silicon layer is greater than or equal to the depth of the contact hole; at least one void is formed at the interface of the first phosphorus doped silicon layer and the second phosphorus doped silicon layer at the position of the contact hole.

According to an embodiment of the present application, optionally, in the semiconductor device, a phosphorus doping amount of the second phosphorus doped silicon layer is less than a phosphorus doping amount of the first phosphorus doped silicon layer.

According to an embodiment of the present application, optionally, in the semiconductor device, a bottom of the void extends into the first phosphorus doped silicon layer;

the top of the void extends into the second phosphorus doped silicon layer.

According to an embodiment of the present application, optionally, in the semiconductor device, a surface of the first phosphorus-doped silicon layer close to the silicon seed layer is in contact with a surface of the silicon seed layer away from the substrate;

the surface of the second phosphorus-doped silicon layer close to the first phosphorus-doped silicon layer is in contact with the surface of the first phosphorus-doped silicon layer far away from the silicon seed layer.

According to an embodiment of the application, optionally, in the semiconductor device described above, the first phosphorus doped silicon layer is concave at the contact hole location.

According to an embodiment of the present application, optionally, in the semiconductor device, the first phosphorus-doped silicon layer is separated from the upper surface of the substrate by the silicon seed layer.

Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:

the preparation method comprises the steps of placing a substrate in a reaction chamber, heating the reaction chamber to a first preset temperature, and forming a silicon seed layer covering the inner wall of a contact hole and the upper surface of the substrate; heating the reaction chamber to a second preset temperature to form a first phosphorus-doped silicon layer covering the surface, far away from the substrate, of the silicon seed layer; heating the reaction chamber to a third preset temperature to form a second phosphorus-doped silicon layer covering the surface, far away from the silicon seed layer, of the first phosphorus-doped silicon layer; the phosphorus doping amount of the second phosphorus-doped silicon layer is different from that of the first phosphorus-doped silicon layer, and the total thickness of the silicon seed layer, the first phosphorus-doped silicon layer and the second phosphorus-doped silicon layer is larger than or equal to the depth of the contact hole. The semiconductor layer of the bit line plug forms a phosphorus doped silicon layer with a certain distribution of doping amount in a layered deposition mode to fill the contact hole on the substrate, the stress change and the size shrinkage of the semiconductor layer are controlled, the flatness of the semiconductor layer is greatly improved, the size of the formed cavity is small and the cavity moves along the direction close to the substrate, and even after the semiconductor layer is flattened and thinned, the cavity cannot influence the film layer on the cavity.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:

FIG. 1 is a schematic diagram of a top view of a front side of a semiconductor device;

FIG. 2 is a schematic cross-sectional view of FIG. 1 taken along lines A-A 'and B-B', respectively;

FIG. 3 is a schematic top plan view of an intermediate structure formed at a step associated with the method of fabricating the semiconductor device shown in FIG. 1;

FIG. 4 is a schematic cross-sectional view of FIG. 3 taken along lines A-A 'and B-B', respectively;

FIG. 5 is a schematic flow chart illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the present application;

FIG. 6 is a schematic top plan view of a first intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in one exemplary embodiment of the present application;

FIG. 7 is a schematic cross-sectional view of FIG. 6 taken along lines C-C 'and D-D', respectively;

FIG. 8 is a schematic top plan view of a second intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in one exemplary embodiment of the present application;

FIG. 9 is a schematic cross-sectional view of FIG. 8 taken along lines C-C 'and D-D', respectively;

FIG. 10 is a cross-sectional structural view of a third intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in one exemplary embodiment of the present application;

FIG. 11 is a cross-sectional view of a fourth intermediate structure formed during a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;

fig. 12 is a schematic cross-sectional view of a fifth intermediate structure formed in a step associated with a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present application;

FIG. 13 is a cross-sectional structural view of a sixth intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;

FIG. 14 is a schematic illustration of a top view of a seventh intermediate structure formed during a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;

FIG. 15 is a schematic cross-sectional view of FIG. 14 taken along lines C-C 'and D-D', respectively;

FIG. 16 is a schematic diagram of a front side top view of a semiconductor device shown in an exemplary embodiment of the present application;

FIG. 17 is a schematic cross-sectional view of FIG. 16 taken along lines C-C 'and D-D', respectively;

fig. 18 is a schematic flow chart illustrating a method of fabricating a first phosphorus doped silicon layer in a semiconductor device in accordance with an exemplary embodiment of the present application;

fig. 19 is a schematic view illustrating a variation in pressure of a reaction chamber in a method for fabricating a first phosphorus doped silicon layer in a semiconductor device according to an exemplary embodiment of the present application;

in the drawings, wherein like parts are designated with like reference numerals, the drawings are not necessarily to scale;

the reference signs are:

101-a substrate; 1011-active pattern; 102-an isolation pattern; 103-a trench gate structure; 1031-gate insulating layer; 1032-a gate; 1033 — a second interlayer insulating layer; 104-a first interlayer insulating layer; 105-a contact hole; 1061-a seed layer; 1062-a semiconductor layer; 1063-void; 1071 — a barrier layer; 1072-metal layer;

201-a substrate; 2011-active pattern; 202-an isolation pattern; 203-a trench gate structure; 2031 — a gate insulating layer; 2032-grid; 2033 — a second interlayer insulating layer; 204 — a first interlayer insulating layer; 205-contact holes; 2061-silicon seed layer; 2062-a first phosphorus doped silicon layer; 2063-a cavity; 2064-a second phosphorus doped silicon layer; 2065-a silicon contact layer; 2071-a barrier layer; 2072-metal layer.

Detailed Description

The following detailed description will be provided with reference to the accompanying drawings and embodiments, so that how to apply the technical means to solve the technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and various features in the embodiments of the present application can be combined with each other without conflict, and the formed technical solutions are all within the scope of protection of the present application. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

In order to provide a thorough understanding of the present application, detailed structures and steps will be provided in the following description in order to explain the technical solutions proposed in the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

Example one

The embodiment provides a method for manufacturing a semiconductor device. Fig. 5 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 6-17 are schematic diagrams of a top view and a cross-sectional structure of a front surface and a cross-sectional structure formed in the relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Next, detailed steps of an exemplary method of a method of manufacturing a semiconductor device proposed by an embodiment of the present application are described with reference to fig. 5 and 6to 17.

As shown in fig. 5, the method for manufacturing a semiconductor device of the present embodiment includes the following steps:

step S110: a semiconductor substrate 201 is provided and a contact hole 205 is formed in the upper surface of the substrate 201 extending into the substrate.

As shown in fig. 6 and 7, before the step of forming the contact hole 205 extending into the substrate 201 on the upper surface of the substrate 201 in step S110, the method further includes:

(a) forming a plurality of active patterns 2011 arranged at intervals in a first direction in the upper surface of the substrate 201; wherein each active pattern 2011 is isolated from each other by the isolation pattern 202;

(b) forming a plurality of trench gate structures 203 arranged at intervals along a second direction in the upper surface of the substrate 201; wherein each trench gate structure 203 intersects with at least one active pattern 2011;

(c) a first interlayer insulating layer 204 is formed covering the upper surface of the substrate.

A plurality of active patterns 2011 are disposed on the substrate 201 at intervals, each of the active patterns 2011 is parallel to each other and disposed along a first direction, the active patterns 2011 are formed by forming doped regions (not shown) by ion implantation, and an upper surface of the active patterns 2011 is flush with an upper surface of the substrate 201. The active patterns 2011 in two adjacent rows are staggered, and the active patterns 2011 in two adjacent columns are staggered.

Each of the active patterns 2011 is isolated from each other by an isolation pattern 202, and the isolation pattern 202 is used to define the shape of the active pattern 2011.

A plurality of trench-gate structures 203 are spaced apart on the substrate 201, each trench-gate structure 203 is parallel to each other and arranged along a second direction (e.g., a transverse direction as shown in fig. 6), each trench-gate structure 203 intersects at least one active pattern 2011, and each trench-gate structure 203 intersects at least one active pattern 2011, for example, as shown in fig. 6. The trench gate structure 203 includes a trench, a gate insulating layer 2031 disposed on a sidewall and a bottom of the trench, and a gate electrode 2032 and a second interlayer insulating layer 2033 filled in a lower portion and an upper portion of the trench, respectively. The thickness of the gate 2032 is smaller than the depth of the trench, but the top of the gate 2032 is higher than the bottom of the doped region (not shown) in the active pattern 2011. The second interlayer insulating layer 2033 is formed of, for example, a silicon nitride layer and/or a silicon oxynitride layer.

The first interlayer insulating layer 204 is disposed over the substrate 201 and covers the active pattern 2011 and the trench gate structure 203, and a material of the first interlayer insulating layer 204 includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

The contact hole 205 penetrates the first interlayer insulating layer 204 and extends into the active pattern 2011, the isolation pattern 202, and the trench gate structure 203.

Step S120: as shown in fig. 8 and 9, the substrate 201 is placed in the reaction chamber and the reaction chamber is heated to a first predetermined temperature to form a silicon seed layer 2061 covering the inner walls of the contact holes 205 and the upper surface of the substrate 201.

The silicon seed layer 2061 has certain crystal characteristics and lattice arrangement direction, and the crystal characteristics and lattice arrangement direction of the silicon layer formed thereon can be controlled.

The silicon source reaction gas used in step S120 may be Dichlorosilane (DCS) and disilane (Si2H 6).

Specifically, Dichlorosilane (DCS) may be introduced first, after a certain period of time, the introduction of Dichlorosilane (DCS) is stopped, disilane (Si2H6) is introduced, after a certain period of time, the above process is repeated once again (a total of two cycles are performed), and the seed layer may be obtained.

The gas flow rates of Dichlorosilane (DCS) and disilane (Si2H6) are both 400sccm, and the preset pressure of the reaction chamber is 0.827 torr.

The first preset temperature may be 380 ℃.

The silicon seed layer 2061 is formed to a thickness of the order of atomic layers. The thickness of the silicon seed layer 2061 may be 0 to 5A.

Step S130: as shown in fig. 10, the reaction chamber is heated to a second predetermined temperature to form a first phosphorus doped silicon layer 2062 covering the surface of the silicon seed layer 2061 remote from the substrate 201.

The reaction gas used in step S130 may be monosilane (SiH4) and phosphane (PH 3).

The gas flow rates for monosilane (SiH4) and phosphine (PH3) can be 600sccm and 168sccm, respectively, and the average pressure of the reaction chamber is 1.127 torr.

The first preset temperature is lower than the second preset temperature.

The second preset temperature may be 470 ℃.

The first phosphorus doped silicon layer 2062 has a thickness of 180A to 260A.

Step S140: as shown in fig. 11, the reaction chamber is heated to a third predetermined temperature to form a second phosphorus doped silicon layer 2064 covering the surface of the first phosphorus doped silicon layer 2062 remote from the silicon seed layer 2061; the phosphorus doping amount of the second phosphorus-doped silicon layer 2064 is different from the phosphorus doping amount of the first phosphorus-doped silicon layer 2062, and the total thickness of the silicon seed layer 2061, the first phosphorus-doped silicon layer 2062 and the second phosphorus-doped silicon layer 2064 is greater than or equal to the depth of the contact hole 205.

The reaction gas used in step S140 may be monosilane (SiH4) and phosphane (PH 3).

The gas flow rates of monosilane (SiH4) and phosphine (PH3) may be 2000 seem and 58 seem, respectively, and a second phosphorus doped silicon layer 2064 having a smaller phosphorus doping amount than the first phosphorus doped silicon layer 2062 may be prepared.

In some cases, the second phosphorus doped silicon layer 2064 having a higher phosphorus doping than the first phosphorus doped silicon layer 2062 may also be produced by adjusting the gas flow rates of monosilane (SiH4) and phosphine (PH 3).

The average pressure of the reaction chamber in step S140 is less than the average pressure of the reaction chamber in step S130. The average pressure of the reaction chamber in step S140 may be 0.676 torr.

The second preset temperature is lower than the third preset temperature.

The third preset temperature may be 530 ℃.

The thickness of the first phosphorus doped silicon layer 2062 is less than the thickness of the second phosphorus doped silicon layer 2064.

The second phosphorus doped silicon layer 2064 has a thickness of 360A.

The total thickness of the silicon seed layer 2061, the first phosphorus-doped silicon layer 2062 and the second phosphorus-doped silicon layer 2064 is greater than or equal to the depth of the contact hole 205, the silicon seed layer 2061, the first phosphorus-doped silicon layer 2062 and the second phosphorus-doped silicon layer 2064 together form a semiconductor layer of the bit line plug, the phosphorus-doped silicon layer with a certain doping amount distribution is formed on the semiconductor layer of the bit line plug in a layered deposition mode to fill the contact hole 205 on the substrate 201, the stress change and the size shrinkage of the semiconductor layer are controlled, the flatness of the semiconductor layer is greatly improved, and the hollow 2063 formed in the way is small in size and moves in the direction close to the substrate 201, and even after subsequent flattening and thinning, the film layers above cannot be influenced.

Step S150: as shown in fig. 12, the reaction chamber is heated to a fourth predetermined temperature to form an undoped silicon contact layer 2065 covering the surface of the second phosphorus doped silicon layer 2064 remote from the first phosphorus doped silicon layer 2062.

The reaction gas used in step S150 may be monosilane (SiH 4).

An undoped silicon contact layer can be prepared with a monosilane (SiH4) gas flow rate of 2000 sccm.

The average pressure of the reaction chamber was 0.676 torr.

The fourth predetermined temperature is equal to the third predetermined temperature.

The fourth preset temperature may be 530 ℃.

The thickness of the silicon contact layer 2065 may be greater than the thickness of the first phosphorus doped silicon layer 2062 and the second phosphorus doped silicon layer 2064.

The formation of the silicon contact layer 2065 can protect the first phosphorus-doped silicon layer 2062 and the second phosphorus-doped silicon layer 2064 therebelow, and since the contact hole 205 is already filled with the silicon seed layer 2061, the first phosphorus-doped silicon layer 2062 and the second phosphorus-doped silicon layer 2064, the shrinkage of the silicon contact layer 2065 is small, and the additional hollow 2063 is not substantially formed, so that the influence on the subsequently formed bit line stack is not caused.

Step S160: as shown in fig. 13, the stacked layer of the silicon seed layer 2061, the first phosphorus-doped silicon layer 2062, the second phosphorus-doped silicon layer 2064, and the silicon contact layer 2065 after the planarization is subjected to the planarization process.

In this planarization step, the uppermost silicon contact layer 2065 is mainly planarized.

Step S170: as shown in fig. 14 and 15, a bit line stack is formed over the stack of silicon seed layer 2061, first phosphorus doped silicon layer 2062, second phosphorus doped silicon layer 2064, and silicon contact layer 2065 after planarization.

The bit line stack includes a barrier layer 2071 and a metal layer 2072 stacked in sequence above the silicon contact layer 2065.

The material of the barrier layer 2071 includes titanium nitride (TiN), and the material of the metal layer 2072 includes tungsten (W).

In the embodiment of the present invention, the cavity 2063 in the semiconductor layer below the bit line stack is located lower, the bit line stack is far away from the cavity 2063 formed in the semiconductor layer below the bit line stack, and the metal ions in the metal layer 2072 do not penetrate into the cavity 2063, and do not affect the barrier layer 2071 and the metal layer 2072.

Step S180: patterning the planarized stack of silicon seed layer 2061, first phosphorus-doped silicon layer 2062, second phosphorus-doped silicon layer 2064, and silicon contact layer 2065, and the bit line stack to obtain bit line contact plugs (not shown) and bit line structures (not shown), respectively; the bit line structure is electrically connected to the substrate 201 through the bit line contact plug.

The bit line contact plug is composed of a silicon seed layer 2061, a first phosphorus-doped silicon layer 2062, a second phosphorus-doped silicon layer 2064, and a silicon contact layer 2065.

The bit line structure is formed from a bit line stack.

In the embodiment of the present invention, the cavity 2063 in the semiconductor layer below the bit line stack is located at a lower position, the bit line stack is far away from the cavity 2063 formed in the semiconductor layer below the bit line stack, and the metal ions in the metal layer 2072 do not penetrate into the cavity 2063, so that the morphology of the bit line structure is not affected during the etching process.

The structure of the resulting semiconductor device is shown in fig. 16 and 17.

The present embodiment provides a method for manufacturing a semiconductor device, which includes placing a substrate 201 in a reaction chamber, and heating the reaction chamber to a first predetermined temperature to form a silicon seed layer 2061 covering the inner wall of a contact hole 205 and the upper surface of the substrate 201; heating the reaction chamber to a second predetermined temperature to form a first phosphorus doped silicon layer 2062 above the silicon seed layer 2061; heating the reaction chamber to a third predetermined temperature to form a second phosphorus doped silicon layer 2064 over the first phosphorus doped silicon layer 2062; the phosphorus doping amount of the second phosphorus-doped silicon layer 2064 is different from the phosphorus doping amount of the first phosphorus-doped silicon layer 2062, and the total thickness of the silicon seed layer 2061, the first phosphorus-doped silicon layer 2062 and the second phosphorus-doped silicon layer 2064 is greater than or equal to the depth of the contact hole 205. The semiconductor layer of the bit line plug forms a phosphorus doped silicon layer with a certain distribution of doping amount in a layered deposition mode to fill the contact hole on the substrate, the stress change and the size shrinkage of the semiconductor layer are controlled, the flatness of the semiconductor layer is greatly improved, the size of the formed cavity is small and the cavity moves along the direction close to the substrate, and even after the semiconductor layer is flattened and thinned, the cavity cannot influence the film layer on the cavity.

Example two

On the basis of the first embodiment, the present embodiment provides a method for manufacturing the first phosphorus doped silicon layer 2062 in the semiconductor device. Fig. 18 is a flowchart illustrating a method for forming a first phosphorus doped silicon layer 2062 in a semiconductor device according to an embodiment of the present application.

As shown in fig. 18, the method for manufacturing the first phosphorus doped silicon layer 2062 in the semiconductor device of this embodiment includes the following steps:

step S132: the reaction chamber is heated to a second predetermined temperature, a first reaction gas is introduced into the reaction chamber until the pressure in the reaction chamber is a first predetermined pressure, and the first predetermined time is maintained, so as to form a first phosphorus-doped silicon layer 2062 above the silicon seed layer 2061.

The first reaction gas may be monosilane (SiH4) and phosphine (PH 3).

The gas flow rates for monosilane (SiH4) and phosphane (PH3) may be 600sccm and 168sccm, respectively.

In some cases, the first predetermined pressure is small, and may be 0.25 torr.

The second preset temperature may be 470 ℃.

The first preset duration may be 15 s.

Step S134: introducing a second reaction gas into the reaction chamber until the pressure in the reaction chamber is a second preset pressure, and keeping the second preset time to thicken the first phosphorus-doped silicon layer 2062; wherein the second preset pressure is different from the first preset pressure.

The second reactive gas, which is the same as the first reactive gas, may be monosilane (SiH4) and phosphane (PH 3).

The gas flow rates for monosilane (SiH4) and phosphane (PH3) may be 600sccm and 168sccm, respectively.

In some cases, the second predetermined pressure is greater than the first predetermined pressure, and the second predetermined pressure is greater, and may be 2.007 torr. Correspondingly, the second preset time length is longer than the first preset time length. The second preset time period may be 1 min.

In some cases, the second preset pressure may be less than the first preset pressure.

Step S136: steps S132 to S134 are repeatedly performed at least 5 times until the thickness of the first phosphorus doped silicon layer 2062 formed above the silicon seed layer 2061 reaches a predetermined thickness.

In some cases, steps S132 to S134 may be repeated (cycled) 75 times.

The pressure change in the reaction chamber during the cycle is shown in fig. 19.

In step S130, the average value of the gas pressure of the reaction chamber is an average value of the first preset pressure and the second preset pressure.

The pressure in the reaction chamber in step S140 is less than an average of the first preset pressure and the second preset pressure.

At each end, the thickness of the first phosphorus doped silicon layer 2062 is increased by a certain amount.

In the embodiment of the present application, the first phosphorus-doped silicon layer 2062 is further refined and formed by a low-pressure to high-pressure cyclic deposition method, so as to further reduce the size of the cavity 2063 formed in the semiconductor layer and further reduce the height of the cavity 2063, so that the distance between the bit line stack and the cavity 2063 formed in the semiconductor layer below the bit line stack is further increased, thereby further preventing the metal ions in the metal layer 2072 from penetrating into the cavity 2063, and further ensuring that the cavity 2063 does not affect the morphology of the bit line structure during the etching process.

The embodiment provides a method for preparing a first phosphorus-doped silicon layer 2062 in a semiconductor device, which includes heating a reaction chamber to a second preset temperature, introducing a first reaction gas into the reaction chamber until the pressure in the reaction chamber is a first preset pressure, and maintaining the first preset pressure for a first preset time period to form the first phosphorus-doped silicon layer 2062 above a silicon seed layer 2061; introducing a second reaction gas into the reaction chamber until the pressure in the reaction chamber is a second preset pressure, and keeping the second preset time to thicken the first phosphorus-doped silicon layer 2062; wherein the second preset pressure is different from the first preset pressure; the above steps are repeated until the thickness of the first phosphorus doped silicon layer 2062 formed above the silicon seed layer 2061 reaches a predetermined thickness. The first phosphorus-doped silicon layer 2062 is further refined and formed by low-pressure to high-pressure cyclic deposition, so that the size of the cavity 2063 formed in the semiconductor layer is further reduced, the height of the cavity 2063 is further reduced, the distance between the bit line stack and the cavity 2063 formed in the semiconductor layer below the bit line stack is further increased, metal ions in the metal layer 2072 are further prevented from penetrating into the cavity 2063, and the cavity 2063 is further ensured not to influence the appearance of the bit line structure in the etching process.

EXAMPLE III

As shown in fig. 16 and 17, the present embodiment provides a semiconductor device including: a semiconductor substrate 201, contact holes 205, a silicon seed layer 2061, a first phosphorus doped silicon layer 2062, a second phosphorus doped silicon layer 2064, and bit line structures.

Contact holes 205 are provided in the substrate surface and extend into the substrate interior.

In some cases, an active pattern 2011, an isolation pattern 202, and a trench gate structure 203 are also disposed in the upper surface of the substrate 201.

A plurality of spaced active patterns 2011 are disposed in the surface of the substrate 201 along a first direction; wherein each active pattern 2011 is isolated from each other by the isolation pattern 202.

A plurality of trench gate structures 203 arranged at intervals are arranged in the surface of the substrate 201 along the second direction; wherein each trench gate structure 203 intersects at least one active pattern 2011.

In some cases, the upper surface of the substrate 201 is also covered with a first interlayer insulating layer 204.

A plurality of active patterns 2011 are disposed on the substrate 201 at intervals, each of the active patterns 2011 is parallel to each other and disposed along a first direction, the active patterns 2011 are formed by forming doped regions (not shown) by ion implantation, and an upper surface of the active patterns 2011 is flush with an upper surface of the substrate 201. The active patterns 2011 in two adjacent rows are staggered, and the active patterns 2011 in two adjacent columns are staggered.

Each of the active patterns 2011 is isolated from each other by an isolation pattern 202, and the isolation pattern 202 is used to define the shape of the active pattern 2011.

A plurality of trench-gate structures 203 are spaced apart on the substrate 201, each trench-gate structure 203 is parallel to each other and arranged along a second direction (e.g., a transverse direction as shown in fig. 16), each trench-gate structure 203 intersects at least one active pattern 2011, and each trench-gate structure 203 intersects at least one active pattern 2011, for example, as shown in fig. 16. The trench gate structure 203 includes a trench, a gate insulating layer 2031 disposed on a sidewall and a bottom of the trench, and a gate electrode 2032 and a second interlayer insulating layer 2033 filled in a lower portion and an upper portion of the trench, respectively. The thickness of the gate 2032 is smaller than the depth of the trench, but the top of the gate 2032 is higher than the bottom of the doped region (not shown) in the active pattern 2011. The second interlayer insulating layer 2033 is formed of, for example, a silicon nitride layer and/or a silicon oxynitride layer.

The first interlayer insulating layer 204 is disposed over the substrate 201 and covers the active pattern 2011 and the trench gate structure 203, and a material of the first interlayer insulating layer 204 includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

The contact hole 205 penetrates the first interlayer insulating layer 204 and extends into the active pattern 2011, the isolation pattern 202, and the trench gate structure 203.

The silicon seed layer 2061 covers at least a part of the inner wall of the contact hole 205 and a part of the upper surface of the substrate 201. The thickness of the silicon seed layer 2061 is in the order of atomic layers. The thickness of the silicon seed layer 2061 may be 0 to 5A.

The first phosphorus doped silicon layer 2062 covers the surface of the silicon seed layer 2061 remote from the substrate 201. The first phosphorus doped silicon layer 2062 has a thickness of 180A to 260A.

Silicon seed layer 2061 is recessed at the location of contact hole 205 and first phosphorus doped silicon layer 2062 is recessed at the location of contact hole 205 due to the presence of contact hole 205.

The second phosphorus doped silicon layer 2064 covers the surface of the first phosphorus doped silicon layer 2062 remote from the silicon seed layer 2061. The surface of the second phosphorus doped silicon layer 2064 near the first phosphorus doped silicon layer 2062 is in contact with the surface of the first phosphorus doped silicon layer 2062 remote from the silicon seed layer 2061.

Wherein the second phosphorus doped silicon layer 2064 has a phosphorus doping amount different from the phosphorus doping amount of the first phosphorus doped silicon layer 2062.

In some cases, the second phosphorus doped silicon layer 2064 may have a phosphorus doping amount less than that of the first phosphorus doped silicon layer 2062.

In some cases, the second phosphorus doped silicon layer 2064 may have a phosphorus doping amount greater than that of the first phosphorus doped silicon layer 2062.

The total thickness of silicon seed layer 2061, first phosphorus doped silicon layer 2062, and second phosphorus doped silicon layer 2064 is greater than or equal to the depth of contact hole 205.

At the location of the contact hole 205, at least one void 2063 is formed at the interface of the first phosphorus doped silicon layer 2062 and the second phosphorus doped silicon layer 2064.

The bottom of the void 2063 extends into the first phosphorus doped silicon layer 2062 and the top of the void 2023 extends into the second phosphorus doped silicon layer 2064.

In this embodiment, the cavity 2063 is located at the interface between the first phosphorus-doped silicon layer 2062 and the second phosphorus-doped silicon layer 2064, so that the cavity 2063 is closer to the substrate 201, and the film layers above are not affected during the film layer patterning process.

The surface of first phosphorus doped silicon layer 2062 near silicon seed layer 2061 is in contact with the surface of silicon seed layer 2061 remote from the substrate.

The first phosphorus doped silicon layer 2062 is isolated from the upper surface of the substrate by the silicon seed layer 2061 and the first insulating layer 204, that is, the topmost part of the first phosphorus doped silicon layer 2062 is higher than the surface of the substrate 101.

In some cases, the semiconductor device further includes an undoped silicon contact layer 2065 covering a surface of the second phosphorus doped silicon layer 2064 remote from the first phosphorus doped silicon layer 2062.

Correspondingly, the silicon seed layer 2061, the first phosphorus doped silicon layer 2062, the second phosphorus doped silicon layer 2064, and the doped silicon contact layer 2065 constitute a bit line plug.

Correspondingly, the semiconductor device further includes a bit line structure located above the bit line plug, and the bit line structure includes a barrier layer 2071 and a metal layer 2072 stacked in sequence above the second phosphorus-doped silicon layer 2064.

The material of the barrier layer 2071 includes titanium nitride (TiN), and the material of the metal layer 2072 includes tungsten (W).

The bit line structures are electrically connected to the substrate 201 through the bit line plugs, the bit line structures and the bit line plugs are similar in shape, and the orthographic projections of the bit line plugs (including the silicon seed layer 2061, the first phosphorus-doped silicon layer 2062, the second phosphorus-doped silicon layer 2064 and the doped silicon contact layer 2065) on the substrate 101 at least cover the orthographic projections of the bit line structures on the substrate 101.

A plurality of bit line structures arranged at intervals are arranged along a third direction (vertical direction shown in fig. 16); the orthographic projection of the bit line structure on the substrate 201 is perpendicular to the trench gate structure 203, that is, the third direction is perpendicular to the second direction. Each of the bit line structures is connected to at least one of the active patterns 1011 through a contact plug at a position of the corresponding contact hole 105, and exemplarily, each of the bit line structures is connected to the active patterns 1011 of a corresponding column through a contact plug at the corresponding contact hole 105 as shown in fig. 16.

In this embodiment, the cavity 2063 in the semiconductor layer below the bit line stack is located at the interface between the first phosphorus-doped silicon layer 2062 and the second phosphorus-doped silicon layer 2064, and the bit line stack is located at a relatively long distance from the cavity 2063 formed in the semiconductor layer below the bit line stack, so that metal ions in the metal layer 2072 do not penetrate into the cavity 2063, and do not affect the barrier layer 2071 and the metal layer 2072.

The present embodiment provides a semiconductor device including a semiconductor substrate 201; a contact hole 205 provided in the surface of the substrate 201 and extending into the substrate 201; a silicon seed layer 2061 covering the inner wall of the contact hole 205 and the upper surface of the substrate 201; a first phosphorus doped silicon layer 2062 covering the surface of the silicon seed layer 2061 remote from the substrate 201; a second phosphorus doped silicon layer 2064 covering the surface of the first phosphorus doped silicon layer 2062 remote from the silicon seed layer 2061; wherein the phosphorus doping amount of the second phosphorus doped silicon layer 2064 is different from the phosphorus doping amount of the first phosphorus doped silicon layer 2062; the total thickness of silicon seed layer 2061, first phosphorus-doped silicon layer 2062, and second phosphorus-doped silicon layer 2064 is greater than or equal to the depth of contact hole 205; at the location of the contact hole 205, at least one void 2063 is formed at the interface of the first phosphorus doped silicon layer 2062 and the second phosphorus doped silicon layer 2064. The voids 2063 are located at the interface between the first phosphorus doped silicon layer 2062 and the second phosphorus doped silicon layer 2064, so that the voids 2063 are closer to the substrate 201 and do not affect the upper film layer during the patterning process.

Although the embodiments disclosed in the present application are described above, the contents thereof are only embodiments adopted to facilitate understanding of the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.