阅读说明：本技术 在图案化中的氧化锡心轴 (Tin oxide mandrels in patterning ) 是由 游正义 萨曼莎·西亚姆华·坦 徐相俊 鲍里斯·沃洛斯基 希瓦南达·克里希南·卡纳卡萨巴保蒂 于 2019-01-29 设计创作，主要内容包括：氧化锡膜在半导体器件制造中用作心轴。在一个实现方式中,该处理开始于提供一种衬底,该衬底具有存在于暴露的蚀刻停止层上的多个突起的氧化锡特征(心轴)。接下来,在心轴的水平表面和侧壁上都形成保形的间隔材料层。然后从水平表面去除间隔材料,从而暴露出心轴的氧化锡材料,而没有完全去除存在于心轴侧壁上的间隔材料(例如,留下初始在侧壁上的高度的至少50％,例如至少90％)。接下来,选择性地去除心轴(例如,使用基于氢的蚀刻化学物质),同时保留存在于心轴侧壁上的间隔材料。所得的间隔件可用于图案化蚀刻停止层和下伏层。(Tin oxide films are used as mandrels in semiconductor device fabrication. In one implementation, the process begins by providing a substrate having a plurality of raised tin oxide features (mandrels) present on an exposed etch stop layer. Next, a conformal layer of spacer material is formed on both the horizontal surfaces and sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces, thereby exposing the tin oxide material of the mandrels, without completely removing the spacer material present on the sidewalls of the mandrels (e.g., leaving at least 50%, such as at least 90%, of the height initially on the sidewalls). Next, the mandrels are selectively removed (e.g., using a hydrogen-based etch chemistry) while retaining the spacer material present on the mandrel sidewalls. The resulting spacers can be used to pattern etch stop layers and underlying layers.)

1. A method of processing a semiconductor substrate, the method comprising

(a) Providing a semiconductor substrate having a patterned photoresist layer overlying a tin oxide layer;

(b) etching a plurality of openings in the tin oxide layer using the patterned photoresist layer as a mask, wherein etching the plurality of openings comprises etching the tin oxide layer using at least one of a hydrogen-based etching chemistry and a chlorine-based etching chemistry;

(c) at least partially removing the photoresist layer using an oxygen-based etch chemistry and forming a plurality of tin oxide mandrels;

(d) depositing a layer of spacer material on the tin oxide mandrels such that the spacer material coats sidewalls of the tin oxide mandrels and horizontal portions of the tin oxide mandrels;

(e) removing the spacer material from the horizontal portion of the tin oxide mandrel, an

(f) The tin oxide mandrels are removed to form a plurality of spacers on the semiconductor substrate.

2. The method of claim 1, wherein (b) comprises etching the tin oxide layer using a hydrogen-based etch chemistry.

3. The method of claim 1, wherein (b) comprises etching the tin oxide layer using a hydrogen-based etch chemistry, and wherein the etching comprises exposing the semiconductor substrate to H activated in a plasma₂And Cl activated in plasma₂And (4) contacting.

4. The method of claim 1, wherein (b) comprises etching the tin oxide layer using a hydrogen-based etch chemistry, wherein the etching comprises contacting the semiconductor substrate with a hydrogen-containing gas comprising H₂And Cl₂Wherein H in the process gas₂The concentration is at least 50%.

5. The method of claim 1, wherein (b) comprises etching the tin oxide layer using a hydrogen-based etch chemistry, wherein the etching comprises contacting the semiconductor substrate with a hydrogen-containing gas comprising H₂And Cl₂Wherein H in the process gas₂The concentration is at least 80%.

6. The method of claim 1, wherein the etching of the tin oxide layer in (b) is performed using an etch chemistry that etches tin oxide at a higher etch rate than photoresist.

7. The method of claim 1, wherein (b) comprises etching the tin oxide layer using a hydrogen-based etch chemistry, wherein the etching comprises forming a plasma in a process gas comprising a material selected from the group consisting of H₂、HBr、NH₃、H₂O, hydrocarbons, and combinations thereof.

8. The method of claim 1, wherein the semiconductor substrate provided in (a) comprises one or more intermediate layers between the tin oxide layer and the patterned photoresist layer, and wherein etching a plurality of openings in the tin oxide layer using the patterned photoresist layer as a mask comprises transferring a pattern of the patterned photoresist layer to the one or more intermediate layers.

9. The method of claim 1, wherein the photoresist is completely removed in (c) after the opening in the tin oxide layer is formed.

10. The method of claim 1, wherein the semiconductor substrate provided in (a) comprises one or more intermediate layers between the tin oxide layer and the patterned photoresist layer, wherein etching a plurality of openings in the tin oxide layer using the patterned photoresist layer as a mask comprises transferring a pattern of the patterned photoresist layer to the one or more intermediate layers, and wherein the photoresist is completely removed in (c) prior to formation of the openings in the tin oxide layer.

11. The method of claim 1, further comprising:

(g) etching one or more underlying layers after (f) using the plurality of spacers as a mask.

12. The method of claim 1, wherein removing the tin oxide mandrels in (e) comprises etching the tin oxide mandrels using a hydrogen-based etch chemistry.

13. The method of claim 1, wherein removing the tin oxide mandrels in (e) comprises using a hydrogen-based etch chemistry by exposing the semiconductor substrate to a gas comprising a material selected from the group consisting of H₂、HBr、NH₃And combinations thereof to etch the tin oxide mandrels.

14. The method of claim 3, wherein the process gas used to etch the tin oxide layer further comprises an inert gas.

15. The method of claim 3, wherein the process gas used to etch the tin oxide layer further comprises a gas selected from the group consisting of argon, N₂And combinations thereof.

16. The method of claim 1, wherein removing the spacer material from the horizontal portions of the tin oxide mandrels comprises using an etch chemistry that etches the spacer material at a faster rate than the tin oxide layer.

17. The method of claim 1, wherein the spacer material is selected from the group consisting of a silicon-containing material, a carbon-containing material, and a metal oxide.

18. The method of claim 1, wherein the spacer material is a silicon-containing material, and wherein (c) comprises removing the spacer material from horizontal surfaces selectively to tin oxide using a fluorocarbon etch chemistry.

19. The method of claim 1, wherein (c) comprises removing the photoresist using an oxygen-based etch chemistry to expose the tin oxide layer.

20. The method of claim 1, further comprising:

(g) after (f), forming a plurality of openings in an etch stop layer and a target layer using the spacer, the etch stop layer underlying the spacer, the target layer underlying the etch stop layer.

Technical Field

The present invention relates to a method of manufacturing a semiconductor device. In particular, embodiments of the invention relate to methods of using tin oxide films in semiconductor processing.

Background

In Integrated Circuit (IC) fabrication, deposition and etching techniques are used to form patterns of materials, such as for forming metal lines embedded in dielectric layers. Some patterning schemes involve the use of spacers that enable precise patterning and formation of small-sized features. The spacers are formed on the substrate such that they are separated by a defined distance (typically determined by previous patterning) and serve as a mask for patterning of the underlying layers. The materials of the spacers and surrounding layers are selected to have an appropriate etch selectivity, which will enable the formation of spacer and underlying layer patterning. After patterning is completed, the spacers are removed by etching, and the spacers are not part of the finally manufactured semiconductor device.

Spacers are used for patterning in various applications, including forming Dynamic Random Access Memories (DRAMs), patterning fins in fin field effect transistors (finfets), and back end of line (BEOL) processing.

Spacers may be formed on a semiconductor substrate using a patterning process involving mandrel-larger raised features that act as a support for the spacers, which are subsequently selectively removed by an etching process, thereby leaving the spacers on the substrate.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

Disclosure of Invention

Tin oxide is used as a mandrel material in the patterning of semiconductor substrates. The patterning methods provided herein can achieve a high degree of control over spacer and mandrel geometry as well as achieve high efficiency.

In one aspect, a method of processing a semiconductor substrate using a tin oxide mandrel is provided. In some embodiments, the method comprises: (a) providing a semiconductor substrate having a plurality of tin oxide protruding features (mandrels) present on an Etch Stop Layer (ESL); (b) forming a layer of spacer material on both horizontal surfaces and sidewalls of the tin oxide protrusion feature; and (c) removing the spacer material from the horizontal surfaces of the tin oxide protrusion features to expose underlying tin oxide without completely removing the spacer material on the sidewalls of the tin oxide protrusion features. In some embodiments, the processing further comprises the operations of: removing the tin oxide protrusion feature without completely removing the spacer material previously present on the sidewalls of the tin oxide protrusion feature, thereby forming a plurality of spacers present over the etch stop layer. In some implementations, after removing the tin oxide protrusion features, the method then etches the etch stop layer in the presence of the plurality of spacers.

In some embodiments, the spacer material is a silicon-containing material (e.g., silicon oxide, silicon nitride, silicon carbide, SiOC, SiNO, SiCNO, or SiCN) or titanium dioxide. In one implementation, the spacer material is titanium dioxide and the etch stop layer includes a silicon-containing material. In other embodiments, the spacer material is silicon oxide and the etch stop layer comprises tungsten.

The spacer etch chemistry used in operation (c) may vary depending on the chemistry of the spacer material. In some embodiments, the spacer material is a silicon-containing material, and removing the spacer material from horizontal surfaces in (c) comprises etching the spacer material using a fluorine-based etch chemistry. In other embodiments, the spacer material is titanium dioxide, and removing the spacer material from horizontal surfaces in (c) comprises etching the spacer material using a chlorine-based etching chemistry.

In some embodiments, after the spacer material has been removed from the horizontal surfaces and after the tin oxide has been exposed, the process continues by: (d) removing tin oxide protrusion features (mandrels) without completely removing the spacer material previously present on the sidewalls of the tin oxide protrusion features, thereby forming a plurality of spacers present over the etch stop layer, wherein the tin oxide protrusion features are removed using a hydrogen-based etch chemistry, thereby resulting in formation of tin hydride. In some implementations, removing the tin oxide protrusion feature includes: contacting the semiconductor substrate with a compound selected from the group consisting of H₂、HBr、NH₃、H₂O, hydrocarbons, and combinations thereof.

Several different process flows may be used to form the semiconductor substrate having the plurality of tin oxide bump features provided in operation (a). In one implementation, forming a plurality of tin oxide protruding features on a semiconductor substrate is achieved by patterning a planar (blanket) tin oxide layer. In another embodiment, forming a plurality of tin oxide protruding features includes: (i) forming a plurality of first mandrels (e.g., photoresist or other carbon-containing mandrels) on a semiconductor substrate; (ii) conformally depositing a tin oxide layer over the plurality of first mandrels; and (iii) etching the deposited tin oxide layer from horizontal surfaces and removing the plurality of first mandrels to form the plurality of tin oxide protrusion features on the semiconductor substrate provided in (a), wherein the plurality of tin oxide protrusion features formed serve as second mandrels in subsequent operations (b) - (c).

In some implementations, the first mandrel comprises a carbon-containing material, such as a photoresist, diamond-like carbon, or amorphous carbon, and operation (iii) includes using a hydrogen-based etch chemistry (e.g., using H)₂Or hydrocarbons, e.g. CH₄Or C₂H₂As a hydrogen-containing gas) or chlorine-based etch chemistries (e.g., using Cl)₂And/or BCl₃) The deposited tin oxide layer is etched from horizontal surfaces, and then the plurality of first mandrels are removed using an oxygen-based etch chemistry.

In some embodiments, the provided methods are used in conjunction with photolithographic processing. For example, in some implementations, the processing includes applying photoresist to a semiconductor substrate, exposing the photoresist to light, patterning the photoresist and transferring a pattern to the substrate, and selectively removing the photoresist from the substrate. In another aspect, a system for processing a semiconductor substrate is provided. In some embodiments, the system comprises: one or more deposition chambers; one or more etching chambers; and a system controller including program instructions for causing a series of operations. In some embodiments, the program instructions are for: causing a spacer material to be deposited on both the horizontal surfaces and the sidewalls of a plurality of tin oxide protrusion features on a semiconductor substrate comprising the tin oxide protrusion features; and causing removal of the spacer material from the horizontal surfaces of the tin oxide protrusion features to expose underlying tin oxide without causing complete removal of the spacer material on the sidewalls of the tin oxide protrusion features. The system controller may also include program instructions for: causing removal of the tin oxide protrusion feature without causing complete removal of the spacer material previously present on the sidewalls of the tin oxide protrusion feature, thereby forming a plurality of spacers on the semiconductor substrate. The system controller may also include program instructions for: the semiconductor substrate including the plurality of tin oxide protruding features is caused to be formed by causing a conformal tin oxide layer to be deposited on a semiconductor substrate having a plurality of first mandrels, then by removing the tin oxide material from horizontal surfaces and by removing the first mandrels.

In another aspect, an etching apparatus is provided. In some embodiments, an etching apparatus comprises: an etch process chamber having an inlet for a process gas; a substrate holder configured to hold a semiconductor substrate in the etching process chamber; and a process controller comprising program instructions for causing one or more operations. In some embodiments, the process controller includes program instructions for: causing etching of a spacer material layer of a plurality of tin oxide protrusion features coated on the semiconductor substrate, thereby completely removing the spacer material from the horizontal surfaces of the semiconductor substrate without completely removing the spacer material on the sidewalls of the plurality of tin oxide protrusion features. In some embodiments, the program instructions for causing etching of the spacer material comprise program instructions for causing etching of the spacer material layer using a fluorine-based etch chemistry, wherein the spacer material is a silicon-containing material.

In another aspect, an apparatus is provided, wherein the apparatus comprises a process chamber and a controller having program instructions for causing any of the methods provided herein.

In another aspect, a partially fabricated semiconductor device is provided, wherein the partially fabricated semiconductor device includes a plurality of tin oxide protruding features coated with a conformal spacer material layer.

These and other aspects of implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

Drawings

Fig. 1A-1F show schematic cross-sectional views of a semiconductor substrate undergoing processing involving spacer formation, according to embodiments provided herein.

Fig. 2 is a process flow diagram of a method according to an embodiment provided herein.

Fig. 3 is a process flow diagram of a method of forming a tin oxide mandrel according to embodiments provided herein.

Fig. 4A-4E show schematic cross-sectional views of a semiconductor substrate being processed to form tin oxide mandrels, in accordance with an embodiment provided herein.

Fig. 5A-5C show schematic cross-sectional views of a semiconductor substrate being processed to form tin oxide mandrels, in accordance with an embodiment provided herein.

Fig. 6 is a process flow diagram of a method of forming a tin oxide mandrel according to embodiments provided herein.

Fig. 7A-7G show schematic cross-sectional views of a semiconductor substrate being processed showing the use of tin oxide spacers as second mandrels in a self-aligned quad patterning (SAQP) process, according to embodiments provided herein.

Fig. 8A-8F show schematic isometric views of a semiconductor substrate being processed showing the use of tin oxide spacers as second mandrels in a SAQP process, according to embodiments provided herein.

Fig. 9 is a schematic diagram of an apparatus suitable for etching tin oxide using the etch chemistries provided herein.

Fig. 10 shows a schematic diagram of a multi-station processing system according to an embodiment provided herein.

Detailed Description

Methods of using tin oxide films in semiconductor device fabrication are provided. The method utilizes a variety of etch processes with tunable etch rates and selectivity that enable integration of tin oxide films into processing schemes employing a variety of materials, such as silicon-containing compounds (e.g., silicon oxide (SiO)₂) Silicon carbide (SiC), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiNO), silicon oxycarbonitride (SiCNO), and silicon carbonitride (SiCN)), elemental silicon (Si), carbon (including amorphous carbon and diamond-like carbon), photoresists, carbon-containing compounds (e.g., organic polymers, metal carbides, tungsten-containing carbon), metals (e.g., tungsten), metal oxides (e.g., titanium oxide, hafnium oxide, zirconium oxide, tantalum oxide), and metal nitrides (e.g., tantalum nitride (TaN) and titanium nitride (TiN)). In some embodiments, the tin oxide is etched in the presence of any of these materials, with an etch selectivity of at least 10: 1, such as at least 20: 1. In some embodiments, any of these materials are etched in the presence of tin oxide, wherein the etch selectivity ratio is at least 10: 1, such as at least 20: 1. The selectivity ratio refers to the ratio of the etch rates of the materials. For example, if the ratio of the etch rate of silicon oxide to the etch rate of tin oxide is at least 10: 1 for a particular etch chemistry, then silicon oxide is etched at a selectivity of at least 10: 1 relative to tin oxide with that etch chemistry.

In the embodiments provided, tin oxide is used for the patterning process, wherein the tin oxide film is used as a mandrel for spacer formation. For example, the tin oxide may be a mandrel in self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP). In conjunction with the selective etch process, tin oxide meets the stringent Critical Dimension (CD)/profile and selectivity requirements imposed by these applications. The etch process may be performed on various tools that allow plasma etching, such as those provided by Lam Research CorporationAnd Flex^TMOn the etching tool.

Tin oxide can be selectively etched for various materials using a hydrogen-based etch, thereby converting the tin oxide to a volatile tin hydride product (e.g., tin tetrahydride). The term "tin hydride" as used herein includes various tin hydrides (compounds having tin-hydrogen bonding), and is not limited to tin tetrahydride (SnH)₄). Terms like "tin chloride" and "silicon fluoride" similarly can include a variety of chlorides and fluorides. Unlike hydrides of many other metals, tin tetrahydride has a low boiling point and can therefore be easily removed from the process chamber by purging and/or pumping, making hydrogen-based etching a particularly attractive process for selective tin oxide etching.

As used herein, tin oxide refers to a material comprising tin (Sn) and oxygen (O), and may optionally include hydrogen. As used herein, tin oxide may also contain minor amounts of other elements, such as carbon and nitrogen (e.g., SnO)_xN_y) Wherein the total amount of other elements is 10 atomic% or less (wherein hydrogen is not included in the calculation of the content). For example, ALD deposited tin oxide may contain about 0.5-5 atomic% carbon. For example, tin oxide may be deposited by ALD, PECVD or PVD. The stoichiometry of the tin oxide can generally vary. In some embodiments, the atomic ratio of tin to oxygen is about 1: 2 (SnO)₂). It should be understood that the deviation 1: 2 in SnO₂May be present in SnO₂Within the scope of the structure. For example, in some SnO₂In an example of (d), the atomic ratio of O to Sn is between about 2.0 and 2.3. As used herein, tin oxide having a ratio of O to Sn of about 1.5 to 2.5 is used in SnO₂Within the range of materials. The tin oxide materials described herein are distinct from indium tin oxide materials and other mixed metal oxides.

It is understood that, unless otherwise indicated, stoichiometry may vary among other chemical compounds used herein. For example, chemical formulas such as SiN and HfO specify elements that are present but not stoichiometric. Further, it is understood that the materials described herein may include hydrogen (even if not specified in the formula) and small amounts of dopants not specifically listed in the chemical name (e.g., less than 10 atomic percent dopants).

The term "semiconductor substrate" as used herein refers to a substrate comprising semiconductor material anywhere within the structure at any stage of semiconductor device fabrication. It should be understood that the semiconductor material in the semiconductor substrate need not be exposed. A semiconductor wafer having multiple layers of other materials (e.g., dielectrics) overlying the semiconductor material is an example of a semiconductor substrate. The following detailed description assumes that the disclosed implementations are implemented on a wafer. However, the disclosed implementations are not so limited. The workpiece may have various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the disclosed implementations include various articles, such as printed circuit boards and the like.

Unless otherwise specified, the term "about," when used in conjunction with a numerical value, refers to a range within 5% of the stated numerical value.

In some embodiments, selective etch chemistries are provided for removing certain materials or features on the substrate without removing other materials or features. As used herein, an etch chemistry "removes" a material or feature when it removes at least 90% (e.g., 100%) (with reference to thickness in the vertical direction). As used herein, the term "not removed" refers to at least 50% of the material or feature remaining after etching (e.g., at least 80%), where% refers to the thickness in the vertical direction.

In some embodiments, methods are provided for removing material from horizontal surfaces of protruding features without removing material present at sidewalls of the protruding features. It should be understood that a horizontal surface as used herein includes a surface having a local deviation from horizontal, such as a convex cap on top of a protruding feature.

A variety of etch chemistries have been developed for selectively etching tin oxide in the presence of other materials, as well as for selectively etching other materials in the presence of tin oxide. Selectively etching tin oxide in the presence of another material is referred to as a tin oxide etch, wherein the ratio of the etch rate of tin oxide to the etch rate of the other material is greater than 1, and wherein the other material and tin oxide are exposed to the same etch chemistry at any time during the etching process. For example, the other material may be exposed at the beginning of the etch, or may be exposed during the etch. The etch selectivity for selectively etching tin oxide in the presence of another material refers to the ratio of the etch rate of tin oxide to the etch rate of the other material for a given chemistry. For example, tin oxide can be selectively etched using a hydrogen-based etch chemistry in the presence of a silicon-containing compound, where the etch selectivity ratio is greater than 50.

Similarly, selective etching of a material in the presence of tin oxide refers to such etching of the material, wherein the ratio of the etch rate of the material to the etch rate of tin oxide is greater than 1, and wherein the tin oxide is exposed to the same etching chemistry as the material being etched at any time during the etching process. For example, tin oxide may be exposed at the beginning of the etch, or may be exposed during the etch. The etch selectivity for selective etching of a material in the presence of tin oxide refers to the ratio of the etch rate of the material to the etch rate of tin oxide for a given chemistry. For example, carbon may be selectively etched using an oxygen-based etch chemistry in the presence of tin oxide, where the etch selectivity ratio is greater than 50.

In some embodiments, methods for removing tin oxide mandrels are provided. First, a semiconductor substrate is provided, wherein the semiconductor substrate comprises a plurality of tin oxide protrusion features (mandrels) and a layer of spacer material, wherein the spacer material is present at sidewalls of the tin oxide protrusion features. Next, the tin oxide is selectively etched in the presence of the second material using one of the selective tin oxide etch chemistries described herein. The tin oxide protrusion features can be removed by these selective etches without completely removing the spacer material previously present on the sidewalls, thereby forming a plurality of spacers.

In some embodiments, a method for removing spacer material from horizontal surfaces on a substrate is provided, wherein the spacer material coats tin oxide mandrels. First, a semiconductor substrate is provided, wherein the semiconductor substrate includes a plurality of tin oxide protruding features (mandrels) and a conformal spacer material layer present on horizontal surfaces and sidewalls of the tin oxide mandrels. Next, the spacer material is removed from the horizontal surfaces without completely removing the spacer material on the sidewalls and exposing the tin oxide. This step may be performed by any selective etch chemistry described herein that allows for selective spacer material etching in the presence of tin oxide.

In some embodiments, methods for depositing a conformal spacer material layer on a plurality of tin oxide mandrels are provided. First, a semiconductor substrate is provided, wherein the semiconductor substrate comprises a plurality of tin oxide mandrels. Next, a spacer material (e.g., a silicon-containing material) is deposited on the substrate such that it coats the mandrels on both the sidewalls and horizontal surfaces.

A hydrogen-based etch. In some embodiments, the selective tin oxide etch is performed using a hydrogen-based etch. Hydrogen-based etching involves exposing tin oxide to a hydrogen-containing reactant (typically in the case of plasma activation of the reactant) such that it converts the tin oxide to a volatile tin hydride. SnH₄Has a boiling point of-52 ℃ and can be easily removed from the process chamber. Examples of hydrogen-containing reactants include H₂、HBr、NH₃、H₂O and hydrocarbons (e.g. CH)₄、C₂H₂Etc.). Mixtures of hydrogen-containing reactants may also be used. Hydrogen-based etching involves forming a plasma in a process gas containing a hydrogen-containing reactant and optionally an inert gas, and contacting the substrate with the formed plasma. Examples of the inert gas include nitrogen (N)₂) Helium (He), argon (Ar), and neon (Ne), and xenon (Xe). In some embodiments, H₂Are preferred hydrogen-containing reactants and, in some embodiments, preferably contain at least 50%, e.g., at least 80%, H by volume₂Forming a plasma in the gas. In other embodimentsIn the scheme, HBr is used as the hydrogen-containing reactant. For example, it can be used in a process gas consisting essentially of HBr and an inert gas (e.g., in HBr, N)₂And argon) selectively etches tin oxide. Hydrogen-based etching is typically performed using a process gas that does not contain oxygen-and fluorine-containing species. In some embodiments, the treatment gas consists essentially of one or more hydrogen-containing reactants and optionally an inert gas.

The hydrogen-based etch can selectively remove tin oxide in the presence of: silicon-containing compounds, e.g. SiO₂SiN, SiC, SiOC, SiCN, SiON, SiCNO, spin-on glass; metal oxides such as titanium oxide, tungsten oxide, and zirconium oxide; metal nitrides such as titanium nitride and tantalum nitride; metals, such as tungsten; and carbon-containing organic materials (e.g., photoresists and organic polymers). In addition, a hydrogen-based etch can be used to selectively etch tin oxide in the presence of silicon covered with silicon oxide. Silicon oxide is typically formed on a silicon surface when the silicon is exposed to the atmosphere. A hydrogen-based etch may also be used to selectively etch tin oxide in the presence of elemental silicon (e.g., amorphous silicon) and carbon. In addition, hydrogen-based etching can be used to selectively etch tin oxide in the presence of metal carbides and metal and carbon containing materials. For example, tin oxide can be selectively etched with a hydrogen-based etch in the presence of a tungsten carbon material (also referred to as tungsten-doped carbon). In some embodiments, the tungsten carbon material comprises between about 20-60 atomic% tungsten.

In some embodiments, methods of removing tin oxide mandrels in the presence of any of these materials are provided. First, a semiconductor substrate is provided, wherein the semiconductor substrate includes a plurality of exposed tin oxide mandrels and a layer of any of these materials (e.g., these materials can be spacer materials present on the sidewalls of the tin oxide mandrels, or these materials can be ESL materials). Next, the tin oxide is selectively etched in the presence of these materials. For example, the tin oxide mandrels can be removed by a hydrogen-based etch without completely removing the spacer material present on the sidewalls of the tin oxide mandrels and without completely removing the ESL material. These materials may be exposed prior to the etch or may be exposed during the tin oxide etch.

In some embodiments, the etch selectivity of the hydrogen-based etch is greater than 10, such as greater than 30, such as greater than 50, or greater than 80. Etch selectivity refers to the ratio of the etch rate of tin oxide to the etch rate of other materials for a selected process condition. In some examples, H is used₂Plasma, relative to SiO₂Etching tin oxide achieves an etch selectivity of 100.

Tin oxide etching processes utilizing hydrogen plasma (referring to the plasma formed in the hydrogen-containing reactant) can be carried out in a variety of equipment under a variety of processing conditions. In one implementation, the method includes: providing a semiconductor substrate having an exposed tin oxide layer to an etch chamber, and contacting the substrate with a solution containing H₂(or another hydrogen-containing gas) and optionally a carrier gas (such as helium or other inert gas). The term "etching chamber" or "etching apparatus" refers to chambers and apparatuses configured for etching. In some embodiments, an "etching chamber" or "etching apparatus" is specifically configured for an etching operation. In other embodiments, an "etching chamber" or "etching apparatus" may be configured to perform other operations in addition to etching, such as deposition. For example, in some embodiments, an etch chamber may also be used for ALD deposition.

In some embodiments, the plasma used for hydrogen plasma etching is generated in the same processing chamber that houses the semiconductor substrate. In other embodiments, the plasma is generated remotely and introduced into the process chamber containing the substrate through one or more inlets in the process chamber.

The etching is controlled to convert the tin oxide to volatile tin hydride. In one embodiment, H in the process gas₂The content is at least 50%, for example at least 80% (up to and including 100%) by volume. In some embodiments, the process gas may further comprise a hydrocarbon, such as CH₄. In some embodiments, the process gas further comprises Cl₂. For example, the process gas may consist essentially of H₂And an inert gas (e.g., He), or the process gas may consist essentially of H₂Inert gases and hydrocarbons (e.g., CH)₄) And (4) forming. The etching is performed at a temperature of less than about 100 ℃ as measured near the substrate. Advantageously, the etching reaction produces only volatile material, e.g. SnH₄Which can be easily removed from the etch process chamber by pumping and/or purging. The etch process temperature is preferably selected to be less than about 100 deg.C, as higher temperatures may result in the formation of SnH₄Decompose and form particles that can contaminate the process chamber and the substrate. The composition of the process gas and the process conditions are selected to reduce or eliminate particle formation during etching. Notably, the etching reaction does not require any significant sputtering components and can be performed without an external bias at the substrate and in the absence of heavy ions (e.g., argon ions). Reducing the sputtering component can be beneficial in improving the etch selectivity relative to the second material on the substrate. Thus, in some embodiments, the etching is performed without providing an external bias to the substrate and/or involves using helium (light gas) as a carrier gas to reduce sputtering.

Various frequencies (low and high) may be used to generate the plasma for hydrogen plasma etching. Examples of suitable frequencies include 400KHz, 2MHz, 13.56MHz, 27MHz, or 2.45 GHz. In some embodiments, the power range for plasma generation may be in a range between about 50W to 1000W, corresponding to about 0.0018W/cm²To 0.36W/cm²Power density in between. The bias at the substrate is optional and the bias power may be in the range between about 0 and 500W.

Suitable gas rates for each showerhead (for processing a 300mm wafer) are:

i.H₂25 to 750 sccm;

ii.Cl₂0 to 500sccm (e.g., 5 to 200 sccm);

he 0 to 500sccm (e.g., 5-100 sccm); and

iv.CH₄0 to 500sccm (e.g., 5-100 sccm).

In some embodiments, the etching process may be performed at a pressure of about 1 to 175 mtorr.

In some embodiments, the plasma is generated using high frequency generation (e.g., 13.56MHz or 27MHz), and using a frequency corresponding to 0.07W/cm²And 0.18W/cm²Between about 200 and 500W of plasma power at a power density between. The bias power at the substrate is between about 0 and 200W. Suitable gas rates for each showerhead (for processing a 300mm wafer) are:

i.H₂100 to 300 sccm;

ii.Cl₂0 to 200sccm (e.g., 5 to 100 sccm);

he 0 to 100sccm (e.g., 5-50 sccm);

iv.CH₄0 to 100sccm (e.g., 5-50 sccm).

In these embodiments, the etching process is performed at a pressure between about 1 to 30 millitorr.

The selectivity of hydrogen-based etching can be significantly enhanced by using a carbon-containing reactant in the process gas that forms a carbon-containing polymer (e.g., CH) on the substrate surface during etching_xA polymer). In some embodiments, the process gas used in this embodiment comprises H₂And hydrocarbons (e.g., methane (CH)₄)). The process gas typically also comprises an inert gas. In some embodiments, H₂The ratio of specific hydrocarbons is preferably at least 5, for example at least 10. In some embodiments, H₂The specific hydrocarbon volume ratio is between about 5 and 500, for example between about 10 and 300. In some embodiments, the selective etching of tin oxide in the presence of another material (or materials) comprises exposing the substrate to a solution comprising H₂And hydrocarbons (e.g. CH)₄) Plasma is formed in the process gas of (1). In one implementation, H₂At a rate of between about 100 and 500sccm, and the hydrocarbon is provided at a rate of between about 1-20sccm (e.g., between about 5-10 sccm). The treatment may be applied to a surface of the substrate corresponding to between about 0.14 and 1.3W/cm²(e.g., 0.28-0.71W/cm)²) Power density between about 100 and 1000W (e.g., about 200 and 500W (for a single 300mm wafer)) Plasma power in between. In some embodiments, the etch is performed using a substrate bias between about 50-500Vb, such as between about 100-200 Vb. The treatment is preferably carried out at a temperature of less than about 100 ℃. In one specific example, the following gases are provided: h of 100sccm₂(ii) a CH of 5sccm₄And 100sccm of helium. A plasma was formed in the process gas using a power of 300W and a substrate bias of 100Vb at a 25% duty cycle was used. The treatment was carried out at 30 ℃ and a pressure of 5 mtorr. Forming a carbon-containing polymer on a substrate as described herein can increase the etch selectivity of tin oxide over any of the materials listed herein. This effect is particularly useful when tin oxide is etched in the presence of photoresist, carbon, carbonaceous materials and silicon (Si). For example, when etching is performed in the presence of photoresist, the etch selectivity ratio may be greater than 100, and in some cases almost infinite. The use of such a high selectivity ratio etch enables the use of smaller thicknesses of photoresist to reduce lithographic exposure dose and/or prevent photoresist line collapse due to high aspect ratios at small fine pitches. In the method, CH_xThe polymer protects the photoresist from etching. In addition, the etching may be used to improve the geometry of the photoresist layer. In some embodiments, the etch is used to selectively etch tin oxide on a semiconductor substrate in the presence of a photoresist disposed over the tin oxide layer and in the presence of a material underlying the tin oxide, wherein the etch selectivity ratio is at least 10 relative to the material underlying the photoresist and tin oxide. In some embodiments, the material underlying the tin oxide includes silicon (e.g., amorphous silicon), silicon-containing compounds (e.g., SiO)₂SiN, SiC, SiON, SiOC), carbon (e.g., amorphous carbon), and carbon-containing compounds (e.g., carbon tungsten).

In some embodiments, HBr is used as the hydrogen-containing reactant in a hydrogen-based etch. In one implementation, the etching method includes flowing HBr at a rate of 100-50sccm and flowing an inert gas (e.g., helium) at a rate of 100-500sccm using a gas flow corresponding to 0.14-1.42W/cm²A power density of 100 and 1000W (per 300mm wafer) forms a plasma in the process gas. The etch may be performed with or without a substrate bias. For example, the substrate bias voltage may be between 0-200Vb, such as between 50-200 Vb. The treatment may be carried out at a temperature below 100 c and a pressure of 5-50 mtorr.

A chlorine-based etch. In some embodiments, the selective tin oxide etch is performed using a chlorine-based etch. Chlorine-based etching involves exposing tin oxide to a chlorine-containing reactant (typically in the case of plasma activation of the reactant) such that it converts the tin oxide to tin chloride. SnCl₄Having a boiling point of 114 c, can be removed from the process chamber. Examples of suitable chlorine-containing reactants include Cl₂And BCl₃. In one embodiment, Cl is used₂And BCl₃A mixture of (a). In one implementation, the chlorine-based etch includes forming a plasma in a process gas containing a chlorine-containing reactant and optionally an inert gas, and contacting the substrate with the formed plasma. The chlorine-based etch can selectively remove tin oxide in the presence of: silicon-containing compounds (e.g. SiO)₂SiN, SiC, SiOC, SiCN, SiON, SiCNO, spin-on-glass), carbon, and photoresist, but the selectivity to silicon-containing materials is generally lower than with hydrogen-based etches. In some embodiments, a semiconductor substrate is provided, wherein the semiconductor substrate comprises an exposed tin oxide layer (e.g., tin oxide mandrels) and a layer of any of these materials (e.g., as a spacer material on the sidewalls of the mandrels or as an ESL material). Next, tin oxide is selectively etched in the presence of these materials using a chlorine-based etch. These materials may be exposed prior to the etch or may be exposed during the tin oxide etch. In one implementation, BCl is used₃/Cl₂The etching selectively etches tin oxide in the presence of any of these materials. In one implementation, the etching method includes subjecting BCl₃Flowing at a rate of 5-100sccm to make Cl₂Flowing at a rate of 50-500sccm and flowing an inert gas (e.g., helium) at a rate of 100-500sccmAnd the amount of the catalyst is 0.14-1.42W/cm²A power density of 100 and 1000W (per 300mm wafer) forms a plasma in the process gas. The etch may be performed with or without substrate bias. For example, the substrate bias voltage may be between 0-100Vb, such as between 10-100 Vb. The treatment may be carried out at a temperature below 100 c and a pressure of 5-50 mtorr.

In some embodiments, a chlorine-based etch is used to selectively etch certain metal oxides in the presence of tin oxide. For example, titanium oxide can be selectively etched in the presence of tin oxide using a chlorine-based etch. In some embodiments, a semiconductor substrate is provided, wherein the semiconductor substrate comprises an exposed layer of titanium oxide and a layer of tin oxide. Next, titanium oxide is selectively etched in the presence of tin oxide using a chlorine-based etching chemistry. The tin oxide may be exposed prior to the etching, or may be exposed during the tin oxide etching. For example, titanium oxide may be a spacer material that coats a tin oxide mandrel. A chlorine-based etch can be used to remove the titanium dioxide spacer material from the horizontal surfaces without completely removing the titanium dioxide on the sidewalls of the tin oxide mandrels.

Fluorocarbon based etching. In some embodiments, a fluorocarbon-based etch is used to selectively etch silicon-containing compounds, such as SiO, in the presence of tin oxide₂SiN, SiC, SiOC, SiCN, SiON, SiCNO, spin-on-glass. The fluorocarbon-based etch comprises exposing a silicon-containing compound to a plasma-activated fluorocarbon (C)_xF_y) So that they are converted into volatile compounds containing Si-F bonds. Examples of suitable fluorocarbon reactants include CF₄、C₂F₆And the like. In one implementation, a fluorocarbon-based etch involves forming a plasma in a process gas containing a fluorocarbon and optionally an inert gas, and contacting the substrate with the formed plasma. The fluorocarbon etch can selectively remove the silicon-containing compound in the presence of tin oxide. In some embodiments, a semiconductor substrate is provided, wherein the semiconductor substrate comprises a silicon-containing compound (e.g., silicon-containing compound)Such as a silicon-containing spacer material or ESL material) and a tin oxide layer (e.g., a tin oxide mandrel). Next, the substrate is contacted with a fluorocarbon plasma and the silicon-containing compound is selectively etched in the presence of tin oxide. In one embodiment, the substrate comprises a tin oxide mandrel coated with a silicon-containing spacer material (e.g., silicon oxide) on both horizontal surfaces and sidewalls of the mandrel. The silicon-containing spacer material is selectively etched and removed from the horizontal surfaces by a fluorocarbon-based etch chemistry such that the silicon-based spacer material remains at the sidewalls of the mandrels. The tin oxide may be exposed prior to the etching, or may be exposed during the etching. The fluorocarbon based etch is a fluorine based etch.

A fluorine-based etch. In some embodiments, fluorine-based etching is used to selectively etch elemental silicon and silicon-containing compounds, such as SiO, in the presence of tin oxide₂SiN, SiC, SiOC, SiCN, SiON, SiCNO and spin-on glasses. Fluorine-based etching includes exposing a silicon-containing material to a fluorine-containing agent (e.g., NF)₃、SF₆Or fluorocarbon) that is plasma activated in some embodiments and converts silicon-containing materials to volatile silicon fluorides. However, tin oxide does not form volatile fluorides and is therefore not substantially etched by such chemicals. In addition to silicon-containing materials, fluorine-based etches may be used to selectively etch titanium oxide, tungsten, and tungsten carbon in the presence of tin oxide. In one implementation, the fluorine-based etch involves the presence of a fluorine-containing reactant (e.g., NF)₃) And optionally an inert gas, and contacting the substrate with the formed plasma. The fluorine-based etch can selectively remove the silicon-containing compound and elemental silicon in the presence of tin oxide. In some embodiments, a semiconductor substrate is provided, wherein the semiconductor substrate comprises an exposed layer of a silicon-containing compound and/or an elemental silicon (Si) layer (e.g., as a spacer material on the sidewalls of the mandrels or as an ESL material) and a tin oxide layer (e.g., as a mandrel material). Next, the substrate is contacted with a fluorine-containing reactant in the plasma and in the presence of tin oxideThe silicon-containing compound and/or Si is selectively etched. The tin oxide may be exposed prior to the etching, or may be exposed during the etching.

In one implementation, silicon (Si) is selectively etched in the presence of tin oxide using a fluorine-based etch. In one implementation, the etching method includes subjecting the NF to₃Flowing at a rate of 5-100sccm to make Cl₂Flowing at a rate of 50-500sccm and flowing an inert gas (e.g., nitrogen and/or helium) at a rate of 100-500sccm and using a flow rate corresponding to 0.14-1.4W/cm²A power density of 100 and 1000W (per 300mm wafer) forms a plasma in the process gas. The etch may be performed with or without substrate bias. For example, the substrate bias voltage may be between 0-100Vb, such as between 10-100 Vb. The treatment may be carried out at a temperature below 100 c and a pressure of 10-300 mtorr.

In some embodiments, a semiconductor substrate is provided, wherein the semiconductor substrate comprises an exposed layer of titanium oxide, tungsten and/or tungsten carbon (e.g., as a spacer material layer) and a layer of tin oxide (e.g., as a mandrel material). Next, the substrate is contacted with a fluorine-containing reactant in a plasma and the titanium oxide, tungsten and/or tungsten carbon are selectively etched in the presence of tin oxide. The tin oxide may be exposed prior to the etching, or may be exposed during the etching.

In one implementation, titanium oxide is selectively etched in the presence of tin oxide using a fluorine-based etch. In one implementation, the etching method includes causing the CF to₄Flowing at a rate of 5-500sccm to effect CHF₃Flowing at a rate of 0-500sccm (e.g., 10-500sccm) and flowing an inert gas (e.g., argon) at a rate of 100-500sccm, and using a flow rate corresponding to 0.71-1.4W/cm²A power density of 500-. The etch may be performed with or without substrate bias. For example, the substrate bias can be between 0-300Vb, such as between 10-300 Vb. The treatment may be carried out at a temperature below 100 c and a pressure of 5-50 mtorr.

In one implementation, the method comprisesThe tungsten carbon is selectively etched with a fluorine-based etch in the presence of tin oxide. In one implementation, the etching method includes subjecting the NF to₃Flowing at a rate of 5-100sccm to make Cl₂Flowing at a rate of 5-500sccm and flowing an inert gas (e.g., argon and/or nitrogen) at a rate of 100-500sccm and using a flow rate corresponding to 0.14-1.4W/cm²A power density of 100 and 1000W (per 300mm wafer) forms a plasma in the process gas. The etch may be performed with or without substrate bias. For example, the substrate bias can be between 0-100Vb, such as between 10-100 Vb. The treatment may be carried out at a temperature below 100 c and a pressure of 10-100 mtorr.

An oxygen-based etch. In some embodiments, one or more materials selected from the group consisting of elemental carbon, carbon-containing compounds, polymers, and photoresists are selectively etched in the presence of tin oxide using an oxygen-based etch. The oxygen-based etch comprises exposing any of the materials listed above to an oxygen-containing reagent (e.g., O)₂、O₃、SO₂Or CO₂) The oxygen-containing reagent is, in some embodiments, plasma-activated and converts the material to volatile products containing carbon-oxygen bonds (e.g., CO or CO)₂). In one implementation, the oxygen-based etch is included in a process that includes an oxygen-containing reactant (e.g., O)₂) And optionally an inert gas, and contacting the substrate with the formed plasma. In other embodiments, the etching may be performed in the absence of plasma. The oxygen-based etch can selectively remove carbon (e.g., amorphous or diamond-like carbon), carbon-containing compounds, and photoresist in the presence of tin oxide. In some embodiments, a semiconductor substrate is provided, wherein the semiconductor substrate comprises one or more materials selected from the group consisting of carbon, carbon-containing compounds, and photoresists, an exposed layer (e.g., as a spacer material) and a tin oxide layer (e.g., as a mandrel material). Next, the substrate is contacted with an oxygen-containing reactant (optionally activated in a plasma) to convert the carbonaceous material to volatile CO or CO₂Thereby selectively etching them in the presence of tin oxide. The tin oxide may be exposed prior to the etching, or may be exposed during the etching. For example, an oxygen-based etch may be used to remove spacer material (e.g., carbon-containing material such as photoresist) from horizontal surfaces, such that the spacer material present on the tin oxide mandrel sidewalls is not completely removed, and such that the tin oxide is exposed by the etch.

And depositing the material. The materials mentioned herein may be deposited using various deposition methods, for example, using CVD (which includes PECVD), ALD (which includes PEALD), PVD (e.g., for depositing metals and metal oxides), spin-on methods (e.g., for depositing carbon and some dielectrics). ALD processes are generally preferred when conformal deposition is desired.

SiO can be deposited using various methods (e.g., CVD, PECVD, and ALD)₂SiC, SiN, SiOC, SiNO, SiCNO, and SiCN materials. Deposition may include a reaction between a silicon-containing precursor and a reactant (e.g., an oxygen-containing reactant, a nitrogen-containing reactant, or a carbon-containing reactant). Various silicon-containing precursors may be used to deposit these materials, including silanes, tetraalkylsilanes, trialkylsilanes, Tetraethylorthosilicate (TEOS), and the like. For example, SiO can be deposited using TEOS or silane as the silicon-containing precursor₂。

By using, for example, hydrocarbon precursors (e.g. CH)₄) Carbon is deposited by CVD or PECVD methods. In other implementations, the carbon may be deposited by a spin-on process or by PVD. Photoresists and organic polymers may be deposited, for example, by spin-on methods.

The tin oxide layer is deposited by any suitable method, such as by CVD (including PECVD), ALD (including PEALD), sputtering, and the like. In some embodiments, it is preferred to conformally deposit SnO₂The film such that it follows the surface of the (follow) substrate, including the surface following any raised and recessed features on the substrate. Conformal SnO₂One suitable deposition method for films is ALD. Thermal or plasma enhanced ALD may be used. In a typical thermal ALD process, a substrate is provided to an ALD process chamber and sequentially exposed to a tin-containing precursor and an oxygen-containing reactant, wherein the tin-containing precursor and the oxygen-containing reactant are reactedThe oxygen-containing reactant reacts on the substrate surface to form SnO₂. After the substrate is exposed to the tin-containing precursor, and prior to passing the oxygen-containing reactant into the process chamber, the ALD process chamber is typically purged with an inert gas to prevent reaction in the bulk (bulk) of the process chamber. In addition, after processing a substrate with an oxygen-containing reactant, the ALD process chamber is typically purged with an inert gas. The successive exposures are repeated for several cycles, for example, between about 10-100 cycles may be performed until a tin oxide layer having a desired thickness is deposited. Examples of suitable tin-containing precursors include tin halide-containing precursors (e.g., SnCl)₄And SnBr₄) And non-halide-containing tin precursors such as organotin compounds, including alkyl-substituted tin amides, and the like. Specific examples of alkyl substituted tin amides suitable for ALD are tetrakis (dimethylamino) tin, tetrakis (ethylmethylamino) tin, N²,N³Di-tert-butyl-butane-2, 3-diamino-tin (II) and (1,3-bis (1,1-dimethylethyl) -4,5-dimethyl- (4R,5R) -1,3, 2-diazazinylalk-2-ylidene ((1,3-bis (1, 1-dimethylethenyl) -4,5-dimethyl- (4R,5R) -1,3, 2-diazananolidin-2-ylidine). oxygen-containing reactants including but not limited to oxygen, ozone, water, hydroperoxide and NO. mixtures of oxygen-containing reactants may also be used the deposition conditions will vary depending on the choice of ALD reactant, with the more reactive precursors typically reacting at lower temperatures than the less reactive precursors. At a pressure below atmospheric pressure. The temperature and pressure are selected so that the reactants remain gaseous in the process chamber to avoid condensation. Each reactant is supplied to the process chamber in gaseous form, either alone or in admixture with a carrier gas (e.g., argon, helium, or nitrogen). The rate of these mixtures will depend on the size of the process chamber and in some embodiments is between about 10-10000 sccm.

In one example, ALD processing includes sequentially and alternately exposing a substrate in an ALD vacuum chamber to SnCl at a temperature of 200-₄(tin-containing precursor) and deionized water (oxygen-containing reactant). In a specific example of an ALD cycle, SnCl is applied₄Steam and N₂A mixture of carrier gases is introduced into the ALD chamber for 0.5 seconds, howeverAnd then exposed to the substrate for 3 seconds. Then, use N₂Purging an ALD process chamber for 10 seconds to remove SnCl from a body of the process chamber₄And is H₂O vapor and N₂The mixture of carrier gases was flowed into the process chamber for 1 second and exposed to the substrate for 3 seconds. Then, use N₂The ALD process chamber is purged and the cycle is repeated. ALD processing is conducted at sub-atmospheric pressures (e.g., 0.4 torr) and temperatures of 200 ℃.

While the use of tin halide precursors in ALD is suitable in many embodiments, in some embodiments, it is more preferred to use non-halogenated organotin precursors to avoid the use of halogenated precursors such as SnCl₄Corrosion problems may occur. Examples of suitable non-halogenated organotin precursors include alkylaminotin (alkylated tin amide) precursors such as tetrakis (dimethylamino) tin. In one example of an ALD process, a substrate is sequentially exposed to tetrakis (dimethylamino) tin and H in an ALD chamber₂O₂And a temperature of between about 50 ℃ and about 300 ℃. Advantageously, the use of the precursor enables deposition of SnO at low temperatures of 100 ℃ or less₂And (3) a membrane. For example, SnO can be deposited at 50 deg.C₂The film does not use plasma to increase the reaction rate.

In some embodiments, SnO is deposited by PEALD₂And (3) a membrane. The same tin-containing precursor and oxygen-containing reactant types described above for thermal ALD may be used. In PEALD, an ALD apparatus is equipped with a system for generating plasma in a process chamber and for processing a substrate with the plasma. In a typical PEALD processing sequence, a substrate is provided to a PEALD processing chamber and exposed to a tin-containing precursor adsorbed on the surface of the substrate. The process chamber is purged with an inert gas (e.g., argon or helium) to remove the precursor from the process chamber and expose the substrate to an oxygen-containing reactant introduced into the process chamber. A plasma is formed in the process chamber simultaneously with or after the introduction of the oxygen-containing reactant. The plasma promotes a reaction between the tin-containing precursor and an oxygen-containing reactant on the surface of the substrate, resulting in the formation of tin oxide. Next, the process chamber is purged with an inert gas, and the process includes dosing a tin precursor, purging, dosing an oxygen-containing reactant, and plasmaThe cycle of the daughter treatment and the second cleaning is repeated as many times as necessary to form the tin oxide film of the desired thickness.

Tin oxide as mandrel

In the provided implementations, a tin oxide layer is used as the mandrel. The use of tin oxide mandrels is described with reference to fig. 1A-1F, which provide schematic cross-sectional views of a semiconductor substrate at various stages of processing. Figure 2 provides a process flow diagram of embodiments of these methods.

Referring to fig. 2, the process begins at 201 by providing a substrate having a plurality of tin oxide protruding features. An illustrative substrate is shown in fig. 1A, which shows two tin oxide mandrels 101 present on an Etch Stop Layer (ESL) 103. In some embodiments, the distance d1 between adjacent mandrels is between about 10-100 nm. In some embodiments, relatively large distances of about 40-100nm are used. In other applications, the distance between the nearest mandrels is between about 10-30 nm. In some embodiments, the distance d2 (also referred to as the pitch) between the centers of the nearest mandrels is between about 30-130 nm. In some embodiments, the pitch is between about 80-130 nm. In other embodiments, the pitch is between about 30-40 nm. The height d3 of the mandrels is typically between about 20-200nm, for example between about 50-100 nm.

The materials of the mandrels and the ESLs are preferably selected to enable subsequent selective etching of the tin oxide mandrel material in the presence of the exposed spacer material, and selective etching of the ESL material in the presence of the exposed spacer material. Thus, for ESL etch chemistries, the ratio of the etch rate of the ESL material to the etch rate of the spacer material is greater than 1, more preferably greater than about 1.5, such as greater than about 2. Similarly, for mandrel pull chemistry, the ratio of the etch rate of the tin oxide mandrel material to the etch rate of the spacer material is greater than 1, more preferably greater than about 1.5, such as greater than about 2.

In some embodiments, the ESL material is a silicon-containing compound (e.g., SiO)₂) Or a metal oxide (e.g., titanium oxide, zirconium oxide, or tungsten oxide). The mandrel material is tin oxideAnd the spacer material may comprise a silicon-containing compound (e.g., SiO)₂SiN or SiC), carbon-containing compounds (e.g., amorphous carbon, diamond-like carbon or photoresist), amorphous silicon (doped or undoped), or metal oxides (TaO, TiO, WO, ZrO, HfO). The ESL material, mandrel material and spacer material are selected to be all different. In some embodiments, the outer material of the mandrel may be different from the mandrel core. The ESL layer and mandrel may be formed by one or more of Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), ALD (plasma-free or by PEALD), or Plasma Enhanced Chemical Vapor Deposition (PECVD), and the pattern of the mandrel may be defined using photolithography techniques or the SAQP type method described herein.

The material for the spacers is preferably selected such that it can be etched selectively to tin oxide using a spacer etch chemistry and the tin oxide mandrels can be etched selectively to the spacer material using a mandrel pull chemistry. In some embodiments, the ESL material is selected such that the ESL can be selectively etched relative to the spacer material using an ESL etch chemistry.

In some embodiments, the spacer material used in conjunction with the tin oxide mandrels includes, but is not limited to, silicon oxide, silicon nitride, or titanium oxide. Other suitable spacer materials that may be used in this embodiment include SiC, SiOC, SiNO, SiCNO, and SiCN. Examples of suitable ESL and spacer material pairs that may be used in conjunction with tin oxide mandrels include: (i) titanium oxide spacers and silicon oxide ESL; (ii) silicon oxide spacers and tungsten ESL; (iii) silicon oxide spacers and silicon carbide ESL.

Referring again to the substrate shown in fig. 1A, the ESL layer 103 is located on and in contact with the target layer 105. The target layer 105 is a layer that needs to be patterned. The target layer 105 may be a semiconductor layer, a dielectric layer, or other layer, and may be made of, for example, silicon (Si), silicon oxide (SiO)₂) Silicon nitride (SiN) or titanium nitride (TiN). In some embodiments, the target layer refers to a hard mask layer and comprises a metal nitride, such as titanium nitride. Target layer 105 may be deposited by ALD (plasma-free or by PEALD), CVD, or other suitable deposition techniqueAnd (4) accumulating. The target layer 105 is located on and in contact with the layer 107, the layer 107 being a BEOL layer in some embodiments, which includes a plurality of metal lines embedded in a layer of dielectric material.

Referring again to fig. 2, the process continues at 203 where a layer of spacer material is deposited on both the horizontal surfaces and sidewalls of the protruding features at 203. Referring to the structure shown in fig. 1B, a layer of spacer material 109 is deposited on the ESL103 and on the tin oxide mandrel 101, including on the sidewalls of the mandrel 101. The spacer material layer is deposited by any suitable method, such as by CVD (including PECVD), ALD (including PEALD), sputtering, and the like.

In some embodiments, the film of spacer material is preferably conformally deposited such that it follows the surface of the ESL103 and the tin oxide mandrels 101, as shown in fig. 1B. A conformal film as used herein generally follows the contours of a substrate. In some embodiments, the thickness of the conformal film is about the same across all (horizontal and vertical) surfaces (with less than 50% fluctuation). In some embodiments, the thickness variation in the deposited conformal film is less than 15%. In other embodiments, the thickness of the conformal film may be significantly greater on horizontal surfaces than on sidewalls. In some embodiments, the spacer material layer is conformally deposited to a thickness of between about 5-30nm, for example, between about 10-20 nm. Typically, the spacer material layer 109 is deposited by any suitable method, such as by CVD (including PECVD), ALD (including PEALD), sputtering, and the like. For example, the spacer material may be any of a PECVD deposited or ALD deposited silicon oxide layer, silicon nitride layer, or titanium oxide layer. In one embodiment, the spacer material is ALD deposited titanium oxide and the ESL is silicon oxide or another silicon containing material. Other examples of spacer materials that can be deposited by PECVD or ALD include SiC, SiOC, SiNO, SiCNO, and SiCN.

Referring to the process diagram of fig. 2, after the layer of spacer material has been deposited, the process continues at 205 with removing the spacer material from horizontal surfaces without completely removing the spacer material at the sidewalls of the tin oxide protrusion features at 205. This step is performed using a spacer etch chemistry. As shown in fig. 1C, the spacers are removed from the horizontal surfaceThe material such that the tin oxide mandrel 101 material and the ESL103 are exposed, while the spacer material 109 at the sidewalls of the mandrel 101 is not completely removed. The spacer etch chemistry is preferably selective to both the tin oxide mandrels and the ESL material. When the spacers are silicon-based, e.g. SiO₂SiN or any of SiC, SiOC, SiNO, SiCNO, and SiCN, fluorine-based etching may be used. For example, a plasma fluorocarbon etch chemistry may be used to selectively etch silicon-containing spacers relative to tin oxide mandrels. The chemistry can be tailored to the type of ESL used. When the spacer is titanium oxide, it can be selectively etched using a chlorine-based chemistry relative to both the tin oxide mandrels and the silicon oxide ESLs. Chlorine-based etch chemistries involve exposing a substrate to a (typically plasma-activated) Cl-containing reactant, such as plasma-activated Cl₂、BCl₃And the like. When the spacers are silicon-based (e.g. SiO)₂SiN or any of SiC, SiOC, SiNO, SiCNO, and SiCN) and ESL is tungsten, a fluorine (fluorine) based etch chemistry (e.g., SF activated by plasma) may be used₆/O₂Mixture) etches the spacers selectively to both tin oxide and tungsten.

Fig. 1C shows the removal of the spacer from the horizontal surface. The spacer layer 109 is etched away from horizontal surfaces above the ESL103 and above the mandrels 101 without being completely etched away from locations that adhere to the sidewalls of the tin oxide mandrels 101. This etch exposes layer 103 anywhere except near the sidewalls of tin oxide mandrels 101. In addition, the etching exposes the top of the tin oxide mandrels 101. The resulting structure is shown in FIG. 1C. Preferably, at least 50%, such as at least 80% or at least 90%, of the initial height of the tin oxide layer at the sidewalls remains after this etching.

Referring to the process shown in fig. 2, after the spacer material is removed from the horizontal surfaces in 205, the tin oxide protruding features are removed without completely removing the spacer material that had previously existed on the sidewalls of the protruding features (mandrels) in a next operation 207, thereby forming a plurality of spacers. The resulting structure is shown in FIG. 1D, which showsA plurality of spacers 109 are present on the ESL103 after removal of the tin oxide mandrels 101. Removal of the mandrels is performed by exposing the substrate to an etch chemistry that selectively etches the mandrel material (mandrel pull chemistry). Thus, in this step, the ratio of the etch rate of the tin oxide mandrel material to the etch rate of the spacer material is greater than 1, and more preferably greater than 1.5. Furthermore, in some embodiments, the etch chemistry used in this step should etch the tin oxide mandrel material selectively to the ESL material. A variety of etching methods may be used and the specific choice of chemistry depends on the material of the spacer and the material of the ESL layer. Next, the tin oxide mandrels 101 are removed using a mandrel pull chemistry. In some embodiments, a hydrogen-based etch is used to remove the tin oxide mandrels. For example, in some embodiments, the substrate is exposed to a plasma-activated hydrogen-containing gas (e.g., comprising H)₂、HBr、NH₃Hydrocarbon, H₂O or a combination thereof) to form volatile tin hydride, which is readily removed from the process chamber. Hydrogen-based etch for various spacer materials (including SiO)₂SiN or SiC, SiOC, SiNO, SiCNO, SiCN and TiO₂Any of the above) and the metal (e.g., W) or metal-containing dielectric (including WO) of the ESL layer₂TiN, TaN, ZrO, HfO) has selectivity. In alternative embodiments, other types of tin oxide etching chemistries provided herein may be used.

Referring to fig. 2, after the spacers have been formed, the ESL material is etched in the presence of the spacers in operation 209, forming a patterned ESL. This step is performed using an ESL etch chemistry. The resulting structure is shown in fig. 1E, where the exposed ESL103 is shown being etched to expose the underlying target layer 105 in all locations not protected by the spacers 109. In some embodiments, the ESL etch chemistry used in this step selectively etches the ESL material in the presence of the spacer material. In other words, in some embodiments, the ratio of the etch rate of the ESL material to the etch rate of the spacer material is greater than 1, and more preferably greater than 1.5, for the ESL etch chemistry. When roomThe barrier material being TiO₂And the ESL material is a silicon-based material (e.g., SiO)₂SiN or any of SiC, SiOC, SiNO, SiCNO, and SiCN), a fluorine-based etch (e.g., a fluorocarbon plasma etch chemistry) may be in the presence of TiO₂The ESL layer is selectively etched.

After the pattern defined by the spacers is transferred to the ESL, the target layer 105 is etched in all locations not protected by the ESL film 103 to expose the underlying layer 107. The spacers 109 may also be removed in this etching step, thereby providing the patterned structure shown in fig. 1F. In some embodiments, the etch chemistry used in this step is selected to remove the target material and the spacer material. In other embodiments, two different etching steps with different chemistries may be used to pattern the target layer 105 and remove the spacers 109, respectively. A variety of etch chemistries may be used depending on the chemistry of the target layer. In an implementation, the target layer 105 is a metal nitride layer (e.g., TiN) layer. For example, a chlorine-based etch chemistry may be used to etch a titanium nitride target layer material. If the spacer material is TiO₂The spacers may then be removed by a chlorine-based etch simultaneously with the target layer etch.

Forming a tin oxide mandrel. Several different methods can be used to form the substrate with the tin oxide mandrels. In some embodiments, the tin oxide mandrels are formed by patterning a tin oxide capping layer. This is illustrated by the process flow diagram shown in fig. 3. The process begins in operation 301 by providing a substrate having a tin oxide coating. For example, tin oxide can be deposited on a substrate having a flat exposed ESL to form a flat tin oxide layer over the ESL. Next, in operation 303, a patterned layer is formed over the tin oxide layer. For example, a photoresist cap layer may be deposited on (but not necessarily in direct contact with) tin oxide and may be patterned using photolithographic techniques. In some embodiments, one or more intermediate capping layers are deposited between the tin oxide layer and the photoresist layer. Next, in operation 305, the tin oxide is etched and the pattern is transferred to the tin oxide layer such that a plurality of tin oxide protrusions are formed on the substrate. If intermediate layers are present between the tin oxide layer and the photoresist, the pattern is first transferred to these intermediate layers. In some embodiments, the tin oxide is etched by a hydrogen-based etch chemistry in the presence of a patterned layer of mask material (such as photoresist, carbon, another carbon-containing material, and/or a silicon-containing material).

An exemplary method of forming a substrate with patterned tin oxide mandrels is shown in fig. 4A-4E, which depict schematic cross-sectional views of a semiconductor substrate during processing. Patterning begins by providing a structure comprising a patterned photoresist layer 401 formed on a blanket layer stack, wherein the stack comprises, from top to bottom: a spin-on glass layer 403 (or another silicon-containing material such as a silicon oxide-based material deposited by low temperature CVD or a SiON layer), a spin-on carbon layer or PECVD deposited amorphous carbon layer 405, a tin oxide layer 407 (deposited by ALD, PECVD, or sputtering, for example), an ESL (409, for example), and a target layer 411 (titanium nitride, for example). First, a spin-on-glass layer (or another silicon-containing material) is etched, for example, by a fluorine-based etch (e.g., a fluorocarbon-based etch chemistry). This etch transfers the pattern of photoresist onto spin-on-glass layer 403. The resulting structure is shown in fig. 4B. Next, after exposing the carbon layer 405, using, for example, an oxygen-based chemistry (e.g., O activated in a plasma)₂、O₃、NO、SO₂、COS、CO、CO₂) The carbon is etched and the pattern is transferred to the carbon. This step may simultaneously remove (part or all) of the photoresist 401. Fig. 4C shows the resulting structure with patterned layers 401, 403 and 405, the patterned layers 401, 403 and 405 having the photoresist 401 partially removed. Next, the blanket tin oxide layer 407 is etched using any suitable tin oxide etch chemistry disclosed herein (e.g., using a hydrogen-based chemistry) and the pattern is transferred to the tin oxide as shown in the structure of fig. 4D. Finally, the carbon layer 405 is ashed and removed using, for example, an oxygen-based chemistry, to provide a structure having patterned tin oxide mandrels as shown in FIG. 4E.

Fig. 5A-5C illustrate an alternative process flow that is similar to the process shown in fig. 4A-4E, but does not include the carbon hard mask 405, as shown in fig. 5A. In this process flow, as shown in fig. 5B, the pattern of photoresist 401 is transferred to spin-on-glass layer 403. Next, the tin oxide layer 407 is etched and the pattern is transferred directly from layer 403 to tin oxide layer 407. A hydrogen-based etch chemistry (e.g., using H) may be used₂And/or HBr) to etch and convert tin oxide to tin hydride, and may also be a chlorine-based chemistry (e.g., using Cl)₂And/or BCl₃). The resulting structure is shown in fig. 5C.

A photolithographic method for patterning a capping layer with a photoresist includes: applying a photoresist to the substrate (over the capping layer to be patterned); exposing the photoresist to light; patterning the photoresist and transferring the pattern to the substrate; and selectively removing the photoresist from the substrate.

In another embodiment, the tin oxide mandrels are formed by a SAQP process, wherein the tin oxide spacers are first formed and then used as mandrels. This process is illustrated by the process flow diagram shown in fig. 6. The process begins at 601 by forming a first mandrel on a semiconductor substrate. In one embodiment, the process begins by providing a substrate having a plurality of raised features formed over an etch stop layer material. The raised features are the first mandrels used during patterning and may comprise any mandrel material that can be selectively etched with respect to tin oxide (e.g., photoresist, carbon-containing materials, silicon-containing materials (e.g., silicon and/or silicon-containing compounds), etc.). The first mandrel material is selected to be different from the etch stop layer material. In some embodiments, the first mandrel is a photoresist mandrel. When the first mandrels are photoresist mandrels, the process can be performed with fewer steps than other mandrel materials that typically need to be patterned using additional photolithography steps.

In some embodiments, the first mandrel is a photoresist and the ESL is a silicon-containing compound, such as silicon oxide, silicon carbide, silicon nitride, and the like. Next, in operation 603, a layer of tin oxide is conformally deposited on the first mandrel. A conformally deposited tin oxide layer covers both the horizontal surfaces of the first mandrel and the sidewalls of the first mandrel and the exposed ESL.

In some embodiments, after the tin oxide layer has been conformally deposited and before the tin oxide is removed from horizontal surfaces, a passivation process is used to protect the tin oxide present on the mandrel sidewalls. Passivation is performed during a subsequent etching step to remove tin oxide from horizontal surfaces to prevent etching of tin oxide present on the sidewalls of the mandrels. In some embodiments, a passivation layer is formed over the tin oxide layer at the sidewalls of the first mandrel by first depositing a passivation material on both horizontal surfaces and sidewalls of the tin oxide coated first mandrel, and then removing the passivation material from the horizontal surfaces. For example, a silicon-containing passivation material may be deposited on both horizontal surfaces and sidewalls of the tin oxide coated first mandrel, and then removed from the horizontal surfaces using a fluorine-based (e.g., fluorocarbon-based) etch chemistry. This will result in a structure in which the tin oxide on the sidewalls is protected by a layer of passivation material containing silicon prior to the tin oxide etch. In another example of passivation, forming a passivation layer over the tin oxide layer at the sidewalls of the protruding features includes depositing a carbon-containing passivation material over the horizontal surfaces of the first mandrel and the tin oxide at the sidewalls, and then removing the carbon-containing passivation material from the horizontal surfaces. In yet another embodiment of the passivation method, forming the passivation layer over the tin oxide layer at the sidewalls of the first mandrels comprises converting the outer portions of the tin oxide layer into a tin-containing passivation material, e.g., SnN, SnBr, SnF. In one example, the outer portion of the tin oxide layer is converted to tin nitride by contacting the substrate with the exposed tin oxide layer with a nitrogen-containing reactant in a plasma.

Next, at 605, the process proceeds by: the tin oxide layer is etched from the horizontal surfaces, and the first mandrels are subsequently removed to form a plurality of tin oxide protrusion features (first spacers or second mandrels). Tin oxide can be removed from horizontal surfaces by any of the selective tin oxide etch chemistries described herein (e.g., by a hydrogen-based etch). The tin oxide is removed from the horizontal surface without completely removing the tin oxide on the sidewalls.

Next, the first mandrel is removed without completely removing the tin oxide present on the sidewalls of the first mandrel, leaving a plurality of raised tin oxide features (first spacers) present on the ESL material layer. For example, the photoresist first mandrels may be removed by an oxygen-based etch chemistry, and the silicon-containing mandrels may be removed by a fluorine-based chemistry. The provided method can be used to form tin oxide first spacers (which serve as second mandrels) having a desired geometry (e.g., square, minimal or no footing, and uniform pitch).

These raised tin oxide features are then used as a second mandrel for subsequent patterning (in the order shown in fig. 1A-1F). Specifically, the process continues by: a second spacer material is conformally deposited on the substrate such that the second spacer material covers the tin oxide second mandrels on both the sidewalls and the horizontal surfaces. The second spacer material is selected such that it can be selectively etched with respect to the tin oxide mandrels. In some embodiments, the second spacer material is a silicon-containing compound, such as silicon oxide. Preferably, the second spacer material is different from the ESL material; the second spacer material is preferably deposited by a conformal deposition method (such as ALD); after the second spacer material is deposited, it is removed from the horizontal plane without being completely removed from locations near the sidewalls of the tin oxide mandrels. The etching may be performed by any etching method that can selectively etch with respect to tin oxide. For example, if the second spacer material is a silicon-containing compound such as silicon oxide, a fluorine-based (e.g., fluorocarbon-based) plasma etch may be used. Next, the tin oxide second mandrel is removed without completely removing the second spacer material present on the sidewalls of the second mandrel. The etching may be performed by any etching method that selectively etches tin oxide. In some embodiments, a hydrogen-based etch is used to selectively remove the tin oxide second mandrels in the presence of a second spacer material (e.g., silicon oxide). After removing the tin oxide mandrels, the substrate includes a plurality of spacers on the etch stop layer. The number of spacers at this stage is four times the number of first mandrels (quadruple pattern). Subsequent processing may include selectively etching and removing the exposed etch stop layer in the presence of the spacers, then selectively etching one or more target materials, and removing the spacers.

One implementation of a processing sequence is shown by the schematic cross-sectional views of the processed substrate shown in fig. 7A-7G, in which a tin oxide spacer is used as the second mandrel in a sapp (self-aligned quad pattern) type implementation. The isometric views are shown in fig. 8A-8F. Fig. 7A shows a semiconductor substrate with a raised feature (first mandrel) 701 present on an etch stop layer 703. A plurality of layers 705 and 707 underlie the etch stop layer. These underlying layers may include a target layer (which needs to be patterned) and/or one or more hard masks. In the depicted embodiment, the first mandrel 701 is made of photoresist and the ESL703 is a silicon-containing compound layer, such as a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon oxynitride layer, or the like. A conformal tin oxide layer is deposited on the substrate to provide the structure shown in figure 7B. In this embodiment, a tin oxide layer 709 is deposited directly on the photoresist mandrels 701 and the ESL 705 such that it covers the horizontal surfaces of the substrate and the surfaces of the sidewalls of the photoresist mandrels 701. A corresponding isometric view is shown in fig. 8A. Next, the tin oxide was removed from the horizontal surfaces without completely removing the tin oxide from the areas near the mandrel sidewalls, providing the structure shown in fig. 7C. An isometric view of such a structure is shown in fig. 8B. The tin oxide can be removed selectively with respect to the photoresist using any of the methods described herein. For example, tin oxide can be etched from horizontal surfaces using a method that includes performing a hydrogen-based etch during at least a portion of the etch. Passivation may be used to provide an optimal geometry for the tin oxide spacers. This step exposes the photoresist material. Next, the photoresist is selectively removed without completely removing the tin oxide present on the sidewalls of the photoresist mandrels. In some embodiments, the photoresist mandrel pull is performed by ashing (e.g., using an oxygen-based chemistry). The removal of the photoresist mandrels is performed using a chemistry that is selective with respect to tin oxide and ESL materials, and oxygen-based ashing is a suitable selective process for removing the photoresist. The resulting structure is shown in fig. 7D, where tin oxide protrusion features 709 (which may be referred to as first spacers and second mandrels) are located on the ESL703 and are spaced apart from each other by a defined distance determined by the dimensions of the first photoresist mandrels. The number of these raised features is twice the number of the first mandrels. A corresponding isometric view is shown in fig. 8C.

After the tin oxide protrusion features are formed, they are used as a second mandrel for subsequent patterning. The process includes conformally depositing a second spacer material on the surface of the substrate. In the illustrated embodiment, the second spacer material is a silicon-containing compound that is different from the ESL material. For example, in some implementations, the second spacer is silicon oxide and the ESL material is a different material (e.g., silicon carbide). The structure obtained after deposition of the second spacer material is shown in fig. 7E, where a second layer of spacer material 711 (silicon oxide in the illustrated embodiment) covers the horizontal surfaces of the tin oxide mandrels 709, the sidewalls of the tin oxide mandrels, and the ESLs 703. In some embodiments, the silicon oxide second spacer layer is deposited by a conformal deposition method, such as ALD. The corresponding equidistant configuration is shown in fig. 8D.

Next, the second spacer material is removed from the horizontal surfaces without completely removing from the sidewall regions of the tin oxide mandrels. The etch is preferably selective with respect to tin oxide. In the depicted implementation, silicon oxide can be selectively etched relative to tin oxide using a fluorine-based (e.g., fluorocarbon-based) etch chemistry. The resulting structure after etching is shown in fig. 7F, where the tin oxide material of the second mandrel 709 is exposed. A corresponding isometric view is shown in fig. 8E. Next, the second mandrels 709 are removed without completely removing the material of the second spacers present at the sidewalls of the second mandrels. The second mandrel pull may be performed using any of the selective tin oxide etch chemistries described herein. In one implementation, the tin oxide second mandrels are removed selectively with respect to the second spacer (e.g., silicon oxide) material using a hydrogen-based etch chemistry. After removing the tin oxide second mandrel, the substrate includes a plurality of second spacers on the ESL layer. The number of the second spacers is twice the number of the second tin oxide mandrels and four times the number of the first photoresist mandrels. Fig. 7G shows a spacer 711 on the ESL 703. Fig. 8F shows a corresponding isometric view. The process may further continue by: similar to any spacer or hard mask processing sequence provided herein (e.g., described with reference to fig. 1D-1F), the underlying layers 703 and 705 are etched at locations not protected by spacers. The second spacers are then removed after or during patterning of the underlying layer.

The illustrated sequence may provide the following processing benefits. First, if SiO is used₂With in-situ sidewall passivation, the tin oxide can be etched to obtain square spacers (which are twice as large as the second mandrels) with minimal footing and no spacer Critical Dimension (CD) loss. The square tin oxide spacer with minimal footing meets the requirements as a second mandrel for the second spacer deposition. When the second spacer is a silicon-containing material (e.g., SiO)₂) The second spacer may be etched using a fluorine-based chemistry, which has a high selectivity to tin oxide. H may be used that has a high etch selectivity to silicon oxide or other silicon containing compounds that may be used as the second spacer material₂The chemistry removes the tin oxide spacer/mandrel.

The other oxide acts as a mandrel. In some embodiments, other oxide materials are used in place of tin oxide in any of the processing sequences described herein. Specifically, an oxide of an element that forms a hydride having a high vapor pressure may be used. Oxides of elements that form volatile hydrides (e.g., hydrides having boiling points less than about 20 ℃, such as less than about 0 ℃) are used, where the hydrides are stable and in a gaseous state at processing temperatures. For example, in some embodiments, antimony oxide or tellurium oxide may be used in place of tin oxide in any of the processing sequences described herein, and etched using similar hydrogen-based chemistries during processing.

Device

The methods described herein may be performed in a variety of apparatuses configured for etching and deposition. Suitable apparatus configured for etching include: an etching processing chamber; a substrate holder in the etch processing chamber configured to hold a substrate in place during etching; and a plasma generating mechanism configured to generate plasma in the process gas.

Examples of suitable apparatus include Inductively Coupled Plasma (ICP) reactors, which may also be suitable for cyclic deposition and activation processes in certain embodiments, including for Atomic Layer Etching (ALE) operations and Atomic Layer Deposition (ALD) operations. Although ICP reactors are described in detail herein, it should be understood that capacitively coupled plasma reactors may also be used in some embodiments.

FIG. 9 schematically illustrates a cross-sectional view of an inductively coupled plasma integrated etch and deposition apparatus 900 suitable for performing the plasma etch described herein, an example of which isA reactor, produced by Lam Research corp. of virmont, california. The inductively coupled plasma apparatus 900 includes a general processing chamber 924 structurally defined by chamber walls 901 and a window 911. The chamber wall 901 may be made of stainless steel or aluminum. The window 911 may be made of quartz or other dielectric material. Optional internal plasma grid 950 divides the overall process chamber into upper subchamber 902 and lower subchamber 903. In most embodiments, plasma grid 950 can be removed, thereby utilizing the chamber space formed by subchambers 902 and 903. A chuck 917 is positioned in the lower subchamber 903 adjacent the bottom inner surface. Chuck 917 is configured to receive and hold a semiconductor wafer 919 on which etching and deposition processes are performed. Chuck 917 can be an electrostatic chuck used to support wafer 919 when wafer 919 is present. In some embodiments, an edge ring (not shown) surrounds the chuck917 and has an upper surface that is substantially planar with the top surface of wafer 919 (when the wafer is present above chuck 917). Chuck 917 also includes an electrostatic electrode that can clamp and unclamp (dechucking) wafer 919. A filter and DC clamp power source (not shown) may be provided for this purpose. Other control systems may also be provided for lifting the wafer 919 off of the chuck 917. The chuck 917 can be charged with an RF power source 923. The RF power source 923 is connected to the matching circuit 921 through a connection 927. The matching circuit 921 is connected to the chuck 917 via a connection 925. In this manner, the RF power source 923 is connected to the chuck 917. In various embodiments, the bias power of the electrostatic chuck may be set at about 50Vb, or may be set at a different bias power depending on the process performed according to the disclosed embodiments. For example, the bias power may be set between about 20Vb and about 100Vb, or between about 30Vb and about 150 Vb.

The elements for plasma generation include a coil 933 located over the window 911. In some embodiments, no coil is used in the disclosed embodiments. The coil 933 is made of a conductive material and includes at least one full turn. The example of the coil 933 shown in fig. 9 includes three turns. The cross-section of coil 933 is shown symbolically, and coil 933 with the symbol "X" indicates that coil 933 extends rotationally into the page, while coil 933 with the symbol "●" indicates extending rotationally out of the page. The element for plasma generation further includes an RF power source 941 configured to supply RF power to the coil 933. Typically, an RF power source 941 is connected to the matching circuit 939 through connection 945. The matching circuit 939 is connected to the coil 933 by a connector 943. In this manner, an RF power source 941 is connected to the coil 933. An optional faraday shield 949a is positioned between the coil 933 and the window 911. The faraday shield 949a may be held in a spaced relationship relative to the coil 933. In some embodiments, a faraday shield 949a is disposed directly above the window 911. In some embodiments, a faraday shield 949b is disposed between the window 911 and the chuck 917. In some embodiments, the faraday shield 949b is not held in a spaced relationship relative to the coil 933. For example, the faraday shield 949b may be positioned directly below the window 911 without a gap. The coil 933, faraday shield 949a and window 911 are each configured substantially parallel to one another. The faraday shield 949a can prevent metal or other materials from depositing on the window 911 of the processing chamber 924.

Process gas (e.g. H)₂And He, etc.) can flow into the process chamber through one or more primary gas flow inlets 960 located in the upper sub-chamber 902 and/or through one or more side gas flow inlets 970. Also, although not explicitly shown, similar gas flow inlets may be used to supply process gases to the capacitively-coupled plasma processing chamber. A vacuum pump, such as one or two stage dry mechanical pumps and/or turbo-molecular pumps 940, may be used to draw process gases from the process chamber 924 and maintain the pressure within the process chamber 924. For example, a vacuum pump may be used to evacuate lower subchamber 903 during the purging operation. The valve-controlled conduit may be used to fluidly couple a vacuum pump to the processing chamber 924 to selectively control the application of the vacuum environment provided by the vacuum pump. This may be done using a closed loop controlled flow restriction device such as a throttle valve (not shown) or a pendulum valve (not shown) during operation of the plasma process. Similarly, vacuum pumps and valves that are controllably fluidly connected to the capacitively coupled plasma processing chamber may also be used.

During operation of the apparatus 900, one or more process gases (e.g., H-containing gases for hydrogen-based etching)₂Gas) may be supplied through gas flow inlets 960 and/or 970. In certain embodiments, the process gas may be supplied only through the main gas flow inlet 960, or only through the side gas flow inlet 970. In some cases, the gas flow inlets shown in the figures may be replaced by more complex gas flow inlets, for example, by one or more showerheads. The faraday shield 949a and/or optional grid 950 can include internal passages and apertures that enable the delivery of process gas to the process chamber 924. One or both of the faraday shield 949a and optional grid 950 can act as a showerhead for delivering the process gas. In some embodiments, a liquid vaporization and delivery system may be located upstream of the process chamber 924 such that once the liquid reactant or precursor is vaporized, the vaporized reactant or precursor is vaporizedThe reactants or precursors are introduced into the process chamber 924 through gas flow inlets 960 and/or 970.

Radio frequency power is supplied from an RF power source 941 to the coil 933 to flow an RF current through the coil 933. An RF current flowing through the coil 933 generates an electromagnetic field around the coil 933. The electromagnetic field generates an induced current within the upper sub-chamber 902. The physical and chemical interactions of the generated ions and radicals with the wafer 919 etch features on the wafer 919 and selectively deposit layers on the wafer 919.

If the plasma grid 950 is used such that both the upper sub-chamber 902 and the lower sub-chamber 903 are present, the induced current acts on the gas present in the upper sub-chamber 902 to generate electron-ion plasma in the upper sub-chamber 902. The optional internal plasma grid 950 limits the amount of hot electrons in the lower sub-chamber 903. In some embodiments, the apparatus 900 is designed and operated such that the plasma present in the lower sub-chamber 903 is an ion-ion plasma.

Both the upper electron-ion plasma and the lower ion-ion plasma may contain cations and anions, although the ion-ion plasma will have a greater anion to cation ratio. Volatile etch and/or deposition byproducts may be removed from lower subchamber 903 through port 922. For example, in the use of H₂Tin hydride generated during the plasma etching of tin oxide can be removed through port 922 during purging and/or pumping. The chuck 917 disclosed herein can operate at an elevated temperature range between about 10 ℃ and about 250 ℃. The temperature will depend on the processing operation and the particular recipe. In some embodiments, the apparatus is controlled to perform the etching at a temperature of less than about 100 ℃.

The device 900 may be coupled to a facility (not shown) when installed in a clean room or manufacturing plant. The facility includes piping that provides process gas, vacuum, temperature control, and environmental particulate control. These facilities are connected to the equipment 900 when installed at the target manufacturing plant. In addition, the apparatus 900 may be coupled to a transfer chamber that allows semiconductor wafers to be transferred into and out of the apparatus 900 by a robot using typical automation.

In some embodiments, the system controller 930 (which may include one or more physical or logical controllers) controls some or all of the operations of the process chambers 924. The system controller 930 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 900 includes a switching system for controlling the flow rate of the process gas. In some embodiments, the controller comprises program instructions for causing the steps of any of the methods provided herein.

In some implementations, the system controller 930 is part of a system, which may be part of the above examples. Such systems may include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more platforms for processing, and/or specific processing components (wafer susceptors, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics may be integrated into a system controller 930, which system controller 930 may control various components or subcomponents of one or more systems. Depending on the process parameters and/or type of system, the system controller can be programmed to control any of the processes disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, Radio Frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transport tools, and/or load locks connected or interfaced with specific systems.

Broadly speaking, the system controller 930 may be defined as an electronic device having various integrated circuits, logic, memory, and/or software to receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and so forth. An integrated circuit may include a chip in firmware that stores program instructions, a Digital Signal Processor (DSP), a chip defined as an Application Specific Integrated Circuit (ASIC), and/or one or more microprocessors or microcontrollers executing program instructions (e.g., software). The program instructions may be instructions communicated to the controller in the form of various separate settings (or program files) that define operating parameters for performing specific processes on or for a semiconductor wafer or system. In some embodiments, the operating parameter may be part of a recipe (recipe) defined by a process engineer for completing one or more process steps during preparation or removal of one or more layer(s), material(s), metal(s), oxide(s), silicon dioxide, surface, circuitry, and/or die of a wafer.

In some implementations, system controller 930 may be part of or coupled to a computer that is integrated with, coupled to, or otherwise connected to the system via a network, or a combination thereof. For example, the controller may be in the "cloud" or be all or part of a fab (fab) host system, which may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of the manufacturing operation, check a history of past manufacturing operations, check trends or performance criteria for multiple manufacturing operations, change parameters of the current process, set process steps to follow the current process or begin a new process. In some examples, a remote computer (e.g., a server) may provide the process recipe to the system over a network, which may include a local network or the internet. The remote computer may include a user interface capable of inputting or programming parameters and/or settings that are then communicated from the remote computer to the system. In some examples, system controller 930 receives instructions in the form of data that specify parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, system controller 930 can be distributed, for example, by including one or more discrete controllers that are networked together and operate toward a common goal (e.g., the processing and control described herein). An example of a distributed controller for these purposes may be one or more integrated circuits on a room that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that are combined to control processing on the room.

Exemplary systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, Physical Vapor Deposition (PVD) chambers or modules, Chemical Vapor Deposition (CVD) chambers or modules, ALD chambers or modules, ALE chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and/or fabrication of semiconductor wafers.

As described above, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, tools located throughout the factory, a host computer, another controller, or tools used in the handling of containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing facility, depending on the process step or steps to be performed by the tool.

Fig. 10 depicts a semiconductor processing cluster configuration in which the various modules interface with a vacuum transfer module 1038 (VTM). The configuration of various modules that "transfer" a wafer between multiple storage devices and processing modules may be referred to as a "cluster tool architecture" system. Hermetic chamber 1030 (also referred to as a load lock or transfer module) is coupled to VTM1038, VTM1038 in turn is coupled to four process modules 1020a-1020d, which may be individually optimized to perform various manufacturing processes for process modules 1020a-1020 d. For example, the process modules 1020a-1020d may be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and/or other semiconductor processing. In some embodiments, the tin oxide deposition and tin oxide etching are performed in the same module. In some embodiments, the tin oxide deposition and tin oxide etching are performed in different modules in the same tool. One or more of the substrate etch process modules (any of 1020a-1020 d) may be implemented as disclosed herein, for example, for depositing conformal films, selectively etching tin oxide, forming air gaps, and other suitable functions described in accordance with the disclosed embodiments. The chamber 1030 and the process modules 1020a-1020d may be referred to as a "station". Each station has a facet 1036(facet 1036) connecting the station with the VTM 1038. Inside each facet, sensors 1-18 are used to detect the passage of wafer 1026 as wafer 1026 moves between stations.

Robot 1022 transfers wafer 1026 between stations. In one embodiment, the robot 1022 has one arm, while in another embodiment, the robot 1022 has two arms, with each arm having an end effector 1024 to pick up a wafer (e.g., wafer 1026) for transport. In an Atmospheric Transfer Module (ATM)1040, a front end robot 1032 is used to transfer wafers 1026 from a wafer cassette or front opening wafer cassette (FOUP)1034 in a Load Port Module (LPM)1042 to the hermetic chamber 1030. Module center 1028 within processing modules 1020a-1020d is a location for placement of wafer 1026. Aligner 1044 in ATM1040 is used to align wafers.

In an exemplary processing method, a wafer is placed in one of the plurality of FOUPs 1034 in the LPM 1042. The front end robot 1032 transfers the wafer from the FOUP 1034 to the aligner 1044, which allows the wafer 1026 to be properly centered before being etched or processed. After alignment, wafer 1026 is moved into hermetic chamber 1030 by front end robot 1032. Because the hermetic chamber 1030 has the ability to match the environment between the ATM1040 and the VTM1038, the wafer 1026 can be moved between the two pressure environments without being damaged. The wafer is moved by robot 1022 from chamber 1030, through VTM1038 and into one of the process modules 1020a-1020 d. To accomplish this wafer movement, robot 1022 uses an end effector 1024 on each of its arms. Once the wafer 1026 has been processed, it is moved from the process modules 1020a-520d into the hermetic chamber 1030 by the robot 1022. From there, the wafer 1026 may be moved by the front end robot 1032 into one of a plurality of FOUPs 1034 or to an aligner 1044.

It should be noted that the computer controlling the wafer movement may be local to the cluster architecture, or it may be located outside the cluster architecture in the manufacturing facility, or at a remote location and connected to the cluster architecture through a network. The controller as described above with reference to figure 9 may be implemented with the tool of figure 10. A machine-readable medium containing instructions for controlling processing operations in accordance with the invention may be coupled to a system controller.

In some embodiments, a system for processing a semiconductor substrate includes one or more deposition chambers; one or more etching chambers; and a system controller having program instructions for performing any of the processes or sub-processes described herein. In some embodiments, the program instructions include instructions for causing the following: causing deposition of a spacer material on horizontal surfaces and sidewalls of the tin oxide protrusion features on a semiconductor substrate having a plurality of tin oxide protrusion features; and causing removal of the spacer material from horizontal surfaces of the tin oxide protrusion feature to expose the underlying tin oxide without causing complete removal of the spacer material on sidewalls of the tin oxide protrusion feature. The controller may further include program instructions for: resulting in removal of the tin oxide protrusion feature without resulting in complete removal of the spacer material previously present on the sidewalls of the tin oxide protrusion feature, thereby forming a plurality of spacers on the semiconductor substrate. In some embodiments, the controller includes program instructions for: the semiconductor substrate having a plurality of tin oxide protruding features is formed by causing a conformal tin oxide layer to be deposited on the semiconductor substrate having a plurality of first mandrels, followed by removing the tin oxide material from horizontal surfaces, and by removing the first mandrels.

In some embodiments, there is provided an etching apparatus comprising: an etch process chamber having an inlet for a process gas; a substrate holder configured to hold a semiconductor substrate in the etching process chamber; and a process controller comprising program instructions for any of the processes and sub-processes provided herein. In some embodiments, the controller includes instructions for: causing etching of a spacer material layer of a plurality of tin oxide protrusion features coated on the semiconductor substrate, thereby completely removing the spacer material from horizontal surfaces of the semiconductor substrate without completely removing the spacer material on sidewalls of the plurality of tin oxide protrusion features.

In another aspect, a non-transitory computer-machine readable medium is provided, wherein it comprises code for enabling performance of any of the methods described herein.

Further implementation mode

The apparatus and processes described herein may be used in conjunction with lithographic patterning tools or processes, e.g., for the manufacture or fabrication of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, but not necessarily, such equipment and processes will be used or performed together in a common manufacturing facility. Lithographically patterning films typically include some or all of the following steps, each of which may be accomplished with a number of possible tools: (1) coating a photoresist on a workpiece (i.e., a substrate) using a spin-on or spray-on tool; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible or UV or X-ray light with a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist to pattern it using a tool such as a wet station; (5) transferring the resist pattern into the underlying film or workpiece by using a dry or plasma assisted etch tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, a system is provided that includes any of the apparatuses and steppers described herein.