阅读说明：本技术 单光子雪崩二极管及其制作方法、单光子雪崩二极管阵列 (Single-photon avalanche diode, manufacturing method thereof and single-photon avalanche diode array ) 是由 魏丹清 于 2021-09-13 设计创作，主要内容包括：本发明涉及一种单光子雪崩二极管及其制作方法、单光子雪崩二极管阵列。所述单光子雪崩二极管在有源区的边缘区域设有沿衬底厚度方向纵向延伸的p型掺杂区,并且,在p型掺杂区的远离隔离沟槽的一侧,还设有沿衬底厚度方向纵向延伸的n型掺杂区,p型掺杂区和n型掺杂区对隔离沟槽处产生的缺陷起到了隔离作用,可以有效降低由于该缺陷引起的暗计数,并且,所述n型掺杂区与有源区内pn结中的与所述n型掺杂区具有相同掺杂类型的掺杂区电连接,能够将因p型掺杂区而收缩的耗尽区拓宽,使得在降低单光子雪崩二极管的暗计数率的同时,不影响器件的光子探测效率。所述单光子雪崩二极管阵列包括阵列排布的上述单光子雪崩二极管。(The invention relates to a single photon avalanche diode, a manufacturing method thereof and a single photon avalanche diode array. The single photon avalanche diode is provided with a p-type doped region longitudinally extending along the thickness direction of a substrate in the edge region of an active region, and is also provided with an n-type doped region longitudinally extending along the thickness direction of the substrate on one side of the p-type doped region far away from an isolation groove, the p-type doped region and the n-type doped region have an isolation effect on defects generated at the isolation groove, so that dark counting caused by the defects can be effectively reduced, in addition, the n-type doped region is electrically connected with a doped region, which has the same doping type as the n-type doped region, in a pn junction in the active region, the depletion region contracted due to the p-type doped region can be widened, the dark counting rate of the single photon avalanche diode is reduced, and meanwhile, the photon detection efficiency of a device is not influenced. The single photon avalanche diode array comprises the single photon avalanche diodes which are arranged in an array mode.)

1. A single photon avalanche diode comprising:

the substrate comprises an active region and an isolation region for limiting the active region, the active region is provided with a pn junction for generating photon triggered avalanche current, and the isolation region is provided with an isolation groove which penetrates through the substrate along the thickness direction of the substrate and is filled with an insulating medium;

the active region is provided with a p-type doped region longitudinally extending along the thickness direction of the substrate at an edge region close to the isolation region, and is further provided with an n-type doped region longitudinally extending along the thickness direction of the substrate at an edge region close to the isolation trench at one side of the p-type doped region far away from the isolation trench, and the n-type doped region is electrically connected with a doped region in the pn junction, wherein the doped region and the n-type doped region have the same doping type.

2. The single photon avalanche diode according to claim 1 wherein said substrate is a p-type doped substrate and an n-type well is disposed in said active region, said n-type well forming said pn junction with the surrounding p-type doped substrate.

3. The single photon avalanche diode according to claim 2 wherein said p-type doped region and said n-type doped region each extend from said front surface of said substrate down said thickness of said substrate and each exceed the depth of said pn junction with a side surface on which said n-type well is disposed being said front surface of said substrate.

4. The single photon avalanche diode according to claim 2 further comprising an electrical interconnect structure disposed above said substrate, said electrical interconnect structure electrically connecting said n-type doped region and said n-type well.

5. The single photon avalanche diode according to claim 2 wherein said n-type doped region and said n-type well are interconnected within said active region.

6. A method for manufacturing a single photon avalanche diode is characterized by comprising the following steps:

providing a substrate, wherein the substrate comprises an active region and an isolation region for limiting the active region;

respectively performing p-type ion implantation and n-type ion implantation on the substrate, and respectively forming a p-type doped region and an n-type doped region which are sequentially and adjacently arranged along the direction far away from the isolation region and longitudinally extend along the thickness direction of the substrate in the edge region of the active region close to the isolation region;

forming a pn junction for generating photon triggered avalanche current in the active region, and electrically connecting the n-type doped region with a doped region of the pn junction having the same doping type as the n-type doped region.

7. The method of manufacturing of claim 6, wherein the method of performing p-type ion implantation and n-type ion implantation on the substrate, respectively, comprises:

carrying out p-type ion implantation by using a first mask pattern, wherein the opening of the first mask pattern exposes the isolation region and part of the active region adjacent to the isolation region;

carrying out n-type ion implantation by utilizing a second mask pattern, wherein the opening of the second mask pattern covers the opening range of the first mask pattern, the opening boundary is expanded, and the concentration of the n-type ion implantation is less than that of the p-type ion implantation;

after the n-type ion implantation, the p-type doped region and the n-type doped region which are sequentially and adjacently arranged along the direction far away from the isolation region are formed in the edge region of the active region close to the isolation region.

8. The method of claim 7, wherein the first mask pattern is a patterned photoresist layer and the second mask pattern is formed by a widening operation performed on the patterned photoresist layer.

9. The method of manufacturing of claim 6, wherein the method of performing p-type ion implantation and n-type ion implantation on the substrate, respectively, comprises:

carrying out p-type ion implantation by utilizing a first mask pattern, and forming a p-type doped region in the edge region of the active region close to the isolation region;

and carrying out n-type ion implantation by using a second mask pattern, and forming the n-type doped region on one side of the p-type doped region, which is far away from the isolation region, wherein the opening of the second mask pattern is not overlapped with the opening of the first mask pattern.

10. The method of manufacturing of claim 6, wherein shallow trench isolation is formed from a front side of a substrate of the isolation region before performing the p-type ion implantation and the n-type ion implantation; after the p-type ion implantation and the n-type ion implantation are performed, the method for manufacturing the single photon avalanche diode further comprises the following steps:

and etching the substrate of the isolation region from the back surface of the substrate opposite to the front surface to form a groove exposing the shallow groove isolation, and then filling an isolation medium in the groove to form a deep groove isolation connected with the exposed shallow groove isolation.

11. A single photon avalanche diode array comprising a plurality of single photon avalanche diodes according to any one of claims 1 to 5 arranged in an array with said isolation trenches disposed between adjacent single photon avalanche diodes.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a single photon avalanche diode, a manufacturing method of the single photon avalanche diode and a single photon avalanche diode array.

Background

A single Photon Avalanche diode, abbreviated as spad (single Photon Avalanche diode), is a solid-state photodetector that achieves photoelectric detection based on a breakdown region where a bias voltage exceeds a pn junction. In a single photon avalanche diode, the pn junction is reverse biased at a voltage above the breakdown voltage, and an avalanche current is generated by the internal photoelectric effect (the emission of electrons or another carrier when a material is struck by a photon). Very low signal intensities, e.g. down to single photon levels, can be detected with single photon avalanche diodes. The single photon detector based on the single photon avalanche diode can be used in a highly sensitive photon capturing environment, and has wide application in the fields of fluorescence lifetime imaging, 3D imaging and the like.

During the operation of the single photon avalanche diode, some stray light (non-signal light) and electrical noise may also be detected as effective light signals, and the misjudgment is called dark counting, and the number of dark counting, namely the dark counting rate, is an important parameter for judging the performance of the single photon avalanche diode device. In order to reduce the dark count rate of the device, in the prior art, a p-type dopant is injected beside an isolation trench for isolating adjacent diodes according to a certain concentration gradient to form a p-type doped region, so that the dark count caused by defects generated at the isolation trench can be effectively reduced.

Disclosure of Invention

In order to reduce the dark counting rate of the single photon avalanche diode and not influence the photon detection efficiency of the device, the invention provides the single photon avalanche diode and a manufacturing method of the single photon avalanche diode, and further provides a single photon avalanche diode array.

In one aspect, the present invention provides a single photon avalanche diode comprising:

the substrate comprises an active region and an isolation region for limiting the active region, the active region is provided with a pn junction for generating photon triggered avalanche current, and the isolation region is provided with an isolation groove which penetrates through the substrate along the thickness direction of the substrate and is filled with an insulating medium;

the active region is provided with a p-type doped region longitudinally extending along the thickness direction of the substrate at an edge region close to the isolation region, and is further provided with an n-type doped region longitudinally extending along the thickness direction of the substrate at an edge region close to the isolation trench at one side of the p-type doped region far away from the isolation trench, and the n-type doped region is electrically connected with a doped region in the pn junction, wherein the doped region and the n-type doped region have the same doping type.

Optionally, the substrate is a p-type doped substrate, an n-type well is disposed in the active region, and the n-type well and the surrounding p-type doped substrate form the pn junction.

Optionally, an implantation surface of the n-type well is used as a front surface of the substrate, and the p-type doped region and the n-type doped region both extend downwards from the front surface of the substrate along a thickness direction of the substrate and both exceed a depth of the pn junction.

Optionally, the single photon avalanche diode further includes an electrical interconnection structure disposed above the substrate, and the electrical interconnection structure is electrically connected to the n-type doped region and the n-type well.

Optionally, the n-type doped region and the n-type well are connected to each other in the active region.

In one aspect, the invention provides a method for manufacturing a single photon avalanche diode, which comprises the following steps:

providing a substrate, wherein the substrate comprises an active region and an isolation region for limiting the active region;

respectively performing p-type ion implantation and n-type ion implantation on the substrate, and respectively forming a p-type doped region and an n-type doped region which are sequentially and adjacently arranged along the direction far away from the isolation region and longitudinally extend along the thickness direction of the substrate in the edge region of the active region close to the isolation region;

forming a pn junction for generating photon triggered avalanche current in the active region, and electrically connecting the n-type doped region with a doped region of the pn junction having the same doping type as the n-type doped region.

Optionally, the method for performing the p-type ion implantation and the n-type ion implantation on the substrate respectively includes:

carrying out p-type ion implantation by using a first mask pattern, wherein the opening of the first mask pattern exposes the isolation region and part of the active region adjacent to the isolation region;

carrying out n-type ion implantation by utilizing a second mask pattern, wherein the opening of the second mask pattern covers the opening range of the first mask pattern, the opening boundary is expanded, and the concentration of the n-type ion implantation is less than that of the p-type ion implantation;

after the n-type ion implantation, the p-type doped region and the n-type doped region which are sequentially and adjacently arranged along the direction far away from the isolation region are formed in the edge region of the active region close to the isolation region.

Optionally, the first mask pattern is a patterned photoresist layer, and the second mask pattern is formed by performing a widening operation on the patterned photoresist layer.

Optionally, the method for performing the p-type ion implantation and the n-type ion implantation on the substrate respectively includes:

carrying out p-type ion implantation by utilizing a first mask pattern, and forming a p-type doped region in the edge region of the active region close to the isolation region;

and carrying out n-type ion implantation by using a second mask pattern, and forming the n-type doped region on one side of the p-type doped region, which is far away from the isolation region, wherein the opening of the second mask pattern is not overlapped with the opening of the first mask pattern.

Optionally, before performing the p-type ion implantation and the n-type ion implantation, a shallow trench isolation is formed on the front surface of the substrate of the isolation region; after the p-type ion implantation and the n-type ion implantation are performed, the method for manufacturing the single photon avalanche diode further comprises the following steps:

and etching the substrate of the isolation region from the back surface of the substrate opposite to the front surface to form a groove exposing the shallow groove isolation, and then filling an isolation medium in the groove to form a deep groove isolation connected with the exposed shallow groove isolation.

In one aspect, the invention further provides a single photon avalanche diode array, which includes a plurality of single photon avalanche diodes arranged in an array, and the isolation trench is arranged between adjacent single photon avalanche diodes.

The single photon avalanche diode provided by the invention is provided with a p-type doped region which longitudinally extends along the thickness direction of the substrate in the edge region of the active region close to the isolation region, and is also provided with an n-type doped region which longitudinally extends along the thickness direction of the substrate in the edge region of the active region close to the isolation trench on one side of the p-type doped region far away from the isolation trench, wherein the p-type doped region and the n-type doped region play an isolation role in isolating the defects generated at the isolation trench, so that the dark count caused by the defects can be effectively reduced, in addition, the n-type doped region is electrically connected with the doped region which has the same doping type as the n-type doped region in the pn junction in the active region, the depletion region contracted by the p-type doped region can be widened, the photon absorption efficiency and the avalanche generation probability can be improved, so that the dark count rate of the single photon diode device can be reduced, the photon detection efficiency of the device is not influenced, and the detection performance of the single photon avalanche diode device is improved.

The single photon avalanche diode formed by the manufacturing method of the single photon avalanche diode not only has lower dark counting rate, but also has higher photon detection efficiency, so the detection performance is better.

The single photon avalanche diode array provided by the invention comprises the single photon avalanche diode provided by the invention, and therefore has the same or similar advantages.

Drawings

Figure 1 is a simulation of a depletion region when a p-type doped region is provided around an isolation trench of a single photon avalanche diode.

Fig. 2 and 3 are schematic cross-sectional views of single photon avalanche diodes according to embodiments of the present invention.

Figure 4 is a simulation of the depletion region of a single photon avalanche diode employing an embodiment of the invention.

Fig. 5 is a schematic flow chart of a method for manufacturing a single photon avalanche diode according to an embodiment of the present invention.

Fig. 6A to 6F are schematic cross-sectional structures of a single photon avalanche diode according to a method for manufacturing a single photon avalanche diode according to an embodiment of the present invention.

Description of reference numerals:

100-a substrate; 110-an active region; a 111-p type doped region; 112-n type doped region; 120-isolation regions; 121-isolation trenches; 200-an electrical interconnect structure; 111' -p-type ion doped region.

Detailed Description

The single photon avalanche diode, the manufacturing method thereof and the single photon avalanche diode array according to the present invention will be described in further detail with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be understood that the drawings in the specification are in simplified form and are not to be taken in a precise scale, for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

It is noted that the terms "first," "second," and the like, hereinafter are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if a method described herein comprises a series of steps, and the order in which these steps are presented herein is not necessarily the only order in which these steps are performed, some of the described steps may be omitted and/or some other steps not described herein may be added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "at … …" can also include "at … …" and other orientational relationships.

Single photon avalanche diodes operate above the breakdown voltage of the pn junction and can be used in highly sensitive photon capture environments. In a device (such as a chip) adopting the single photon avalanche diode, a plurality of single photon avalanche diodes are formed on the same substrate in an array mode, and an isolation groove filled with an isolation medium is arranged between the adjacent single photon avalanche diodes, the depth of the isolation groove usually exceeds the depth of a longitudinally arranged pn junction, and even penetrates through the substrate from the thickness direction, namely complete physical isolation is formed. However, the dark count rate is easily increased by defects generated at the isolation trench, and one solution is to form a p-type doped region around the isolation trench to reduce the dark count rate.

Figure 1 is a simulation of a depletion region when a p-type doped region is provided around an isolation trench of a single photon avalanche diode. In fig. 1, the white curve in the p-type substrate region is the boundary line of the depletion region. As can be seen from comparison between the simulation result shown in fig. 1 and the simulation result without the p-type doped region, although the dark count rate can be reduced due to the p-type doped region, the depletion region (especially, in the edge region of the active region, i.e., the left end and the right end in fig. 1) narrows upward, i.e., inward contraction transition occurs, for the single photon avalanche diode, the probability of avalanche occurrence is reduced due to the depletion region contraction shown in fig. 1, which further affects photon detection efficiency, and is not beneficial to ensuring the detection performance of the avalanche single photon diode device.

In order to reduce the dark counting rate of a single photon avalanche diode device and ensure the photon detection efficiency of the device, the embodiment of the invention introduces a single photon avalanche diode and a manufacturing method of the single photon avalanche diode, and also introduces a single photon avalanche diode array.

Referring to fig. 2 and 3, embodiments of the present invention relate to a single photon avalanche diode. The single photon avalanche diode comprises a substrate 100, wherein the substrate 100 comprises an active region 110 and an isolation region 120 for limiting the active region 110, a pn junction for generating photon triggered avalanche current is arranged in the active region 110 of the substrate 100, and an isolation trench 121 which penetrates through the substrate 100 along the thickness direction of the substrate 100 and is filled with an insulating medium is arranged in the isolation region 120 of the substrate 100; wherein the active region 110 is provided with a p-type doped region 111 longitudinally extending in a thickness direction of the substrate 100 at an edge region near the isolation region 120, and, on the side of the p-type doped region 111 remote from the isolation trench 121, the active region 110 is further provided with an n-type doped region 112 extending longitudinally in the thickness direction of the substrate 100 in an edge region near the isolation region 120, wherein, the p-type doped region 111 and the n-type doped region 112 can be sequentially disposed adjacently along a direction away from the isolation region 120, the substrate 100 can also be disposed between the p-type doped region 111 and the n-type doped region 112 and between the isolation region 120, alternatively, the p-type doped region 111 and the n-type doped region 112 are sequentially disposed adjacently in a direction away from the isolation region 120 with the substrate 100 spaced therebetween, and, the n-doped region 112 is electrically connected to the same doping region of the pn junction within the active region 110 that has the same doping type as the n-doped region 112.

The material of the substrate 100 may be silicon, germanium, silicon carbide, gallium oxide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or the like, or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or may be another material such as GaAs, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP, or the like, or may be a combination of the above materials. Substrate 100 may include a doped epitaxial layer, a graded semiconductor layer, and a semiconductor layer (e.g., a silicon layer on a silicon germanium layer) overlying other semiconductor layers of different types. Certain dopant ions may also be implanted into the substrate 100 to change electrical parameters according to design requirements. The active region 110 and the isolation region 120 extend in the thickness direction of the substrate 100.

As shown in fig. 2 and 3, the substrate 100 is, for example, a p-type doped substrate (e.g., a silicon substrate), i.e., the active region 110 has p-type doping (e.g., doping with boron B or boron difluoride BF) in its entirety₂). Fig. 2 and 3 differ in the structure of the pn junction provided in the active region 110 for generating a photon-triggered avalanche current. As shown in fig. 2, in an embodiment, an n-type well (NW) is disposed in the active region 110, and the substrate in the n-type well is doped with, for example, phosphorus P or arsenic As. An n-type well extends into the substrate 100 from the upper surface of the substrate 100, the n-type well forming a pn junction with the surrounding p-type substrate. For convenience of careTo solve this problem, the surface on which the n-type well is provided is a front surface (i.e., an upper surface) of the substrate 100, and the surface opposite to the front surface is a rear surface (i.e., a lower surface) of the substrate 100. As shown in fig. 3, in an embodiment, the substrate 100 includes a heavily p-doped base layer (p + Sub) and a lightly p-doped epitaxial layer (p Epi), and in the active region 110, a p-type well (PW) and an n-type well (NW) on the p-type well are formed in the epitaxial layer, in which embodiment the n-type well forms a pn junction with the surrounding p-type substrate, and the p-type well further defines the location of the pn junction. The invention is not limited to this, and in the single photon avalanche diode of the embodiment of the invention, the pn junction arranged in the active region for generating photon triggered avalanche current can adopt various specific structures disclosed in the field. Depletion regions are formed on two sides of the interface of the pn junction in the embodiment of the invention, the depletion regions are widened under the action of reverse bias voltage, and when the pn junction works above breakdown voltage, avalanche current is generated under the action of internal photoelectric effect (when one material is impacted by photons, electrons or other carriers are emitted). The single photon avalanche diode according to the embodiment of the present invention will be further described below by taking the pn junction shown in fig. 3 as an example.

In the single photon avalanche diode according to the embodiment of the present invention, the p-type doped region 110 is disposed in an edge region of the active region 110 close to the isolation region 120 (the "edge region" of the active region 110 refers to a region of the active region 110 closer to the isolation region 120 than a region of the pn junction), the p-type doped region 111 extends longitudinally along the thickness direction of the substrate 100, and the concentration of p-type ions in the substrate region is around the concentration of p-type ions in the p-type doped region 111. By using the p-type doped region 111, the defects generated at the isolation trench 121 are not easy to trap carriers for generating avalanche current, so that the p-type doped region 111 has an isolation effect on the defects generated at the isolation trench 121, and contributes to reducing the dark count rate. The p-type doped region 111 extends from the upper surface to the lower surface of the substrate 100 along the isolation trench 121, but is not limited thereto, the p-type doped region 111 may also be disposed only in a partial depth range of the isolation trench 121, for example, may extend from the upper surface of the substrate 100 into the active region 110 below the pn junction without extending to the lower surface of the substrate 100, and such a non-penetrating p-type doped region 111 may also perform an isolation function on defects at the interface of the isolation trench 121 during the operation of the single photon avalanche diode, thereby contributing to reducing the dark count rate.

In the single photon avalanche diode, on the side of the p-type doped region 111 far away from the isolation trench 121, the active region 110 is further provided with an n-type doped region 112 extending longitudinally along the thickness direction of the substrate 100 in the edge region near the isolation region 120. The n-type doped region 112 extends from the upper surface to the lower surface of the substrate 100 along the isolation trench 121, but is not limited thereto, and the n-type doped region 112 may be disposed only in a partial depth range of the isolation trench 121, and may extend from the upper surface of the substrate 100 into the active region 110 below the pn junction without extending to the lower surface of the substrate 100. The p-doped region 111 and the n-doped region 112 are arranged between the isolation trench 121 and the pn-junction for generating the photon triggered avalanche current, seen in a lateral arrangement on the substrate 100, i.e. the p-doped region 111 and the n-doped region 112 separate the isolation trench 121 from the pn-junction. Since the n-type doped region 112 and the p-type doped region 111 have opposite doping types and are disposed between the p-type doped region 111 and the pn junction, the isolation of the defect generated at the isolation trench 121 can be further formed, which is helpful for further reducing the dark count caused by the defect generated at the isolation trench 121, thereby being helpful for improving the performance of the single photon diode device.

In the embodiment of the present invention, the n-type doped region 112 is electrically connected to the same doped region in the pn junction, and the n-type doped region 112 is also used to improve the depletion region shrinkage phenomenon as shown in fig. 1. Specifically, as shown in fig. 2 and 3, in some embodiments, the n-doped region 112 is not connected to the n-well (NW) forming the pn junction in the active region 110, with a p-type substrate region therebetween. In order to electrically connect the n-type doped regions 112 and the n-type well, the single photon avalanche diode further comprises an electrical interconnect structure 200 disposed over the substrate 100, the electrical interconnect structure 200 may comprise multiple patterned conductive layers separated by dielectric material and conductive plugs providing interconnections between the doped regions, circuitry and input/output of one or more of the single photon avalanche diodes. Here, the n-doped region 112 and the n-well used to form the pn junction can be electrically connected using an electrical interconnect structure 200. Alternatively, the top of the n-type well and n-type doped region 112 may be formed with an extraction region having n-type heavy doping (n +) for contacting the interconnect structure 200. The invention is not limited thereto, and in other embodiments, the n-type doped region 112 and the n-type well constituting the pn junction may be connected to each other in the active region 110, that is, the two are electrically connected in the active region 110, and in this case, an electrical interconnection element for electrically connecting the two may or may not be disposed above the substrate 100.

Figure 4 is a simulation of the depletion region of a single photon avalanche diode employing an embodiment of the invention. Wherein, the white curve in the p-type substrate region represents the boundary of depletion regions generated at two sides of the pn junction when the single photon avalanche diode works. Referring to fig. 4, in combination with fig. 1, it can be seen that, by disposing the n-type doped region 112 on the side of the p-type doped region 111 away from the isolation region 120 and electrically connecting the n-type doped region 112 with the same doped region in the pn junction in the active region 110, when the active region is in operation, the boundary of the depletion region on one side of the p-type substrate region is pulled down, the depletion region contracted by the p-type doped region 111 can be widened, which helps to improve the efficiency of photon absorption and the probability of avalanche generation, and the p-type doped region 111 and the n-type doped region 112 can isolate defects generated at the isolation trench, so that the dark count rate of the single photon avalanche diode can be reduced. That is to say, the single photon avalanche diode of the embodiment of the invention can have both lower dark counting rate and higher photon detection efficiency, thereby having better detection performance.

In order to better implement the above scheme of the embodiment of the present invention, a method for manufacturing a single photon avalanche diode is also provided below, which can be used for manufacturing the single photon avalanche diode described in the above embodiment. In the drawings, the thickness of layers and regions are exaggerated for convenience of explanation, and the illustrated size does not represent an actual size. Reference to the figures is a schematic illustration of idealized embodiments of the present invention and the embodiments shown in the figures should not be construed as limited to the particular shapes of regions shown in the figures but are to include shapes resulting from manufacturing, such as deviations that result from manufacturing.

Fig. 5 is a schematic flow chart of a method for manufacturing a single photon avalanche diode according to an embodiment of the present invention. Referring to fig. 5, the method for manufacturing the single photon avalanche diode of the embodiment of the invention includes the following steps:

step S1, providing a substrate, wherein the substrate comprises an active region and an isolation region for limiting the active region;

step S2, performing p-type ion implantation and n-type ion implantation on the substrate respectively, and forming a p-type doped region and an n-type doped region which are sequentially and adjacently arranged along the direction far away from the isolation region and longitudinally extend along the thickness direction of the substrate respectively in the edge region of the active region close to the isolation region;

step S3, forming a pn junction in the active region for generating photon triggered avalanche current, and electrically connecting the n-type doped region with a doped region in the pn junction having the same doping type as the n-type doped region.

Fig. 6A to 6F are schematic cross-sectional structures of a single photon avalanche diode according to a method for manufacturing a single photon avalanche diode according to an embodiment of the present invention. Referring to fig. 6A to 6F, in one embodiment, the fabrication of the single photon avalanche diode includes the following processes:

first, as shown in fig. 6A, a substrate 100 is provided, the substrate 100 includes an active region 110 and an isolation region 120 for defining the active region 110, a Shallow Trench Isolation (STI) is formed from a front surface of the substrate of the isolation region 120, and an upper surface of the substrate 100 has a pad oxide layer (not shown) for protecting the substrate surface at the time of ion implantation;

next, as shown in fig. 6B, a first MASK pattern (labeled MASK1) for performing p-type ion implantation, such as a patterned photoresist layer (PR), is formed on the substrate 100, the opening of the first MASK pattern exposing the isolation region 120 and a portion of the active region 110 adjacent to the isolation region 120;

then, as shown in fig. 6C, p-type ion implantation is performed using the first mask pattern, for example, p-type ion implantation is performed several times from different depths, and p-type dopants (such as boron B or boron difluoride BF) are implanted from deep to shallow with a concentration gradient by adjusting the implantation energy₂) So as to be in the edge region of the active region 110 and the isolation region 120 forming a p-type ion doped region 111' extending longitudinally in a thickness direction of the substrate 100;

next, as shown in fig. 6D, a widening operation (descum) is performed on the patterned photoresist layer as a first MASK pattern, and the formed photoresist layer is used as a second MASK pattern (marked as MASK2) for performing n-type ion implantation, wherein an opening of the second MASK pattern covers an opening range of the first MASK pattern MASK1 and an opening boundary is enlarged (i.e., a line width is increased);

then, As shown in fig. 6E, n-type ion implantation is performed by using a second mask pattern, for example, n-type ion implantation is performed several times from different depths, and n-type dopants (such As phosphorus P or arsenic As) are implanted from deep to shallow according to a certain concentration gradient by adjusting the implantation energy, so As to form a P-type doped region 111 and an n-type doped region 112, which are sequentially and adjacently disposed along a direction away from the isolation region 120, in an edge region of the active region 110 close to the isolation region 120;

next, as shown in fig. 6F, the photoresist layer as the second mask pattern is removed.

Through the above process, steps S1 and S2 shown in fig. 5 are completed. In step S2, the second mask pattern is formed by the widening operation, so that a mask process dedicated to forming the second mask pattern can be omitted. In addition, when the n-type ion implantation is performed using the second mask pattern, since the n-type dopant is also implanted into the p-type ion doped region at the same time, in order to satisfy the p-type doping concentration of the p-type doped region 111 formed in the p-type ion doped region after the n-type ion implantation is completed, the n-type ion implantation concentration in step S2 should be lower than the p-type ion implantation concentration.

The above step S2 is not limited to being performed by the method in the manufacturing process shown in fig. 6A to 6F. In another embodiment, the first mask pattern is used to perform p-type ion implantation, and the second mask pattern is used to perform n-type ion implantation to form the above-described p-type doped region 111 and n-type doped region 112, but the opening of the second mask pattern does not overlap the opening of the first mask pattern. In this embodiment, the first mask pattern may be used to perform p-type ion implantation several times from different depths, respectively, to form a p-type doped region 111 in the edge region of the active region 110 close to the isolation region 120, and then the second mask pattern may be used to perform n-type ion implantation several times from different depths, respectively, to form an n-type doped region 112 on the side of the p-type doped region 111 away from the isolation region 120. But not limited thereto, in another embodiment, a portion of the open region of the first mask pattern for performing p-type ion implantation overlaps a portion of the open region of the second mask pattern for performing n-type ion implantation, in this embodiment, p-type ion implantation is performed using the first mask pattern to form a p-type ion doped region, and then n-type ion implantation is performed using the second mask pattern to form an n-type ion doped region, and the p-type ion doped region outside the overlapping region may be the p-type doped region 111, and the n-type ion doped region outside the overlapping region may be the n-type doped region 112, in this case, the overlapping region is a gap between the p-type doped region 111 and the n-type doped region 112. In the above embodiments, the p-type ion implantation process is performed first and then the n-type ion implantation process is performed, but the invention is not limited thereto, and the n-type ion implantation process and then the p-type ion implantation process may be performed first.

After the above steps S1 and S2 are completed, step S3 is performed to form a pn junction for generating a photon triggered avalanche current in the active region 110 and to electrically connect the n-type doped region 112 with the same kind of doped region in the pn junction. The pn junction can adopt a structure as shown in fig. 2 or fig. 3 or a structure disclosed in the field, and an ion implantation region constituting the pn junction can be formed by performing corresponding ion implantation. In the process of forming the pn junction, the n-type doped region (e.g., n-type well) and the n-type doped region 112 constituting the pn junction may be directly contacted and electrically connected, but the two regions are not directly contacted with each other in the active region, and after the pn junction is formed, an electrical interconnection structure (refer to the electrical interconnection structure 200 in fig. 2 and 3) is further formed above the substrate 100, and the n-type doped region 112 and the n-type doped region (e.g., n-type well) of the pn junction are electrically connected by using the electrical interconnection structure.

In addition, after step S2 is executed, the method for manufacturing a single photon avalanche diode further includes: the substrate 100 of the isolation region 120 is etched from the back side to form a trench exposing a Shallow Trench Isolation (STI), and then the trench is filled with an isolation medium to form a Deep Trench Isolation (DTI) connected to the exposed STI. The shallow trench isolation and the deep trench isolation may be used as the isolation trench 121 as shown in fig. 2 and 3. The above-mentioned methods for forming the pn junction and the isolation trench 121 can refer to the processes disclosed in the art, and are not described herein.

According to the manufacturing method of the single photon avalanche diode, the formed single photon avalanche diode not only has a low dark counting rate, but also has high photon detection efficiency, and therefore detection performance is good. Further, the manufacturing process shown in fig. 6A to 6F is used to form the p-type doped region 111 and the n-type doped region 112 in the substrate 100, and the second mask pattern is manufactured by the widening operation, so that a mask process dedicated for forming the second mask pattern can be omitted, the manufacturing is convenient, and the cost is low.

The embodiment of the present invention further relates to a single photon avalanche diode array, which includes a plurality of single photon avalanche diodes arranged in an array, each single photon avalanche diode has the features described in the above embodiments, and adjacent single photon avalanche diodes can be isolated by the isolation trench 121. In the single photon avalanche diode array, the p-type doping area 111 and the n-type doping area 112 of each single photon avalanche diode play a role in isolating defects generated at an isolation groove, so that dark counting caused by the defects can be effectively reduced, in addition, the n-type doping area 112 is electrically connected with the same doping area in a pn junction in the active area 110, a depletion area contracted due to the p-type doping area 111 can be widened, the photon absorption efficiency and the avalanche generation probability are favorably improved, the photon detection efficiency of a single photon avalanche diode device is not influenced while the dark counting rate of the single photon avalanche diode device is reduced, and therefore, the single photon avalanche diode array can realize excellent detection performance.

The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.