阅读说明：本技术 一种低emi自动变频的pwm控制电路 (PWM control circuit of low EMI automatic frequency conversion ) 是由 陈艳波 冯延蓬 李云杰 何国坤 于 2021-08-11 设计创作，主要内容包括：一种低EMI自动变频的PWM控制电路,包括自动变频控制模块、频率可编程时钟模块和PWM模块；自动变频控制模块的输出为CTRL<11:0>,连接到频率可编程时钟模块；频率可编程时钟模块的输出时钟CLK作为PWM模块的源时钟；PWM模块的输出PWMOUT为最终的PWM输出信号,而输出信号PWMTRG为自动变频控制模块的输入；该自动变频控制模块包含一个定时器和一个加减法器,且需要设置定时计数寄存器、中心频率寄存器、步进寄存器和步进计数寄存器；该PWM模块由预分频器、16位的计数器和比较器组成。本发明不仅实现了很好的出雾效果,并在不增加硬件成本的条件下,有效降低了EMI。(A PWM control circuit with low EMI automatic frequency conversion comprises an automatic frequency conversion control module, a frequency programmable clock module and a PWM module; the output of the automatic frequency conversion control module is CTRL <11:0> and is connected to the frequency programmable clock module; the output clock CLK of the frequency programmable clock module is used as the source clock of the PWM module; the output PWMOUT of the PWM module is a final PWM output signal, and the output signal PWMTRG is the input of the automatic frequency conversion control module; the automatic frequency conversion control module comprises a timer and an adder-subtractor, and a timing counting register, a central frequency register, a stepping register and a stepping counting register are required to be arranged; the PWM module consists of a prescaler, a 16-bit counter and a comparator. The invention not only realizes good mist generation effect, but also effectively reduces EMI without increasing hardware cost.)

1. A PWM control circuit with low EMI automatic frequency conversion is characterized by comprising an automatic frequency conversion control module, a frequency programmable clock module and a PWM module;

the output of the automatic frequency conversion control module is CTRL <11:0> and is connected to the frequency programmable clock module;

the output clock CLK of the frequency programmable clock module is used as the source clock of the PWM module;

the output PWMOUT of the PWM module is a final PWM output signal, and the output signal PWMTRG is the input of the automatic frequency conversion control module;

the automatic frequency conversion control module comprises a timer and an adder-subtractor, and a timing counting register, a central frequency register, a stepping register and a stepping counting register are required to be arranged;

the timer is an 8-bit timer, and TUNM <7:0> is a timing counting register of the timer and is used for updating the frequency of the primary source clock after setting the number of PWM cycles; the PWMTRG signal is used as an input clock of a timer, the timer starts counting from 0, and 1 is added to the timer every time when one PWMTRG signal comes; when the counting value of the timer is equal to the value of TNUM <7:0>, a trigger signal TRIG of an adder-subtractor is generated, and counting is started from the value of 0 again;

the adder-subtractor is a 12-bit counter, and each time the adder-subtractor is triggered by a TRIG signal, a value is calculated once; CENTER <11:0> is the value of the central frequency register, and is the source clock value set according to the resonance frequency of the atomizing sheet; the value of the adder-subtractor is CENTER <11:0> at the beginning, and the value of the STEP register STEP <7:0> is added when the trigger works; the 8-bit step counter in the step counter is added with 1, and the initial value of the step counter is the value of a step counting register STEPNUM <7:0 >; then, every time the adder-subtractor is triggered, one STEP <7:0> is added, and the STEP counter is added with 1; until the value of the STEP counter equals 2 × STEPNUM <7:0>, the adder-subtractor will change the direction, the adder-subtractor triggers once, will subtract one STEP <7:0>, and the STEP counter subtracts 1, until the value of the STEP counter is 0, change the direction of the adder-subtractor again;

the output result CTRL <11:0> of the adder-subtractor is used as an adjusting control signal of a frequency programmable clock module, and the frequency programmable clock module adopts an oscillator structure of a current mirror array to realize the precise monotonous linear adjusting clock frequency; the clock range of the frequency programmable clock module is 18 MHz-36 MHz, and the frequency programmable clock module has 12 bit adjusting signals; assuming that the frequency of the central clock is 24MHz, the minimum adjustable step which can be realized is 4.4KHz, and the precision reaches 0.18 per thousand;

the PWM module consists of a prescaler, a 16-bit counter and a comparator;

the output clock CLK of the frequency programmable clock module is used as the source clock of the PWM module, the prescaler divides the frequency of the source clock again, DIV <7:0> is a prescaler register, and the output signal CKD of the prescaler is the clock of the counter;

the counter initially starts counting from 0, increments by 1 every clock, clears 0 and recounts when the counter value CNT <15:0> equals the value of the period register PERD <15:0 >; and simultaneously generating a high-level PWMTRG signal with the pulse width of one period and outputting the signal to the automatic frequency conversion control module;

the comparator will compare CNT <15:0> with the value of the compare register CMP <15:0>, and when CNT <15:0> is less than or equal to CMP <15:0>, the output PWMOUT of the PWM module is high; the output PWMOUT of the PWM module is low when CNT <15:0> is greater than CMP <15:0 >.

Technical Field

The invention relates to the field of integrated circuits related to atomization electronic technology, in particular to a Pulse Width Modulation (PWM) control circuit with low EMI (electromagnetic interference) automatic frequency conversion.

Background

The ultrasonic atomization technology is mainly applied to electronic and electrical equipment such as a humidifier, an aromatherapy machine, an atomization electronic cigarette and an atomizer, and the technology utilizes high-frequency resonance of an atomization sheet to break up a natural structure of liquid and form water mist.

The resonance frequency of the commonly used atomization plate is 1.7MHz, 2.4MHz, 3MHz and 3.3MHz, and the resonance of the atomization plate is generally realized by controlling a power switch through a PWM (Pulse Width Modulation) signal. When the PWM frequency is the same as the central resonance frequency of the atomization plate, the atomization plate has the maximum resonance amplitude and the highest conversion efficiency, and the atomization effect is optimal. However, the main frequency signal of the atomizing plate and its higher harmonics will oscillate on a PCB (Printed Circuit Board) Board, which becomes a main EMI (electromagnetic interference) interference source and seriously interferes with the transmission of other signals.

In order to enable the atomizer to pass the EMI test smoothly, the EMI interference is reduced by generally adding a capacitor and a magnetic bead on a circuit board or changing hardware rectification modes such as PCB wiring and the like. This not only increases the hardware cost on the PCB board, but also increases the debug cost of the solution. At present, there is a scheme that changes the PWM frequency by a software frequency conversion method to reduce the signal strength near the resonance main frequency, so as to reduce the strength of EMI interference. However, the step of the software frequency conversion is very large, and if 1.7MHz PWM is generated by taking a 170MHz clock as a source clock, the minimum step for changing the PWM frequency also reaches 1%. This causes the PWM frequency after frequency conversion to shift too much from the center resonant frequency, resulting in low conversion efficiency, poor mist generation effect, and low mist generation amount. And the software frequency conversion speed is relatively slow, and the effect of reducing EMI interference is not obvious.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the invention provides a low-EMI automatic frequency conversion PWM control circuit, which can realize good fog generation effect and effectively reduce EMI without increasing hardware cost.

In order to solve the technical problems, the invention provides the following technical scheme: a PWM control circuit with low EMI automatic frequency conversion is characterized by comprising an automatic frequency conversion control module, a frequency programmable clock module and a PWM module;

the output of the automatic frequency conversion control module is CTRL <11:0> and is connected to the frequency programmable clock module;

the output clock CLK of the frequency programmable clock module is used as the source clock of the PWM module;

the output PWMOUT of the PWM module is a final PWM output signal, and the output signal PWMTRG is the input of the automatic frequency conversion control module;

the automatic frequency conversion control module comprises a timer and an adder-subtractor, and a timing counting register, a central frequency register, a stepping register and a stepping counting register are required to be arranged;

the timer is an 8-bit timer, and TUNM <7:0> is a timing counting register of the timer and is used for updating the frequency of the primary source clock after setting the number of PWM cycles; the PWMTRG signal is used as an input clock of a timer, the timer starts counting from 0, and 1 is added to the timer every time when one PWMTRG signal comes; when the counting value of the timer is equal to the value of TNUM <7:0>, a trigger signal TRIG of an adder-subtractor is generated, and counting is started from the value of 0 again;

the adder-subtractor is a 12-bit counter, and each time the adder-subtractor is triggered by a TRIG signal, a value is calculated once; CENTER <11:0> is the value of the central frequency register, and is the source clock value set according to the resonance frequency of the atomizing sheet; the value of the adder-subtractor is CENTER <11:0> at the beginning, and the value of the STEP register STEP <7:0> is added when the trigger works; the 8-bit step counter in the step counter is added with 1, and the initial value of the step counter is the value of a step counting register STEPNUM <7:0 >; then, every time the adder-subtractor is triggered, one STEP <7:0> is added, and the STEP counter is added with 1; until the value of the STEP counter equals 2 × STEPNUM <7:0>, the adder-subtractor will change the direction, the adder-subtractor triggers once, will subtract one STEP <7:0>, and the STEP counter subtracts 1, until the value of the STEP counter is 0, change the direction of the adder-subtractor again;

the output result CTRL <11:0> of the adder-subtractor is used as an adjusting control signal of a frequency programmable clock module, and the frequency programmable clock module adopts an oscillator structure of a current mirror array to realize the precise monotonous linear adjusting clock frequency; the clock range of the frequency programmable clock module is 18 MHz-36 MHz, and the frequency programmable clock module has 12 bit adjusting signals; assuming that the frequency of the central clock is 24MHz, the minimum adjustable step which can be realized is 4.4KHz, and the precision reaches 0.18 per thousand;

the PWM module consists of a prescaler, a 16-bit counter and a comparator;

the output clock CLK of the frequency programmable clock module is used as the source clock of the PWM module, the prescaler divides the frequency of the source clock again, DIV <7:0> is a prescaler register, and the output signal CKD of the prescaler is the clock of the counter;

the counter initially starts counting from 0, increments by 1 every clock, clears 0 and recounts when the counter value CNT <15:0> equals the value of the period register PERD <15:0 >; and simultaneously generating a high-level PWMTRG signal with the pulse width of one period and outputting the signal to the automatic frequency conversion control module;

the comparator will compare CNT <15:0> with the value of the compare register CMP <15:0>, and when CNT <15:0> is less than or equal to CMP <15:0>, the output PWMOUT of the PWM module is high; the output PWMOUT of the PWM module is low when CNT <15:0> is greater than CMP <15:0 >.

Compared with the prior art, the invention has the following beneficial effects: according to the invention, through a design method of a hardware integrated circuit, rapid and small-step automatic frequency conversion of the PWM control signal of the atomizing sheet is realized, and on the premise of ensuring the mist outlet effect, the EMI interference is effectively reduced, the hardware cost is saved, and the scheme debugging difficulty is reduced.

Drawings

Fig. 1 is a block diagram of a PWM control circuit for low EMI automatic frequency conversion according to the present invention.

Fig. 2 is a block diagram of an automatic frequency conversion control module.

FIG. 3 is a waveform diagram of the output frequency of the frequency programmable clock module.

FIG. 4 is a block diagram of a PWM module

Detailed Description

Please refer to fig. 1, which is a block diagram of a PWM control circuit for low EMI automatic frequency conversion according to the present invention.

The PWM control circuit with the low EMI automatic frequency conversion comprises an automatic frequency conversion control module, a frequency programmable clock module and a PWM module.

The output of the automatic frequency conversion control module is CTRL <11:0> and is connected to the frequency programmable clock module.

The output clock CLK of the frequency programmable clock module is used as the source clock of the PWM module.

The output PWMOUT of the PWM module is the final PWM output signal and the output signal PWMTRG is the input of the automatic frequency conversion control module.

As shown in fig. 2, it is a block diagram of the structure of the automatic frequency conversion control module. The automatic frequency conversion control module comprises a timer and an adder-subtractor, and a timing counting register, a central frequency register, a stepping register and a stepping counting register are required to be arranged.

The timer is an 8-bit timer, and TUNM <7:0> is a timing counting register of the timer and is used for updating the source clock frequency once after setting how many PWM cycles. The PWMTRG signal is used as an input clock of a timer, the timer starts counting from 0, and 1 is added to the timer every time when one PWMTRG signal comes; when the timer count equals TNUM <7:0>, an adder-subtractor trigger signal TRIG is generated and starts counting again from 0.

The adder-subtractor is a 12-bit counter, and each time triggered by the TRIG signal, the value is calculated once. CENTER <11:0> is the value of the CENTER frequency register, which is the source clock value set according to the resonant frequency of the atomizing plate. The adder-subtractor has a CENTER <11:0> value initially, and a STEP register STEP <7:0> value is added during the trigger operation. The 8-bit step counter in the step counter is added with 1, and the initial value of the step counter is the value of a step counting register STEPNUM <7:0 >; then every time the adder-subtractor triggers, one STEP <7:0> is added, and the STEP counter is added with 1. Until the value of the STEP counter equals 2 × STEPNUM <7:0>, the adder-subtractor changes the direction, the adder-subtractor subtracts one STEP <7:0> every time the adder-subtractor is triggered, and the STEP counter subtracts 1 until the value of the STEP counter is 0, and then the direction of the adder-subtractor is changed.

The output result CTRL <11:0> of the adder-subtractor is used as an adjusting control signal of the frequency programmable clock module, and the frequency programmable clock module can adopt an oscillator structure of a current mirror array to realize the precise monotonous linear adjusting clock frequency. The clock range of the frequency programmable clock module is 18 MHz-36 MHz, and the frequency programmable clock module has 12 bit adjusting signals. Assuming that the central clock frequency is 24MHz, the minimum adjustment step which can be realized is 4.4KHz, and the precision reaches 0.18 per thousand.

As shown in fig. 3, which is the output frequency waveform of the frequency programmable clock module, CENTER <11:0> -400H, STEP <7:0> -2H and STEP num <7:0> -4H are set, and it can be seen that the frequency fclk of the CLK signal varies with the CTRL <11:0> signal STEPs.

As shown in fig. 4, it is a block diagram of the PWM module. The PWM module consists of a prescaler, a 16-bit counter and a comparator.

The output clock CLK of the frequency programmable clock module is used as the source clock of the PWM module, the prescaler divides the frequency of the source clock again, DIV <7:0> is a prescaler register, and the output signal CKD of the prescaler is the clock of the counter.

The counter initially starts counting from 0, increments by 1 every clock, and clears 0 and re-counts when the counter value CNT <15:0> equals the value of the period register PERD <15:0 >. And simultaneously generates a high-level PWMTRG signal with the pulse width of one period and outputs the signal to the automatic frequency conversion control module.

The comparator will compare CNT <15:0> with the value of the compare register CMP <15:0>, and when CNT <15:0> is less than or equal to CMP <15:0>, the output PWMOUT of the PWM module is high; the output PWMOUT of the PWM module is low when CNT <15:0> is greater than CMP <15:0 >.

The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment. The technical effects of the invention can be achieved by the same means, and the technical effects belong to the protection scope of the invention.