阅读说明：本技术 半导体结构的制备方法 (Method for manufacturing semiconductor structure ) 是由 朱一明 应战 张强 于 2020-05-20 设计创作，主要内容包括：本发明提供一种半导体结构的制备方法,其包括：提供具有若干个第一沟槽的衬底,相邻所述第一沟槽之间形成有第一图案；形成第一介质层,所述第一介质层至少覆盖所述第一图案的侧壁；形成第二介质层,所述第二介质层填充所述第一沟槽；隔断所述第一图案形成第二图案；去除所述第二介质层。其优点是：通过至少在第一图案的侧壁上形成第一介质层作为保护层,这样当对第一图案进行刻蚀形成第二图案时,由于第一图案的侧壁始终受到第一介质层的保护,由隔断形成的第二图案所构成的有源区的末端在刻蚀过程中就不容易遭到破坏。(The invention provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate with a plurality of first grooves, wherein a first pattern is formed between every two adjacent first grooves; forming a first dielectric layer at least covering the side wall of the first pattern; forming a second dielectric layer, wherein the second dielectric layer fills the first groove; cutting off the first pattern to form a second pattern; and removing the second dielectric layer. The advantages are that: by forming the first dielectric layer as a protective layer on at least the side wall of the first pattern, when the first pattern is etched to form the second pattern, the side wall of the first pattern is always protected by the first dielectric layer, so that the tail end of an active area formed by the second pattern formed by the partition is not easily damaged in the etching process.)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate with a plurality of first grooves, wherein a first pattern is formed between every two adjacent first grooves;

forming a first dielectric layer at least covering the side wall of the first pattern;

forming a second dielectric layer, wherein the second dielectric layer fills the first groove;

cutting off the first pattern to form a second pattern;

and removing the second dielectric layer.

2. The method of claim 1, wherein forming the first dielectric layer to cover at least sidewalls of the first pattern comprises:

and forming a first dielectric layer on the side wall of the first pattern and the bottom of the first groove.

3. The method of claim 1, wherein forming the first dielectric layer to cover at least sidewalls of the first pattern comprises:

and forming the first dielectric layer on the side wall of the first pattern, the bottom of the first groove and the upper surface of the first pattern.

4. The method of claim 2 or 3, further comprising, after forming the first dielectric layer and before forming the second dielectric layer:

and removing the first dielectric layer at the bottom of the first trench.

5. The method of claim 1, wherein:

the width of the first pattern is less than or equal to 20 nm.

6. The method of claim 5, wherein:

the distance between the adjacent first patterns is less than or equal to 30 nm.

7. The method of claim 1, wherein the hardness of the first dielectric layer is greater than the hardness of the second dielectric layer.

8. The method of claim 7, wherein:

the first dielectric layer comprises a silicon dioxide layer.

9. The method of claim 7, wherein:

the second dielectric layer comprises a spin-on carbon layer or a spin-on glass layer.

10. The method of claim 1, wherein:

blocking the first pattern to form the second pattern includes: forming a plurality of second grooves on each of the first patterns to divide each of the first patterns into a plurality of second patterns.

11. The method of claim 10, wherein:

after removing the second dielectric layer, the method further comprises the following steps: filling a third dielectric layer in the first groove and the second groove, wherein the third dielectric layer fills the first groove and the second groove; and the first dielectric layer is not present between the third dielectric layer in the second trench and the second pattern.

12. The method of claim 11, wherein:

the third dielectric layer comprises a silicon dioxide layer.

13. The method of claim 10, wherein forming a plurality of second trenches over each of the first patterns to divide each of the first patterns into a plurality of second patterns comprises:

forming a mask layer on the upper surface of the substrate;

carrying out graphical processing on the mask layer to obtain a graphical mask layer, wherein the graphical mask layer comprises a plurality of opening patterns penetrating through the mask layer, and the positions and the shapes of the second grooves are defined by the opening patterns;

and etching the first patterns based on the patterned mask layer to form a plurality of second grooves on each first pattern so as to divide each first pattern into a plurality of second patterns.

14. The method of claim 10, wherein:

the extending direction of the first pattern is oblique to the arrangement direction of the second grooves which are positioned in different columns and have adjacent shortest intervals.

15. The method of claim 10, wherein:

the depth of the first trench is greater than the depth of the second trench.

16. The method of claim 10, wherein:

the width of the first trench is smaller than the width of the second trench.

17. The method of claim 10, wherein:

the second groove only cuts off the first pattern, and the first dielectric layer on the side wall of the first pattern is not cut off.

18. The method of claim 17, wherein:

and isolating the first pattern by using an etching process in which the etching selection ratio of the first pattern to the first dielectric layer is greater than 8.

19. The method of claim 13, wherein:

the size of the opening pattern is larger than the width of the first pattern.

20. The method of claim 19, wherein:

the size of the second groove is smaller than 15nm, the thickness range of the first dielectric layer is 1nm-5nm, and the size of the opening pattern is smaller than 30 nm.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure.

Background

A Dynamic Random Access Memory (DRAM) is a semiconductor memory widely used in a multi-computer system, and as the technology of semiconductor integrated circuit devices is developed, the critical dimension of the DRAM is getting smaller, for example, the dimension of an Active Area (AA) is getting smaller, which requires a very high semiconductor manufacturing process, and when the width of an active area is very small, the end portion (the end of an elongated active area) is often damaged when the active area is etched by using the existing etching process.

Disclosure of Invention

Accordingly, it is necessary to provide a method for fabricating a semiconductor structure, which can avoid damage to the end portion of the active region when the active region is formed by etching, in order to solve the problem of damage to the end portion of the elongated active region during etching.

A method for fabricating a semiconductor structure, comprising:

providing a substrate with a plurality of first grooves, wherein a first pattern is formed between every two adjacent first grooves;

forming a first dielectric layer at least covering the side wall of the first pattern;

forming a second dielectric layer, wherein the second dielectric layer fills the first groove;

cutting off the first pattern to form a second pattern;

and removing the second dielectric layer.

In one embodiment, forming the first dielectric layer covering at least the sidewalls of the first pattern comprises:

and forming a first dielectric layer on the side wall of the first pattern and the bottom of the first groove.

In one embodiment, forming the first dielectric layer covering at least the sidewalls of the first pattern comprises:

and forming the first dielectric layer on the side wall of the first pattern, the bottom of the first groove and the upper surface of the first pattern.

In one embodiment, after forming the first dielectric layer and before forming the second dielectric layer, the method further includes:

and removing the first dielectric layer at the bottom of the first trench.

In one embodiment, the width of the first pattern is less than or equal to 20 nm.

In one embodiment, the distance between the adjacent first patterns is less than or equal to 30 nm.

In one embodiment, the hardness of the first dielectric layer is greater than the hardness of the second dielectric layer.

In one embodiment, the first dielectric layer comprises a silicon dioxide layer.

In one embodiment, the second dielectric layer comprises a spin-on carbon layer or a spin-on glass layer.

In one embodiment, blocking the first pattern to form the second pattern comprises: forming a plurality of second grooves on each of the first patterns to divide each of the first patterns into a plurality of second patterns.

In one embodiment, after removing the second dielectric layer, the method further includes: filling a third dielectric layer in the first groove and the second groove, wherein the third dielectric layer fills the first groove and the second groove; and the first dielectric layer is not present between the third dielectric layer in the second trench and the second pattern.

In one embodiment, the third dielectric layer comprises a silicon dioxide layer.

In one embodiment, forming a plurality of second trenches on each of the first patterns to divide each of the first patterns into a plurality of second patterns includes:

forming a mask layer on the upper surface of the substrate;

carrying out graphical processing on the mask layer to obtain a graphical mask layer, wherein the graphical mask layer comprises a plurality of opening patterns penetrating through the mask layer, and the positions and the shapes of the second grooves are defined by the opening patterns;

and etching the first patterns based on the patterned mask layer to form a plurality of second grooves on each first pattern so as to divide each first pattern into a plurality of second patterns.

In one embodiment, the extending direction of the first pattern is oblique to the arrangement direction of the second trenches located at the adjacent shortest intervals in different columns.

In one embodiment, the depth of the first trench is greater than the depth of the second trench.

In one embodiment, the width of the first trench is smaller than the width of the second trench.

In one embodiment, the second trench only blocks the first pattern, and the first dielectric layer on the sidewall of the first pattern is not blocked.

In one embodiment, the first pattern is isolated by an etching process in which the etching selectivity ratio of the first pattern to the first dielectric layer is greater than 8.

In one embodiment, the size of the opening pattern is larger than the width of the first pattern.

In one embodiment, the size of the second trench is less than 15nm, the thickness of the first dielectric layer ranges from 1nm to 5nm, and the size of the opening pattern is less than 30 nm.

According to the preparation method of the semiconductor structure, the first dielectric layer is at least formed on the side wall of the first pattern to serve as the protective layer, so that when the first pattern is etched to form the second pattern, the side wall of the first pattern is always protected by the first dielectric layer, and the tail end of the active region formed by the second pattern formed by separation is not easily damaged in the etching process.

Drawings

FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

fig. 2 is a schematic perspective view of the substrate with a plurality of first trenches obtained in step S1 according to the method for fabricating a semiconductor structure of the present invention;

fig. 3 is a schematic perspective view of the semiconductor structure obtained in step S2 in the method for fabricating a semiconductor structure according to the present invention;

FIG. 4 is a schematic perspective view of a semiconductor structure obtained after removing the first dielectric layer at the bottom of the first trench in an embodiment of the method for fabricating a semiconductor structure according to the present invention;

fig. 5 is a schematic perspective view of the semiconductor structure obtained in step S3 in the method for manufacturing the semiconductor structure according to the embodiment of the invention;

fig. 6 is a schematic perspective view of the semiconductor structure obtained in step S42 in the method for manufacturing the semiconductor structure according to the embodiment of the invention;

fig. 7 is a schematic perspective view of the semiconductor structure obtained in step S5 in the method for manufacturing the semiconductor structure according to the embodiment of the invention;

fig. 8 is a schematic perspective view of the semiconductor structure obtained in step S6 in the embodiment of the method for manufacturing a semiconductor structure according to the present invention.

Reference numerals: 1. a substrate; 11. a first pattern; 111. a second pattern; 112. a second trench; 12. a first trench; 2. a first dielectric layer; 3. patterning the mask layer; 31. opening patterns; 4. a second dielectric layer; 5. and a third dielectric layer.

Detailed Description

For better understanding of the objects, technical solutions and effects of the present invention, the present invention will be further explained with reference to the accompanying drawings and examples. Meanwhile, the following described examples are only for explaining the present invention, and are not intended to limit the present invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Where the terms "comprising," "having," and "including" are used herein, another component or method can be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.

In the existing semiconductor process, a one-step etching process is adopted to perform dry etching on a substrate to form a shallow trench in the substrate so as to isolate a plurality of active regions in the substrate, and then an insulating material layer is filled in the shallow trench to form a trench isolation structure. Then, especially with the decreasing of the design size of the semiconductor structure, the tail end of the active region becomes more and more slender, when the substrate is directly etched by using the dry etching process to form the active region, because the etching gas contains high-energy charged particles or radicals, when the substrate is bombarded by the charged particles or radicals to form a shallow trench, the tail end of the active region can be damaged or destroyed; adversely affecting device performance.

Therefore, in view of the above problems, there is a need for a method for fabricating a semiconductor structure to reduce the damage to the end of the active region caused by the etching process.

As shown in fig. 1, the present invention provides a method for fabricating a semiconductor structure, which comprises:

s1: providing a substrate with a plurality of first grooves, wherein a first pattern is formed between every two adjacent first grooves;

s2: forming a first dielectric layer at least covering the side wall of the first pattern;

s3: forming a second dielectric layer, wherein the second dielectric layer fills the first groove;

s4: blocking the first pattern to form a second pattern;

s5: and removing the second dielectric layer.

The preparation method of the semiconductor structure comprises the steps of forming a first dielectric layer on the side wall of a first pattern in a substrate to serve as a protective layer, and then separating the first pattern to form a second pattern to obtain an active region formed by the second pattern, so that when the first pattern is separated to form the second pattern forming the active region, the side wall of the first pattern is always protected by the first dielectric layer, and the tail end of the second pattern formed by separation (namely the tail end of the active region) can be well protected in the separation process.

Referring to fig. 2, step S1 may include the following steps:

s11: providing a substrate 1;

s12: the substrate 1 is etched to form first trenches 12 in the substrate 1, and first patterns 11 are formed between adjacent first trenches 12.

By way of example, the substrate 1 includes, but is not limited to, a silicon substrate, a gallium nitride substrate, a silicon-on-insulator or silicon carbide substrate, and the like, and in the present embodiment, the substrate 1 may be a silicon substrate. A doped well region formed by an ion implantation process may be formed in the substrate 1, and a doping type of the doped well region may be P-type or N-type.

As an example, the first pattern 11 and the first trench 12 form a stripe array structure, wherein the first pattern 11 is a plate-shaped wall structure, and specifically, the first pattern 11 may be, but is not limited to, a rectangular plate-shaped wall structure; the plurality of first patterns 11 are arranged in an interval array, and a first groove 12 is formed between every two adjacent first patterns 11; specifically, the plurality of first patterns 11 are arranged in parallel at intervals.

As an example, as shown in fig. 2, the width d of the first pattern 11 in step S12, which is the length of the cross section perpendicular to the extending direction of the first pattern 11 in the horizontal direction along the substrate 1, may be set according to actual needs. Preferably, the width d of the first pattern 11 may be less than or equal to 20nm, and more specifically, the width d of the first pattern 11 may be 20nm, 15nm, 10nm, or the like, within which the technical problem described in the present invention is more prominent, and the technical solution described in this embodiment has better economical efficiency and beneficial technical effects; the distance L between adjacent first patterns 11 may be set according to actual needs, specifically, the distance L between adjacent first patterns 11 may be less than or equal to 30nm, and more specifically, the gap between adjacent first patterns 11 may be 30nm, 25nm, 20nm, 15nm, or 10nm, etc., but in other embodiments, the distance L between adjacent first patterns 11 is not limited to the above data. It should be noted that the pitch L ≦ 30nm between adjacent first patterns 11 as used herein refers to the center-to-center pitch between two adjacent first patterns 11.

As an example, a SADP (self-aligned double patterning) process or a SAQP (self-aligned quadruple patterning) process may be employed in step S12 to form a stripe array structure including a plurality of first patterns 11 and a plurality of first trenches 12 on the substrate 1. The SADP process and the SAQP process are known to those skilled in the art and will not be described herein.

As an example, referring to fig. 3, step S2 may include the following steps:

forming a first dielectric layer 2 on the side surface and the bottom of the first trench 12, wherein the first dielectric layer 2 serves as a protective layer; optionally, the first dielectric layer 2 may be further formed on the side surface of the first trench 12, the bottom of the first trench 12, and the upper surface of the first pattern 11, so that when the second trench is subsequently etched, the first dielectric layer 2 may effectively protect the first pattern 11.

Specifically, the thickness of the first dielectric layer 2 may be set according to actual needs, and more specifically, the thickness of the first dielectric layer 2 is smaller than half of the width of the first trench 12, and at this time, after the first dielectric layer 2 is formed, a gap is further formed in the first trench 12. Preferably, the thickness of the first dielectric layer 2 is in the range of 1nm to 5nm, and in this range, the first dielectric layer 2 can provide sufficient protection for the first pattern 11 and leave enough space for the subsequent third dielectric layer to fill.

As an example, the first dielectric layer 2 may be formed by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a thermal oxidation process, and the first dielectric layer 2 may include, but is not limited to, silicon dioxide (SiO) as a protective layer₂) A layer, a silicon oxide (SiO) layer, a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, or the like, and in this embodiment, the first dielectric layer 2 may be a silicon dioxide layer.

In one example, referring to fig. 4, after forming the first dielectric layer 2 and before forming the second dielectric layer 4, the method further includes: the first dielectric layer 2 at the bottom of the first trench 12 is removed. Therefore, the bottom of the first dielectric layer 2 is isolated to form a discontinuous isolation structure, so that too many carriers are not accumulated at the bottom of the first trench 12, and electric leakage caused by accumulation of holes or electrons in the substrate of the transistor near the first dielectric layer 2 is avoided. It should be noted that the first dielectric layer 2 at the bottom of the first trench 12 may be removed completely or partially, in this embodiment, all the first dielectric layer 2 at the bottom of the first trench 12 is removed. Specifically, the first dielectric layer 2 at the bottom of the first trench 12 may be removed by, but not limited to, a dry etching process.

Referring to fig. 5, step S3 may include the following steps:

and forming a second dielectric layer 4 in the first trench 12, wherein the second dielectric layer 4 fills the first trench 12.

By way of example, the second dielectric layer 4 may be formed using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a spin-on process. The material of the second dielectric layer 4 may be different from the material of the first dielectric layer 2; specifically, the hardness of the first dielectric layer 2 is greater than that of the second dielectric layer 4, so that the first dielectric layer 2 can provide good protection for the first pattern 11, and meanwhile, under the same etching condition, the removal rate of the second dielectric layer 4 is much greater than that of the first dielectric layer 2, so that the first dielectric layer 2 on the upper surface of the first pattern 11 is hardly removed when the second dielectric layer 4 is subsequently removed; more specifically, in the present embodiment, the second dielectric layer 4 may include, but is not limited to, a spin-on-carbon (SOC) layer, a spin-on-glass (SOG) layer, or the like. Of course, in other examples, any other material layer meeting the above criteria may be used herein.

More specifically, step S3 may include the following steps:

s31: forming a second dielectric material layer (not shown) filling the first trench 12 and covering the first dielectric layer 2 on the upper surface of the first pattern 11; specifically, the second dielectric material layer may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a spin coating process;

s32: removing the second dielectric material layer covering the first dielectric layer 2 on the upper surface of the first pattern 11, wherein the second dielectric material layer remained in the first trench 12 is the second dielectric layer 4; specifically, the second dielectric material layer covering the first dielectric layer 2 on the upper surface of the first pattern 11 may be removed by, but not limited to, a chemical mechanical polishing process. In other embodiments, the second dielectric material layer is further located on the first dielectric layer 2 on the upper surface of the first pattern 11, and the second dielectric material layer on the first dielectric layer 2 on the upper surface of the first pattern 11 and the second dielectric material layer in the first trench 12 have a continuous flat upper surface.

Step S4 includes the following steps: a plurality of second grooves 112 are formed on each first pattern 11 to divide each first pattern 11 into a plurality of second patterns 111.

Specifically, step 4 may include the following steps:

s41: forming a mask layer on the upper surface of the substrate 1;

s42: performing patterning processing on the mask layer to obtain a patterned mask layer 3, where the patterned mask layer 3 includes a plurality of opening patterns 31 penetrating through the mask layer, and the opening patterns 31 define the positions and shapes of the second trenches 112, as shown in fig. 6; alternatively, the shape of the opening pattern 31 may be circular, elliptical, rectangular, or the like

S43: etching the first patterns 11 based on the patterned mask layer 3 to form a plurality of second trenches 112 on each of the first patterns 11, so as to divide each of the first patterns 11 into a plurality of second patterns 111;

s44: the patterned mask layer 3 is removed.

As an example, in step S41, the mask layer may include, but is not limited to, an amorphous carbon layer, a silicon oxynitride layer, a silicon oxide layer, or a combination of at least two of the foregoing. Specifically, the mask layer may be formed by at least one of a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, and a spin coating process.

As an example, in step S42, the mask layer may be patterned based on a photolithography process to obtain a patterned mask layer 3; in another example, the size of the opening pattern 31 is larger than the width of the first pattern 11, and specifically, the size of the opening pattern 31 may be a size in a width direction of the first pattern 11, or may be a maximum size in a horizontal direction of the substrate. For example, the width of the first pattern 11 is less than or equal to 20nm, the size of the second trench 112 is less than or equal to 15nm, the thickness of the first dielectric layer 2 ranges from 1nm to 5nm, and the size of the opening pattern 31 is less than 30 nm. The size of the opening pattern 31 is larger than the width of the first pattern 11, which is beneficial to increasing the process window and improving the product yield. It should be noted that the size of the second trench 112 may be a size in a width direction of the first pattern 11, and may also be a maximum size in a substrate horizontal direction.

As an example, in step S43, the first pattern 11 may be etched based on the patterned mask layer 3 by using a dry etching process; in another example, the second trench 112 only blocks the first pattern 11, and the first dielectric layer 2 on the sidewall of the first pattern 11 is not blocked, specifically, the second trench 112 is formed by etching the first pattern 11 using the opening pattern 31 and an etching process with an etching selectivity ratio of the first pattern 11 to the first dielectric layer 2 being greater than 8, the second pattern 111 is formed between the first trench 12 and the second trench 112, and the first dielectric layer 2 on the sidewall of the first pattern 11 is not blocked by etching. Only the first pattern 11 is etched and isolated by utilizing the high etching selection ratio process, the complete first dielectric layer 2 is reserved, the shape of the end part of the formed second pattern 111 can be better ensured, and the performance of the device is further improved.

As an example, in step S44, an etching process or a chemical mechanical polishing process may be used to remove patterned mask layer 3.

Referring to FIG. 7, in one embodiment: the extending direction of the first pattern 11 is oblique to the arrangement direction of the second trenches 112 located at the adjacent shortest pitches in different columns. Specifically, the second grooves 112 on the same first pattern 11 are arranged at intervals, and the second grooves 112 on adjacent first patterns 11 are arranged in a staggered manner; more specifically, the second trenches 112 in the first patterns 11 in the adjacent odd-numbered columns are staggered with the second trenches 112 in the first patterns 11 in the adjacent even-numbered columns, the second trenches 112 in the first patterns 11 in the adjacent odd-numbered columns are arranged in a one-to-one correspondence manner, and the second trenches 112 in the first patterns 11 in the adjacent even-numbered columns are arranged in a one-to-one correspondence manner. In particular, the first pattern is an active region of the memory device, and the arrangement is advantageous for maximizing the storage density of the memory device.

In another embodiment: referring to fig. 2 and 7, the depth H1 of the first trench 12 may be greater than or equal to the depth H2 of the second trench 112, in this embodiment, the depth H1 of the first trench 12 may be greater than the depth H2 of the second trench 112, and the depth of the first trench 12 is greater than the depth of the second trench 112, so that the isolation effect is better, and the adjacent active regions are prevented from being affected by each other.

In another embodiment: referring to fig. 2 and 7, the width D1 of the first trench 12 may be less than or equal to the width D2 of the second trench 112, in this embodiment, the width D1 of the first trench 12 may be less than the width D2 of the second trench 112; it is noted that the width of the second trench 112 refers to a dimension in the extending direction of the first pattern 11.

In step S5, the second dielectric layer 4 in the first trench 12 is removed, as shown in fig. 7.

As an example, the second dielectric layer 4 in the first trench 12 may be removed by a wet etching process or a dry etching process, specifically, in this embodiment, the second dielectric layer 4 in the first trench 12 is removed by a wet etching process, and more specifically, the second dielectric layer 4 in the first trench 12 is removed by an etching solution that can remove the second dielectric layer 4 in the first trench 12, but can hardly remove the first dielectric layer 2 on the upper surface of the first pattern 11 and can hardly remove the substrate 1.

In an embodiment, after removing the second dielectric layer 4 in the first trench 12, the method further includes:

s6: the third dielectric layer 5 is filled in the first trench 12 and the second trench 112, and the first dielectric layer 2 does not exist between the third dielectric layer 5 in the second trench 112 and the second pattern 111, as shown in fig. 8. Specifically, the third dielectric layer 5 in the first trench 12 is in direct contact with the first dielectric layer 2, and the third dielectric layer 5 in the second trench 112 is in direct contact with the second pattern 111.

As an example, physical vapor deposition process, chemical vapor deposition may be employedAnd forming the third dielectric layer 5 by other methods such as a process, an atomic layer deposition process or a spin coating process. The material of the third dielectric layer 5 may be the same as that of the first dielectric layer 2, or may be different from that of the first dielectric layer 2. Specifically, the third dielectric layer 5 may include, but is not limited to, silicon dioxide (SiO)₂) A layer or a silicon nitride (SiN) layer. Finally, the third dielectric layer 5 and the first dielectric layer 2 jointly serve as a shallow trench isolation structure.

The invention has simple preparation process, wide application prospect in the field of semiconductor manufacturing, and high industrial utilization value, and effectively overcomes the defects in the prior art.

It should be understood that, although the steps in the flowcharts of the figures are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in the figures may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of execution of the steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least some of the other steps or stages.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.