阅读说明：本技术 存储器件及其形成方法 (Memory device and method of forming the same ) 是由 于业笑 于 2021-07-19 设计创作，主要内容包括：一种存储器件及其形成方法,所述形成方法形成的金属字线层包括两部分,第一部分位于字线沟槽中,第二部分凸起于所述有源区的表面。这种特定结构的金属字线层相比于只形成在字线沟槽中的字线结构,可以在保持较小宽度的同时保持较长的长度和较大的深度,实现字线沟槽的深度和长度与尺寸之间的平衡,以满足先进工艺的需求,并且在第二开口中形成外延半导体层后,外延半导体层和底部的有源区一起作为沟槽型晶体管的沟道区,使得沟槽型晶体管可以保持较长的有效沟道长度,有利于提高存储器(DRAM)的性能。(A metal word line layer formed by the forming method comprises two parts, wherein the first part is positioned in a word line groove, and the second part is raised above the surface of an active area. Compared with a word line structure only formed in a word line groove, the metal word line layer with the specific structure can keep a longer length and a larger depth while keeping a smaller width, balance between the depth, the length and the size of the word line groove is realized to meet the requirement of advanced technology, and after an epitaxial semiconductor layer is formed in the second opening, the epitaxial semiconductor layer and an active region at the bottom are used as a channel region of a groove type transistor together, so that the groove type transistor can keep a longer effective channel length, and the performance of a memory (DRAM) is improved.)

1. A method of forming a memory device, comprising:

providing a semiconductor substrate, wherein a plurality of discrete active regions extending along a first direction are formed in the semiconductor substrate, and the active regions are isolated by an isolation layer;

two parallel word line grooves extending along the second direction are formed in each active region and the corresponding isolation layer;

forming a first word line dielectric layer on the side wall and the bottom surface of the word line groove;

forming a metal material layer in the word line groove and on the active region and the isolation layer, wherein the metal material layer is filled in the word line groove, and the surface of the metal material layer is higher than that of the active region; forming a plurality of mask patterns extending along a second direction on the metal material layer, wherein one mask pattern is correspondingly arranged right above each word line groove, and a first opening exposing the surface of the metal material layer is arranged between every two adjacent mask patterns;

etching the metal material layer by taking the plurality of mask patterns as masks, forming a second opening exposing the surfaces of the corresponding active area and the isolation layer in the metal material layer, and taking the remaining metal material layer below the mask patterns as a metal word line layer;

and forming an epitaxial semiconductor layer on the surface of the active region exposed by the second opening.

2. The method of forming a memory device of claim 1, wherein the metallic material layer is TiN, Ti, or W.

3. The method of forming a memory device of claim 1, wherein the width of the active region is in a range of 25nm to 65nm, and the width of the word line trench is in a range of 20nm to 40 nm.

4. The method of forming a memory device of claim 3, wherein the depth of the word line trench is 70nm to 210 nm; the thickness of the metal material layer is 60nm-110 nm.

5. The method of forming a memory device of claim 1, wherein the plurality of mask patterns are formed by a self-aligned double patterning process.

6. The method of forming a memory device of claim 1, wherein the forming of the plurality of mask patterns comprises: forming a mask material layer on the metal material layer; forming a plurality of discrete sacrificial layers extending along a second direction on the mask material layer; forming side wall material layers on the side wall and the top surface of the sacrificial layer; etching the side wall material layer to form a side wall on the side wall of the sacrificial layer; and removing the sacrificial layer, and etching the mask material layer by taking the side walls as masks to form a plurality of mask patterns.

7. The method of forming a memory device of claim 1, wherein a material of an epitaxial semiconductor layer is the same as a material of the active region.

8. The method of forming a memory device of claim 7, wherein the material of the active region and the epitaxial semiconductor layer is silicon.

9. The method of forming a memory device of claim 1 or 7, wherein the epitaxial semiconductor layer is formed by a selective epitaxial process.

10. The method of forming a memory device of claim 1, further comprising, prior to forming the epitaxial semiconductor layer, the steps of: forming a second word line dielectric layer on the side wall of the word line metal layer on two sides of the second opening; after forming the epitaxial semiconductor layer, further comprising the steps of: forming an isolation medium layer filling the second opening; etching back the metal word line layer with the partial thickness removed; and forming a semiconductor word line layer on the surface of the residual metal word line layer.

11. The method of forming a memory device of claim 10, wherein the material of the semiconductor word line layer is polysilicon.

12. The method of forming a memory device of claim 10, wherein a capping layer is formed on the semiconductor word line layer.

13. A memory device, comprising:

the semiconductor device comprises a semiconductor substrate, a first electrode, a second electrode and a third electrode, wherein the semiconductor substrate is provided with a plurality of discrete active regions extending along a first direction, and the active regions are isolated by isolation layers;

two parallel word line grooves extending along the second direction are formed in each active region and the corresponding isolation layer;

a metal word line layer in the word line trench, a top surface of the metal word line layer being higher than a surface of the active region;

and the epitaxial semiconductor layers are positioned on the surfaces of the active regions on the two sides of the metal word line layer and are isolated from the metal word line layer and the active regions on the two sides of the word line groove through word line dielectric layers.

14. The memory device of claim 13, wherein the metal word line layer is TiN, Ti, or W.

15. The memory device of claim 13 wherein the width of the active region is in a range of 25nm to 65nm and the width of the word line trench is in a range of 20nm to 40 nm.

16. The memory device of claim 15 wherein said word line trench has a depth of 70nm to 210 nm; the thickness of the metal material layer is 60nm-110 nm.

17. The memory device of claim 13, wherein a material of the epitaxial semiconductor layer is the same as a material of the active region.

18. The memory device of claim 17, wherein the material of the active region and the epitaxial semiconductor layer is silicon.

19. The memory device of claim 13, wherein a semiconductor word line layer is located on a surface of the metal word line layer, the word line dielectric layer further being located between the semiconductor word line layer and the epitaxial semiconductor layer.

20. The memory device of claim 19, wherein the material of the semiconductor word line layer is polysilicon.

21. The memory device of claim 19, wherein a top surface of a metal word line layer and a semiconductor word line layer is below a top surface of the epitaxial semiconductor layer, the surface of the semiconductor word line layer further having a capping layer.

Technical Field

The present invention relates to the field of memory devices, and more particularly, to a memory device and a method of forming the same.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell generally includes a capacitor and a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor, and a voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage.

In order to increase the integration of the memory structure, the transistors in the Dynamic Random Access Memory (DRAM) generally adopt a trench type transistor structure. The specific structure of the trench type transistor generally includes: a semiconductor substrate; an active region in the semiconductor substrate; at least one word line trench in the active region, a buried word line (or gate) in the word line trench; and the middle drain region and the at least one source region are positioned in the active region at two sides of the word line groove.

As the size of memory devices is scaled down, the word line trench has reached the limit of the etching process, and therefore, achieving the balance between the depth and length of the word line trench and the size becomes a problem to be solved by those skilled in the art.

Disclosure of Invention

The technical problem to be solved by the invention is how to realize the balance between the depth and length of the word line groove and the size when the size of the memory device is reduced.

To this end, the present invention provides a method of forming a memory device, comprising:

providing a semiconductor substrate, wherein a plurality of discrete active regions extending along a first direction are formed in the semiconductor substrate, and the active regions are isolated by an isolation layer;

two parallel word line grooves extending along the second direction are formed in each active region and the corresponding isolation layer;

forming a first word line dielectric layer on the side wall and the bottom surface of the word line groove;

forming a metal material layer in the word line groove and on the active region and the isolation layer, wherein the metal material layer is filled in the word line groove, and the surface of the metal material layer is higher than that of the active region;

forming a plurality of mask patterns extending along a second direction on the metal material layer, wherein one mask pattern is correspondingly arranged right above each word line groove, and a first opening exposing the surface of the metal material layer is arranged between every two adjacent mask patterns;

etching the metal material layer by taking the plurality of mask patterns as masks, forming a second opening exposing the surfaces of the corresponding active area and the isolation layer in the metal material layer, and taking the remaining metal material layer below the mask patterns as a metal word line layer;

and forming an epitaxial semiconductor layer on the surface of the active region exposed by the second opening.

Optionally, the metal material layer is TiN, Ti or W.

Optionally, the width range of the active region is 25nm to 65nm, and the width range of the word line trench is 20nm to 40 nm.

Optionally, the depth of the word line trench is 70nm to 210 nm. The thickness of the metal material layer is 60nm-110 nm.

Optionally, the mask patterns are formed by a self-aligned double patterning process.

Optionally, the forming process of the mask patterns includes: forming a mask material layer on the metal material layer; forming a plurality of discrete sacrificial layers extending along a second direction on the mask material layer; forming side wall material layers on the side wall and the top surface of the sacrificial layer; etching the side wall material layer to form a side wall on the side wall of the sacrificial layer; and removing the sacrificial layer, and etching the mask material layer by taking the side walls as masks to form a plurality of mask patterns.

Optionally, the material of the epitaxial semiconductor layer is the same as the material of the active region.

Optionally, the active region and the epitaxial semiconductor layer are made of silicon.

Optionally, the epitaxial semiconductor layer is formed by a selective epitaxy process.

Optionally, before forming the epitaxial semiconductor layer, the method further includes: forming a second word line dielectric layer on the side wall of the word line metal layer on two sides of the second opening; after forming the epitaxial semiconductor layer, further comprising the steps of: forming an isolation medium layer filling the second opening; etching back the metal word line layer with the partial thickness removed; and forming a semiconductor word line layer on the surface of the residual metal word line layer.

Optionally, the material of the semiconductor word line layer is polysilicon.

Optionally, a capping layer is formed on the semiconductor word line layer.

The present invention also provides a memory device, characterized by comprising:

the semiconductor device comprises a semiconductor substrate, a first electrode, a second electrode and a third electrode, wherein the semiconductor substrate is provided with a plurality of discrete active regions extending along a first direction, and the active regions are isolated by isolation layers;

two parallel word line grooves extending along the second direction are formed in each active region and the corresponding isolation layer;

a metal word line layer in the word line trench, a top surface of the metal word line layer being higher than a surface of the active region;

and the epitaxial semiconductor layers are positioned on the surfaces of the active regions on the two sides of the metal word line layer and are isolated from the metal word line layer and the active regions on the two sides of the word line groove through word line dielectric layers.

Optionally, the metal word line layer is TiN, Ti or W.

Optionally, the width range of the active region is 25nm to 65nm, and the width range of the word line trench is 20nm to 40 nm.

Optionally, the depth of the word line trench is 70nm to 210 nm. The thickness of the metal material layer is 60nm-110 nm.

Optionally, the material of the epitaxial semiconductor layer is the same as that of the active region.

Optionally, the active region and the epitaxial semiconductor layer are made of silicon.

Optionally, the semiconductor word line layer is located on the surface of the metal word line layer, and the word line dielectric layer is also located between the semiconductor word line layer and the epitaxial semiconductor layer.

Optionally, the material of the semiconductor word line layer is polysilicon.

Optionally, the top surfaces of the metal word line layer and the semiconductor word line layer are lower than the top surface of the epitaxial semiconductor layer, and the surface of the semiconductor word line layer further has a cap layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the forming method of the memory device, after two parallel word line grooves extending along the second direction are formed in each active region and the corresponding isolation layer, first word line dielectric layers are formed on the side wall and the bottom surface of each word line groove; forming a metal material layer in the word line groove and on the active region and the isolation layer, wherein the metal material layer is filled in the word line groove, and the surface of the metal material layer is higher than that of the active region; forming a plurality of mask patterns extending along a second direction on the metal material layer, wherein one mask pattern is correspondingly arranged right above each word line groove, and a first opening exposing the surface of the metal material layer is arranged between every two adjacent mask patterns; etching the metal material layer by taking the plurality of mask patterns as masks, forming a second opening exposing the surfaces of the corresponding active area and the isolation layer in the metal material layer, and taking the remaining metal material layer below the mask patterns as a metal word line layer; and forming an epitaxial semiconductor layer on the surface of the active region exposed by the second opening. Since the metal word line layer is formed to include two portions, the first portion is located in the word line trench and the second portion is raised above the surface of the active area (the top surface of the second portion is higher than the surface of the active area). Compared with a word line structure only formed in a word line groove, the metal word line layer with the specific structure can keep a longer length (the length is the size of the metal word line layer along the second direction) and a larger depth (the depth is the size of the metal word line layer along the direction vertical to the substrate surface) while keeping a smaller width (the width is the size of the metal word line layer along the direction parallel to the substrate surface vertical to the second direction), balance among the depth, the length and the size of the word line groove is achieved, the requirement of advanced technology is met, and after an epitaxial semiconductor layer is formed in a second opening in a follow-up mode, the epitaxial semiconductor layer and an active region at the bottom are used as a channel region of a groove type transistor together, so that the groove type transistor can keep a longer effective channel length, and the performance of a memory (DRAM) is improved.

Furthermore, a plurality of mask patterns are formed through a self-aligning double-pattern process, so that the formed mask patterns can have smaller size (width) and longer length, the position progress is higher, and the side wall appearance is better.

The memory device of the invention has the advantages that the metal word line layer comprises two parts, the first part is positioned in the word line groove, and the second part is raised above the surface of the active area (the top surface of the second part is higher than the surface of the active area). Compared with a word line structure only formed in a word line groove, the metal word line layer with the specific structure can keep a longer length (the length is the size of the metal word line layer along the second direction) and a larger depth (the depth is the size of the metal word line layer along the direction vertical to the surface of the substrate) while keeping a smaller width (the width is the size of the metal word line layer along the direction parallel to the surface of the substrate), balance among the depth, the length and the size of the word line groove is achieved, the requirement of advanced technology is met, and the epitaxial semiconductor layer and the active region at the bottom are used as a channel region of a groove type transistor together, so that the groove type transistor can keep a longer effective channel length, and the performance of a memory (DRAM) is improved.

Drawings

Fig. 1-18 are schematic structural diagrams illustrating a memory device forming process according to an embodiment of the invention.

Detailed Description

As background art shows, as the size of memory devices is scaled down, the word line trench has reached the limit of the etching process, and therefore, achieving the balance between the depth and length of the word line trench and the size becomes a problem to be solved by those skilled in the art.

It has been found that as the feature size of the memory device is further reduced, when the word line trench is etched, it is difficult to maintain a smaller size (or width) when the word line trench is formed with a deeper depth and/or a longer length when the word line trench is formed with a smaller size (or width) due to the limitation of the etching process.

The invention provides a memory device and a forming method thereof, wherein the forming method comprises the steps of forming two parallel word line grooves extending along a second direction in each active region and a corresponding isolation layer, and then forming first word line dielectric layers on the side walls and the bottom surfaces of the word line grooves; forming a metal material layer in the word line groove and on the active region and the isolation layer, wherein the metal material layer is filled in the word line groove, and the surface of the metal material layer is higher than that of the active region; forming a plurality of mask patterns extending along a second direction on the metal material layer, wherein one mask pattern is correspondingly arranged right above each word line groove, and a first opening exposing the surface of the metal material layer is arranged between every two adjacent mask patterns; etching the metal material layer by taking the plurality of mask patterns as masks, forming a second opening exposing the surfaces of the corresponding active area and the isolation layer in the metal material layer, and taking the remaining metal material layer below the mask patterns as a metal word line layer; and forming an epitaxial semiconductor layer on the surface of the active region exposed by the second opening. Since the metal word line layer is formed to include two portions, the first portion is located in the word line trench and the second portion is raised above the surface of the active area (the top surface of the second portion is higher than the surface of the active area). Compared with a word line structure only formed in a word line groove, the metal word line layer with the specific structure can keep a longer length (the length is the size of the metal word line layer along the second direction) and a larger depth (the depth is the size of the metal word line layer along the direction vertical to the substrate surface) while keeping a smaller width (the width is the size of the metal word line layer along the direction parallel to the substrate surface vertical to the second direction), balance among the depth, the length and the size of the word line groove is achieved, the requirement of advanced technology is met, and after an epitaxial semiconductor layer is formed in a second opening in a follow-up mode, the epitaxial semiconductor layer and an active region at the bottom are used as a channel region of a groove type transistor together, so that the groove type transistor can keep a longer effective channel length, and the performance of a memory (DRAM) is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Referring to fig. 1 and 2, fig. 1 is a top view, and fig. 2 is a schematic cross-sectional structure view along a cutting line AB in fig. 1, a semiconductor substrate 201 is provided, a plurality of discrete active regions 202 extending along a first direction are formed in the semiconductor substrate 201, and the plurality of active regions 202 are isolated by an isolation layer 203.

The material of the semiconductor substrate 201 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the semiconductor substrate 201 is made of silicon. The semiconductor substrate is doped with certain impurity ions according to needs, and the impurity ions can be N-type impurity ions or P-type impurity ions. In some embodiments, the doping may include well region doping and source drain region doping.

The active region 202 is subsequently used to form a double trench transistor. Several active regions 202 are discrete, with adjacent active regions separated by an isolation layer 203.

In some embodiments, the forming process of the active region 202 and the isolation layer 203 includes: forming a first mask layer (not shown in the figure) on the semiconductor substrate 201, wherein the first mask layer is provided with a plurality of first mask openings which are distributed in parallel; etching the semiconductor substrate 201 along a first mask opening by taking the first mask layer as a mask, forming a plurality of discrete strip-shaped active areas in the semiconductor substrate 201, and forming a first groove between every two adjacent strip-shaped active areas; etching the strip-shaped active area to form a plurality of second grooves in the strip-shaped active area, wherein each strip-shaped active area is divided into a plurality of active areas 202 by the second grooves; the first trench and the second trench are filled with an isolation material to form an isolation layer 203, and the material of the isolation layer 203 may be silicon oxide or other suitable isolation material. In other embodiments, an isolation material may be filled in the first trench to form a first isolation layer, and after the first isolation layer is formed, the strip-shaped active region is etched to form a plurality of second trenches in the strip-shaped active region; then, an isolation material is filled in the second trench to form a second isolation layer, and the first isolation layer and the second isolation layer constitute the isolation layer 203. In this embodiment, the top surface of the isolation layer 203 is flush with the top surface of the active region 202, and in other embodiments, the top surface of the isolation layer 203 may be higher than the top surface of the active region 202 and may cover the top surface of the active region 203. In this embodiment, referring to fig. 1, the active regions 202 are distributed in the semiconductor substrate 201 in a staggered manner along the first direction. In other embodiments, the active regions may be arranged in other forms (such as an array). Note that, in fig. 2, in order to distinguish the active region 202 from the semiconductor substrate 201, the active region 202 and the semiconductor substrate 201 are separated by a dotted line.

In other embodiments, the active region 202 may be formed by an epitaxial process or other suitable process.

Referring to fig. 3-5, fig. 3 is performed on the basis of fig. 1, fig. 4 is performed on the basis of fig. 2, and fig. 5 is performed on the basis of fig. 4, and two parallel word line trenches 205 (refer to fig. 5) extending in the second direction are formed in each of the active regions 202 and the corresponding isolation layer 203.

The word line trench 205 is subsequently used to form a word line or a gate of a trench transistor. In this embodiment, each active region 202 has two word line trenches 205 therein, and a double trench transistor may be formed subsequently.

The first direction in which the active region 203 extends and the second direction in which the word line trench 205 extends are at a first acute angle α, which in some embodiments ranges from 60 degrees to 75 degrees.

In some embodiments, the formed word line trench 205 has a depth in the range of 70nm to 210nm and a width in the range of 20nm to 40 nm.

The active regions 202 and the isolation layers 203 are etched by an etching process, and two parallel word line trenches 205 extending in the second direction are formed in each of the active regions 202 and the corresponding isolation layer 203. The etching process may be an anisotropic dry etching process, such as an anisotropic plasma etching process.

In some embodiments, referring to fig. 3 and 4, before etching the active region 202 and the isolation layer 203, a mask layer 204 is formed on the active region 202 and the isolation layer 203; a plurality of openings 220 extending along the second direction are formed in the mask layer 204, each of the openings 220 correspondingly exposes a plurality of active regions 202 and a portion of the surface of the isolation layer 203 between the active regions 202, and each of the active regions 202 correspondingly has two openings 220. Referring to fig. 4 and 5, the active region 202 and the isolation layer 203 on both sides of the active region 202 are etched along the opening 220, two word line trenches 205 are formed in each of the active region 202 and the isolation layer 203 on both sides of the active region 202, and each of the active regions is divided into a drain region located between the two word line trenches 205 and two source regions located outside the two word line trenches 205 by the two word line trenches 205. It should be noted that, in some embodiments, the mask layer 204 may be removed simultaneously when the active region 202 and the isolation layer are etched to form the word line trench 205. In other embodiments, the remaining mask layer 204 may also be removed after forming the word line trench 205.

Referring to fig. 6, a first word line dielectric layer 206 is formed on the sidewall and bottom surface of the word line trench 205.

The first word line dielectric layer 206 is used for isolation between the word lines formed in the subsequent word line trenches 205 and the active region.

In some embodiments, the first wordline dielectric layer 20The material of 6 may be silicon oxide or a high K dielectric material. When the first wordline dielectric layer 206 is made of silicon oxide, the first wordline dielectric layer 206 is formed by oxidation or a furnace process. When the first word line dielectric layer 206 is made of a high-K (K is greater than 2.5) dielectric material (such as HfO)₂、TiO₂、HfZrO、HfSiNO、Ta₂O₅Or ZrO₂) The first wordline dielectric layer 206 may be formed by a deposition process including an atomic layer deposition process.

Referring to fig. 7, a metal material layer 207 is formed in the word line trench and on the active region and the isolation layer, the metal material layer 207 fills the word line trench, and the surface of the metal material layer 207 is higher than the surface of the active region 202.

The metal material layer 207 is subsequently used to form a metal word line layer, so that the subsequently formed metal word line layer can be partially located in the word line trench and partially located above the word line trench, protruding from the surface of the active region 202.

In some embodiments, the metallic material layer 207 is TiN, Ti, or W.

In some embodiments, the forming process of the metal material layer 207 includes: forming an initial metal material layer in the word line groove and on the surfaces of the active region 202 and the isolation layer 203 through a sputtering or physical vapor deposition process, wherein the initial metal material layer fills the word line groove, and the surface of the initial metal material layer is higher than the surface of the active region 202; and planarizing the surface of the initial metal material layer by adopting a chemical mechanical polishing process to form a metal material layer 207, wherein the metal material layer 207 has a flat surface, and the surface of the metal material layer is higher than the surface of the active region 202.

In some embodiments, the formed metal material layer 207 has a thickness of 60nm to 110 nm. Note that the thickness of the metal material layer 207 is higher than the sum of the thickness of the metal material layer 207 on the surface of the active region 202 and the height in the trench.

Referring to fig. 12, a plurality of mask patterns 218 extending in the second direction are formed on the metal material layer 207, one mask pattern 208 is correspondingly disposed right above each word line trench, and a first opening 219 exposing the surface of the metal material layer 207 is disposed between adjacent mask patterns 208.

The mask pattern 208 is used as a mask when the metal material layer 207 is subsequently etched to form a metal word line layer.

In some embodiments, the mask patterns 208 are formed by a self-aligned dual patterning process, and the process of forming the mask patterns 208 is described in detail below with reference to fig. 8-12.

Referring to fig. 8, a mask material layer 208 is formed on the metal material layer 207; a number of discrete sacrificial layers 209 extending in a second direction are formed over the layer of masking material.

A mask pattern is subsequently formed by etching the layer 207 of masking material. The masking material layer 207 may be a single layer or a multi-layer stack (e.g., a bi-layer or tri-layer stack). In some embodiments, the material of the mask material layer 207 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbide nitride.

The sacrificial layer 209 is used to define the position of a subsequently formed spacer material layer. The material of the sacrificial layer 209 may be different from the material of the mask material layer 207. In some embodiments, the material of the sacrificial layer 209 may be photoresist, polysilicon, or other suitable sacrificial material.

The formed sacrificial layer 209 is located above an active area between adjacent word line grooves, so that the distance between the adjacent sacrificial layers 209 is large, the position accuracy of the sacrificial layer 209 formed by the existing process is high, and the sidewall morphology is good, so that the position accuracy of a subsequently formed sidewall material layer is improved, the good surface morphology is ensured, the subsequently formed sidewall and mask patterns have high position accuracy and surface morphology, and the formed metal word line layer has high position accuracy and surface morphology when the metal word line layer is formed by subsequently etching the metal material layer 207 by taking the mask patterns as masks.

Referring to fig. 9, a spacer material layer 210 is formed on the sidewall and the top surface of the sacrificial layer 209.

The side wall material layer 210 is subsequently used to form a side wall on the side wall of the sacrificial layer, and the material of the side wall material layer 210 may be different from the material of the sacrificial layer 209 and the material of the mask material layer 207. In some embodiments, the material of the sidewall material layer 210 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbide nitride.

In some embodiments, the side wall material layer 210 is formed by an atomic layer deposition process, so that the formed side wall material layer 210 can maintain a better surface topography and thickness accuracy, and is beneficial to further improving the position and thickness accuracy of a subsequently formed side wall.

Referring to fig. 10, the spacer material layer 209 is etched (refer to fig. 9), and a spacer 211 is formed on the sidewall of the sacrificial layer 209.

The sidewall material layer 209 may be etched by using a maskless plasma etching process to remove the sidewall material layer on the top surface of the sacrificial layer 209 and the surface of the mask material layer 208, and the sidewall material layer on the sidewall surface of the sacrificial layer 209 is reserved as the sidewall 211.

In other embodiments, a filling layer may also be formed on the sidewall material layer 209 first, the filling layer fills the groove between the adjacent sacrificial layers 209, and the filling layer and the sidewall material layer higher than the top surface of the sacrificial layer 209 are removed by planarization; and then, etching to remove the residual filling layer and the spacer material layer on the surface of the mask material layer 208, and forming a spacer 211 on the surface of the sidewall of the sacrificial layer 209.

Referring to fig. 11 and 12, the sacrificial layer 209 (refer to fig. 10) is removed, and the masking material layer 208 (refer to fig. 11) is etched using the sidewalls 211 as a mask, thereby forming a plurality of mask patterns 218 (refer to fig. 12).

In some embodiments, the sacrificial layer 209 may be removed by an isotropic wet etching process, and the mask material layer may be etched by an anisotropic dry etching process, such as a plasma etching process.

A plurality of mask patterns 208 formed through the aforementioned self-aligned dual patterning process in this application can have a smaller size (width) and can have a longer length, and the position progress is higher, and the topography of the side wall is better, thus with when the mask pattern forms the metal word line layer for the metal material layer 207 at the mask moment, the metal word line layer that forms also can keep a smaller size (width), a longer length, and a higher position progress and a better sidewall topography.

Referring to fig. 13, the metal material layer 207 (refer to fig. 12) is etched using the mask patterns 218 as masks, a second opening 220 exposing the surface of the corresponding active region 202 and the surface of the isolation layer 203 is formed in the metal material layer, and the metal material layer remaining under the mask patterns 218 serves as a metal word line layer 212.

The etching may employ an anisotropic dry etching process, such as a plasma etching process.

The second opening 220 and the metal word line layer 212 are formed to extend in a second direction.

In this embodiment, the formed metal word line layer 212 includes two portions, a first portion is located in the word line trench, and a second portion is raised above the surface of the active area 202 (the top surface of the second portion is higher than the surface of the active area). Such a specially structured metal word line layer 212 formed by the foregoing method is compared to a word line structure formed only in the word line trench, it is possible to maintain a long length (the length is the dimension of the metal word line layer 212 in the second direction) and a large depth (the depth is the dimension of the metal word line layer 212 in the direction perpendicular to the substrate surface) while maintaining a small width (the width is the dimension of the metal word line layer 212 in the direction parallel to the substrate surface) to achieve a balance between the depth and the length and the dimension of the word line trench, to meet the requirements of advanced processes, and subsequently forming an epitaxial semiconductor layer in the second opening, the epitaxial semiconductor layer and the active region at the bottom together serve as a channel region of the trench transistor, the trench transistor can keep longer effective channel length, which is beneficial to improving the performance of a memory (DRAM).

It should be noted that, during the etching of the metal material layer 207, the mask patterns 218 may be removed simultaneously. In other embodiments, the number of mask patterns 218 may be removed by an etching process.

Referring to fig. 14, second word line dielectric layers 213 are formed on sidewall surfaces of the metal word line layers 212 at both sides of the second opening.

The second wordline dielectric layer 213 and the first wordline dielectric layer 206 together form a wordline dielectric layer.

The second wordline dielectric layer 213 is the same material as the first wordline dielectric layer 206, and the second wordline dielectric layer 213 may be formed by sputtering (deposition) and etching processes.

Referring to fig. 15, an epitaxial semiconductor layer 214 is formed on the surface of the active region 202 exposed by the second opening.

In some embodiments, the epitaxial semiconductor layer 214 is formed to fill the second opening, and the epitaxial semiconductor layer 214 is formed by a selective epitaxy process, wherein the semiconductor material is formed only on the surface of the active region 202 at the bottom of the second opening until the second opening 202 is filled because the growth rate of the semiconductor material on the surface of the active region 202 is much higher than the production rate of the semiconductor material elsewhere (e.g., on the top surface of the metal word line layer 212).

The formed epitaxial semiconductor layer 214 and the active region 202 at the bottom of the epitaxial semiconductor layer 214 together form a channel region of the trench transistor, and a conductive channel is formed in the epitaxial semiconductor layer 214 and the active region 202 at the bottom of the epitaxial semiconductor layer 214 under the control of the word line metal layer 212.

In some embodiments, the material of the epitaxial semiconductor layer 212 is the same as the material of the active region 202.

In some embodiments, the material of the active region 202 and the epitaxial semiconductor layer 212 is silicon.

In other embodiments, the active region 202 and the epitaxial semiconductor layer 212 may be silicon germanium or silicon carbide.

In some embodiments, referring to fig. 15, after forming the epitaxial semiconductor layer 212, further comprising the steps of: forming an isolation dielectric layer 215 filling the second opening; referring to fig. 16, the metal word line layer 212 is etched back to remove a portion of the thickness; referring to fig. 17, a semiconductor word line layer 213 is formed on the surface of the remaining metal word line layer 212.

The isolation dielectric layer 215 is used for electrical isolation between adjacent word line metal layers, and the isolation dielectric layer 215 may be made of one or more of silicon oxide, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), and a low-k dielectric material (such as SiCOH) or an ultra-low-k dielectric material.

The material of the semiconductor word line layer 213 may be silicon, silicon germanium, or silicon carbide.

The semiconductor word line layer 213 and the metal word line layer 212 together form a word line structure of the trench transistor, and the electrical performance of the trench transistor can be improved.

In some embodiments, referring to FIG. 18, a cap layer 217 may also be formed on the semiconductor word line layer 216. The material of the cap layer 217 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbide nitride.

An embodiment of the present invention further provides a memory device with reference to fig. 18, including:

the semiconductor device comprises a semiconductor substrate, a plurality of first isolation layers and a plurality of second isolation layers, wherein the semiconductor substrate is provided with a plurality of discrete active regions 202 extending along a first direction, and the plurality of active regions 202 are isolated through isolation layers 203;

two parallel word line grooves extending along the second direction are formed in each active region and the corresponding isolation layer;

a metal word line layer 212 in the word line trench, a top surface of the metal word line layer 212 being higher than a surface of the active area 202;

an epitaxial semiconductor layer 214 on the active area surface on both sides of the metal word line layer 212, the epitaxial semiconductor layer 214 being isolated from the metal word line layer 212 and the active area 202 on both sides of the word line trench by a word line dielectric layer (206/213).

In some embodiments, the metallic material layer is TiN, Ti, or W.

In some embodiments, the width of the active region 202 ranges from 25nm to 65nm, and the width of the word line trench ranges from 20nm to 40 nm.

In some embodiments, the depth of the word line trench is 70nm-210 nm. The thickness of the metal material layer is 60nm-110 nm.

In some embodiments, the material of the epitaxial semiconductor layer 214 is the same as the material of the active region 202. In one embodiment, the material of the active region and the epitaxial semiconductor layer is silicon.

In some embodiments, further comprising: a semiconductor word line layer 216 disposed on a surface of the metal word line layer 212, the word line dielectric layer (213) further disposed between the semiconductor word line layer 216 and the epitaxial semiconductor layer 214.

In some embodiments, the material of the semiconductor word line layer 216 is polysilicon.

In some embodiments, the top surfaces of the metal word line layer 212 and the semiconductor word line layer 216 are lower than the top surface of the epitaxial semiconductor layer 214, the surface of the semiconductor word line layer 216 also having a cap layer 217.

It should be noted that, the definition or description of the same or similar structure in this embodiment (memory device) and the foregoing embodiment (formation process of memory device) is not repeated in this embodiment, and specific reference is made to the definition or description of the corresponding part in the foregoing embodiment.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.