阅读说明：本技术 一种具有多浮空场板的自适应soi ligbt器件 (Self-adaptive SOI LIGBT device with multiple floating field plates ) 是由 魏杰 李�杰 戴恺伟 马臻 杨可萌 罗小蓉 于 2021-08-31 设计创作，主要内容包括：本发明属于功率半导体技术领域,具体涉及一种具有多浮空场板的自适应SOI LIGBT器件。相比传统结构,本发明在集电极端引入自适应性NMOS结构,漂移区表面采用间断的浮空场板。正向导通时,集电极端NMOS沟道关闭,集电极端电子抽取路径被阻断而消除电压折回效应,且阻挡槽栅的存在将提高漂移区载流子浓度,新器件可获得低的正向导通压降。关断过程中,随集电极电压上升,集电极NMOS沟道自适应性开启形成电子抽取路径,加速器件关断以降低关断损耗。同时,由于浮空场板群的存在,阻断状态下器件的表面电场得到优化,器件的表面电场得到优化,使得新器件可以在维持耐压等级不变的情况下,缩短漂移区长度,进一步降低器件的导通压降和关断损耗。(The invention belongs to the technical field of power semiconductors, and particularly relates to a self-adaptive SOI LIGBT device with multiple floating field plates. Compared with the traditional structure, the invention introduces the adaptive NMOS structure at the collector terminal, and the surface of the drift region adopts a discontinuous floating field plate. When the forward conduction is carried out, the NMOS channel of the collector terminal is closed, the electron extraction path of the collector terminal is blocked to eliminate the voltage folding effect, the carrier concentration of a drift region is improved due to the existence of the blocking groove gate, and the new device can obtain low forward conduction voltage drop. In the turn-off process, as the voltage of the collector rises, the channel of the NMOS of the collector is self-adaptively opened to form an electron extraction path, and the turn-off of the device is accelerated to reduce the turn-off loss. Meanwhile, due to the existence of the floating field plate group, the surface electric field of the device in a blocking state is optimized, and the surface electric field of the device is optimized, so that the length of a drift region can be shortened under the condition that the withstand voltage grade of a new device is not changed, and the conduction voltage drop and the turn-off loss of the device are further reduced.)

1. A self-adaptive SOI LIGBT device with a plurality of floating field plates comprises a P-type substrate (1), an insulating medium layer (2) and an N drift region (3) which are sequentially stacked from bottom to top; the upper layer of the N-type drift region (3) is sequentially provided with an emitter structure, a field plate structure and a collector structure along the transverse direction of the device;

the emitter structure comprises a first P-type well region (41), a first P + body contact region (51), a first N + emission region (61), a second N + emission region (62), a second P + body contact region (52) and a third N + emission region (63), wherein the first P + body contact region (51), the first N + emission region (61), the second N + emission region (62), the second P + body contact region (52) and the third N + emission region (63) are arranged on the upper layer of the first P-type well region (41) in sequence; the common leading-out ends of the first P + body contact region (51), the second P + body contact region (52), the first N + emitter region (61), the second N + emitter region (62) and the third N + emitter region (63) are emitters;

the upper layer of the first P-type well region (41) is provided with a groove gate structure;

the groove gate structure comprises a control groove gate and a blocking groove gate, the control groove gate consists of a first groove gate dielectric layer (72) and a first groove gate polycrystalline silicon layer (71) positioned in the first groove gate dielectric layer (72), the control groove gate is positioned between a first N + emission region (61) and a second N + emission region (62), penetrates through a P well region (41) along the vertical direction of a device and then extends into an N drift region (3), and two sides of the control groove gate are respectively contacted with the first N + emission region (61) and the second N + emission region (62); the blocking groove gate is composed of a second groove gate dielectric layer (74) and a second groove gate polycrystalline silicon layer (73) located in the second groove gate dielectric layer (74), the blocking groove gate penetrates through the P well region (41) along the vertical direction of the device and then extends into the N drift region (3), one side of the blocking groove gate is in contact with the third N + emitter region (63), and the other side of the blocking groove gate is the P well region (41); the common leading-out end of the first groove grid polycrystalline silicon layer (71) and the second groove grid polycrystalline silicon layer (73) is a grid;

the field plate structure is positioned on the surface of an N drift region between an emitter electrode structure and a collector electrode structure, two ends of the field plate structure respectively extend to the upper parts of a first P-type well region (41) and an N-type buffer layer (10), and the field plate structure comprises a dielectric layer (8) and a discontinuous polycrystalline silicon field plate positioned on the dielectric layer; the intermittent polysilicon field plate comprises a first field plate (91) close to an emitter end, a second field plate (93) close to a collector end and a floating field plate group (92) which is positioned between the first field plate (91) and the second field plate (93) and consists of a plurality of floating field plates; the first field plate (91) is shorted to the emitter, and the second field plate (93) is shorted to the collector;

the collector structure comprises an N-type buffer layer (10), a P + collector region (53) and a collector NMOS structure; the P + collector region (53) is positioned on the upper layer of the N-type buffer layer (10); the collector NMOS structure comprises a second P-type well region (42), a P + well potential region (54), an N + collector region (64) and a collector groove grid, wherein the second P-type well region, the P + well potential region and the N + collector region are positioned in an N-type buffer layer (10); the collector grooved gate consists of a third grooved gate dielectric layer (76) and a third grooved gate polycrystalline silicon layer (75) positioned in the third grooved gate dielectric layer (76), and is in contact with the side surface of the P + collector region (53) far away from the emitter side, the second P-type well region (42) is positioned on the upper layer of an N-type buffer layer (10) on the side surface of the collector grooved gate far away from the emitter side, a P + well potential region (54) and an N + collector region (64) are respectively positioned at two ends of the upper layer of the second P-type well region (42), and the N + collector region (64) is in contact with the collector grooved gate; the common leading-out end of the P + collector region (53), the third trench gate polycrystalline silicon layer (75) and the N + collector region (64) is a collector; the leading-out end of the P + well potential area (54) is in short circuit with the leading-out end of one floating field plate in the floating field plate group (92).

Technical Field

The invention belongs to the technical field of power semiconductors, and relates to a self-adaptive SOI LIGBT (Lateral Insulated Gate Bipolar Transistor) with a multi-floating field plate.

Background

The insulated gate bipolar transistor is a gate-controlled bipolar conductive device, has the advantages of high input impedance and easiness in driving due to the gate-controlled characteristic, and is easy to realize low conduction voltage drop and large current density in a bipolar conductive mode, so that the insulated gate bipolar transistor is widely applied to the high-voltage and high-power electronic fields such as smart grids, rail transit, industrial control and the like. The semiconductor device based on the SOI technology can realize all-dielectric isolation and has lower leakage current and smaller parasitic effect.

When the LIGBT is in forward conduction, a conductance modulation effect occurs in a drift region of the LIGBT, so that a large amount of excess carriers are stored, and low forward conduction voltage drop (V) is favorably realized_on) Correspondingly, however, during turn-off, a longer tail current results due to the presence of a large number of excess carriers, resulting in turn-off losses (E)_off) And (4) increasing. Meanwhile, due to the conductance modulation effect, the proportion of the divided voltage of the channel resistance in the forward conduction voltage drop of the IGBT can be increased.

In order to alleviate the contradiction between the turn-off loss and the turn-on voltage drop of the LIGBT device, a common approach is to use a short-circuited anode structure, i.e. a short-circuited anode N + region is introduced beside an anode P + region, and an electron extraction path is provided to accelerate the turn-off and reduce the turn-off loss in the turn-off process of the device. However, the short-circuited anode structure causes the snapback effect caused by the conversion from the unipolar conduction mode to the bipolar conduction mode when the device is conducted, and the reliability of the parallel connection of the devices is reduced. Therefore, on the basis of the above, various anode auxiliary gate control structures are proposed, and an auxiliary gate potential is provided by an external gate driving control circuit for controlling whether the anode N + region is effective or not. When the anode is conducted in the forward direction, the anode N + region is shielded, so that the snapback effect is eliminated; in the turn-off process, the anode N + region and the anode P + region are conducted to form an electron extraction path, so that the turn-off of the device is accelerated, and the turn-off loss is obviously reduced. However, the additional gate driving control circuit increases design cost and manufacturing difficulty.

The contradiction relationship also exists among turn-off loss, conduction voltage drop and withstand voltage. The length of the drift region is shortened, so that the conduction voltage drop of the device can be reduced, the number of surplus carriers stored in the drift region is reduced, the trailing current in the turn-off process is reduced, and the turn-off loss is reduced.

Disclosure of Invention

In order to solve the problems, the invention provides an adaptive SOI LIGBT device with multiple floating field plates.

The technical scheme of the invention is as follows: a self-adaptive SOI LIGBT device with a plurality of floating field plates comprises a P-type substrate 1, an insulating medium layer 2 and an N drift region 3 which are sequentially stacked from bottom to top; the upper layer of the N-type drift region 3 is transversely provided with an emitter structure, a field plate structure and a collector structure in sequence;

the emitter structure comprises a first P-type well region 41, a first P + body contact region 51, a first N + emission region 61, a second N + emission region 62, a second P + body contact region 52 and a third N + emission region 63 which are arranged on the upper layer of the first P-type well region 41 in sequence, wherein the third N + emission region 63 is positioned on one side close to the collector structure; the common leading-out ends of the first P + body contact region 51, the second P + body contact region 52, the first N + emitter region 61, the second N + emitter region 62 and the third N + emitter region 63 are emitters;

a groove gate structure is arranged on the upper layer of the first P-type well region 41;

the groove gate structure comprises a control groove gate and a blocking groove gate, the control groove gate consists of a first groove gate dielectric layer 72 and a first groove gate polycrystalline silicon layer 71 positioned in the first groove gate dielectric layer 72, is positioned between the first N + emission region 61 and the second N + emission region 62, penetrates through the P well region 41 along the vertical direction of the device and then extends into the N drift region 3, and two sides of the control groove gate are respectively contacted with the first N + emission region 61 and the second N + emission region 62; the barrier trench gate consists of a second trench gate dielectric layer 74 and a second trench gate polysilicon layer 73 positioned in the second trench gate dielectric layer 74, penetrates through the P-well region 41 along the vertical direction of the device and then extends into the N drift region 3, one side of the barrier trench gate is in contact with the third N + emitter region 63, and the other side is the P-well region 41; the common leading-out end of the first groove grid polysilicon layer 71 and the second groove grid polysilicon layer 73 is a grid;

the self-adaptive NMOS structure is characterized in that the field plate structure and the self-adaptive NMOS structure in the collector structure;

the field plate structure is positioned on the surface of an N drift region between the emitter electrode structure and the collector electrode structure, two ends of the field plate structure respectively extend to the upper parts of the first P-type well region 41 and the N-type buffer layer 10, and the field plate structure comprises a dielectric layer 8 and a discontinuous polysilicon field plate positioned on the dielectric layer; the discontinuous field plates comprise a field plate 91 close to an emitter end, a field plate 93 close to a collector end and a floating field plate group 92 consisting of a plurality of floating field plates, wherein the floating field plates are positioned between the field plate 91 and the field plate 93; the field plate 91 is in short circuit with an emitter, and the field plate 93 is in short circuit with a collector;

the collector structure comprises an N-type buffer layer 10, a P + collector region 53 and a collector NMOS structure; the P + collector region 53 is positioned on the upper layer of the N-type buffer layer 10; the collector NMOS structure comprises a second P-type well region 42, a P + well potential region 54, an N + collector region 64 and a collector groove grid which are positioned in the N-type buffer layer 10; the collector grooved gate consists of a third grooved gate dielectric layer 76 and a third grooved gate polycrystalline silicon layer 75 positioned in the third grooved gate dielectric layer 76, and is contacted with the side surface of the P + collector region 53 far away from the emitter side, the second P-type well region 42 is positioned on the upper layer of the N-type buffer layer 10 on the side surface of the collector grooved gate far away from the emitter side, the P + well potential region 54 and the N + collector region 64 are respectively positioned at two ends of the upper layer of the second P-type well region 42, and the N + collector region 64 is contacted with the collector grooved gate; the common leading-out ends of the P + collector region 53, the third trench gate polysilicon layer 75 and the N + collector region 64 are collectors; the leading-out end of the P + well potential area 54 is in short circuit with one of the floating field plate leading-out ends in the floating field plate group 92.

Compared with the traditional LIGBT structure, the field plate structure disclosed by the invention can modulate the surface electric field of the drift region in a blocking state, so that the electric field distribution is more uniform, and the voltage resistance of a device is improved. The collector NMOS structure can effectively improve the turn-off speed of the device and reduce turn-off loss without an additional control circuit, and cannot introduce snapback phenomenon.

Drawings

FIG. 1 is a schematic view of the structure of example 1

Detailed Description

The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:

example 1

As shown in fig. 1, this example is an SOI LIGBT device with a multi-floating field plate and collector NMOS structure.

The working principle of the embodiment is as follows:

when a new device is conducted in the forward direction, the two sides of the control groove grid and one side, close to the emitter, of the blocking groove grid are provided with channels, the channel density of the device can be improved, the blocking groove grid has a physical blocking effect, holes stored in the drift region can be prevented from being rapidly drawn away by the first P + body contact region 51 and the second P + body contact region 52 through the first P well region 41 at the emitter end, the improvement of the carrier concentration and the current capacity of the drift region is facilitated, and low conduction voltage drop is obtained.

In the field plate structure, each floating field plate is an equipotential body, a capacitance structure is formed by each floating field plate and the adjacent field plates, and the potential on each field plate is linearly reduced from a collector terminal to an emitter terminal. A floating field plate is selected from the floating field plate group as a potential extraction field plate, a proper potential is extracted and applied to a P + well potential region 54 in the NMOS structure of the collector electrode, and the potential extraction field plate is not selected exclusively, but the potential extraction field plate is generally selected from the floating field plates near the collector electrode side in order to obtain a proper potential. Therefore, in the on state, the potential extraction field plate is close to the field plate 93, so that the voltage difference between the potential extraction field plate and the collector electrode is small, the potential extraction field plate is short-circuited with the P + well potential region 54, the potential difference between the collector electrode and the P + well potential region 54 is also small (smaller than the threshold voltage of the NMOS structure of the collector electrode), an inversion layer cannot be formed in the second P well region 42, the conductive path between the N + collector region 64 and the N-type buffer layer 10 is blocked, and the device cannot enter a unipolar conductive mode, so that the snapback effect when the device is in forward conduction is eliminated.

In the turn-off process of the new device, the voltage of the collector rises, so that the potential difference between the collector and the potential lead-out field plate is large enough, the NMOS channel of the corresponding collector is opened, the N + collector region 64 is in short circuit with the N type buffer layer 10, the P + collector region 53 is in almost equal potential short circuit with the N type buffer layer 10, the P + collector region 53 stops injecting holes into the drift region, electrons in the drift region are also rapidly extracted by the N + collector region 64 through the NMOS channel of the collector, the turn-off of the device is further accelerated, and the turn-off loss is reduced.

When the new device is in a blocking state, because the floating field plate group in the field plate structure introduces a plurality of electric field peaks on the surface of the drift region, the electric field distribution on the surface of the device is more uniform, the electric field peak value on the surface of the main junction is reduced, the voltage resistance of the device can be effectively improved, the length of the drift region can be shortened under the condition that the voltage resistance level of the new device is not changed, and the conduction voltage drop and the turn-off loss of the device are further reduced.

Compared with the traditional LIGBT structure, the invention can accelerate the turn-off of the device to reduce the turn-off loss, eliminate the snapback effect and improve the voltage endurance capability of the device without an additional control circuit, so that the length of a drift region can be shortened under the condition of maintaining the voltage endurance level, and the turn-on voltage drop and the turn-off loss of the device are further reduced.