阅读说明：本技术 逆向变换器及其控制方法 (Flyback converter and control method thereof ) 是由 林冠宇 陈佑民 郑荣霈 林天麒 张湘忠 于岳平 于 2021-05-08 设计创作，主要内容包括：一种逆向变换器,包括：一变压器、一第一开关、一第二开关和一控制电路。所述变压器包括一第一侧和一第二侧。所述第一开关在所述第一侧耦接到一输入端。所述第二开关耦接到所述第二侧和一输出端。所述控制电路耦接在所述输出端和所述第二开关之间,其中所述控制电路用于通过改变第二开关和第二侧之间的电流来调整所述输入端上的电压。(A flyback converter comprising: a transformer, a first switch, a second switch and a control circuit. The transformer includes a first side and a second side. The first switch is coupled to an input at the first side. The second switch is coupled to the second side and an output. The control circuit is coupled between the output and the second switch, wherein the control circuit is configured to adjust the voltage on the input by changing a current between the second switch and the second side.)

1. A flyback converter comprising:

a transformer including a first side and a second side;

a first switch and a second switch, wherein the first switch is coupled to the first side with respect to an input terminal, and the second switch is coupled to the second side and an output terminal; and

a control circuit coupled between the output terminal and the second switch, wherein the control circuit is configured to adjust a voltage at the input terminal by changing a current direction of a current between the second switch and the second side.

2. The flyback converter of claim 1 wherein the control circuit comprises:

a trigger circuit for generating a trigger signal by comparing an output voltage at the output terminal with a reference voltage; and

a first on-time control circuit coupled to the trigger circuit, wherein the first on-time control circuit is configured to generate a first enable signal to enable the second switch when the trigger signal indicates that the output voltage is less than the reference voltage.

3. The flyback converter of claim 2 wherein the first on-time control circuit is further configured to disable the second switch by the first enable signal when the second switch has been enabled for a predetermined length of time.

4. The flyback converter of claim 3 wherein the predetermined length of time is inversely related to a rate of change of the current between the second switch and the second side.

5. The flyback converter of claim 4 wherein the trigger circuit comprises:

a comparison circuit coupled to the output terminal, wherein the comparison circuit is configured to generate an indication signal by comparing the output voltage with the reference voltage; and

a pulse generating circuit coupled to the comparing circuit, wherein the pulse generating circuit is configured to generate the trigger signal when the indication signal indicates that the output voltage is less than the reference voltage.

6. The flyback converter of claim 5 further comprising:

a first capacitor connected in parallel with the first switch, wherein when the second switch is deactivated, a sense current flows from the first capacitor to the input voltage to reduce the voltage on the input terminal.

7. The flyback converter of claim 2 wherein the control circuit further comprises:

a delay circuit coupled to the trigger circuit, wherein the delay circuit is used for delaying the trigger signal to generate a delay signal;

a second on-time control circuit for generating an on-time signal when receiving the delay signal, wherein the on-time signal indicates an on-time of the first switch.

8. The flyback converter of claim 1 wherein the control circuit comprises:

a trigger circuit for generating a trigger signal when a current magnitude of the current between the second switch and the second side drops to zero; and

a first on-time control circuit coupled to the trigger circuit, wherein the first on-time control circuit is configured to generate a first enable signal to enable the second switch when receiving the trigger signal and to change the current direction of the current between the second switch and the second side.

9. The flyback converter of claim 8 wherein the trigger circuit comprises:

a current sensing circuit for generating an indication signal by sensing the magnitude of the current between the second switch and the second side; and

a pulse generation circuit coupled to the current detection circuit, wherein the pulse generation circuit is configured to generate the trigger signal when the indication signal indicates that the current magnitude of the current between the second switch and the second side has dropped to zero.

10. The flyback converter of claim 9 wherein the current sense circuit is further operable to instruct the first on-time control circuit to deactivate the second switch based on the magnitude of the current between the second switch and the second side.

11. A flyback (flyback) converter comprising:

a transformer including a first side and a second side;

a first switch, wherein the first switch and the first side are connected in series between an input voltage and a ground terminal;

a second switch, wherein the second switch and the second side are connected in series between an output terminal and the ground terminal;

a first control circuit coupled to the output terminal and the second switch, wherein the first control circuit is configured to compare an output voltage at the output terminal with a reference voltage, and to enable the second switch at a first time point when the output voltage is less than the reference voltage, and to disable the second switch at a second time point; and

a second control circuit coupled to the first switch, wherein the second control circuit is configured to enable the first switch at a third time point after the second switch is disabled.

12. The flyback converter of claim 11 wherein when the first control circuit enables the second switch at the first point in time, the current between the second switch and the second side is zero.

13. The flyback converter of claim 11 wherein the first control circuit is further configured to enable the second switch at a fourth time after the first switch is enabled.

14. The flyback converter of claim 13 wherein a current between the second switch and the second side has a current direction opposite to a current direction at the first point in time and the fourth point in time.

15. The flyback converter of claim 11 wherein a voltage at a terminal between the first switch and the first side drops to zero from the second time point to the third time point.

16. The flyback converter of claim 11 wherein the first control circuit comprises:

a comparison circuit for comparing the output voltage with the reference voltage to generate an indication signal; and

a pulse generating circuit coupled to the comparing circuit, wherein the pulse generating circuit is configured to generate a pulse signal at the first time point when the indication signal indicates that the output voltage is less than the reference voltage.

17. The flyback converter of claim 16 wherein the first control circuit further comprises:

a first on-time control circuit coupled to the pulse generating circuit, wherein the first on-time control circuit is configured to generate a first enable signal to enable the second switch when receiving the pulse signal.

18. The flyback converter of claim 17 wherein the first control circuit further comprises:

a delay circuit coupled to the pulse generating circuit, wherein the delay circuit is configured to delay the pulse signal from the first time point to the third time point to generate a delayed signal; and

a second on-time control circuit coupled to the delay circuit, wherein the second on-time control circuit is configured to generate an on-time signal when receiving the delay signal.

19. The flyback converter of claim 18 wherein the second control circuit comprises:

an isolation transmission circuit coupled to the second on-time control circuit, wherein the isolation transmission circuit is configured to receive and transmit the on-time signal; and

a receive circuit coupled to the isolated transmit circuit, wherein the receive circuit is configured to transmit a second enable signal to enable the first switch by identifying and decoupling information in the on-time signal when receiving the on-time signal.

20. A method of controlling a flyback converter, wherein the flyback converter includes a transformer, a first switch coupled to a first side of the transformer with respect to an input terminal, and a second switch coupled to a second side of the transformer, the method comprising:

enabling a switch coupled to a second side of a transformer at a first time point to induce and generate an output current;

deactivating the switch at a second time point, and reducing the output current to zero at the second time point;

enabling the switch to inductively generate the output current at a third time point, wherein the current direction of the output current at the third time point is opposite to the current direction at the second time point;

deactivating the switch at a fourth time point to induce an input current flowing from the input terminal to an input voltage; and

another switch coupled to a first side of the transformer is enabled at a fifth point in time, and the voltage on the input terminal drops to zero at the fifth point in time.

Technical Field

The present invention relates to an electronic device, and more particularly, to a flyback converter and a control method thereof.

Background

The commercially available power supplies can be roughly classified into linear power supplies and switching power supplies. Various switching power supplies, such as flyback converters, are the mainstream in the market. However, the switching loss of the switch in the switching power supply is a major obstacle to improving the system efficiency.

Disclosure of Invention

Therefore, an object of the present application is to provide a flyback converter and a control method thereof to solve the above problems.

According to an embodiment of the present application, a flyback converter is disclosed. The flyback converter includes: a transformer, a first switch, a second switch and a control circuit. The transformer includes a first side and a second side. The first switch is coupled to an input at the first side. The second switch is coupled to the second side and an output. The control circuit is coupled between the output and the second switch, wherein the control circuit is configured to adjust the voltage on the input by changing a current between the second switch and the second side.

According to an embodiment of the present application, a flyback converter is disclosed. The flyback converter includes: the circuit comprises a transformer, a first switch, a second switch, a first control circuit and a second control circuit. The transformer includes a first side and a second side. The first switch and the first side are connected in series between an input voltage and a ground terminal. The second switch and the second side are connected in series between an output terminal and the ground terminal. The first control circuit is coupled to the second switch, and the first control circuit is configured to compare an output voltage at the output terminal with a reference voltage, and enable the second switch at a first time point when the output voltage is less than the reference voltage. The first control circuit is further configured to deactivate the second switch at a second point in time. The second control circuit is coupled to the first switch, wherein the second control circuit is configured to enable the first switch at a third point in time after the second switch is disabled.

According to an embodiment of the present application, a method of controlling a flyback converter is disclosed. The flyback converter includes a transformer, a first switch coupled to a first side of the transformer, and a second switch coupled to a second side of the transformer. The control method comprises the following steps: enabling the second switch at a first time point to generate an output current; deactivating the second switch at a second point in time, and the output current decreasing to zero at the second point in time; enabling the second switch at a third time point to generate the output current, wherein the current direction of the output current at the third time point is opposite to the current direction at the second time point; deactivating the second switch at a fourth time point to generate an input current, wherein the input current flows from the input terminal to an input voltage source; and enabling the first switch at a fifth time point, and enabling the voltage on the input end to be reduced to zero at the fifth time point.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is a schematic diagram of a flyback converter according to an embodiment of the present application.

Fig. 2 is a timing diagram of the operation of a first portion of a flyback converter according to an embodiment of the present application.

FIG. 3 is a diagram of a first control circuit according to an embodiment of the present application.

FIG. 4 is a schematic diagram of a trigger circuit according to an embodiment of the present application.

Fig. 5 is a timing diagram illustrating the operation of the second portion of the flyback converter according to an embodiment of the present application.

FIG. 6 is a diagram of a second control circuit according to an embodiment of the present application.

Fig. 7 is a flowchart of a control method of a flyback converter according to an embodiment of the present application.

Description of the symbols:

10 flyback converter

11 transformer

110 first control circuit

120 second control circuit

Vin input voltage

IP input current

Voltage of VP

IN input terminal

SW1 first switch

D1 first diode

C1 first capacitor

VGP, VGS enable signals

IS output current

Vout output voltage

C2 second capacitor

D2 second diode

SW2 second switch

Rd detection resistance

FD feedback information

CO output capacitor

OUT1, OUT2 output terminal

210 trigger circuit

220 first on-time control circuit

230 delay circuit

240 second on-time control circuit

TG trigger signal

DS delay signal

OTS, OTS' on-time signal

211 comparison circuit

212 pulse generating circuit

VREF reference voltage

ID indication signal

250 keep apart transmission circuit

260 receiving circuit

901 step 905 step

t0-t5 time points.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different components of the disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, a first means formed over or on a second means in the following description may include embodiments in which the first and second means are formed in direct contact, and may also include embodiments in which additional means may be formed between the first and second means, such that the first and second means may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, for convenience in description, spatially relative terms, such as "below," "under," "over," "up," and the like, may be used herein to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Further, as used herein, the term "about" generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable standard error of the mean value when considered by those of skill in the art. Except in the operating/working examples, or unless otherwise expressly specified, all numerical ranges, amounts, values, and percentages such as for amounts of materials, durations of time, temperatures, operating conditions, ratios of amounts, and the like, disclosed herein are to be understood as modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that may vary depending upon the desired properties. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one end point to the other end point or between the two end points. All ranges disclosed herein are inclusive of the endpoints unless otherwise specified.

Fig. 1 is a schematic diagram of a flyback converter 10 according to an embodiment of the invention. The flyback converter 10 includes a transformer 11, a first switch SW1, a second switch SW2, a first diode D1, a second diode D2, a first capacitor C1, a second capacitor C2, a first control circuit 110, and a second control circuit 120.

The transformer 11 comprises a first side and a second side. In the present embodiment, the first side is the primary side of the transformer 11, and the second side is the secondary side of the transformer 11. In the present embodiment, the turn ratio of the primary side and the secondary side is N, where N is a natural number. The first side and first switch SW1 are connected in series between the input voltage Vin and ground. The first diode D1, the first capacitor C1, and the first switch SW1 are connected in parallel. In the present embodiment, the first switch SW1 is implemented by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). A drain terminal of the first switch SW1, a cathode of the first diode D1, and one end of the first capacitor C1 are connected to the first side of the transformer 11 through the input terminal IN. A source terminal of the first switch SW1, an anode of the first diode D1, and the other end of the first capacitor C1 are connected to the ground terminal.

It is noted that in other embodiments, the first switch SW1 can be implemented by a Bipolar Junction Transistor (BJT) or other device with similar functions. In addition, the first diode D1 and the first capacitor C1 may be components added by a designer or parasitic components formed in the first switch SW 1. In addition, the position of the first switch SW1 is not limited to being coupled between the first side and ground. In other embodiments, the first switch SW1 is coupled between the input voltage Vin and the first side.

The second side and second switch SW2 are connected in series between the output terminals OUT1 and OUT2 of the flyback converter 10. The second diode D2, the second capacitor C2, and the second switch SW2 are connected in parallel. In the present embodiment, the second switch SW2 is implemented by a MOSFET. A drain terminal of the second switch SW2, a cathode of the second diode D2, and one end of the second capacitor C2 are connected to the second side of the transformer 11. A source terminal of the second switch SW2, an anode of the second diode D2, and the other end of the second capacitor C2 are connected to the output terminal OUT 2.

It is noted that in other embodiments, the second switch SW2 can be implemented by a BJT or other device with similar functions. In addition, the second diode D2 and the second capacitor C2 may be components added by a designer or parasitic components formed in the second switch SW 2. In addition, the position of the second switch SW2 is not limited to being coupled between the second side and the output terminal OUT 2. In other embodiments, the second switch SW2 is coupled between the second side and the output terminal OUT 1.

The first control circuit 110 is coupled between the output terminal OUT1 and the second switch SW 2. The first control circuit 110 enables/disables the second switch SW2 by an enable signal VGS according to the output voltage Vout and the output current IS. When the second switch SW2 is enabled, energy is provided from the second side of the transformer 11 to the output load between the output terminals OUT1 and OUT 2. The second control circuit 120 is coupled between the first control circuit 110 and the first switch SW 1. The second control circuit 120 is used to enable/disable the first switch SW1 by an enable signal VGP. When the first switch SW1 is enabled, energy is provided from the input voltage Vin to the first side of the transformer 11.

For the flyback converter 10, the on-times of the first switch SW1 and the second switch SW2 are staggered. That is, when the first switch SW1 is enabled, the second switch SW2 is disabled, and vice versa. Referring to fig. 1 and 2 together, fig. 2 is a timing diagram illustrating the operation of a first portion of the flyback converter 10 according to an embodiment of the present application. As shown in fig. 2, at time point t0, the enable signal VGP is pulled high and indicates that the first switch SW1 is turned on. In response to the enabling of the first switch SW1, an input current IP is provided to the first side of the transformer 11. Specifically, the input current IP flows from the input voltage Vin to the first side of the transformer 11 and is stored as electrical energy.

At time point t1, the enable signal VGP is pulled low and indicates that the first switch SW1 is disabled. At the same time, the enable signal VGS is pulled high and indicates that the second switch SW2 is enabled. In response to the deactivation of the first switch SW1 and the activation of the second switch SW2, an output current IS induced on the second side of the transformer 11. Specifically, the output current IS flows from the second side of the transformer 11 to the output load. Further, at time t1, the voltage VP on the input terminal IN is pulled up to Vin + NVout. From the time point t1, the output current IS continuously supplies energy to the output load, so that the magnitude of the output current IS gradually decreases. On the other hand, the output voltage Vout gradually rises to a peak and then falls.

At time t2, the magnitude of output current IS decreases to zero. Accordingly, the enable signal VGS is pulled low and indicates that the second switch SW2 is disabled. To this end, the first control circuit 110 and the second control circuit 120 end the first part of the operation in the switching cycle.

Referring again to fig. 1, the flyback converter 10 further includes an output capacitor CO coupled between the output terminals OUT1 and OUT2, and a sensing resistor Rd coupled between the second side of the transformer 11 and the first control circuit 110. The output capacitor CO stores the energy provided by the output current IS. The sense resistor Rd provides feedback information FD to the first control circuit 110. In some embodiments, feedback information FD is the voltage across sense resistor Rd. In some embodiments, the feedback information FD reflects the magnitude of the output current IS. For example, when the output current IS decreases to zero at the time point t2, the feedback information FD informs the first control circuit 110, and the first control circuit 110 accordingly deactivates the second switch at the time point t 2.

IN the present embodiment, the first control circuit 110 IS further configured to adjust the voltage VP at the input terminal IN by changing the current direction of the output current IS between the second switch SW2 and the second side of the transformer 11. This reduces the switching loss of the first switch SW1 and improves efficiency. The details of the first control circuit 110 and the second control circuit 120 will be described in the subsequent paragraphs.

Fig. 3 is a schematic diagram of the first control circuit 110 according to an embodiment of the invention. The first control circuit 110 includes a trigger circuit 210. The trigger circuit 210 generates a trigger signal TG by comparing the output voltage Vout with the reference voltage VREF. Specifically, referring to fig. 4, fig. 4 is a schematic diagram of a trigger circuit 210 according to an embodiment of the present application. The flip-flop circuit 210 includes a comparison circuit 211 and a pulse generation circuit 212. The comparison circuit 211 generates an indication signal ID by comparing the output voltage Vout with the reference voltage VREF. When the indication signal ID indicates that the output voltage Vout is less than the reference voltage VREF, the pulse generation circuit 212 generates a pulse signal as the trigger signal TG.

Referring again to fig. 3, the first control circuit 110 further includes a first on-time control circuit 220. The first on-time control circuit 220 enables/disables the second switch SW2 by an enable signal VGS. In the present embodiment, the first on-time control circuit 220 includes, but is not limited to, an SR control circuit for controlling activation/deactivation of the second switch SW 2. For example, at time point t2, when the feedback information FD indicates that the output current IS reduced to zero, the SR control circuit disables the second switch SW 2.

In addition, the first on-time control circuit 220 further enables the second switch SW2 by an enable signal VGS when the trigger signal TG indicates that the output voltage Vout is less than the reference voltage VREF, and disables the second switch SW2 by the enable signal VGS when the second switch SW2 is enabled for a preset time period.

Reference is also made to fig. 1 and 5, wherein fig. 5 is a timing diagram illustrating the operation of the second portion of the flyback converter 10 according to an embodiment of the present application. As described above, at the time point t2, the output current IS decreases to zero and the supply of energy IS stopped. However, the output capacitor CO will supply energy to the output load, so that the output voltage Vout continues to decrease after the time point t 2. IN addition, since both the first switch SW1 and the second switch SW2 are deactivated at the time point t2, the voltage VP on the input terminal IN starts oscillating. In other words, from time t2 to time t3, the voltage VP may rise or fall. The waveform of the voltage VP from the time point t2 to the time point t3 depends on the output load.

At time point t3, the output voltage Vout is smaller than the reference voltage VREF. The trigger signal TG having a pulse waveform is thus generated, and the enable signal VGS is pulled high accordingly. Therefore, the second switch SW2 is enabled at time point t 3. IN response to the enabling of the second switch SW2, the voltage VP on the input terminal IN is pulled up to Vin + NVout again.

Since the second switch SW2 IS enabled after the output current IS reduced to zero, the output current IS having a different current direction IS further induced at the time point t 3. Specifically, the current direction of the output current IS clockwise from the time point t1 to the time point t 2. In other words, the output current IS passes through the transformer 11, the output capacitor CO, the second switch SW2, and then returns to the transformer 11. From the time point t3, the current direction of the output current IS counterclockwise. In other words, the output current IS passes through the transformer 11, the second switch SW2, the output capacitor CO, and then returns to the transformer 11.

At time t4, the enable signal VGS is pulled low. Therefore, the second switch SW2 is deactivated at time point t 4. In response to the second switch SW2 being deactivated at time t4, the magnitude of the output current IS reduced to zero again.

Since the magnitude of the output current IS pulled to zero at time t4, the input current IP IS accordingly induced on the first side of the transformer 11. Specifically, the input current IP flows from the first capacitor C1 to the input voltage Vin via the input terminal IN. IN response to the generation of the input current IP at the time point t4, the voltage VP on the input terminal IN starts to decrease. At time t5, voltage VP decreases to zero. By this the operation of the second part of the switching cycle of the flyback converter 10 is finished, the operation of the flyback converter 10 will return to the first part, and so on. Each switching cycle is repeated from t1 to t5, so that the voltage stabilization effect can be achieved.

By inducing an output current IS with an opposite current direction between the time point t3 and the time point t4, the voltage VP at the input terminal IN can be reduced to zero via an input current IP flowing from the first capacitor C1 to the input voltage Vin through the input terminal IN. With this arrangement, the switching loss of the first switch SW1 can be reduced, and the efficiency of the flyback converter 10 can be improved.

It is to be noted that, in order to accurately reduce the voltage VP to zero, the energy supplied by the input current IP during the period from the time point t4 to the time point t5 must be accurate. The energy supplied by the input current IP in the period from the time point t4 to the time point t5 IS related to the energy supplied by the output current IS in the period from the time point t3 to the time point t 4. The energy provided by the output current IS related to the magnitude of the output current IS and the duration from time t3 to time t 4. In particular, when the output current IS strong, only a short period of time IS required. On the other hand, when the output current IS weak, a long period of time IS required. That IS, in order to provide energy sufficient to reduce the voltage VP to zero, the duration from time t3 to time t4 IS inversely related to the rate of change of the output current IS, which may be reflected in the slope of the output current IS in fig. 5.

However, the voltage VP is not limited to decrease to zero. In other embodiments, the voltage VP may be decreased to the predetermined voltage in a period from a time point t4 to a time point t 5. For example, the predetermined voltage may be one fifth of Vin + NVout. The magnitude of the predetermined voltage depends on designer considerations.

Referring again to fig. 3, the first control circuit 110 further includes a delay circuit 230 and a second on-time control circuit 240. The delay circuit 230 is configured to generate a delay signal DS by delaying the trigger signal TG. The second on-time control circuit 240 is configured to generate an on-time signal OTS when receiving the delay signal DS, wherein the on-time signal OTS indicates the on-time of the first switch SW1 according to the feedback information FD. Specifically, the on-time of the first switch SW1 indicated by the on-time signal OTS is inversely related to the voltage across the detection resistor Rd indicated by the feedback information FD. That is, the larger the voltage across the detection resistor Rd is, the shorter the on time of the first switch SW1 is.

In the present embodiment, the delay signal DS is generated by delaying the trigger signal TG from the time point t3 to the time point t 5. When the second on-time control circuit 240 receives the delay signal DS at a time point t5, the on-time signal OTS is output to the second control circuit 120 to instruct the second control circuit 120 to activate the first switch SW1 at a time point t 5.

Fig. 6 is a schematic diagram of the second control circuit 120 according to an embodiment of the invention. The second control circuit 120 includes an isolated transmit circuit 250 and a receive circuit 260. The isolated transmission circuit 250 is used to generate the on-time signal OTS' by transmitting the on-time signal OTS from the second side of the transformer 11 to the first side of the transformer 11. It should be understood by those skilled in the art that the magnitude of the on-time signal OTS' and the on-time signal OTS may be different after being transmitted through the isolated transmission device 250. However, the information in the on-time signal OTS will be completely transmitted. For example, the indications of the on-time and off-time of the first switch SW1 would be fully transmitted. In the present embodiment, the isolation transmission circuit 250 includes, but is not limited to, a transformer, an optical coupler, or a capacitor.

The receiving circuit 260 is configured to receive the on-time signal OTS 'from the isolation transmission circuit 250 and generate an enable signal VGP to enable/disable the first switch SW1 according to the on-time signal OTS'. In particular, the receiving circuit 260 is used to identify and decouple information in the on-time signal OTS'. For example, the receiving circuit 260 may recognize the on-time and the off-time of the first switch SW1 according to the rising edge and the falling edge of the on-time signal OTS', respectively.

In the present embodiment, the on-time signal OTS' indicates that the first switch SW1 should be enabled at the time point t5, and the enabled duration is the same as the duration from the time point t0 to the time point t 1. Therefore, the enable signal VGP indicates that the first switch SW1 is enabled at a time point t5, and the enabled duration is the same as the duration from the time point t0 to the time point t 1.

In the flyback converter 10, the trigger circuit 210 generates the trigger signal TG by comparing the output voltage Vout with the reference voltage VREF. When the trigger signal TG indicates that the output voltage Vout is less than the reference voltage VREF, the first on-time control circuit 220 generates an enable signal VGS to enable the second switch SW 2. However, this is not a limitation of the present application. In other embodiments, the trigger signal TG may be generated based on a different mechanism.

For example, the trigger circuit 210 may include a current detection circuit for detecting the magnitude of the output current IS according to the feedback information FD to generate the indication signal ID. With this arrangement, the pulse generating circuit 212 IS also configured to generate a pulse signal as the trigger signal TG when the indication signal ID indicates that the magnitude of the output current IS reduced to zero.

In some embodiments, the trigger circuit 210 immediately generates the trigger signal TG when the magnitude of the output current IS decreases to zero. For example, when the output current IS reduced to zero at a time point t2, a trigger signal TG having a pulse waveform IS also generated at a time point t 2. Therefore, at the time point t2, the enable signal VGS instructs the second switch SW2 to turn off and immediately turn back on.

In some embodiments, the trigger circuit 210 generates the trigger signal TG after the output current IS decreases to zero. For example, when the output current IS reduced to zero at the time point t2, the trigger signal TG IS not immediately generated. For example, the trigger signal TG will be generated at a time point t 3. Therefore, the enable signal VGS indicates that the second switch SW2 is turned off at time point t2 and turned on at time point t 3.

Fig. 7 is a flow chart of a method 900 for controlling a flyback converter according to an embodiment of the present application. In this embodiment, the control method 900 may be applied to the flyback converter 10. For a better understanding, please refer to fig. 5 and 7 simultaneously. The present application does not require that the steps be performed exactly according to the flow of steps shown in fig. 7, provided that substantially the same results are achieved. The control method 900 is summarized generally as follows.

Step 901, a switch coupled to a second side of a transformer is enabled at a first time point to induce an output current.

For example, at time t1, the second switch SW2 IS enabled and the output current IS induced on the second side of the transformer 11.

Step 902, the switch is deactivated at a second time point, and the output current drops to zero at the second time point.

For example, the output current IS drops to zero at time point t2, and the second switch SW2 IS deactivated accordingly.

And 903, enabling the switch to inductively generate the output current at a third time point, wherein the current direction of the output current at the third time point is opposite to the current direction at the second time point.

For example, the second switch SW2 IS enabled at time point t3, wherein the current direction of the output current IS at time point t3 IS opposite to the current direction at time point t 2.

Step 904, deactivating the switch at a fourth time point to induce an input current flowing from the input terminal to an input voltage.

For example, the second switch SW2 is disabled at the time point t4, and the input current IP is inductively generated at the first side of the transformer 11. Specifically, an input current flows from the first capacitor C1 to the input voltage Vin through the input terminal IN.

Step 905, another switch coupled to a first side of the transformer is enabled at a fifth time point, and the voltage on the input terminal drops to zero at the fifth time point.

For example, at time t5, the voltage VP on the input terminal IN drops to zero, and the first switch SW1 is enabled.

The details of the control method 900 will be readily understood by those skilled in the art after reading the above-described embodiments. The detailed description is omitted here for brevity.

The foregoing summarizes features of various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.