阅读说明：本技术 电子设备 (Electronic device ) 是由 洪正杓 朴锺宇 边昌雨 郑胤宰 于 2021-04-29 设计创作，主要内容包括：电子设备包括：显示模块,具有前表面和与前表面相对的后表面,并且包括设置在前表面上的像素和连接到像素并从后表面暴露的显示焊盘；保护膜,设置在显示模块的后表面上；电路板,设置在显示模块与保护膜之间并且具有前表面和后表面,电路板的前表面面向显示模块的后表面,电路板包括连接到显示焊盘并且从电路板的前表面暴露的第一衬底焊盘和从电路板的后表面暴露的第二衬底焊盘；以及驱动元件,连接到第二衬底焊盘以驱动像素,其中,第二衬底焊盘和保护膜彼此间隔开。(The electronic device includes: a display module having a front surface and a rear surface opposite to the front surface, and including pixels disposed on the front surface and display pads connected to the pixels and exposed from the rear surface; a protective film disposed on a rear surface of the display module; a circuit board disposed between the display module and the protective film and having a front surface and a rear surface, the front surface of the circuit board facing the rear surface of the display module, the circuit board including first substrate pads connected to the display pads and exposed from the front surface of the circuit board and second substrate pads exposed from the rear surface of the circuit board; and a driving element connected to the second substrate pad to drive the pixel, wherein the second substrate pad and the protective film are spaced apart from each other.)

1. An electronic device, comprising:

a display module having a front surface and a rear surface opposite to the front surface, the display module including pixels disposed on the front surface and display pads connected to the pixels and exposed from the rear surface;

a protective film disposed on the rear surface of the display module;

a circuit board disposed between the display module and the protective film and having a front surface facing the rear surface of the display module and a rear surface opposite to the front surface of the circuit board, the circuit board including first substrate pads connected to the display pads and exposed from the front surface of the circuit board and second substrate pads exposed from the rear surface of the circuit board; and

a driving element connected to the second substrate pad to drive the pixel,

wherein the second substrate pad and the protective film are spaced apart from each other.

2. The electronic device of claim 1, wherein the circuit board further comprises:

a first solder resist layer;

a plurality of substrate insulating layers disposed on the first solder resist layer and including at least one of polyimide and polyethylene terephthalate;

a plurality of substrate signal lines disposed between the plurality of substrate insulating layers; and

a second solder resist layer covering the plurality of substrate insulating layers,

wherein the first substrate pad and the second substrate pad are connected to a same substrate signal line of the plurality of substrate signal lines.

3. The electronic device of claim 1, wherein the first substrate pad overlaps at least a portion of the second substrate pad.

4. The electronic device of claim 1, wherein:

the first substrate pad is spaced apart from the second substrate pad; and

the driving element is surrounded by the protective film.

5. The electronic device of claim 4, wherein:

the protective film comprises a through accommodating hole; and

the drive element is accommodated in the accommodation hole.

6. The electronic device of claim 1, wherein the circuit board includes a line area in which a substrate signal line is disposed and a dummy area adjacent to the line area.

7. The electronic device of claim 6, further comprising an electronic module disposed on an underside of the protective film and including at least one of an audio output module, a light emitting module, a light receiving module, and a camera module,

wherein the circuit board further comprises a connector connected to the electronic module.

8. The electronic device of claim 6, wherein the circuit board further comprises a metal pattern disposed in the dummy area.

9. The electronic device of claim 1, wherein the display module comprises:

a base substrate comprising a base layer and a barrier layer disposed on the base layer, wherein the base layer comprises an organic material and the barrier layer comprises an inorganic material;

a transistor disposed on the base layer and including a semiconductor pattern having a plurality of electrodes;

an organic light emitting element connected to the transistor; and

a signal line connecting the transistor and the display pad, an

Wherein the signal line is disposed on the same layer as at least one of the plurality of electrodes of the semiconductor pattern.

10. The electronic device of claim 9, wherein:

the base substrate includes a substrate hole penetrating through the base layer and the barrier layer and exposing a portion of the signal line; and

the display pad includes a conductive pattern filled in the substrate hole.

11. The electronic device of claim 9, wherein:

the base substrate further comprises an additional barrier layer disposed on an underside of the base layer and an additional base layer disposed on an underside of the additional barrier layer and comprising polyimide;

a substrate via passing through the base layer, the barrier layer, the additional base layer, and the additional barrier layer and exposing a portion of the signal line; and

the display pad is formed of a metal filled in the substrate hole.

12. The electronic device of claim 1, further comprising an adhesive layer disposed between the display module and the circuit board to join the display module and the circuit board,

wherein the adhesive layer includes at least one of a pressure sensitive adhesive, an optically clear adhesive and an optically clear resin.

13. The electronic device of claim 12, wherein the adhesive layer comprises an antistatic material.

14. The electronic device according to claim 1, wherein the display pad and the first substrate pad are connected by an anisotropic conductive film, and the second substrate pad and the driving element are connected by another anisotropic conductive film.

15. The electronic device of claim 1, wherein the protective film comprises at least one of a light blocking layer, a heat spreading layer, and a buffer layer.

16. The electronic device of claim 1, wherein the circuit board covers the entire rear surface of the display module.

Technical Field

Exemplary embodiments of the present invention relate generally to electronic devices and, more particularly, to electronic devices having improved reliability.

Background

In an electronic apparatus, a display panel is manufactured, and then a circuit board is connected to the display panel. For example, a Tape Automated Bonding (TAB) mounting method bonds a circuit board to a display panel using an Anisotropic Conductive Film (ACF).

The above information disclosed in this background section is only for background understanding of the inventive concept and, therefore, it may contain information that does not constitute prior art.

Disclosure of Invention

The electronic apparatus configured according to the exemplary embodiment of the present invention can improve durability by including the circuit board disposed between the display panel and the protective film.

Additional features of the inventive concept will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the inventive concept.

An electronic device according to an exemplary embodiment includes: a display module having a front surface and a rear surface opposite to the front surface, the display module including pixels disposed on the front surface and display pads connected to the pixels and exposed from the rear surface; a protective film disposed on a rear surface of the display module; a circuit board disposed between the display module and the protective film and having a front surface facing the rear surface of the display module and a rear surface opposite to the front surface of the circuit board, the circuit board including first substrate pads connected to the display pads and exposed from the front surface of the circuit board and second substrate pads exposed from the rear surface of the circuit board; and a driving element connected to the second substrate pad to drive the pixel, wherein the second substrate pad and the protective film are spaced apart from each other.

The circuit board may further include: a first solder resist layer; a plurality of substrate insulating layers disposed on the first solder resist layer and including at least one of polyimide and polyethylene terephthalate (PET); a plurality of substrate signal lines disposed between the plurality of substrate insulating layers; and a second solder resist layer covering the plurality of substrate insulating layers, wherein the first substrate pad and the second substrate pad may be connected to a same substrate signal line among the plurality of substrate signal lines.

The first substrate pad may overlap at least a portion of the second substrate pad.

The first substrate pad may be spaced apart from the second substrate pad, and the driving element may be surrounded by the protective film.

The protective film may include a receiving hole therethrough, and the driving element may be received in the receiving hole.

The circuit board may include a line region in which the substrate signal line is disposed and a dummy region adjacent to the line region.

The electronic device may further include an electronic module disposed on a lower side of the protective film and including at least one of an audio output module, a light emitting module, a light receiving module, and a camera module, wherein the circuit board may further include a connector connected to the electronic module.

The circuit board may further include a metal pattern disposed in the dummy region.

The display module may include: a base substrate including a base layer and a barrier layer disposed on the base layer, wherein the base layer includes an organic material and the barrier layer includes an inorganic material; a transistor disposed on the base layer and including a semiconductor pattern having a plurality of electrodes; an organic light emitting element connected to the transistor; and a signal line connecting the transistor and the display pad, wherein the signal line may be disposed on the same layer as at least one of the plurality of electrodes of the semiconductor pattern.

The base substrate may include a substrate hole penetrating through the base layer and the barrier layer and exposing a portion of the signal line, and the display pad may include a conductive pattern filled in the substrate hole.

The base substrate may further include an additional barrier layer disposed on a lower side of the base layer and an additional base layer disposed on a lower side of the additional barrier layer and including polyimide, the base substrate may include a substrate hole penetrating through the base layer, the barrier layer, the additional base layer and the additional barrier layer and exposing a portion of the signal line, and the display pad may be formed of a metal filled in the substrate hole.

The electronic apparatus includes an adhesive layer disposed between the display module and the circuit board to join the display module and the circuit board, wherein the adhesive layer includes at least one of a Pressure Sensitive Adhesive (PSA), an Optically Clear Adhesive (OCA), and an Optically Clear Resin (OCR).

The adhesive layer may include an antistatic material.

The display pad and the first substrate pad may be connected by an anisotropic conductive film, and the second substrate pad and the driving element may be connected by an additional Anisotropic Conductive Film (ACF).

The protective film may include at least one of a light blocking layer, a heat dissipation layer, and a buffer layer.

The circuit board may cover the entire rear surface of the display module.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

Fig. 1 is a perspective view of an electronic device according to an exemplary embodiment.

Fig. 2A is an exploded perspective view of an electronic device according to an example embodiment.

Fig. 2B is a block diagram of an electronic module according to an example embodiment.

Fig. 3A is a cross-sectional view of a display module according to an exemplary embodiment.

Fig. 3B is a cross-sectional view of a display module according to an exemplary embodiment.

Fig. 4 is a plan view of a display panel according to an exemplary embodiment.

Fig. 5 is a cross-sectional view taken along line I-I' of fig. 4, according to an exemplary embodiment.

Fig. 6 is a sectional view taken along line I-I' of fig. 4 according to another exemplary embodiment.

Fig. 7A is a plan view of a circuit board according to an example embodiment.

Fig. 7B is a rear view of a circuit board according to an example embodiment.

Fig. 8 is a sectional view taken along line II-II' of fig. 7A.

FIG. 9 is a cross-sectional view of some components of an electronic device according to an example embodiment.

Fig. 10A is a cross-sectional view of some components of an electronic device according to an example embodiment.

Fig. 10B is a plan view illustrating a protective film and a driving element according to an exemplary embodiment.

Fig. 11 is a plan view of a circuit board according to an example embodiment.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiments" and "implementations" are interchangeable words, which are non-limiting examples of apparatuses or methods that employ one or more of the inventive concepts disclosed herein. It may be evident, however, that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Moreover, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, the particular shapes, configurations and characteristics of the exemplary embodiments may be used or practiced in another exemplary embodiment without departing from the inventive concept.

Unless otherwise indicated, the illustrated exemplary embodiments should be understood as providing exemplary features of varying detail of some ways in which the inventive concept may be practiced. Thus, unless otherwise indicated, features, components, modules, layers, films, panels, regions, and/or aspects and the like (hereinafter, referred to individually or collectively as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

In the drawings, the use of cross-hatching and/or shading is generally employed to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-sectional lines or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated elements, and/or any other characteristic, attribute, property, etc. of an element. Moreover, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or description. When the exemplary embodiments may be implemented differently, a specific processing order may be performed differently from the described order. For example, two processes described in succession may be executed substantially concurrently or in the reverse order to that described. Further, like reference numerals denote like elements.

When an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it may be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this end, the term "connected" may mean physically, electrically, and/or fluidically connected with or without intervening elements. Further, the DR1 axis, DR2 axis, and DR3 axis are not limited to three axes (such as x-axis, y-axis, and z-axis) of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be construed as X only, Y only, Z only, or any combination of two or more of X, Y and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms first, second, etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

Spatially relative terms such as "below", "under", "lower", "above", "over", "upper", "side", etc. (e.g. as in "side wall") may be used herein for descriptive purposes and thus to describe the relationship of one element to another element(s) as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Further, the devices may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises," "comprising," "includes," and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and thus are used to leave a margin for inherent variations in measured, calculated, and/or provided values that would be recognized by those of ordinary skill in the art.

Various exemplary embodiments are described herein with reference to cross-sectional and/or exploded views as illustrations of idealized exemplary embodiments and/or intermediate structures. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature and the shapes of the regions may not reflect the actual shape of a region of a device and are, therefore, not necessarily intended to be limiting.

Some example embodiments are described and illustrated in the figures as functional blocks, units and/or modules, as is conventional in the art. Those skilled in the art will appreciate that the blocks, units, and/or modules are physically implemented via electronic (or optical) circuitry (e.g., logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wired connections, etc.) that may be formed using semiconductor-based fabrication techniques or other fabrication techniques. Where a block, unit, and/or module is implemented by a microprocessor or other similar hardware, the block, unit, and/or module may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and optionally may be driven by firmware and/or software. It is also contemplated that each block, unit, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, each block, unit and/or module of some example embodiments may be physically divided into two or more interactive and discrete blocks, units and/or modules without departing from the scope of the present inventive concept. Furthermore, the blocks, units and/or modules of some example embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a perspective view of an electronic device according to an exemplary embodiment. Fig. 2A is an exploded perspective view of an electronic device according to an example embodiment. Fig. 2B is a block diagram of an electronic module according to an example embodiment. Fig. 3A is a cross-sectional view of a display module according to an exemplary embodiment. Fig. 3B is a cross-sectional view of a display module according to an exemplary embodiment. Fig. 4 is a plan view of a display panel according to an exemplary embodiment. Fig. 5 is a cross-sectional view taken along line I-I' of fig. 4, according to an exemplary embodiment. Fig. 6 is a cross-sectional view of the display panel taken along line I-I' of fig. 4 according to another exemplary embodiment.

Referring to fig. 1 and 2, the electronic device EA may be a device activated according to an electrical signal. The electronic device EA may be used in various applications. For example, the electronic apparatus EA may be used for large-sized display apparatuses such as televisions, monitors, or outdoor billboards, and small-and medium-sized display apparatuses such as personal computers, laptop computers, personal digital terminals, car navigation units, game consoles, portable electronic apparatuses, and cameras. The inventive concept is not limited thereto and the electronic device may be used for other display devices. In the following, the electronic device EA will exemplarily be shown as a smartphone.

The electronic apparatus EA may display the image IM toward the third direction DR3 on the display surface FS parallel to the first direction DR1 and the second direction DR 2. The image IM may include a still image as well as a moving image. Fig. 1 shows a viewing window and icons as an example of the image IM. The display surface FS on which the image IM is displayed may correspond to a front surface of the electronic device EA, and may correspond to a front surface of the window panel WP.

As used herein, the front surface (or upper surface) and the rear surface (or lower surface) of each member are defined with respect to the direction in which the image IM is displayed. The front and rear surfaces may be opposite to each other in the third direction DR3, and a normal direction of each of the front and rear surfaces may be parallel to the third direction DR 3. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts, and thus may be changed to other directions. As used herein, "on-plane" may be defined as viewing from a third direction DR 3.

The electronic device EA may include a window panel WP, an antireflection panel RPP, a display module DM, a circuit board PCB, a driving element D-IC, a protective film PF, an electronic module EM, a power supply module PM, and a housing HU. In the illustrated exemplary embodiment, the window panel WP and the housing HU may be combined to form an external appearance of the electronic device EA.

The window panel WP may comprise an optically transparent insulating material. For example, the window panel WP can comprise glass or plastic. The window panel WP may have a multi-layer structure or a single-layer structure. For example, the window panel WP can include a plurality of plastic films joined by an adhesive, or can include a glass substrate and a plastic film joined by an adhesive.

As described above, the display surface FS of the window panel WP may define the front surface of the electronic device EA. The window panel WP can include a transmissive region TA and a bezel region BZA. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may have a visible light transmittance of about 90% or more.

The bezel area BZA may have a relatively lower light transmittance than the transmission area TA. The bezel area BZA may define the shape of the transmission area TA. The bezel area BZA may be adjacent to the transmission area TA, and may surround the transmission area TA.

The bezel area BZA may have a predetermined color. The bezel area BZA may cover the peripheral area NAA of the display module DM to prevent the peripheral area NAA from being seen from the outside. In some example embodiments, the bezel area BZA may be omitted.

The anti-reflective panel RPP may be disposed below the window panel WP. The anti-reflection panel RPP may reduce the reflectivity of external light incident from the upper side of the window panel WP. In some exemplary embodiments, the anti-reflection panel RPP may be omitted and may be included in the display module DM.

The display module DM may display the image IM and sense an external input. The display module DM may comprise a front surface IS having an active area AA and a peripheral area NAA. The active area AA may be an area activated according to an electrical signal.

The effective area AA according to an exemplary embodiment may be an area where the image IM is displayed, and may also be an area where an external input is sensed. The transmissive area TA may overlap at least a portion of the active area AA. For example, the transmissive area TA may overlap with at least a portion of the front surface IS or the active area AA.

Accordingly, the user can view the image IM or provide an external input through the transmissive area TA. However, the inventive concept is not limited thereto, and in some exemplary embodiments, for example, an area displaying the image IM and an area sensing an external input may be separated from each other in the effective area AA.

The peripheral area NAA may be an area covered by the bezel area BZA. The peripheral area NAA may be adjacent to the effective area AA. The peripheral area NAA may surround the effective area AA. Driving elements or driving wirings for driving the effective area AA may be provided in the peripheral area NAA.

The display module DM may include a display panel DP and a detection sensor ISP. The display panel DP may be configured to substantially generate the image IM. The user can view the image IM generated by the display panel DP from the outside through the transmissive area TA.

The detection sensor ISP may sense an external input applied from the outside. For example, the detection sensor ISP may sense an external input provided to the window panel WP.

The external input may include various forms of input provided externally from the electronic device EA. For example, the external input may include an external input applied when proximate to the electronic device EA or adjacent to the electronic device at a predetermined distance (e.g., hovering), and a contact made by a portion of the body, such as a user's hand. Further, the external input may be provided in various forms such as, but not limited to, force, pressure, and light.

The display module DM includes a display pad region PDD. The display pads of the display pad region PDD may be arranged in the second direction DR2, and a plurality of display pads may be exposed from the rear surface IU of the display module DM.

The display pad area PDD may be an area of the substrate pad area PDC connected to the circuit board PCB. The display module DM includes a plurality of display pads disposed in the display pad region PDD. The display pads may be disposed on the rear surface IU of the display module DM.

The circuit board PCB may be disposed at a lower side of the display module DM. More specifically, the circuit board PCB may be disposed on the rear surface IU of the display module DM. The circuit board PCB may cover at least a portion of the rear surface IU of the display module DM.

The circuit board PCB comprises a substrate pad area PDC. A plurality of pads in the substrate pad area PDC may be exposed from the front surface PS of the circuit board PCB.

As described above, the substrate pad region PDC may be a region connected to the display pad region PDD of the display module DM. The substrate pad region PDC may include a plurality of pads corresponding to the display pads included in the display pad region PDD.

The circuit board PCB is electrically connected to the display module DM. The circuit board PCB may generate and provide electrical signals to the display module DM or receive and process the electrical signals generated from the display module DM.

The electric signal generated in the circuit board PCB may be supplied to the pixels PX through the signal lines of the display panel DP. The signal line may include at least one or more of a power line PL, a scan line GL, a data line DL, and a light emission control line EL, which will be described later in more detail with reference to fig. 4.

An adhesive layer ADL may be disposed between the display module DM and the circuit board PCB to join the display module DM and the circuit board PCB. The area of the adhesive layer ADL in the first direction DR1 and the second direction DR2 may be smaller than the area of each of the display module DM and the circuit board PCB.

The adhesive layer ADL may be spaced apart from the display pad area PDD exposed on the rear surface IU of the display module DM and the substrate pad area PDC exposed in the front surface PS of the circuit board PCB. Accordingly, the display pad region PDD and the substrate pad region PDC may be electrically connected to each other without the adhesive layer ADL interposed therebetween.

The adhesive layer ADL may include a Pressure Sensitive Adhesive (PSA), an Optically Clear Adhesive (OCA), and/or an Optically Clear Resin (OCR).

The adhesive layer ADL according to the exemplary embodiment may include an antistatic material known in the art. In this way, the adhesive layer ADL including the antistatic material may prevent static electricity from flowing into the display module DM.

The driving element D-IC may be disposed on the rear surface PU of the circuit board PCB to be connected to the circuit board PCB. The circuit board PCB may electrically connect the driving element D-IC and the display module DM, and the driving element D-IC may generate an electrical signal to be provided to the display module DM or process the electrical signal provided from the display module DM.

The driving element D-IC may include a gate driving circuit generating a gate signal or a data driving circuit generating a data signal. However, the inventive concept is not limited thereto, and the driving element D-IC in some exemplary embodiments may include various control circuits that generate and process various control signals for driving the display module DM.

The protective film PF may be disposed on the rear surface PU of the circuit board PCB to be bonded to the circuit board PCB by an adhesive layer. The protective film PF may be disposed on a lower side of the display module DM to protect the display module DM from external impact.

The protective film PF may be spaced apart from the second substrate pad IP (see fig. 7B) exposed on the rear surface PU of the circuit board PCB. As used herein, the term "spaced apart" may refer to "non-overlapping" in a plane.

The protective film PF may include a plurality of layers. For example, the protective film PF may include a light blocking layer, a heat dissipation layer, a buffer layer, and a plurality of adhesive layers.

The light blocking layer may prevent components disposed on the rear surface IU of the display module DM from being seen. The light blocking layer may include a binder and a plurality of pigment particles dispersed therein. The pigment particles may include carbon black and the like.

The display module DM according to the exemplary embodiment may include a protective film PF including a light blocking layer to enhance light blocking performance as well as impact resistance. In this way, the electronic device EA employing the display module DM according to the exemplary embodiment may have improved visibility and reliability against external shock or stress generated during use.

The heat dissipation layer may effectively dissipate heat generated from the display module DM. The heat dissipation layer may be provided as a metal plate having good heat dissipation performance. For example, the heat dissipation layer may include at least any one of stainless steel, graphite, copper (Cu), and aluminum (Al), but is not limited thereto. The heat dissipation layer can not only enhance heat dissipation performance but also have electromagnetic wave shielding performance or electromagnetic wave absorption performance.

The buffer layer may include any one of sponge, foam, or urethane resin. When the cushioning layer comprises a foam, the cushioning layer comprises a matrix member and a plurality of voids. A plurality of voids may be dispersed in the matrix member defined by the matrix member. The buffer layer may have an elastic and porous structure.

The substrate member may comprise a flexible material. For example, the substrate layer may include a synthetic resin. For example, the substrate layer may include at least any one of Acrylonitrile Butadiene Styrene (ABS), Polyurethane (PU), Polyethylene (PE), Ethylene Vinyl Acetate (EVA), and polyvinyl chloride (PVC).

The plurality of voids easily absorbs an impact applied to the cushion layer. The plurality of voids may be defined by the porous structure of the buffer layer. The plurality of voids ensures to facilitate transformation of the shape of the buffer layer to ensure elasticity of the buffer layer, thereby enhancing impact resistance of the electronic apparatus EA. The buffer layer may include various synthetic resins, but is not limited thereto.

Referring to fig. 2B, the electronic device EA may include a display module DM, a power supply module PM, and an electronic module EM. The electronic module EM may comprise a first electronic module EM1 and a second electronic module EM 2. The display module DM, the power supply module PM, the first electronic module EM1 and the second electronic module EM2 may be electrically connected to each other.

The display module DM may include a display panel DP and a detection sensor ISP. The display panel DP may be configured to generate the image IM, and the detection sensor ISP may be configured to sense an external input.

The first electronic module EM1 and the second electronic module EM2 may comprise various functional modules for operating the electronic device EA. The first electronic module EM1 may be mounted on a motherboard electrically connected to the display module DM, or may be mounted on a separate substrate to be electrically connected to the motherboard through a connector.

The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM and an external interface IF. Some of the modules may not be mounted on the motherboard but may be electrically connected to the motherboard by a circuit board PCB.

The control module CM controls the overall operation of the electronic device EA. The control module CM may comprise a microprocessor. For example, the control module CM activates or deactivates the display module DM. The control module CM may control other modules such as the image input module IIM or the audio input module AIM based on the touch signal received from the display module DM.

The wireless communication module TM may transmit/receive wireless signals with other terminals using a bluetooth or Wi-Fi line. The wireless communication module TM may transmit/receive a voice signal using a general communication line. The wireless communication module TM includes a transmission unit TM1 that modulates a signal to be transmitted and transmits the signal, and a reception unit TM2 that demodulates the received signal.

The image input module IIM processes an image signal and converts the signal into image data that can be displayed on the display module DM. The audio input module AIM receives an external sound signal through a microphone in a recording mode, a voice recognition mode, and the like, and converts the signal into electrical voice data.

The external interface IF may be an interface connected to an external charger, a wired/wireless data port, a card (e.g., memory card, SIM/UIM card) holder, and the like.

The second electronic module EM2 may comprise an audio output module AOM, a light emitting module LM, a light receiving module LRM and a camera module CMM. These components may be directly mounted on the motherboard or mounted on a separate substrate to be electrically connected to the display module DM through a connector, or may be electrically connected to the first electronic module EM 1.

The audio output module AOM converts sound data received from the wireless communication module TM or sound data stored in the memory MM and outputs the data to the outside.

The light emitting module LM generates and outputs light. The light emitting module LM can output infrared light. For example, the light emitting module LM may include an LED element. For example, the light receiving module LRM may detect infrared light. The light receiving module LRM may be activated when infrared light having a predetermined level or higher is detected. The light receiving module LRM may include a CMOS sensor. After the infrared light generated from the light emitting module LM is output to be reflected by an external object (e.g., a user's finger or face), the reflected infrared light may be incident on the light receiving module LRM. The camera module CMM may capture external images.

The power supply module PM supplies power required for the overall operation of the electronic device EA. The power module PM may include a conventional battery module.

Referring to fig. 3A, the display module DM may include a display panel DP, a detection sensor ISP, and an engaging member SLM.

The display panel DP may include the first base substrate BS1, the circuit element layer ML-D, and the display element layer EML. The detection sensor ISP may comprise a second base substrate BS2 and a sensing circuit layer ML-T.

The first base substrate BS1 and the second base substrate BS2 may each be a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a stacked structure including a plurality of insulating layers.

The circuit element layer ML-D may be provided on the first base substrate BS 1. The circuit element layer ML-D may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the circuit element layer ML-D may form a signal line or a control circuit for the pixel PX.

The display element layer EML may be disposed on the circuit element layer ML-D. The display element layer EML may include an organic light emitting diode. However, the inventive concept is not limited thereto, and in other exemplary embodiments, the display element layer EML may include an inorganic light emitting diode, an organic-inorganic light emitting diode, or a liquid crystal layer.

The second base substrate BS2 may be disposed on the display element layer EML. A predetermined space may be defined between the second base substrate BS2 and the display element layer EML. The space may be filled with air or an inert gas. In some exemplary embodiments, the space may additionally or alternatively be filled with a filler, such as a silicone-based polymer, an epoxy-based resin, or an acrylic-based resin.

The sensing circuit layer ML-T may be disposed on the second base substrate BS 2. The sensing circuit layer ML-T may include a plurality of insulating layers and a plurality of conductive layers. The plurality of conductive layers may include a sensing electrode sensing an external input, a sensing wiring electrically connected to the sensing electrode, and a sensing pad electrically connected to the sensing wiring.

The joining member SLM may be arranged between the first base substrate BS1 and the second base substrate BS 2. The joining member SLM may join the first base substrate BS1 and the second base substrate BS 2. The joining member SLM may include an organic material such as a photocurable resin or a photoplastic resin or an inorganic material such as a frit seal, but is not limited thereto.

Referring to fig. 3B, the display module DM-1 according to an exemplary embodiment may include a display panel DP-1 and a detection sensor ISP-1.

The display panel DP-1 may include a first base substrate BS1, a circuit element layer ML-D, a display element layer EML, and a thin film encapsulation layer ETL. The detection sensor ISP-1 may comprise a sensing circuit layer ML-T. The thin film encapsulation layer ETL and the second base substrate BS2 may have substantially the same configuration.

The thin film encapsulation layer ETL may seal the display element layer EML from the outside to prevent moisture, oxygen, and the like from flowing into the display element layer EML. The thin film encapsulation layer ETL may include an organic layer and a plurality of inorganic layers sealing the organic layer.

The inorganic layer may prevent external moisture, oxygen, and the like from penetrating into the display element layer EML. The inorganic layer may comprise silicon oxide (SiO)_x) Silicon oxynitride (SiO)_xN_y) Zirconium oxide (ZrO)_x) Or a combination thereof. For example, the inorganic layer may be formed by a deposition process.

An organic layer may be disposed on the display element layer EML to provide a flat surface. The curved portions or particles formed on the upper surface of the display element layer EML may be covered with an organic layer to prevent a component (e.g., the detection sensor ISP-1) formed on the organic layer from being affected.

According to an exemplary embodiment, the display panel DP-1 and the detection sensor ISP-1 may be formed through a continuous process. In particular, the sensing circuit layer ML-T may be directly formed on the thin film encapsulation layer ETL.

Referring to fig. 4, the display panel DP may include a plurality of pixels PX, a plurality of signal lines GL, DL, PL, and EL, and a plurality of display pads VP.

The effective area AA of the display panel DP may be an area where an image is displayed, and the peripheral area NAA may be an area where a driving circuit, a driving wiring, and the like may be disposed. In the effective area AA, a light emitting area in which the plurality of pixels PX emit light and a non-light emitting area adjacent to the light emitting area may be disposed.

A plurality of signal lines GL, DL, PL, and EL may be connected to the pixel PX to transmit electric signals to the pixel PX. Fig. 4 exemplarily shows the scanning lines GL, the data lines DL, the power lines PL, and the light emission control lines EL among the signal lines included in the display panel DP. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the initialization voltage line may be further included in the peripheral area NAA.

Further, the power pattern may be provided in the peripheral area NAA to be connected to the plurality of power lines PL. Accordingly, the display panel DP may supply the same power signal to the pixels PX.

The display pads VP exposed on the rear surface IU of the display module DM may be provided in plurality to be respectively connected to the data lines DL. The remaining display pads VP may be connected to the power pattern to be electrically connected to the power lines PL. The display panel DP may supply the electric signal supplied from the driving element D-IC to the pixel PX through the display pad VP.

Referring to fig. 5, the display panel DP according to an exemplary embodiment may include a plurality of insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layer, the semiconductor layer, and the conductive layer can be formed by, for example, coating or vapor deposition. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography method. In this way, a semiconductor pattern, a conductive pattern, a signal line, and the like can be formed.

The base substrate BS1 may comprise a multilayer structure with a base layer PI and a barrier layer BI. The base layer PI may include an organic material.

For example, the substrate layer PI may include at least one or more of polyimide, polyethylene naphthalate, polyethylene terephthalate, polyarylate, polycarbonate, polyetherimide and polyethersulfone. In this way, the base layer PI may be flexible. However, the inventive concept is not so limited, and in some exemplary embodiments, base substrate BS1 may be rigid.

The barrier layer BI is disposed on the base layer PI. The barrier layer BI may cover the base layer PI. The barrier layer BI may be an insulating layer including an inorganic material. For example, the barrier layer BI may include aluminum oxide (AlO)_x) Titanium oxide (TiO)_x) Silicon oxide (SiO)_x) Silicon oxynitride (Si)O_xN_y) Zirconium oxide (ZrO)_x) And hafnium oxide (HfO)_x) At least one or more of (a). The barrier layer BI may be formed of a plurality of inorganic layers. The barrier layer BI may prevent impurities from entering from the outside.

The transistor TR may include a plurality of electrodes. For example, the source SE, the active electrode AP, and the drain DE of the transistor TR are formed of a semiconductor pattern. The transistor TR controls charge transfer in the semiconductor pattern through the gate electrode GE to output an electric signal input from the source electrode SE through the drain electrode DE.

The first insulating layer 10 is provided on the base substrate BS 1. The first insulating layer 10 covers the semiconductor pattern. The first insulating layer 10 may include an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include aluminum oxide (AlO)_x) Titanium oxide (TiO)_x) Silicon oxide (SiO)_x) Silicon oxynitride (SiO)_xN_y) Zirconium oxide (ZrO)_x) And hafnium oxide (HfO)_x) At least one or more of (a).

In the illustrated embodiment, the first insulating layer 10 may be a single layer of silicon oxide (SiO)_x) And (3) a layer. An insulating layer to be described later other than the first insulating layer 10 may include an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

The gate electrode GE is disposed on the first insulating layer 10. The gate electrode GE may be a part of the metal pattern. The gate electrode GE may overlap the active electrode AP. The gate electrode GE may function as a mask in a process of doping a semiconductor pattern.

The second insulating layer 20 covering the gate electrode GE is disposed on the first insulating layer 10. The second insulating layer 20 may include an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. In the exemplary embodiment shown, the second insulating layer 20 may be a single layer of silicon oxide (SiO)_x) And (3) a layer.

The first connection electrode SD1 may be disposed on the second insulation layer 20. The first connection electrode SD1 may be connected to any one of the signal lines shown in fig. 4 through a contact hole penetrating the first insulating layer 10 and the second insulating layer 20.

The third insulating layer 30 is disposed on the second insulating layer 20. The third insulating layer 30 may include an organic layer. The second connection electrode SD2 may be disposed on the third insulation layer 30. The second connection electrode SD2 may be connected to the first connection electrode SD1 through a contact hole penetrating the third insulating layer 30.

The fourth insulating layer 40 covering the second connection electrode SD2 is disposed on the third insulating layer 30. The fourth insulating layer 40 may include an organic layer.

In the illustrated exemplary embodiment, the organic light emitting diode OLED may include a first electrode EL1, a hole control layer HCL, a light emitting layer ELP, an electron control layer ECL, and a second electrode EL 2.

The first electrode EL1 is disposed on the fourth insulating layer 40. The first electrode EL1 is connected to the second connection electrode SD2 through a contact hole passing through the fourth insulating layer 40.

A display opening is defined in the pixel defining film PDL. The display opening of the pixel defining film PDL exposes at least a portion of the first electrode EL 1. A portion of the first electrode EL1 exposed through the display opening may be defined as a light-emitting region, and a portion adjacent to the light-emitting region may be defined as a non-light-emitting region.

The hole control layer HCL may be disposed in the light-emitting region and the non-light-emitting region in common. The hole control layer HCL may include a hole transport layer, and may further include a hole injection layer. The light emitting layer ELP is disposed on the hole control layer HCL. The light emitting layer ELP may be disposed in a region corresponding to the display opening. The light emitting layer ELP may be separately formed in each of the pixels PX.

The electron control layer ECL is disposed on the light emitting layer ELP. The electron control layer ECL may include an electron transport layer and may also include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be collectively formed in the plurality of pixels PX using an open mask. The second electrode EL2 is disposed on the electron control layer ECL. The second electrode EL2 may be continuously formed in common in the plurality of pixels PX.

The thin film encapsulation layer ETL is disposed on the second electrode EL 2. The thin film encapsulation layer ETL is commonly disposed in the plurality of pixels PX. In the exemplary embodiment shown, the thin film encapsulation layer ETL may directly cover the second electrode EL 2. In some exemplary embodiments, a capping layer covering the second electrode EL2 may also be disposed between the thin film encapsulation layer ETL and the second electrode EL 2. In this case, the thin film encapsulation layer ETL may directly cover the capping layer. The thin film encapsulation layer ETL according to the illustrated exemplary embodiment may correspond to the thin film encapsulation layer ETL described with reference to fig. 3B.

According to an exemplary embodiment, one of the signal lines (e.g., the data line DL, and hereinafter also referred to as the signal line DL) shown in fig. 4 may extend from the semiconductor pattern and be connected to the display pad VP. In particular, the signal line DL may extend from the effective area AA to the peripheral area NAA to be connected to the display pad VP.

The signal line DL may be disposed on the same layer as any one of the electrodes included in the transistor TR. For example, the signal line DL may be branched from the source SE. In the illustrated exemplary embodiment, the signal line DL may be disposed on the barrier layer BI.

In the illustrated exemplary embodiment, the base substrate BS1 overlaps the peripheral region NAA, and a substrate hole VH penetrating the base layer PI and the barrier layer BI may be defined in the base substrate BS1 to expose a portion of the signal line DL.

The display pad VP may be connected to a portion of the signal line DL. The display pad VP may be formed of a metal filled in the substrate hole VH. The display pad VP and the signal line DL may be provided in plurality to be connected to the corresponding pixel PX.

Referring to fig. 6, the base substrate BS1- ｃA of the display panel DP- ｃA according to the illustrated exemplary embodiment may include ｃA barrier layer BI1, ｃA base layer PI1, an additional barrier layer BI2, and an additional base layer PI2 stacked along the third direction DR 3. The additional substrate layer PI2 may comprise polyimide.

The components of the display panel DP- ｃA according to the illustrated exemplary embodiment are substantially the same as those of the display panel DP shown in fig. 5 except for the base substrate BS1- ｃA. Thus, in order to avoid redundancy, ｃA repeated description of substantially the same components of the display panel DP- ｃA, which have been described above, will be omitted.

The base substrate BS1-a overlaps the peripheral region NAA, and a substrate hole VH-a penetrating the barrier layer BI1, the base layer PI1, the additional barrier layer BI2, and the additional base layer PI2 may be defined in the base substrate BS1-a to expose a portion of the signal line DL.

The display pad VP- ｃA may be connected to ｃA portion of the signal line DL. The display pad VP- ｃA may be formed of ｃA metal filled in the substrate hole VH- ｃA. The display pad VP- ｃA and the signal line DL may be provided in plurality to be connected to the corresponding pixel PX.

Fig. 7A is a plan view of a circuit board according to an example embodiment. Fig. 7B is a rear view of a circuit board according to an example embodiment. Fig. 8 is a sectional view taken along line II-II' of fig. 7A.

Referring to fig. 7A and 7B, the circuit board PCB according to the illustrated exemplary embodiment may be divided into a line area CBA and a dummy area DMA adjacent to the line area CBA. The circuit board PCB comprises a front surface PS facing the rear surface IU of the display module DM and a rear surface PU facing the front surface PS.

The line area CBA of the circuit board PCB may include a substrate signal line mounted on the circuit board PCB, a first substrate pad CP disposed in the first substrate pad area PDC, and a second substrate pad IP disposed in the second substrate pad area PDI.

The first substrate pad CP is disposed on the front surface PS and overlaps the line region CBA. The first substrate pad CP may be connected to a display pad VP of the display module DM. The second substrate pad IP is disposed on the rear surface PU and overlaps the line area CBA. The second substrate pad IP may be connected to the driving element D-IC.

In the illustrated exemplary embodiment, the circuit board PCB may further include a connector CNT protruding from the line region CBA in the second direction DR 2. The connector CNT may be used as a test connector for checking whether the circuit board PCB is operated or not in a process of assembling the display module DM. Furthermore, the connector CNT may be bent in a direction toward the rear surface PU to be connected to the electronic module EM, but is not limited thereto.

The line regions CBA according to the illustrated exemplary embodiment are illustrated as being disposed on the right and bottom sides of the circuit board PCB, but the inventive concept is not limited thereto. For example, in other exemplary embodiments, the position of the line area CBA may be changed according to the configuration of the display module DM and the circuit board PCB.

Referring to fig. 8, a circuit board PCB according to the illustrated exemplary embodiment may include a plurality of insulating layers. For example, the circuit board PCB may include a first solder resist layer SR-1, a first substrate insulating layer IL-1, a second substrate insulating layer IL-2, and a second solder resist layer SR-2, which are sequentially stacked.

The first and second substrate insulating layers IL-1 and IL-2 may include at least any one of polyimide, polyethylene naphthalate, polyethylene terephthalate, polyarylate, polycarbonate, polyetherimide and polyethersulfone. The second solder resist layer SR-2 may cover the first substrate insulating layer IL-1 and the second substrate insulating layer IL-2.

The circuit board PCB may comprise conductive pads arranged between a plurality of insulating layers. For example, the circuit board PCB may include a first substrate signal line SL-1 disposed on the first solder resist layer SR-1 and a second substrate signal line SL-2 insulated from the first substrate signal line SL-1, wherein the first substrate insulating layer IL-1 is interposed between the first substrate signal line SL-1 and the second substrate signal line SL-2.

The circuit board PCB may comprise a first substrate pad CP and a second substrate pad IP. The first substrate pad CP may be disposed in a hole penetrating the second solder resist layer SR-2 and the second substrate insulating layer IL-2 to expose a portion of the second substrate signal line SL-2 from the front surface PS. The second substrate pad IP may be disposed in a hole penetrating the first solder resist layer SR-1 and the first substrate insulating layer IL-1 to expose a portion of the second substrate signal line SL-2 from the rear surface PU.

In the illustrated exemplary embodiment, the first substrate pad CP may overlap at least a portion of the second substrate pad IP.

The first substrate pad CP and the second substrate pad IP may be connected to opposite surfaces of the second substrate signal line SL-2 of the substrate signal lines SL-1 and SL-2.

Fig. 8 exemplarily shows the circuit board PCB as having two substrate insulating layers IL-1 and IL-2 and two substrate signal lines SL-1 and SL-2, but the inventive concept is not limited thereto. For example, in some example embodiments, a circuit board PCB may include two or more substrate insulating layers and substrate signal lines.

In addition, in some exemplary embodiments, the circuit board PCB may further include a bridge pattern penetrating the substrate insulating layers IL-1 and IL-2 to connect the first substrate signal line SL-1 and the second substrate signal line SL-2 disposed on different layers.

FIG. 9 is a cross-sectional view of some components of an electronic device according to an example embodiment.

Referring to fig. 9, the display pad VP of the display module DM and the first substrate pad CP of the circuit board PCB may be connected by the conductive adhesive member ACF. Further, the driving element D-IC and the second substrate pad IP of the circuit board PCB may be connected by the conductive adhesive member ACF. The conductive adhesive member ACF may include an anisotropic conductive adhesive film (ACF).

In an area other than the area where the display pad VP and the first substrate pad CP are connected by the conductive adhesive member ACF, the display module DM and the circuit board PCB may be connected by the first adhesive layer ADL 1. Further, in an area other than the area where the driving element D-IC and the second substrate pad IP are connected by the conductive adhesive member ACF, the circuit board PCB and the protective film PF may be connected by the second adhesive layer ADL 2.

In the illustrated exemplary embodiment, the first substrate pad CP may overlap at least a portion of the second substrate pad IP.

The first adhesive layer ADL1 and the second adhesive layer ADL2 may each include at least one of a Pressure Sensitive Adhesive (PSA), an Optically Clear Adhesive (OCA), and an Optically Clear Resin (OCR), but are not limited thereto.

According to an exemplary embodiment, the circuit board PCB is disposed between the display module DM and the protective film PF. In this way, the flexible circuit board bent from the display panel DP to be connected to the driving elements D-IC can be avoided, and defects such as cracks in the signal lines that may be generated due to bending of the display panel DP can be prevented or at least suppressed.

Further, the bending process that circumvents the display panel DP during manufacturing may simplify the process for manufacturing the electronic apparatus EA. Further, since the insulating layer provided in the circuit board PCB may include any one of polyimide and polyethylene terephthalate (PET), impact resistance of the electronic apparatus EA may be improved.

Fig. 10A is a cross-sectional view of some components of an electronic device according to an example embodiment. Fig. 10B is a plan view illustrating a protective film and a driving element according to an exemplary embodiment. The same/similar components shown in fig. 9 are given the same/similar reference numerals, and thus, a repetitive description thereof will be omitted. Hereinafter, the electronic device EA-1 according to the illustrated exemplary embodiment will be described.

Referring to fig. 10A and 10B, the display pad VP of the display module DM and the first substrate pad CP of the circuit board PCB-1 according to the illustrated exemplary embodiment may be connected by a conductive adhesive member ACF. Further, the driving element D-IC and the second substrate pad IP-1 of the circuit board PCB-1 may be connected by the conductive adhesive member ACF. The conductive adhesive member ACF may include an anisotropic conductive adhesive film (ACF).

In an area other than the area where the display pad VP and the first substrate pad CP are connected by the conductive adhesive member ACF, the display module DM and the circuit board PCB-1 may be connected by the first adhesive layer ADL 1.

Further, the circuit board PCB-1 and the protective film PF-1 may be connected by the second adhesive layer ADL2-1 in an area other than an area where the driving element D-IC and the second substrate pad IP-1 are connected by the conductive adhesive member ACF.

In the illustrated exemplary embodiment, the first substrate pad CP may be spaced apart from the second substrate pad IP-1. Accordingly, the driving element D-IC may be connected to the second substrate pad IP-1 exposed through the first hole A-OP of the second adhesive layer ADL2-1 and the second hole P-OP of the protective film PF-1. In this case, the driving element D-IC may be surrounded by the second adhesive layer ADL2-1 and the protective film PF-1.

Fig. 11 is a plan view of a circuit board according to an example embodiment. The same/similar components shown in fig. 7A and 7B are given the same/similar reference numerals, and thus, a repetitive description thereof will be omitted.

The circuit board PCB-1 according to the illustrated exemplary embodiment may be divided into a line area CBA and a dummy area DMA adjacent to the line area CBA. The line region CBA may include a substrate pad CP disposed on the first substrate pad region PDC and a connector CNT protruding from the line region CBA along the second direction DR 2. The circuit board PCB-1 according to the illustrated exemplary embodiment may further include a metal pattern DMP disposed in the dummy area DMA.

The metal pattern DMP may have an electromagnetic wave shielding property or an electromagnetic wave absorbing property. Since the metal pattern DMP is embedded in the circuit board PCB-1, the functional layer including the metal plate in the protective film PF described in fig. 2A may be omitted. Therefore, it is possible to provide the electronic apparatus EA thinner than the electronic apparatus with the provided separate metal plate.

According to an exemplary embodiment, the circuit board PCB is disposed between the display module and the protective film. In this way, a flexible circuit board bent from the display panel to be connected to the driving element can be avoided, and defects that may be generated due to bending of the display panel, such as cracks in the signal lines, can be prevented or at least suppressed.

Further, the bending process that circumvents the display panel DP during manufacturing may simplify the process for manufacturing the electronic apparatus EA. Further, since the insulating layer provided in the circuit board includes any one of polyimide and polyethylene terephthalate (PET), the impact resistance of the electronic apparatus EA can be improved.

While certain exemplary embodiments and examples have been described herein, other embodiments and modifications will be apparent from this description. The inventive concept is therefore not limited to the embodiments but is to be defined by the appended claims and by the various modifications and equivalent arrangements which are apparent to those skilled in the art.