阅读说明：本技术 一种cpu与fpga的数据传输动态监测方法及系统 (Dynamic monitoring method and system for data transmission of CPU and FPGA ) 是由 谢元睿 史晓岩 于 2021-09-27 设计创作，主要内容包括：本发明公开了一种CPU与FPGA的数据传输动态监测方法及系统,其中,所述方法包括：构建CPU与FPGA间的数据传输通道；获得CPU端的第一数据包,且进行初始动态标记,获得第一动态标记；获得所述第一数据包传输至所述FPGA端的第二数据包；设定FPGA端的数据回传应答规则；根据所述数据回传应答规则,获得所述FPGA端对所述第二数据包的第一回传应答序号,且进行回传动态标记,获得第二动态标记；将所述第一动态标记和所述第二动态标记上传至数据传输动态监测系统,获得动态监测结果,对所述CPU与所述FPGA的数据传输进行动态监测。解决了现有技术中存在CPU与FPGA之间进行大数据传输时,常会由于FPGA的反压/阻塞问题,导致传输过程中数据丢失的技术问题。(The invention discloses a method and a system for dynamically monitoring data transmission of a CPU and an FPGA, wherein the method comprises the following steps: constructing a data transmission channel between the CPU and the FPGA; acquiring a first data packet at a CPU end, and carrying out initial dynamic marking to acquire a first dynamic mark; acquiring a second data packet transmitted from the first data packet to the FPGA end; setting a data return response rule of an FPGA end; according to the data return response rule, obtaining a first return response serial number of the FPGA end to the second data packet, and carrying out return dynamic marking to obtain a second dynamic mark; and uploading the first dynamic mark and the second dynamic mark to a data transmission dynamic monitoring system to obtain a dynamic monitoring result, and dynamically monitoring the data transmission of the CPU and the FPGA. The technical problem that data are lost in the transmission process due to the back pressure/blockage problem of the FPGA when big data are transmitted between the CPU and the FPGA in the prior art is solved.)

1. A data transmission dynamic monitoring method of a CPU and an FPGA is disclosed, wherein the method comprises the following steps:

constructing a data transmission channel between the CPU and the FPGA;

acquiring a first data packet at a CPU end, and carrying out initial dynamic marking to acquire a first dynamic mark;

acquiring a second data packet transmitted from the first data packet to the FPGA terminal based on the data transmission channel;

setting a data return response rule of an FPGA end;

according to the data return response rule, obtaining a first return response serial number of the FPGA end to the second data packet, and carrying out return dynamic marking to obtain a second dynamic mark;

and uploading the first dynamic mark and the second dynamic mark to a data transmission dynamic monitoring system to obtain a dynamic monitoring result, and dynamically monitoring the data transmission of the CPU and the FPGA.

2. The method of claim 1, wherein the method further comprises:

acquiring a first data transmission rate and first data packet information according to the first dynamic mark;

obtaining a second data transmission rate and second data packet information according to the second dynamic mark;

obtaining data transmission rate difference information based on the first data transmission rate and the second data transmission rate;

judging whether the second data packet information has packet loss or not based on the first data packet information;

and if the second data packet information has packet loss, synthesizing the data transmission rate difference information to generate a first dynamic monitoring result.

3. The method of claim 2, wherein the method further comprises:

acquiring a returned response sequence number accommodating threshold value of the CPU end;

presetting a data transmission rate response rule according to the return response serial number accommodating threshold;

according to the data transmission rate response rule and the data transmission rate difference information, backward predicting the real-time returned response serial number capacity value of the CPU end;

judging whether the real-time returned response serial number capacity value reaches a preset early warning capacity value or not;

if the real-time return response serial number capacity value reaches the preset early warning capacity value, generating a first early warning instruction;

and early warning is carried out on the first dynamic monitoring result according to the first early warning instruction.

4. The method according to claim 3, wherein the presetting of the data transmission rate response rule according to the backhaul acknowledgement sequence number accommodation threshold further comprises:

according to the return response serial number accommodating threshold value, acquiring a first-order return response serial number capacity value, a second-order return response serial number capacity value and a third-order return response serial number capacity value;

generating a first preset transmission rate according to the first-order return response serial number capacity value and the second-order return response serial number capacity value;

generating a second preset transmission rate according to the third-order return response sequence number capacity value, wherein the second preset transmission rate is lower than the first preset transmission rate;

and constructing the data transmission rate response rule based on the first preset transmission rate and the second preset transmission rate.

5. The method of claim 4, wherein the method further comprises:

generating a first-order transmission rate according to the first-order return response sequence number capacity value;

generating a second-order transmission rate according to the second-order return response sequence number capacity value, wherein the first-order transmission rate and the second-order transmission rate are both contained in the first preset transmission rate, and the first-order transmission rate is higher than the second-order transmission rate;

marking the first-order transmission rate to obtain first marking information, wherein the first marking information comprises that the serial number capacity value in a serial number pool loaded by the CPU end is in a satisfied state;

marking the second-order transmission rate to obtain second marking information, wherein the second marking information comprises that the serial number capacity value in the serial number pool loaded by the CPU end is in a half-full state;

and marking the second preset transmission rate to obtain third marking information, wherein the third marking information comprises that the serial number capacity value in the serial number pool loaded by the CPU end is in an unsatisfied state, and the first early warning instruction is generated.

6. The method according to claim 1, wherein the setting of the data feedback response rule at the FPGA side further comprises:

obtaining a first exclusive response packet;

according to the first exclusive response packet, performing matching response on the second data packet transmitted to the FPGA end;

obtaining a first additional response packet, wherein the first additional response packet is included in the first data packet;

and matching and responding the second data packet transmitted to the FPGA end according to the first additional response packet.

7. The method according to claim 6, wherein the performing matching response on the second data packet transmitted to the FPGA end according to the first additional response packet further comprises:

judging whether the second data packet is consistent with the first data packet or not;

and if the second data packet is consistent with the first data packet, matching and responding the second data packet transmitted to the FPGA end according to the first additional response packet.

8. A data transmission dynamic monitoring system of a CPU and an FPGA, wherein the system comprises:

a first building unit: the first construction unit is used for constructing a data transmission channel between the CPU and the FPGA;

a first obtaining unit: the first obtaining unit is used for obtaining a first data packet at the CPU end and carrying out initial dynamic marking to obtain a first dynamic mark;

a second obtaining unit: the second obtaining unit is configured to obtain, based on the data transmission channel, a second data packet transmitted to the FPGA side by the first data packet;

a first setting unit: the first setting unit is used for setting a data return response rule of the FPGA end;

a third obtaining unit: the third obtaining unit is configured to obtain a first return response serial number of the second data packet from the FPGA end according to the data return response rule, and perform a return dynamic marking to obtain a second dynamic marking;

a first uploading unit: the first uploading unit is used for uploading the first dynamic mark and the second dynamic mark to a data transmission dynamic monitoring system to obtain a dynamic monitoring result, and dynamically monitoring data transmission of the CPU and the FPGA.

9. A CPU and FPGA data transmission dynamic monitoring system comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the method of any one of claims 1-7 when executing the program.

Technical Field

The invention relates to the field of data transmission, in particular to a method and a system for dynamically monitoring data transmission of a CPU (central processing unit) and an FPGA (field programmable gate array).

Background

In recent years, with the rapid development of social service informatization, data in various aspects such as the internet, the internet of things, finance, logistics, electromagnetism and the like all show exponential growth. The transmission of big data is an important ring of a big data processing basic flow, and the high-performance data transmission can provide guarantee for subsequent data analysis, particularly real-time analysis.

However, in the process of implementing the technical solution of the invention in the embodiments of the present application, the inventors of the present application find that the above-mentioned technology has at least the following technical problems:

in the prior art, when big data is transmitted between a CPU and an FPGA, data is lost in the transmission process due to the back pressure/blockage problem of the FPGA.

Disclosure of Invention

Aiming at the defects in the prior art, the embodiment of the application aims to solve the technical problem that data is lost in the transmission process due to the back pressure/blockage problem of the FPGA when large data is transmitted between the CPU and the FPGA in the prior art by providing the dynamic monitoring method and the system for data transmission of the CPU and the FPGA. The data transmission of the CPU end of the data transmission is dynamically marked initially, the response serial number returned by the FPGA end is marked secondarily dynamically, the initial mark and the secondary mark are subjected to characteristic comparison, including data transmission rate, whether packet loss exists or not, and the like, so that the data transmission process is dynamically monitored according to the comparison result, the data transmission between the CPU and the FPGA is monitored in real time, normal and reliable data transmission is ensured, and the technical effect of improving the data transmission rate is achieved.

In one aspect, an embodiment of the present application provides a method for dynamically monitoring data transmission between a CPU and an FPGA, where the method includes: constructing a data transmission channel between the CPU and the FPGA; acquiring a first data packet at a CPU end, and carrying out initial dynamic marking to acquire a first dynamic mark; acquiring a second data packet transmitted from the first data packet to the FPGA terminal based on the data transmission channel; setting a data return response rule of an FPGA end; according to the data return response rule, obtaining a first return response serial number of the FPGA end to the second data packet, and carrying out return dynamic marking to obtain a second dynamic mark; and uploading the first dynamic mark and the second dynamic mark to a data transmission dynamic monitoring system to obtain a dynamic monitoring result, and dynamically monitoring the data transmission of the CPU and the FPGA.

On the other hand, the application also provides a data transmission dynamic monitoring system of the CPU and the FPGA, wherein the system includes: a first building unit: the first construction unit is used for constructing a data transmission channel between the CPU and the FPGA; a first obtaining unit: the first obtaining unit is used for obtaining a first data packet at the CPU end and carrying out initial dynamic marking to obtain a first dynamic mark; a second obtaining unit: the second obtaining unit is configured to obtain, based on the data transmission channel, a second data packet transmitted to the FPGA side by the first data packet; a first setting unit: the first setting unit is used for setting a data return response rule of the FPGA end; a third obtaining unit: the third obtaining unit is configured to obtain a first return response serial number of the second data packet from the FPGA end according to the data return response rule, and perform a return dynamic marking to obtain a second dynamic marking; a first uploading unit: the first uploading unit is used for uploading the first dynamic mark and the second dynamic mark to a data transmission dynamic monitoring system to obtain a dynamic monitoring result, and dynamically monitoring data transmission of the CPU and the FPGA.

One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

the data transmission of the CPU end of the data transmission is dynamically marked initially, the response serial number returned by the FPGA end is marked secondarily dynamically, the initial mark and the secondary mark are subjected to characteristic comparison, including data transmission rate, whether packet loss exists or not, and the like, so that the data transmission process is dynamically monitored according to the comparison result, the data transmission between the CPU and the FPGA is monitored in real time, normal and reliable data transmission is ensured, and the technical effect of improving the data transmission rate is achieved.

The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic flow chart of a method for dynamically monitoring data transmission between a CPU and an FPGA according to an embodiment of the present application;

fig. 2 is a schematic flow chart illustrating a process of generating a first dynamic monitoring result by integrating data transmission rate difference information according to the data transmission dynamic monitoring method for the CPU and the FPGA according to the embodiment of the present application;

fig. 3 is a schematic flow chart illustrating a process of correcting the first dynamic monitoring result according to the first warning instruction in the dynamic data transmission monitoring method for the CPU and the FPGA according to the embodiment of the present application;

fig. 4 is a schematic flow chart illustrating the construction of the data transmission rate response rule in the data transmission dynamic monitoring method for the CPU and the FPGA according to the embodiment of the present application;

fig. 5 is a schematic flow chart illustrating a process of marking a transmission rate in a dynamic data transmission monitoring method for a CPU and an FPGA according to an embodiment of the present application;

fig. 6 is a schematic flow chart illustrating a setting of a data return response rule of an FPGA terminal in the dynamic monitoring method for data transmission between a CPU and an FPGA according to the embodiment of the present application;

fig. 7 is a schematic flowchart of a method for dynamically monitoring data transmission between a CPU and an FPGA according to an embodiment of the present application, for determining whether a second data packet and a first data packet are consistent;

fig. 8 is a schematic structural diagram of a data transmission dynamic monitoring system of a CPU and an FPGA according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of an exemplary electronic device according to an embodiment of the present application.

Detailed Description

The embodiment of the application provides a method and a system for dynamically monitoring data transmission of a CPU and an FPGA, and solves the technical problem that data is lost in the transmission process due to back pressure/blockage of the FPGA when large data is transmitted between the CPU and the FPGA in the prior art. The data transmission of the CPU end of the data transmission is dynamically marked initially, the response serial number returned by the FPGA end is marked secondarily dynamically, the initial mark and the secondary mark are subjected to characteristic comparison, including data transmission rate, whether packet loss exists or not, and the like, so that the data transmission process is dynamically monitored according to the comparison result, the data transmission between the CPU and the FPGA is monitored in real time, normal and reliable data transmission is ensured, and the technical effect of improving the data transmission rate is achieved.

Hereinafter, example embodiments according to the present application will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are merely some embodiments of the present application and not all embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein.

Summary of the application

In recent years, with the rapid development of social service informatization, data in various aspects such as the internet, the internet of things, finance, logistics, electromagnetism and the like all show exponential growth. The transmission of big data is an important ring of a big data processing basic flow, and the high-performance data transmission can provide guarantee for subsequent data analysis, particularly real-time analysis. In the prior art, when big data is transmitted between a CPU and an FPGA, data is lost in the transmission process due to the back pressure/blockage problem of the FPGA.

In view of the above technical problems, the technical solution provided by the present application has the following general idea:

the embodiment of the application provides a method for dynamically monitoring data transmission of a CPU and an FPGA, wherein the method comprises the following steps: constructing a data transmission channel between the CPU and the FPGA; acquiring a first data packet at a CPU end, and carrying out initial dynamic marking to acquire a first dynamic mark; acquiring a second data packet transmitted from the first data packet to the FPGA terminal based on the data transmission channel; setting a data return response rule of an FPGA end; according to the data return response rule, obtaining a first return response serial number of the FPGA end to the second data packet, and carrying out return dynamic marking to obtain a second dynamic mark; and uploading the first dynamic mark and the second dynamic mark to a data transmission dynamic monitoring system to obtain a dynamic monitoring result, and dynamically monitoring the data transmission of the CPU and the FPGA.

For better understanding of the above technical solutions, the following detailed descriptions will be provided in conjunction with the drawings and the detailed description of the embodiments.

Example one

As shown in fig. 1, an embodiment of the present application provides a method for dynamically monitoring data transmission between a CPU and an FPGA, where the method includes:

step S100: constructing a data transmission channel between the CPU and the FPGA;

step S200: acquiring a first data packet at a CPU end, and carrying out initial dynamic marking to acquire a first dynamic mark;

specifically, when large data is transmitted between the CPU and the FPGA, data loss is often caused by the backpressure/blocking problem of the FPGA during transmission, and in order to solve the problem of data loss, in the embodiment of the present application, by dynamically marking data transmission between the CPU and the FPGA, occurrence of such a problem can be effectively avoided, specifically, a data transmission channel between the CPU and the FPGA can be constructed, the data transmission channel is used for transmitting a data packet between the CPU and the FPGA, and a Central Processing Unit (CPU) is used as an operation and control core of a computer system and is a final execution unit for information processing and program operation; FPGA (field Programmable Gate array) is a product which is further developed on the basis of Programmable devices such as PAL, GAL and the like, and is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), thereby not only solving the defects of the custom circuit, but also overcoming the defect of limited Gate circuits of the original Programmable devices. And then, a first data packet at the CPU end can be obtained, and initial dynamic marking is performed to obtain a first dynamic mark, specifically, any host can send a data packet with any source address. When data packets are transmitted over long distances, many relay stations are needed. Each relay station is a host or router that forwards packets to the next relay station based on routing information. On the way of data transmission, if a router encounters a large data traffic, it may drop some packets without any hints. The first data packet comprises transmitted data information, and a first dynamic mark can be obtained by carrying out initial dynamic marking on the first data packet, wherein the first dynamic mark comprises the transmitted data information, the transmission rate and the like.

Step S300: acquiring a second data packet transmitted from the first data packet to the FPGA terminal based on the data transmission channel;

step S400: setting a data return response rule of an FPGA end;

specifically, it is known to construct the data transmission channel, and based on this, a second data packet transmitted from the first data packet to the FPGA side is obtained, generally speaking, if the transmission process is error-free, the data information in the second data packet is consistent with the transmission data information of the first data packet, otherwise, there is a difference. Further, in order to ensure that data is transmitted to the FPGA end safely and correctly, a data return response rule of the FPGA end may be set, that is, when data is transmitted to the FPGA end, the FPGA end may feed back a response serial number to the CPU end, and if the CPU end receives the response serial number, it indicates that current data transmission is normal.

Step S500: according to the data return response rule, obtaining a first return response serial number of the FPGA end to the second data packet, and carrying out return dynamic marking to obtain a second dynamic mark;

step S600: and uploading the first dynamic mark and the second dynamic mark to a data transmission dynamic monitoring system to obtain a dynamic monitoring result, and dynamically monitoring the data transmission of the CPU and the FPGA.

Specifically, when the first data packet is transmitted to the FPGA end, the FPGA end sends a return response serial number to the CPU end according to the second data packet, and performs a return dynamic flag, where the first return response serial number has a direct correlation with the second data packet, and specifically, if the data transmission process is accurate and the second data packet is consistent with the first data packet, the first return response serial number indirectly has a direct correlation with the first data packet; on the contrary, if there is a problem in the data transmission process, the second data packet has a packet loss or the like compared with the first data packet, so that the first reply serial number has a direct correlation with the second data packet, therefore, the first reply serial number can be marked, and then the first dynamic mark and the second dynamic mark are compared, and the dynamic monitoring result is a comparison result.

Further, as shown in fig. 2, the embodiment of the present application further includes:

step S610: acquiring a first data transmission rate and first data packet information according to the first dynamic mark;

step S620: obtaining a second data transmission rate and second data packet information according to the second dynamic mark;

step S630: obtaining data transmission rate difference information based on the first data transmission rate and the second data transmission rate;

step S640: judging whether the second data packet information has packet loss or not based on the first data packet information;

step S650: and if the second data packet information has packet loss, synthesizing the data transmission rate difference information to generate a first dynamic monitoring result.

Specifically, in order to dynamically monitor the data transmission between the CPU and the FPGA, more specifically, a first data transmission rate and first data packet information may be obtained according to the first dynamic flag, where the first data transmission rate is the transmission rate of the first data packet and the first data packet information is data information included in the first data packet because the first dynamic flag and the first data packet have direct correlation, and similarly, the second data transmission rate is the transmission rate of the second data packet and the second data packet information is data information included in the second data packet, and further, data transmission rate difference information is obtained based on the first data transmission rate and the second data transmission rate, where the data transmission rate difference information is the first data transmission rate and the second data transmission rate The difference of the rates may affect the data transmission dynamics to a certain extent, and meanwhile, based on the first data packet information, it is determined whether the second data packet information has a packet loss, that is, whether there are abnormal situations such as data packet loss in the transmission process of the data, and if the second data packet information has a packet loss, the data transmission rate difference information is integrated to generate a first dynamic monitoring result, where the first dynamic monitoring result includes abnormal situations such as data packet loss in the transmission process of the data transmission channel of the first data packet, so that the abnormal problem of data transmission is discovered in time.

Further, as shown in fig. 3, the embodiment of the present application further includes:

step S710: acquiring a returned response sequence number accommodating threshold value of the CPU end;

step S720: presetting a data transmission rate response rule according to the return response serial number accommodating threshold;

step S730: according to the data transmission rate response rule and the data transmission rate difference information, backward predicting the real-time returned response serial number capacity value of the CPU end;

step S740: judging whether the real-time returned response serial number capacity value reaches a preset early warning capacity value or not;

step S750: if the real-time return response serial number capacity value reaches the preset early warning capacity value, generating a first early warning instruction;

step S760: and correcting the first dynamic monitoring result according to the first early warning instruction.

Specifically, in order to further monitor the data transmission process, more specifically, the determination may be performed based on the capacity value of the sequence number pool loaded on the CPU, that is, to obtain the returned response sequence number accommodating threshold of the CPU, where the returned response sequence number accommodating threshold may be understood as the maximum receivable returned response sequence number value in the sequence number pool loaded on the CPU, which is described as 100 as an example, and meanwhile, a data transmission rate response rule may be preset according to the returned response sequence number accommodating threshold, in other words, a corresponding data transmission rate response rule may be set according to the returned response sequence number accommodating threshold, that is, when the returned response sequence number capacity value in the sequence number pool is 100, a full-rate data transmission may be set, and when the returned response sequence number capacity value in the sequence number pool is 50, a half-full-rate data transmission may be set, and further, according to the data transmission rate response rule and the data transmission rate difference information, the real-time returned response serial number capacity value of the CPU is reversely predicted, that is, if the data transmission rate difference information is smaller, it indicates that the real-time returned response serial number capacity value of the CPU is close to 100, and is in a satisfied state, otherwise, it is in a non-satisfied state, and then it is determined whether the real-time returned response serial number capacity value reaches a preset early warning capacity value, where the preset early warning capacity value is illustrated here by taking 50 as an example, that is, if the real-time returned response serial number capacity value is reduced to 50, the first dynamic monitoring result may be corrected according to the first early warning instruction, that is, since the real-time returned response serial number capacity value is reduced to 50, the returned response serial number capacity value in the serial number pool is in a half-full state, the data cannot be transmitted at a full rate, and then the transmission efficiency of the data is affected.

Further, as shown in fig. 4, the step S720 further includes, according to the returned response sequence number accommodating threshold, presetting a data transmission rate response rule:

step S721: according to the return response serial number accommodating threshold value, acquiring a first-order return response serial number capacity value, a second-order return response serial number capacity value and a third-order return response serial number capacity value;

step S722: generating a first preset transmission rate according to the first-order return response serial number capacity value and the second-order return response serial number capacity value;

step S723: generating a second preset transmission rate according to the third-order return response sequence number capacity value, wherein the second preset transmission rate is lower than the first preset transmission rate;

step S724: and constructing the data transmission rate response rule based on the first preset transmission rate and the second preset transmission rate.

Specifically, in order to further preset a data transmission rate response rule according to the backhaul response serial number accommodation threshold, and more specifically, a first-order backhaul response serial number capacitance value, a second-order backhaul response serial number capacitance value, and a third-order backhaul response serial number capacitance value may be obtained according to the backhaul response serial number accommodation threshold, where the first-order backhaul response serial number capacitance value is illustrated by 80-100, the second-order backhaul response serial number capacitance value is illustrated by 50-79, and the third-order backhaul response serial number capacitance value is illustrated by 1-49, and further, a first preset transmission rate may be generated according to the first-order backhaul response serial number capacitance value and the second-order backhaul response serial number capacitance value, for example, when the backhaul response serial number capacitance value is between 50-100, the first preset transmission rate may be generated, where the first preset transmission rate is illustrated by data high-rate transmission, further, when the returned response sequence number tolerance value is between 1 and 49, the second preset transmission rate may be generated, where the second preset transmission rate is described by taking data low-rate transmission as an example, and then the data transmission rate response rule is constructed based on the first preset transmission rate and the second preset transmission rate, so that the data transmission rate response rule is further preset according to the returned response sequence number tolerance threshold value.

Further, as shown in fig. 5, the embodiment of the present application further includes:

step S725: generating a first-order transmission rate according to the first-order return response sequence number capacity value;

step S726: generating a second-order transmission rate according to the second-order return response sequence number capacity value, wherein the first-order transmission rate and the second-order transmission rate are both contained in the first preset transmission rate, and the first-order transmission rate is higher than the second-order transmission rate;

step S727: marking the first-order transmission rate to obtain first marking information, wherein the first marking information comprises that the serial number capacity value in a serial number pool loaded by the CPU end is in a satisfied state;

step S728: marking the second-order transmission rate to obtain second marking information, wherein the second marking information comprises that the serial number capacity value in the serial number pool loaded by the CPU end is in a half-full state;

step S729: and marking the second preset transmission rate to obtain third marking information, wherein the third marking information comprises that the serial number capacity value in the serial number pool loaded by the CPU end is in an unsatisfied state, and the first early warning instruction is generated.

Specifically, the first preset transmission rate may be further subdivided, and more specifically, when the first-order return response sequence number capacity is between 80 and 100, the first-order transmission rate is described herein by taking full-rate data transmission as an example, and when the second-order return response sequence number capacity is between 50 and 79, the second-order transmission rate is described herein by taking non-full-rate data transmission as an example, wherein the first-order transmission rate and the second-order transmission rate are both high-rate transmission, and the first-order transmission rate is marked as first marking information, that is, the sequence number capacity in the sequence number pool loaded by the CPU is in a satisfied state; marking the second-order transmission rate as second marking information, namely that the serial number capacity value in the serial number pool loaded by the CPU end is in a half-full state; and marking the second preset transmission rate as third marking information, namely, the serial number capacity value in the serial number pool loaded by the CPU end is in an unsatisfied state, and then early warning is carried out on the unsatisfied state.

Further, as shown in fig. 6, the setting of the data return response rule of the FPGA end further includes:

step S410: obtaining a first exclusive response packet;

step S420: according to the first exclusive response packet, performing matching response on the second data packet transmitted to the FPGA end;

step S430: obtaining a first additional response packet, wherein the first additional response packet is included in the first data packet;

step S440: and matching and responding the second data packet transmitted to the FPGA end according to the first additional response packet.

Specifically, in order to further set a data feedback response rule of the FPGA, more specifically, a first dedicated response packet may be obtained based on the first data packet, that is, a response sequence number of the first data packet is loaded to the first dedicated response packet, and then a matching response is performed on the second data packet transmitted to the FPGA; in addition, a first additional response packet may be obtained, that is, a response sequence number to the first data packet is loaded to the first additional response packet, where the first additional response packet is included in the first data packet and is an additional packet of the first data packet, and then the second data packet transmitted to the FPGA end is subjected to matching response.

Further, as shown in fig. 7, before the performing matching response on the second data packet transmitted to the FPGA end according to the first additional response packet, step S440 further includes:

step S441: judging whether the second data packet is consistent with the first data packet or not;

step S442: and if the second data packet is consistent with the first data packet, matching and responding the second data packet transmitted to the FPGA end according to the first additional response packet.

Specifically, before performing a matching response on the second data packet transmitted to the FPGA end according to the first additional response packet, it may be determined whether the second data packet and the first data packet are consistent, in other words, if data is normally transmitted in the transmission process, the second data packet and the first data packet are consistent, and the matching response may be performed on the second data packet transmitted to the FPGA end according to the first additional response packet; on the contrary, if the data transmission is abnormal, the second data packet and the first data packet cannot be kept consistent, and further the first reply sequence number is abnormal, it indicates that the data transmission of the first data packet is abnormally blocked, and the like.

Compared with the prior art, the invention has the following beneficial effects:

1. the data transmission of the CPU end of the data transmission is dynamically marked initially, the response serial number returned by the FPGA end is marked secondarily dynamically, the initial mark and the secondary mark are subjected to characteristic comparison, including data transmission rate, whether packet loss exists or not, and the like, so that the data transmission process is dynamically monitored according to the comparison result, the data transmission between the CPU and the FPGA is monitored in real time, normal and reliable data transmission is ensured, and the technical effect of improving the data transmission rate is achieved.

Example two

Based on the same inventive concept as the data transmission dynamic monitoring method of the CPU and the FPGA in the foregoing embodiment, the present invention further provides a data transmission dynamic monitoring system of the CPU and the FPGA, as shown in fig. 8, the system includes:

the first building unit 11: the first construction unit 11 is configured to construct a data transmission channel between the CPU and the FPGA;

the first obtaining unit 12: the first obtaining unit 12 is configured to obtain a first data packet at the CPU end, and perform initial dynamic marking to obtain a first dynamic mark;

the second obtaining unit 13: the second obtaining unit 13 is configured to obtain, based on the data transmission channel, a second data packet transmitted to the FPGA end by the first data packet;

first setting unit 14: the first setting unit 14 is configured to set a data return response rule of the FPGA end;

the third obtaining unit 15: the third obtaining unit 15 is configured to obtain a first return response serial number of the second data packet from the FPGA end according to the data return response rule, and perform a return dynamic marking to obtain a second dynamic marking;

the first upload unit 16: the first uploading unit 16 is configured to upload the first dynamic mark and the second dynamic mark to a dynamic data transmission monitoring system, obtain a dynamic monitoring result, and dynamically monitor data transmission between the CPU and the FPGA.

Further, the system further comprises:

a fourth obtaining unit: the fourth obtaining unit is configured to obtain a first data transmission rate and first data packet information according to the first dynamic flag;

a fifth obtaining unit: the fifth obtaining unit is configured to obtain a second data transmission rate and second data packet information according to the second dynamic flag;

a sixth obtaining unit: the sixth obtaining unit is configured to obtain data transmission rate difference information based on the first data transmission rate and the second data transmission rate;

a first judgment unit: the first judging unit is used for judging whether packet loss exists in the second data packet information based on the first data packet information;

a first generation unit: the first generating unit is configured to synthesize the data transmission rate difference information to generate a first dynamic monitoring result if the second data packet information has a packet loss.

Further, the system further comprises:

a seventh obtaining unit: the seventh obtaining unit is configured to obtain a returned response sequence number accommodating threshold of the CPU end;

a first preset unit: the first preset unit is used for presetting a data transmission rate response rule according to the return response serial number accommodating threshold;

a first prediction unit: the first prediction unit is used for reversely predicting the real-time returned response serial number capacity value of the CPU end according to the data transmission rate response rule and the data transmission rate difference information;

a second judgment unit: the second judging unit is used for judging whether the real-time return response serial number capacity value reaches a preset early warning capacity value;

a second generation unit: the second generating unit is used for generating a first early warning instruction if the real-time return response serial number capacity value reaches the preset early warning capacity value;

the first early warning unit: the first early warning unit is used for early warning the first dynamic monitoring result according to the first early warning instruction.

Further, the system further comprises:

an eighth obtaining unit: the eighth obtaining unit is configured to obtain a first-order return response serial number capacitance value, a second-order return response serial number capacitance value, and a third-order return response serial number capacitance value according to the return response serial number accommodation threshold;

a third generation unit: the third generating unit is configured to generate a first preset transmission rate according to the first-order return response sequence number capacity value and the second-order return response sequence number capacity value;

a fourth generation unit: the fourth generating unit is configured to generate a second preset transmission rate according to the third-order return response sequence number capacity value, where the second preset transmission rate is lower than the first preset transmission rate;

a second building element: the second constructing unit is configured to construct the data transmission rate response rule based on the first preset transmission rate and the second preset transmission rate.

Further, the system further comprises:

a fifth generation unit: the fifth generating unit is used for generating a first-order transmission rate according to the first-order return response sequence number capacity value;

a sixth generation unit: the sixth generating unit is configured to generate a second-order transmission rate according to the second-order return response sequence number capacity value, where the first-order transmission rate and the second-order transmission rate are both included in the first preset transmission rate, and the first-order transmission rate is higher than the second-order transmission rate;

a first marking unit: the first marking unit is used for marking the first-order transmission rate to obtain first marking information, wherein the first marking information comprises that the serial number capacity value in the serial number pool loaded by the CPU end is in a satisfied state;

a second marking unit: the second marking unit is used for marking the second-order transmission rate to obtain second marking information, wherein the second marking information comprises that the serial number capacity value in the serial number pool loaded by the CPU end is in a half-full state;

a third marking unit: and the third marking unit is used for marking the second preset transmission rate to obtain third marking information, wherein the third marking information comprises that the serial number capacity value in the serial number pool loaded by the CPU end is in an unsatisfied state, and the first early warning instruction is generated.

Further, the system further comprises:

a ninth obtaining unit: the ninth obtaining unit is configured to obtain a first dedicated response packet;

a first response unit: the first response unit is used for performing matching response on the second data packet transmitted to the FPGA end according to the first exclusive response packet;

a tenth obtaining unit: the tenth obtaining unit is configured to obtain a first additional response packet, where the first additional response packet is included in the first data packet;

a second response unit: and the second response unit is used for performing matching response on the second data packet transmitted to the FPGA end according to the first additional response packet.

Further, the system further comprises:

a third judging unit: the third judging unit is used for judging whether the second data packet is consistent with the first data packet or not;

a third response unit: and the third response unit is used for matching and responding the second data packet transmitted to the FPGA end according to the first additional response packet if the second data packet is consistent with the first data packet.

Various changes and specific examples of the data transmission dynamic monitoring method for the CPU and the FPGA in the first embodiment of fig. 1 are also applicable to the data transmission dynamic monitoring system for the CPU and the FPGA of this embodiment, and through the foregoing detailed description of the data transmission dynamic monitoring method for the CPU and the FPGA, those skilled in the art can clearly know the implementation method of the data transmission dynamic monitoring system for the CPU and the FPGA in this embodiment, so for the brevity of the description, detailed description is not repeated here.

EXAMPLE III

The electronic apparatus of the embodiment of the present application is described below with reference to fig. 9.

Fig. 9 illustrates a schematic structural diagram of an electronic device according to an embodiment of the present application.

Based on the inventive concept of a method for dynamically monitoring data transmission of a CPU and an FPGA in the foregoing embodiments, the present invention further provides a system for dynamically monitoring data transmission of a CPU and an FPGA, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the methods of the system for dynamically monitoring data transmission of a CPU and an FPGA are implemented.

Where in fig. 9 a bus architecture (represented by bus 300), bus 300 may include any number of interconnected buses and bridges, bus 300 linking together various circuits including one or more processors, represented by processor 302, and memory, represented by memory 304. The bus 300 may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. A bus interface 305 provides an interface between the bus 300 and the receiver 301 and transmitter 303. The receiver 301 and the transmitter 303 may be the same element, i.e., a transceiver, providing a means for communicating with various other systems over a transmission medium. The processor 302 is responsible for managing the bus 300 and general processing, and the memory 304 may be used for storing data used by the processor 302 in performing operations.

The embodiment of the application provides a method for dynamically monitoring data transmission of a CPU and an FPGA, wherein the method comprises the following steps: constructing a data transmission channel between the CPU and the FPGA; acquiring a first data packet at a CPU end, and carrying out initial dynamic marking to acquire a first dynamic mark; acquiring a second data packet transmitted from the first data packet to the FPGA terminal based on the data transmission channel; setting a data return response rule of an FPGA end; according to the data return response rule, obtaining a first return response serial number of the FPGA end to the second data packet, and carrying out return dynamic marking to obtain a second dynamic mark; and uploading the first dynamic mark and the second dynamic mark to a data transmission dynamic monitoring system to obtain a dynamic monitoring result, and dynamically monitoring the data transmission of the CPU and the FPGA.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a system for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction system which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.