阅读说明：本技术 半导体结构及其制备方法 (Semiconductor structure and preparation method thereof ) 是由 巩金峰 林志成 于 2021-08-30 设计创作，主要内容包括：本发明涉及一种半导体结构及其制备方法。该方法包括：提供基底,基底包括介质层；形成接触孔于介质层中；形成第一导电层于接触孔的侧壁和底部上；形成第二导电层于第一导电层上,以填满接触孔,其中,第一导电层的晶格常数和第二导电层的晶格常数不同；移除部分介质层,以使得第一导电层和第二导电层的顶部突出于介质层。上述半导体的制备方法,通过沉积晶格常数不同的第一导电层和第二导电层,从而得到致密程度不同的导电层,在刻蚀介质层以突出导电层顶部的过程中,在导电层顶部形成不平整的顶面,从而增大导电层的表面积,降低接触电阻,提高器件性能。(The invention relates to a semiconductor structure and a preparation method thereof. The method comprises the following steps: providing a substrate, wherein the substrate comprises a dielectric layer; forming a contact hole in the dielectric layer; forming a first conductive layer on the side wall and the bottom of the contact hole; forming a second conductive layer on the first conductive layer to fill the contact hole, wherein the lattice constant of the first conductive layer is different from that of the second conductive layer; and removing part of the dielectric layer so that the top parts of the first conductive layer and the second conductive layer protrude out of the dielectric layer. According to the preparation method of the semiconductor, the first conducting layer and the second conducting layer with different lattice constants are deposited to obtain the conducting layers with different compactness degrees, and in the process of etching the dielectric layer to protrude the top of the conducting layer, an uneven top surface is formed on the top of the conducting layer, so that the surface area of the conducting layer is increased, the contact resistance is reduced, and the performance of a device is improved.)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a dielectric layer;

forming a contact hole in the dielectric layer;

forming a first conductive layer on the side wall and the bottom of the contact hole;

forming a second conductive layer on the first conductive layer to fill the contact hole, wherein the lattice constant of the first conductive layer is different from the lattice constant of the second conductive layer;

and removing part of the dielectric layer so that the top parts of the first conductive layer and the second conductive layer protrude out of the dielectric layer.

2. The method of claim 1, further comprising etching a top portion of the first conductive layer and a top portion of the second conductive layer.

3. The method of claim 2, wherein a lattice constant of the first conductive layer is smaller than a lattice constant of the second conductive layer, and an etching rate of the first conductive layer is smaller than an etching rate of the second conductive layer.

4. The method according to claim 3, wherein a top of the first conductive layer is higher than a top of the second conductive layer.

5. The method of claim 2, wherein a lattice constant of the first conductive layer is greater than a lattice constant of the second conductive layer, and an etching rate of the first conductive layer is greater than an etching rate of the second conductive layer.

6. The method of claim 5, wherein a top of the first conductive layer is lower than a top of the second conductive layer.

7. The method according to claim 1, wherein a material of the first conductive layer is the same as a material of the second conductive layer.

8. The method of claim 1, further comprising:

and forming a first metal layer on the dielectric layer, wherein the first metal layer covers the tops of the first conducting layer and the second conducting layer.

9. The method of claim 8, further comprising:

and forming a second metal layer which covers the first metal layer.

10. A semiconductor structure, comprising:

a substrate comprising a dielectric layer;

the contact hole is positioned in the dielectric layer;

a first conductive layer on a sidewall and a bottom of the contact hole;

the second conducting layer is positioned on the first conducting layer and fills the contact hole;

the lattice constant of the first conducting layer is different from that of the second conducting layer, and the tops of the first conducting layer and the second conducting layer protrude out of the dielectric layer.

11. The semiconductor structure of claim 10, wherein the lattice constant of the first conductive layer is less than the lattice constant of the second conductive layer, and wherein the top of the first conductive layer is higher than the top of the second conductive layer.

12. The semiconductor structure of claim 10, wherein the lattice constant of the first conductive layer is greater than the lattice constant of the second conductive layer, and wherein the top of the first conductive layer is lower than the top of the second conductive layer.

13. The semiconductor structure of claim 10, further comprising a first metal layer on the dielectric layer, the first metal layer covering a top of the first conductive layer and the second conductive layer.

14. The semiconductor structure of claim 13, further comprising a second metal layer overlying the first metal layer.

Technical Field

The present invention relates to semiconductor manufacturing processes, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers. Along with the shrinking of the DRAM manufacturing process, the volume of the bit line structure is also sharply reduced, so that the contact resistance between the bit line structure and other conductive devices is increased, the current is reduced, and the performance of the device is reduced.

Disclosure of Invention

Accordingly, it is desirable to provide a semiconductor structure and a method for fabricating the same, which can solve the problem of large contact resistance caused by DRAM process shrinkage.

The invention provides a preparation method of a semiconductor structure, which is characterized by comprising the following steps: providing a substrate, wherein the substrate comprises a dielectric layer; forming a contact hole in the dielectric layer; forming a first conductive layer on the side wall and the bottom of the contact hole; forming a second conductive layer on the first conductive layer to fill the contact hole, wherein the lattice constant of the first conductive layer is different from the lattice constant of the second conductive layer; and removing part of the dielectric layer so that the top parts of the first conductive layer and the second conductive layer protrude out of the dielectric layer.

According to the preparation method of the semiconductor, the first conducting layer and the second conducting layer with different lattice constants are deposited to obtain the conducting layers with different compactness degrees, and in the process of etching the dielectric layer to protrude the top of the conducting layer, an uneven top surface is formed on the top of the conducting layer, so that the surface area of the conducting layer is increased, the contact resistance is reduced, and the performance of a device is improved.

In one embodiment, the method for fabricating a semiconductor structure further comprises: and etching the top of the first conducting layer and the top of the second conducting layer.

In one embodiment, the lattice constant of the first conductive layer is smaller than the lattice constant of the second conductive layer, and the etching rate of the first conductive layer is smaller than the etching rate of the second conductive layer. .

In one embodiment, the top of the first conductive layer is higher than the top of the second conductive layer.

In one embodiment, the lattice constant of the first conductive layer is larger than the lattice constant of the second conductive layer, and the etching rate of the first conductive layer is larger than that of the second conductive layer.

In one embodiment, the top of the first conductive layer is lower than the top of the second conductive layer.

In one embodiment, the material of the first conductive layer is the same as the material of the second conductive layer.

In one embodiment, the method further includes forming a first metal layer on the dielectric layer, the first metal layer covering the top of the first conductive layer and the second conductive layer.

In one embodiment, the method further comprises forming a second metal layer overlying the first metal layer.

The present invention also provides a semiconductor structure comprising: a substrate; the dielectric layer is positioned on the substrate; the contact hole is positioned in the dielectric layer; a first conductive layer on a sidewall and a bottom of the contact hole; the second conducting layer is positioned on the first conducting layer and fills the contact hole; the lattice constant of the first conducting layer is different from that of the second conducting layer, and the tops of the first conducting layer and the second conducting layer protrude out of the dielectric layer.

In one embodiment, the lattice constant of the first conductive layer is smaller than the lattice constant of the second conductive layer, and the top of the first conductive layer is higher than the top of the second conductive layer.

In one embodiment, the lattice constant of the first conductive layer is greater than the lattice constant of the second conductive layer, and the top of the first conductive layer is lower than the top of the second conductive layer.

In one embodiment, the semiconductor structure further comprises a first metal layer, wherein the first metal layer is located on the dielectric layer, and the first metal layer covers the top of the first conductive layer and the top of the second conductive layer.

In one embodiment, the semiconductor structure further comprises a second metal layer overlying the first metal layer.

According to the semiconductor structure, the heights of the tops of the first conducting layer and the second conducting layer are different, so that the contact area between the conducting layer and the metal layer is increased, the contact resistance is reduced, and the performance of a device is improved.

Drawings

Fig. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional structure diagram of a substrate provided in an embodiment of the present application.

Fig. 3 is a schematic cross-sectional view of a semiconductor structure obtained after forming a contact hole in a dielectric layer according to an embodiment of the present disclosure.

Fig. 4 is a schematic cross-sectional view of a semiconductor structure obtained after forming a first conductive material layer according to an embodiment of the present disclosure.

Fig. 5 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second conductive material layer according to an embodiment of the present application.

Fig. 6 is a schematic cross-sectional structure diagram of a semiconductor structure obtained after forming a first conductive layer and a second conductive layer in an embodiment of the present application.

Fig. 7 is a schematic cross-sectional view of a semiconductor structure obtained after removing a portion of a dielectric layer according to an embodiment of the present application.

Fig. 8 is a schematic cross-sectional structure diagram of a semiconductor structure obtained by etching tops of the first conductive layer and the second conductive layer in an embodiment of the present application.

Fig. 9 is a schematic cross-sectional structure diagram of a semiconductor structure obtained after etching tops of the first conductive layer and the second conductive layer in another embodiment of the present application.

Fig. 10 is a schematic cross-sectional view of a semiconductor structure obtained after forming a first metal layer according to an embodiment of the present application.

Fig. 11 is a schematic cross-sectional view of a semiconductor structure obtained after forming a first metal layer according to another embodiment of the present application.

Fig. 12 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second metal layer according to an embodiment of the present application.

Fig. 13 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second metal layer according to another embodiment of the present application.

The reference numbers illustrate: 10. a substrate; 11. an oxide layer; 12. a conductive structure; 20. a dielectric layer; 21. a first dielectric layer; 22. a second dielectric layer; 23. a contact hole; 31. a first conductive layer; 32. a second conductive layer; 33. a first layer of conductive material; 34. a second layer of conductive material; 35. a first metal layer; 36. a second metal layer.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In describing positional relationships, unless otherwise specified, when an element such as a layer, film or substrate is referred to as being "on" another layer, it can be directly on the other layer or intervening layers may also be present. Further, when a layer is referred to as being "under" another layer, it can be directly under, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.

One embodiment of the present application provides a method of fabricating a semiconductor structure, as shown in fig. 1. The method comprises the following steps:

s10: providing a substrate, wherein the substrate comprises a dielectric layer;

s20: forming a contact hole in the dielectric layer;

s30: forming a first conductive layer on the side wall and the bottom of the contact hole;

s40: forming a second conductive layer on the first conductive layer to fill the contact hole, wherein the lattice constant of the first conductive layer is different from the lattice constant of the second conductive layer;

s50: and removing part of the dielectric layer so that the top parts of the first conductive layer and the second conductive layer protrude out of the dielectric layer.

In step S10, a substrate including a dielectric layer 20 is provided. The base further comprises a substrate 10 and an oxide layer 11, the oxide layer 11 being located between the substrate 10 and a dielectric layer 20, as shown in fig. 2.

Wherein the substrate 10 includes but is not limited to a silicon substrate, and the oxide layer 11 may include but is not limited to a silicon dioxide layer. At least two conductive structures 12 are formed in the oxide layer 11, and the conductive structures 12 may include, but are not limited to, metal layer wires, and may also include metal layer wires and metal plugs connected to the metal layer wires under the metal layer wires. The upper surface of the metal layer wire is flush with the upper surface of the oxide layer 11. The material forming the conductive structure 12 may be copper.

Specifically, the oxide layer 11 may be formed on the substrate 10 by, but not limited to, a thermal oxidation process. Illustratively, the dielectric layer 20 comprises a stacked structure. The step of forming the dielectric layer 20 includes: forming a first dielectric layer 21 on the oxide layer 11, wherein the first dielectric layer 21 can also protect the conductive structure 12; forming a second dielectric layer 22 on the first dielectric layer 21; the thickness of the second dielectric layer 22 is greater than that of the first dielectric layer 21, so that the sidewall morphology of a contact hole formed later can be improved. Also, the bottom of the first dielectric layer 21 is in contact with the conductive structure 12. By way of example, the first dielectric layer 21 may include, but is not limited to, a silicon nitride layer, and the second dielectric layer 22 may include, but is not limited to, an oxide layer, such as a silicon dioxide layer.

In step S20, a contact hole 23 is formed in the dielectric layer 20, as shown in fig. 3. Illustratively, at least two contact holes 23 are formed in the dielectric layer 20, and the contact holes 23 expose the conductive structures 12 in the oxide layer 11.

As an example, a dry etching process may be used to form the contact hole 23 in the dielectric layer 20, and the specific steps include: forming a BARC layer (Bottom Anti-Reflective Coatings) on the top surface of the dielectric layer 20; forming a graphical photoresist layer on the BARC layer; the pattern in the patterned photoresist layer is transferred into the dielectric layer 20 by dry etching to form a contact hole 23 in the dielectric layer 20.

In steps S30 and S40, the step of forming a first conductive layer and a second conductive layer includes:

s41: a first conductive material layer 33 is formed on the dielectric layer 20 and on the sidewalls and bottom of the contact hole 23, as shown in fig. 4.

Illustratively, as shown in fig. 4, the first conductive material layer 33 may include, but is not limited to, a tungsten layer having a first lattice constant, and a bottom portion of the first conductive material layer 33 is in contact with the conductive structure 12. The thickness of the first conductive material layer 33 can be set according to actual requirements.

S42: a second conductive material layer 34 is formed on the first conductive material layer 33, and the second conductive material layer 34 fills the contact hole 23 and covers the upper surface of the first conductive material layer 33, as shown in fig. 5.

Illustratively, as shown in fig. 5, the second layer of conductive material 34 may include, but is not limited to, a layer of tungsten having a second lattice constant. Wherein the second lattice constant is different from the first lattice constant.

The lattice constant of the layer of conductive material can be controlled by varying the process parameters. Illustratively, in forming the conductive material layer, the lattice constant of the conductive material layer may be reduced by increasing the radio frequency power. Alternatively, the lattice constant of the conductive material layer may also be decreased by increasing the flow of argon gas. In the present embodiment, for example, the first conductive material layer 33 and the second conductive material layer 34 are formed by a physical vapor deposition process, the rf power during the formation of the first conductive material layer 33 and the second conductive material layer 34 is, for example, 500-. In forming the first conductive material layer 33 or the second conductive material layer 34, if the radio frequency power or the argon flow rate is increased, the crystal grains of the first conductive material layer 33 or the second conductive material layer 34 are smaller when the first conductive material layer 33 or the second conductive material layer 34 is formed, and thus the lattice constant of the first conductive material layer 33 or the second conductive material layer 34 is smaller.

S43: the first conductive material layer 33 and the second conductive material layer 34 on the second dielectric layer 22 are removed to obtain the first conductive layer 31 and the second conductive layer 32, as shown in fig. 6.

Illustratively, as shown in fig. 6, the tops of the first conductive layer 31 and the second conductive layer 32 are flush with the upper surface of the second dielectric layer 22, and the first conductive layer 31 and the second conductive layer 32 fill the contact hole 23.

In step S50, as shown in fig. 7, a portion of the dielectric layer 20 is removed so that the top portions of the first conductive layer 31 and the second conductive layer 32 protrude from the dielectric layer 20.

Specifically, after the semiconductor structure shown in fig. 6 is obtained, the etching selection ratio of the oxide layer (second dielectric layer 22) to the tungsten layer (first conductive layer 31 and second conductive layer 32) is increased, and the second dielectric layer 22, the first conductive layer 31 and the second conductive layer 32 are etched, so that the upper surface of the second dielectric layer 22 is lower than the tops of the first conductive layer 31 and the second conductive layer 32, as shown in fig. 7, because the etching rate of the second dielectric layer 22 is higher. In this process, the first conductive layer 31 and the second conductive layer 32 are also partially etched away, and since the lattice constant of the second conductive layer 32 is different from that of the first conductive layer 31, the etching rate of the second conductive layer 32 is different from that of the first conductive layer 31, and thus, the tops of the first conductive layer 31 and the second conductive layer 32 are not flat, as shown in fig. 7.

According to the preparation method of the semiconductor, the first conducting layer 31 and the second conducting layer 32 with different lattice constants are deposited to obtain conducting layers with different compactness degrees, and in the process of etching the dielectric layer to protrude the top of the conducting layers, uneven top surfaces are formed on the top of the conducting layers, so that the surface area of the conducting layers is increased, the contact resistance is reduced, and the performance of devices is improved.

In one embodiment, the method for manufacturing the semiconductor structure further includes:

s60: the top of the first conductive layer 31 and the top of said second conductive layer 32 are etched.

It should be noted that, in this step, the etching selectivity of the first conductive layer 31 and the second conductive layer 32 with respect to the second dielectric layer 22 is also increased, so that the etching process on the top of the first conductive layer 31 and the second conductive layer 32 has a smaller influence on the second dielectric layer 22.

Illustratively, when the lattice constant of the first conductive layer 31 is smaller than the lattice constant of the second conductive layer 32, the etching rate of the first conductive layer 31 is smaller than the etching rate of the second conductive layer 32. This is because when the lattice constant of the first conductive layer 31 is smaller than the lattice constant of the second conductive layer 32, the lattice size of the first conductive layer 31 is smaller than the lattice size of the second conductive layer 32, which means that the first conductive layer 31 is denser with respect to the second conductive layer 32, and therefore, the etching rate of the first conductive layer 31 is smaller than that of the second conductive layer 32 when the first conductive layer 31 and the second conductive layer 32 are etched. After etching, the second conductive layer 32 is etched more, and the first conductive layer 31 is etched less, so that the top of the first conductive layer 31 is higher than the top of the second conductive layer 32, and thus, the tops of the first conductive layer 31 and the second conductive layer 32 are recessed, as shown in fig. 8.

Illustratively, when the lattice constant of the first conductive layer 31 is greater than the lattice constant of the second conductive layer 32, the etching rate of the first conductive layer 31 is greater than the etching rate of the second conductive layer 32. After etching, the first conductive layer 31 is etched more, and the second conductive layer 32 is etched less, so that the top of the first conductive layer 31 is lower than the top of the second conductive layer 32, and thus, the tops of the first conductive layer 31 and the second conductive layer 32 are convex, as shown in fig. 10.

In one embodiment, the material of the first conductive layer 31 is the same as the material of the second conductive layer 32. Illustratively, the first conductive layer 31 and the second conductive layer 32 are both tungsten layers.

Alternatively, the number of conductive layers in the contact hole 23 may be increased, and the lattice constant of each conductive layer may be different. Alternatively, two conductive layers with different lattice constants are arranged at intervals and repeated one or more times. After the top of the conducting layer is etched, the top of the conducting layer is wavy, so that the contact area between the conducting layer and an external metal layer is increased, the contact resistance is reduced, and the performance of a semiconductor device is improved.

According to the preparation method of the semiconductor structure, the first conducting layer and the second conducting layer with different lattice constants are deposited to obtain the conducting layers with different compactness degrees, so that the etching rates of the first conducting layer and the second conducting layer are different in the process of etching the conducting layers, and after the same etching process is carried out, the etched part in the first conducting layer is larger than or smaller than the etched part in the second conducting layer, so that the heights of the tops of different conducting layers are different. The conducting layer prepared by the method has larger surface area, can reduce contact resistance and improve device performance.

In one embodiment, as shown in fig. 10 and 11, the method of manufacturing a semiconductor further includes: a first metal layer 35 is formed on the dielectric layer 20, and the first metal layer 35 covers the top of the first conductive layer 31 and the second conductive layer 32. Illustratively, the first metal layer 35 may include, but is not limited to, a titanium layer.

In one embodiment, as shown in fig. 12 and 13, the method of manufacturing a semiconductor further includes: a second metal layer 36 is formed, the second metal layer 36 covering the first metal layer 35. Illustratively, the second metal layer 36 may include, but is not limited to, an aluminum layer.

Illustratively, the thickness of the second metal layer 36 may be greater than the thickness of the first metal layer 35.

Since the adhesion between the metal aluminum and the oxide layer 11 is poor, and the adhesion between the metal titanium and the oxide layer 11 is good, the first metal layer 35, the first conductive layer 31 and the second conductive layer 32 are stably connected by forming a layer of metal titanium on the upper surfaces of the dielectric layer 20, the first conductive layer 31 and the second conductive layer 32, and then covering the second metal layer 36 on the first metal layer 35, the selection of the second metal layer 36 is not limited by the adhesion strength between the second metal layer 36 and the oxide layer 11.

Another aspect of the present application also discloses a semiconductor structure, as shown in fig. 7, comprising: a substrate including a dielectric layer 20; a contact hole 23 in the dielectric layer 20; a first conductive layer 31 on sidewalls and a bottom of the contact hole 23; a second conductive layer 32 located on the first conductive layer 31 and filling the contact hole 23; the lattice constant of the first conductive layer 31 is different from the lattice constant of the second conductive layer 32, and the top portions of the first conductive layer 31 and the second conductive layer 32 protrude from the dielectric layer 20.

Wherein the base further comprises a substrate 10 and an oxide layer 11. The substrate 10 may include, but is not limited to, a silicon substrate, the oxide layer 11 may include, but is not limited to, a silicon dioxide layer, the dielectric layer 20 includes a first dielectric layer 21 and a second dielectric layer 22 stacked in sequence from bottom to top, and the thickness of the second dielectric layer 22 is greater than that of the first dielectric layer 21. Illustratively, the first dielectric layer 21 may include, but is not limited to, a silicon nitride layer, and the second dielectric layer 22 may include, but is not limited to, a silicon dioxide layer. The first conductive layer 31 and the second conductive layer 32 may include, but are not limited to, tungsten layers having different lattice constants, the top portions of the first conductive layer 31 and the second conductive layer 32 protrude from the dielectric layer 20, and the top portions of the first conductive layer 31 and the second conductive layer 32 have different heights, as shown in fig. 7.

Illustratively, the oxide layer 11 in the semiconductor structure includes at least two conductive structures 12, and the bottom of the first conductive layer 31 is in contact with the conductive structures 12. For example, the conductive structure 12 may include, but is not limited to, a metal layer wire, and may also include a metal layer wire and a metal plug connected to the metal layer wire under the metal layer wire; the material forming the metal layer wire includes copper.

In one embodiment, as shown in fig. 8, the lattice constant of the first conductive layer 31 is smaller than the lattice constant of the second conductive layer 32, and the top of the first conductive layer 31 is higher than the top of the second conductive layer 32. Illustratively, the first conductive layer 31 and the second conductive layer 32 are, for example, tungsten layers.

In one embodiment, as shown in fig. 9, the lattice constant of the first conductive layer 31 is greater than the lattice constant of the second conductive layer 32, and the top of the first conductive layer 31 is lower than the top of the second conductive layer 32. Illustratively, the first conductive layer 31 and the second conductive layer 32 are, for example, tungsten layers.

In the semiconductor structure, the heights of the tops of the first conductive layer 31 and the second conductive layer 32 are different, so that the contact area between the conductive layers and the contact metal layer can be increased, the contact resistance is reduced, and the performance of the device is improved.

In one embodiment, as shown in fig. 10 and 11, the semiconductor structure further includes a first metal layer 35, wherein the first metal layer 35 is located on the dielectric layer 20 and covers the top of the first conductive layer 31 and the second conductive layer 32. Illustratively, the first metal layer 35 may be a titanium layer.

In one embodiment, as shown in fig. 12 and 13, the semiconductor structure further includes: a second metal layer 36, the second metal layer 36 covering the first metal layer 35. Illustratively, the second metal layer 36 may include, but is not limited to, an aluminum layer.

Illustratively, the thickness of the second metal layer 36 may be greater than the thickness of the first metal layer 35.

Because the adhesion between the metal aluminum and the oxide layer (the second dielectric layer 22) is poor, and the adhesion between the metal titanium and the oxide layer (the second dielectric layer 22) is good, the metal titanium layer is arranged between the aluminum layer and the oxide layer (the second dielectric layer 22), so that the connection between the metal layer and the conductive layer is firmer, and the stability of the device is improved.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.