阅读说明：本技术 时钟控制电路、时钟电路和电子设备 (Clock control circuit, clock circuit, and electronic device ) 是由 石欢 杨运福 刘昂立 寇博华 江鹏 王彤 李一帆 蒲宇 周明忠 于 2021-08-24 设计创作，主要内容包括：提供一种时钟控制电路、时钟电路和电子设备。该时钟控制电路包括：倍频电路,用于接收其时钟周期为设定时钟周期的第一时钟信号,并输出其时钟周期为设定时钟周期的0.5倍的第二时钟信号；正交分频器,用于接收所述第二时钟信号,并输出第一路正交时钟信号至第四路正交时钟信号,其中,所述第一路正交时钟信号至第四路正交时钟信号的时钟周期为设定时钟周期；相位处理电路,用于接收所述第一路正交时钟信号至第四路正交时钟信号,并输出其时钟周期为设定时钟周期的1.25倍的第三时钟信号。和现有技术相比,该时钟控制电路通过对信号的分频、锁存、门控等逻辑操作产生时钟周期为输入信号的1.25倍的时钟信号,从而避免使用DLL和PLL产生的技术问题。(A clock control circuit, a clock circuit and an electronic apparatus are provided. The clock control circuit includes: the frequency multiplier circuit is used for receiving a first clock signal of which the clock period is a set clock period and outputting a second clock signal of which the clock period is 0.5 times of the set clock period; the quadrature frequency divider is used for receiving the second clock signal and outputting a first path of quadrature clock signal to a fourth path of quadrature clock signal, wherein the clock period from the first path of quadrature clock signal to the fourth path of quadrature clock signal is a set clock period; and the phase processing circuit is used for receiving the first path of orthogonal clock signal to the fourth path of orthogonal clock signal and outputting a third clock signal of which the clock period is 1.25 times of the set clock period. Compared with the prior art, the clock control circuit generates a clock signal with the clock period being 1.25 times of that of the input signal through logic operations such as frequency division, latching, gating and the like of the signal, thereby avoiding the technical problems generated by using DLL and PLL.)

1. A clock control circuit, comprising:

the frequency multiplier circuit is used for receiving a first clock signal of which the clock period is a set clock period and outputting a second clock signal of which the clock period is 0.5 times of the set clock period;

the quadrature frequency divider is used for receiving the second clock signal and outputting a first path of quadrature clock signal to a fourth path of quadrature clock signal, wherein the clock period from the first path of quadrature clock signal to the fourth path of quadrature clock signal is the set clock period;

and the phase processing circuit is used for receiving the first path of orthogonal clock signal to the fourth path of orthogonal clock signal and outputting a third clock signal of which the clock period is 1.25 times of the set clock period.

2. The clock control circuit of claim 1, wherein the frequency multiplier circuit comprises:

the delay unit is used for delaying the first clock signal for a set time length to obtain a delayed fourth clock signal;

the calibration unit is used for providing the set time length for the delay unit, and the set time length is 0.25 time of the set clock period;

and an exclusive or gate for exclusive or-ing the first clock signal and the fourth clock signal and outputting the second clock signal.

3. The clock control circuit of claim 1, wherein the quadrature divider comprises:

the second buffer is used for buffering the second clock signal;

a first inverter for inverting the second clock signal and outputting a fifth clock signal;

a first latch including an input terminal and an output terminal;

a second latch comprising an input and an output;

a first tri-state inverter comprising a first enable terminal, a second enable terminal, a first input terminal, a second input terminal, a first output terminal and a second output terminal, the first and second enable terminals of the first tri-state inverter receiving the second clock signal and the fifth clock signal, respectively,

a second tri-state inverter comprising a first enable terminal, a second enable terminal, a first input terminal, a second input terminal, a first output terminal and a second output terminal, the first and second enable terminals of the second tri-state inverter receiving the fifth clock signal and the second clock signal, respectively,

wherein a first input of the first tri-state inverter is coupled to an output of the first latch, and an intermediate node therebetween is coupled to a first output of the second tri-state inverter,

a first output terminal of the first tri-state inverter is coupled to an output terminal of the second latch, an intermediate node between the first output terminal and the output terminal of the second tri-state inverter is coupled to a second input terminal of the second tri-state inverter,

a first input of the second tri-state inverter is coupled to an input of the second latch, an intermediate node between the two is coupled to a second output of the first tri-state inverter,

the second output terminal of the second tri-state inverter is coupled to the input terminal of the first latch, and an intermediate node between the second output terminal and the input terminal of the first tri-state inverter is coupled to the second input terminal of the first tri-state inverter.

4. The clock control circuit according to claim 3, wherein the first latch and the second latch have the same circuit structure and are each composed of two inverters connected end to end.

5. The clock control circuit of claim 1, wherein the phase processing circuit comprises:

the clock five-frequency division circuit is used for receiving the first path of orthogonal clock signals and outputting first to fourth selection signals of which the clock period is five times of the set clock period;

the first to fourth trigger circuits are configured to receive the first to fourth selection signals, respectively receive the first to fourth paths of orthogonal clock signals, respectively output first to fourth synchronization signals, and respectively cover rising edges of the first to fourth paths of orthogonal clock signals, where a clock period of the first to fourth synchronization signals is five times of the set clock period;

first to fourth gating circuits for receiving the first to fourth synchronization signals, receiving the first to fourth quadrature clock signals, respectively, and outputting first to fourth gated output signals, respectively, wherein a clock period of the first to fourth gated output signals is five times of the set clock period, and a phase difference between adjacent signals in the first to fourth gated output signals is 1.25 times of the set clock period;

and the exclusive-OR circuit is used for receiving the first gating output signal, the second gating output signal, the third gating output signal and the fourth gating output signal, and outputting the third clock signal through exclusive-OR operation.

6. The clock control circuit of claim 5, wherein the first through fourth synchronization signals respectively covering rising edges of the first through fourth paths of quadrature clock signals comprises:

rising edges of the first to fourth synchronous signals are aligned with rising edges of the first to fourth paths of quadrature clock signals.

7. The clock control circuit of claim 5, wherein the first through fourth trigger circuits are comprised of D flip-flops.

8. A clock circuit, comprising:

a clock generating circuit for generating a first clock signal having a clock period set to a set clock period;

a clock control circuit for receiving a first clock signal having a clock period of a set clock period and outputting a third clock signal having a clock period 1.25 times the set clock period,

further, the clock control circuit is the clock control circuit according to any one of claims 1 to 7.

9. An electronic device, comprising:

a processor;

a storage device;

the clock circuit of claim 8;

a bus to couple the processing unit, the memory device, and the clock circuit.

10. The electronic device of claim 9, wherein the electronic device is a system on a chip.

11. A method for frequency up control of a clock signal, comprising:

generating a first clock signal, the first clock signal having a set clock period;

judging whether the difference between the target frequency corresponding to the set clock period and the current frequency of the system exceeds a set threshold, if so, stretching the clock period of the first clock signal by 1.25 times, taking the stretched first clock signal as the clock signal of the system, and taking the unstretched first clock signal as the clock signal of the system after a preset stable condition is reached, further, keeping the stretched first clock signal as the clock signal of the system for a preset time length.

12. The up-conversion control method of claim 11, the stretching the clock period of the first clock signal by a factor of 1.25 comprising:

performing frequency multiplication operation on the first clock signal to output a second clock signal with a clock period 0.5 times of a set clock period;

generating a first path of orthogonal clock signals to a fourth path of orthogonal clock signals based on the second clock signals, wherein the clock period from the first path of orthogonal clock signals to the fourth path of orthogonal clock signals is the set clock period; and

and generating a third clock signal with the clock period 1.25 times of the set clock period based on the first path of orthogonal clock signal to the fourth path of orthogonal clock signal.

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a clock control circuit, a clock circuit, and an electronic device.

Background

At present, most of high-performance/low-power processors need to integrate an adaptive clock circuit so as to flexibly and rapidly change the clock frequency according to the change condition of a power supply Voltage (VDD). For example, the adaptive clock circuit automatically divides the clock of the processor after detecting that the power supply voltage has dropped to a certain threshold value, so as to ensure that the timing inside the processor is normal.

However, when the power supply voltage returns to the normal voltage, the clock frequency of the processor cannot be directly switched from the frequency division state to the full frequency state, otherwise the power consumption of the load is suddenly increased, and the power supply voltage is pulled down again.

To this end, the prior art proposes to insert an intermediate frequency state when the processor switches from the frequency-divided state to the full frequency state. Two main embodiments of this technical idea currently exist.

The first scheme is as follows: based on a closed-loop DLL (Delay locked loop) structure, an accurate multi-phase clock is generated, and a stretching clock signal is generated after phase selection. However, the scheme needs to build a closed-loop DLL circuit, and is complex in structure, high in power consumption and large in area.

The second scheme is as follows: a control signal (e.g., a frequency division ratio) of a PLL (Phase Lock Loop) is directly changed, thereby changing an output clock frequency of the PLL. But this scheme cannot meet the requirement of fast response to VDD drop because the PLL needs a long time to stabilize the clock frequency.

Disclosure of Invention

In view of the above, it is an object of the present disclosure to provide a clock control circuit, a clock circuit and an electronic device, so as to solve the problems in the prior art.

In a first aspect, an embodiment of the present disclosure provides a clock control circuit, including:

the frequency multiplier circuit is used for receiving a first clock signal of which the clock period is a set clock period and outputting a second clock signal of which the clock period is 0.5 times of the set clock period;

the quadrature frequency divider is used for receiving the second clock signal and outputting a first path of quadrature clock signal to a fourth path of quadrature clock signal, wherein the clock period from the first path of quadrature clock signal to the fourth path of quadrature clock signal is a set clock period;

and the phase processing circuit is used for receiving the first path of orthogonal clock signal to the fourth path of orthogonal clock signal and outputting a third clock signal of which the clock period is 1.25 times of the set clock period.

Optionally, the frequency multiplier circuit includes:

the delay unit is used for delaying the first clock signal for a set time length to obtain a delayed fourth clock signal;

the calibration unit is used for providing the set time length for the delay unit, and the set time length is 0.25 time of the set clock period;

and an exclusive or gate for exclusive or-ing the first clock signal and the fourth clock signal and outputting the second clock signal.

Optionally, the quadrature divider comprises:

the second buffer is used for buffering the second clock signal;

a first inverter for inverting the second clock signal and outputting a fifth clock signal;

a first latch including an input terminal and an output terminal;

a second latch comprising an input and an output;

a first tri-state inverter comprising a first enable terminal, a second enable terminal, a first input terminal, a second input terminal, a first output terminal and a second output terminal, the first and second enable terminals of which receive the second clock signal and the fifth clock signal, respectively,

a second tri-state inverter comprising a first enable terminal, a second enable terminal, a first input terminal, a second input terminal, a first output terminal and a second output terminal, the first and second enable terminals of which receive the fifth clock signal and the second clock signal, respectively,

wherein a first input of the first tri-state inverter is coupled to an output of the first latch, and an intermediate node therebetween is coupled to a first output of the second tri-state inverter,

a first output terminal of the first tri-state inverter is coupled to an output terminal of the second latch, an intermediate node between the first output terminal and the output terminal of the second tri-state inverter is coupled to a second input terminal of the second tri-state inverter,

a first input of the second tri-state inverter is coupled to an input of the second latch, an intermediate node between the two is coupled to a second output of the first tri-state inverter,

the second output terminal of the second tri-state inverter is coupled to the input terminal of the first latch, and an intermediate node between the second output terminal and the input terminal of the first tri-state inverter is coupled to the second input terminal of the first tri-state inverter.

Optionally, the first latch and the second latch have the same circuit structure and are each composed of two inverters connected end to end.

Optionally, the phase processing circuit comprises:

the clock five-frequency division circuit is used for receiving the first path of orthogonal clock signals and outputting first to fourth selection signals of which the clock period is five times of the set clock period;

the first to fourth trigger circuits are configured to receive the first to fourth selection signals, respectively receive the first to fourth paths of orthogonal clock signals, respectively output first to fourth synchronization signals, and respectively cover rising edges of the first to fourth paths of orthogonal clock signals, where a clock period of the first to fourth synchronization signals is five times of the set clock period;

first to fourth gating circuits for receiving the first to fourth synchronization signals, receiving the first to fourth quadrature clock signals, respectively, and outputting first to fourth gated output signals, respectively, wherein a clock period of the first to fourth gated output signals is five times of the set clock period, and a phase difference between adjacent signals in the first to fourth gated output signals is 1.25 times of the set clock period;

and the exclusive-OR circuit is used for receiving the first gating output signal, the second gating output signal, the third gating output signal and the fourth gating output signal, and outputting the third clock signal through exclusive-OR operation.

Optionally, the step of covering the rising edges of the first path of orthogonal clock signal to the fourth path of orthogonal clock signal by the first synchronization signal to the fourth synchronization signal respectively includes:

rising edges of the first to fourth synchronous signals are aligned with rising edges of the first to fourth paths of quadrature clock signals.

Optionally, the first to fourth trigger circuits are constituted by D flip-flops.

In a second aspect, an embodiment of the present disclosure provides a clock circuit, including:

a clock generating circuit for generating a first clock signal having a clock period set to a set clock period;

and the clock control circuit is used for receiving the first clock signal of which the clock period is the set clock period and outputting a third clock signal of which the clock period is 1.25 times of the set clock period.

Optionally, the clock control circuit is any one of the clock control circuits described above.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including:

a processor;

a storage device;

the clock circuit described above;

an on-chip bus to couple the processing unit, the memory device, and the clock circuit.

Optionally, the electronic device is a system on a chip.

In a fourth aspect, an embodiment of the present disclosure provides an up-conversion control method for a clock signal, including:

generating a first clock signal, the first clock signal having a set clock period;

and judging whether the difference between the target frequency corresponding to the set clock period and the current frequency of the system exceeds a set threshold, if so, stretching the clock period of the first clock signal by 1.25 times, taking the stretched first clock signal as the clock signal of the system, and taking the unstretched first clock signal as the clock signal of the system after a preset stable condition is reached.

Optionally, the preset stable condition is that the stretched first clock signal is used as a clock signal of a system to be kept for a preset duration.

Optionally, the stretching the clock period of the first clock signal by a factor of 1.25 comprises:

performing frequency multiplication operation on the first clock signal to output a second clock signal with a clock period 0.5 times of a set clock period;

generating a first path of orthogonal clock signals to a fourth path of orthogonal clock signals based on the second clock signals, wherein the clock cycles of the first path of orthogonal clock signals to the fourth path of orthogonal clock signals are set clock cycles;

and generating a third clock signal with the clock period 1.25 times of the set clock period based on the first path of orthogonal clock signal to the fourth path of orthogonal clock signal.

Compared with the prior art, the embodiment does not use the DLL and the PLL, but constructs the clock control circuit, and the clock control circuit generates the clock signal with the clock period being 1.25 times of the input signal through the logic operations of frequency division, latching, gating and the like of the signal, thereby avoiding the technical problems generated by using the DLL and the PLL.

Drawings

The foregoing and other objects, features, and advantages of the disclosure will be apparent from the following description of embodiments of the disclosure, which refers to the accompanying drawings in which:

FIG. 1 is a block diagram of a system on a chip according to an embodiment of the present disclosure;

FIG. 2a is a block diagram of a clock circuit according to an embodiment of the present disclosure;

FIG. 2b is a block diagram of a clock circuit coupled to a processing unit according to an embodiment of the present disclosure;

FIG. 3 is a timing diagram of the various signals shown in FIG. 2 a;

FIG. 4 is a circuit diagram of an exemplary frequency multiplier circuit;

FIG. 5 is a timing diagram of signals referenced in FIG. 4;

FIG. 6 is a circuit diagram of an exemplary quadrature divider;

FIG. 7 is an exemplary diagram of an exemplary latch;

FIG. 8 is a circuit diagram of a typical tri-state inverter;

fig. 9a to 9i are circuit configuration diagrams related to a phase processing circuit provided in an embodiment of the present disclosure;

FIG. 10 is a timing diagram of signals referenced in FIGS. 9a through 9 i;

fig. 11 is a flowchart of an up-conversion control method for a clock signal according to an embodiment of the present disclosure;

FIG. 12 illustrates a general computer architecture to which embodiments of the disclosure may be applied;

fig. 13 is a structural diagram of an embedded system to which the embodiment of the present disclosure is applied.

Detailed Description

The present disclosure is described below based on examples, but the present disclosure is not limited to only these examples. In the following detailed description of the present disclosure, some specific details are set forth in detail. It will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. Well-known methods, procedures, and procedures have not been described in detail so as not to obscure the present disclosure. The figures are not necessarily drawn to scale.

Before describing the various embodiments of the present disclosure, some terms or concepts used by the present disclosure are explained and clarified.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" is intended to encompass any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

D, a trigger: the memory is an information storage device with a memory function and two stable states, is the most basic logic unit for forming various sequential circuits, and is also an important unit circuit in a digital logic circuit. The D flip-flop has two stable states, "0" and "1", and can be flipped from one stable state to the other under the action of a certain external signal.

System on chip

Referring to the figures, an on-chip bus 102 couples various components together with the processing unit 101. An on-chip bus 102, such as an AXI bus. The AXI Bus is the most important part of the amba (advanced Microcontroller Bus architecture)3.0 and above protocol proposed by ARM corporation, and is an on-chip Bus oriented to high performance, high bandwidth, and low latency. The AIX bus separates address/control and data phases, supports unaligned data transmission, and simultaneously supports burst transmission and out-of-order transmission, thereby meeting the requirements of ultrahigh performance and complex system-on-chip design.

As shown, high speed memory 104 is coupled to processing unit 101 through on-chip bus 102. The system-on-chip 100 may further comprise interface circuitry, not shown, through which it is coupled to an off-chip external device. The external devices may be, for example, text, audio and video input/output devices and various other memories. The system-on-chip 100 may access off-chip external devices through the interface circuit. Unlike the high-speed memory 104 disposed in a system-on-chip, off-chip memory may be larger in capacity but slower and less costly, e.g., the on-chip high-speed memory 104 may be Static Random Access Memory (SRAM) while the off-chip memory is DRAM (dynamic random access memory) and flash (flash) memory.

As shown, the system-on-chip 100 may include an fm regulator controller 103. The fm/voltage regulator controller 103 is configured to generate an fm signal REGF and a voltage regulating signal REGV, send the fm signal REGF to the clock circuit 105, send the voltage regulating signal REGV to the power management circuit 211, the clock circuit 105 outputs a clock signal FCPU according to the fm signal REGF, and the power management circuit 211 outputs a voltage signal VCPU according to the voltage regulating signal REGV.

In some embodiments, fm regulator controller 103 determines the target frequency based on fm instructions received from processing unit 101. Specifically, the fm regulator controller 103 may store a plurality of frequencies in advance, extract a target frequency from the stored plurality of frequencies after receiving the fm command, compare the target frequency with each of the plurality of frequencies, and generate the fm signal REGF according to the target frequency if the target frequency is the target frequency.

In other embodiments, the fm regulator controller 103 determines the target frequency itself. For example, the fm regulator controller 103 obtains real-time detection values of parameters such as circuit physical characteristics, operating temperature, and operating voltage through sensors, determines a target frequency to be adjusted by the system according to the real-time detection values of the parameters, and generates the fm signal REGF according to the target frequency.

Clock circuit

Fig. 2a is a structural block diagram of a clock circuit provided in an embodiment of the present disclosure. The clock circuit 20 may be used in a variety of electronic devices to provide the clock signals required by the system.

As shown in fig. 2a, the clock circuit 20 includes a clock generation circuit 201 and a clock control circuit 200. The clock generation circuit 201 is configured to generate a clock signal clk _ in with a clock period T. The clock control circuit 200 is configured to generate a clock signal clk _ strosized _ out having a clock period of 1.25T based on the clock signal clk _ in.

Referring to fig. 2a, clock control circuit 200 includes a frequency multiplier circuit 202, a quadrature frequency divider 203, and a phase processing circuit 204. The frequency multiplier circuit 202 is configured to receive the clock signal clk _ in and output a clock signal clk _ doubler having a clock period of T/2. The quadrature divider 203 is configured to receive a clock signal clk _ doubler, and generate four quadrature clock signals ck _ p0, ck _ p90, ck _ p180, and ck _ p270, where the four quadrature clock signals are adjacent clock signals having a phase difference of 90 degrees, a clock period of the four clock signals is T, and a clock frequency is 1/T. The phase processing circuit 204 is used for performing various logic operations based on the clock signals ck _ p0, ck _ p90, ck _ p180, ck _ p270 to output a clock signal clk _ strosized _ out with a clock period of 1.25T.

Fig. 3 is a timing diagram of the signals according to fig. 2 a. As shown in the figure, the clock period of the clock signal clk _ in is T, and the clock frequency is 1/T. The clock period of clk _ doubler is T/2, the clock frequency is 2/T, and the frequency of the clock signal clk _ doubler is twice the frequency of the clock signal clk _ in. ck _ p0, ck _ p90, ck _ p180, ck _ p270 are quadrature clock signals, the phase difference between adjacent clock signals is 90 degrees, the clock period is T, and the clock frequency is 1/T. The clock period of the clock signal clk _ rectified _ out is 1.25T (0.5T high, 0.75T low), and the clock frequency is 0.8/T.

It is conceivable that, based on the above clock circuit, in order to avoid the problem that the power supply voltage is pulled down due to the abrupt change of the frequency during the frequency up operation, a clock signal of a target frequency is generated by the clock generation circuit 101, and then a clock signal of a frequency 0.8 times (clock cycle 1.25 times) the target frequency is output by the clock control circuit 20, and after the clock signal is stabilized for a certain period of time, the clock signal of the target frequency is output.

In conjunction with fig. 1, clock circuit 20 described above may be used in place of clock circuit 105 in fig. 1. If the clock circuit is used to replace the clock circuit 105 in fig. 1, the clock generation circuit 201 may obtain the clock frequency 1/T to be reached (i.e. the clock period to be reached is T) from the fm signal REGF provided by the fm regulator controller 103, and accordingly generate the clock signal clk _ in. Further, the fm signal REGF may further include a flag bit, where the flag bit is used to specify whether the clock signal is directly raised to the target frequency, if so, the clock signal generated by the clock generation circuit 201 is directly provided to the processing unit, so that the clock frequency of the system on chip is directly raised from the current frequency to the target frequency, and if not, the clock signal of the target frequency of the clock generation circuit 201 is first provided to the processing unit via the clock control circuit 200, so that the clock frequency of the system on chip is raised from the current frequency to the target frequency 0.8, and after the clock signal is stable for a period of time, the clock signal of the target frequency is provided to the processing unit (i.e., the clock frequency of the system is first raised from the current frequency to 0.8 times of the target frequency and then raised to the target frequency). In a specific implementation, as shown in fig. 2b, one input terminal of the two-way selector 210 is coupled to the clock control circuit 200 to receive clk _ stronched _ out, the other input terminal is coupled to the clock generation circuit 201 to receive clk _ in, the output terminal is coupled to the processing unit 101, the control terminal receives the control signal from the fm regulator controller 103, and under the action of the control signal, the two-way selector 210 determines to output one of the two input signals at the output terminal.

Fig. 4 is a circuit diagram of an exemplary frequency multiplier circuit. As shown in fig. 4, the frequency multiplier circuit 400 includes a delay unit 401, a calibration unit 402, and an exclusive or gate 403, and its input signal is a clock signal clk _ in and its output signal is a clock signal clk _ doubler.

Specifically, the input clock clk _ in is delayed to obtain the clock signal clk _ in _ delay, and then the clk _ in and clk _ in _ delay are subjected to an exclusive-or operation to generate the frequency-multiplied clock signal clk _ doubler. Wherein the delay unit 401 is configured to delay the clock signal clk _ in, and the calibration unit 402 is configured to provide the delay unit 401 with a delay value calibrated to a quarter of the input clock period at each PVT. There are many ways to implement the calibration unit 402, such as by detecting the clock cycle of clk _ doubler. The exclusive or gate 403 is used to exclusive or clk _ in and clk _ in _ delay.

Fig. 5 is a signal timing chart related to fig. 4. As shown in the figure, the clock period of the clock signal clk _ in is T, the clock frequency is 1/T, and clk _ in _ delay is delayed by T/4 compared with the clock signal clk _ in, but the frequency is still 1/T. clk _ doubler is a clock signal obtained by exclusive-oring the clock signals clk _ in and clk _ in _ delay. As can be seen from the figure, the clock period of clk _ doubler is T, the clock frequency is 2/T, and the frequency of the clock signal clk _ doubler is twice the frequency of the clock signal clk _ in.

Fig. 6 is a circuit diagram of an exemplary quadrature divider. The effect of quadrature divider 600 is to output a quadrature clock signal, wherein the frequency of the output clock signal is 0.5 times the frequency of the input clock signal.

Referring to the figure, the input terminal of the quadrature frequency divider 600 receives the clock signal clk _ doubler, and outputs the clock signal clkbuf after passing through the conventional buffer Buf1 and the conventional buffer Buf2, while the clock signal clkn is output by the clk _ doubler through the conventional buffer Buf1 and the inverter Inv 1. The conventional buffer Buf2 is connected in parallel with the inverter Inv1 and in series with the conventional buffer Buf 1. Since the buffers Buf1 and Buf2 do not change the frequency and phase of the input clock signal, the clock signal clkbuf is the same frequency and the same phase as the clock signal clk _ doubler, but the inverter Inv1 inverts the input clock signal and outputs the inverted clock signal, so that the clock signal clkn is the same frequency and the inverted clock signal clk _ doubler. In some embodiments, the quadrature divider shown in fig. 6 may not include buffer Buf 1.

As shown in the figure, the tri-state inverters tri1 and tri2 have enable terminals oe, oen and input terminals a1, a2 and output terminals z1n, z2 n. Latch1 and latch2 have input terminal d and output terminal qn.

The input a1 of tri-state inverter tri1 is coupled to the qn terminal of latch1, and the output z1n of tri1 is coupled to the qn terminal of latch 2. The d terminal of latch1 is coupled to the output terminal z2n of tristate inverter tri 2. The d terminal of latch2 is coupled to input a1 of tristate inverter tri 2.

The intermediate node M1, at which the input a1 of the tristate inverter tri1 is connected to the qn terminal of the latch1, is coupled to the output z1n of the tristate inverter tri 2. The intermediate node M2, at which the output terminal z1n of the tristate inverter tri1 is connected to the qn terminal of the latch2, is coupled to the input terminal a2 of the tristate inverter tri 2. The intermediate node M3, whose terminal d of the latch1 is connected to the output terminal z2n of the tristate inverter tri2, is coupled to the input terminal a2 of the tristate inverter tri 1. The intermediate node M4, whose terminal d of the latch2 is connected to the input a1 of the tristate inverter tri2, is coupled to the output z2n of the tristate inverter tri 1.

The enable terminals oen and oe of the tri-state inverter tri1 are coupled to the clock signals clkn and clkbuf, respectively. The enable terminals oe and oen of the tri-state inverter tri2 are coupled to the clock signals clkn and clkbuf, respectively. clkbuf is a clock signal that is in phase with clk _ doubler. clkn is the clock signal inverted from clk _ doubler.

A first output of the quadrature divider 600 leads from the intermediate node M2, which leads to the quadrature clock signal ck _ p 0. A second output of the quadrature divider 600 leads from the intermediate node M1, which leads to the quadrature clock signal ck _ p 90. A third output of the quadrature divider 600 leads from the intermediate node M3, which leads to the quadrature clock signal ck _ p 270. A fourth output of the quadrature divider 600 leads from the intermediate node M4, which leads to the quadrature clock signal ck _ p 180. For convenience, we shall designate the first output terminal as ckout <0>, the second output terminal as ckout <1>, the third output terminal as ckout <3>, and the fourth output terminal as ckout <2 >.

For tri-state inverters tri1 and tri2, when the signal of oe input is high and the signal of oe input is low, the signals output by z1n and a1 are inverted, z2n is inverted with the signal output by a2, and when the signal of oe input is low and the signal of oe input is high, z1n and z2n are in high impedance state.

Based on this, when clkbuf is low, clkn is high, the signal input by tri-state inverter tri2 on oe is high, and the signal input by tri 3578 on oen is low, at this time, tri2 outputs inverted signals at ends z1n and z2n, at the same time, the signal of tri1 on oe is low, and the signal input by tri1 on oen is high, at this time, tri1 is high impedance. When clkbuf is high, clkn is low, the signal input by tristate inverter tri2 on oe is low, and the signal input by reen is high, at which time tristate inverter tri2 is high impedance state, at the same time, the signal of tristate inverter tri1 on oe is high, and the signal input by reen is low, at which time, tristate inverter tri1 outputs inverted signal.

The operating principle of the quadrature divider is explained below on the basis of the waveform diagram shown in fig. 3.

As shown in fig. 3, assuming that the initial value of ck _ p0 is high, that is, the initial value of latch2 is 1, then ckout <2> is 0, and then ckout <1> and ckout <3> are driven by ckout <2> and ckout <0> respectively, and are inverses of them.

In the first cycle, clkbuf is low, clkn is high, tristate buffer tri1 outputs high impedance, tri2 tristate buffer outputs inverted, and if the initial value of the latch2 latch is ckout <0> to 1, then ckout <2> to 0, then ckout <1> and ckout <3> are driven by and are the inverse of ckout <2> and ckout <0> respectively.

In the second cycle, clkbuf is high, clkn is low, tristate buffer tri1 outputs inverted, tri2 tristate buffer outputs high impedance, and ckout <0> and ckout <2> are driven by and are the inverse of ckout <1> and ckout <3>, respectively.

In the third cycle clk in is low, clkn is high, tri1 tri-state buffer outputs high impedance, tri2 tri-state buffer outputs inverted, and ckout <1> and ckout <3> are driven by and are the inverse of ckout <2> and ckout <0>, respectively.

In the fourth period, the same as the second period.

FIG. 7 is an exemplary diagram of an exemplary latch. As shown, latch 700 is formed by inverters Inv2 and Inv3 connected end-to-end, the ends and terminations of inverters Inv2 and Inv3 being identified by ZN and I, respectively. The latches Inv2 and Inv3 are used to invert the input signal and output it.

Fig. 8 is a circuit diagram of a typical tri-state inverter. As shown, the tri-state inverter 800 includes PMOS transistors P1-P3 and NMOS transistors N1-N3.

The source electrode of the PMOS tube P3 is connected with the power dvdd08, the drain electrode is connected with the source electrode of the PMOS tube P1 and the source electrode of the PMOS tube P2, and the grid electrode is the enabling end oen of the tri-state inverter and is used for accessing an enabling signal.

The drain electrode of the PMOS pipe P1 and the drain electrode of the PMOS pipe P2 are respectively connected with the drain electrode of the NMOS pipe N1 and the drain electrode of the NMOS pipe N2. The input end a1 of the tri-state inverter is led out from the middle node of the connection between the grid electrode of the PMOS pipe P1 and the grid electrode of the NMOS pipe N1, and the output end z1N of the tri-state inverter is led out from the middle node of the connection between the drain electrode of the PMOS pipe P1 and the drain electrode of the NMOS pipe N1. The intermediate node of the grid of the PMOS pipe P2 and the grid of the NMOS pipe N2 is connected with the input end a2 of the tri-state inverter, and the intermediate node of the drain of the PMOS pipe P2 and the drain of the NMOS pipe N2 is connected with the output end z2N of the tri-state inverter. The source of the NMOS transistor N1 is connected to the drain of the NMOS transistor N3. The source of the NMOS transistor N2 is connected to the drain of the NMOS transistor N3. The gate of the NMOS transistor N3 serves as the enable terminal oe of the tri-state inverter. The source of the NMOS transistor N3 is grounded dvss.

As shown in the figure, when the signal of oe input is low, N3 is turned off, and oen is high, P3 is turned off, and at this time, P1 and N1, and P2 and N2 are in a high-impedance state. When the signal of oe input is high level, N3 is turned on, when oen is low level, P3 is turned on, when a1 is high level, P1 is turned off, N1 is turned on, the level of the output end z1N is consistent with dvss, and low level is output, when a1 is low level, P1 is turned on, N1 is turned off, the level of the output end z1N is consistent with dvdd08, and high level is output; similarly, when a2 is at high level, P2 is turned off, N2 is turned on, the level of the output terminal z2N is kept at dvss, and low level is output, and when a2 is at low level, P2 is turned on, N2 is turned off, the level of the output terminal z2N is kept at dvdd08, and high level is output, so that for the tri-state inverter, when the signal input oe is at high level and the signal input oen is at low level, a signal inverted from the input is output.

Fig. 9a to 9i are circuit configuration diagrams of a phase processing circuit according to an embodiment of the present disclosure. Fig. 10 is a signal timing diagram according to fig. 9a to 9 i.

Referring to fig. 9a, the clock signal ck _ p0 is frequency-divided by the clock divide-by-five circuit clock _ div5 and outputs a selection signal sel <3,0> of 1/5 whose frequency is the frequency of the input clock signal ck _ p0, and in the selection signal sel <3,0>, the delay value of adjacent signals is T.

Referring to FIG. 10, the frequencies sel <0> to sel <3> are 1/5 of the frequency of the clock signal ck _ p0, respectively (i.e., the clock periods of sel <0> to sel <3> are 5T). It can be seen from the figure that sel <0> and the clock signal ck _ p0 have a delay time diff due to the circuit characteristics of the clock divide-by-five circuit, and the delay values of two adjacent signals among the selection signals sel <0> to sel <3> are T.

In FIG. 9a, ck _ p0 is the input clock signal of the Clk terminal of D flip-flop trg1, sel <0> is the input signal of the D terminal, and sel _ sync <0> is the synchronization signal output by the Q terminal.

Referring to fig. 10, the clock periods of sel <0> and sel _ sync <0> are both 5T, but the output sel _ sync <0> is delayed from sel <0> by one clock period by D flip-flop trg1, the high level of sel _ sync <0> covers the rising edge of ck _ p0, and thus the two inputs (en and clk) of the subsequent clock gating cell gate1 can meet the timing requirement of the cell, and avoid timing errors.

In FIG. 9b, the Clk terminal of the D flip-flop trg2 inputs the selection signal sel <1>, the Clk terminal inputs the clock signal ck _ p90, the Q terminal of the D flip-flop trg2 outputs the synchronization signal sel _ sync _ a <1>, the Clk terminal of the D flip-flop trg3 receives the clock signal ck _ p90, the D terminal is coupled to the Q terminal of the D flip-flop trg2 to receive the synchronization signal sel _ sync _ a <1>, and the Q terminal of the D flip-flop trg3 outputs the synchronization signal sel _ sync _ b <1 >.

Referring to fig. 10, the clock periods of sel <1>, sel _ sync _ a <1> and sel _ sync _ b <1> are all 5T, and the two D flip-flops trg2 and trg3 are used to cover the high level of sel _ sync _ b <1> to the correct rising edge of ck _90, so that the two inputs (en and clk) of the subsequent clock gating cell gate2 can meet the timing requirement of the cell, and the occurrence of timing errors is avoided.

In FIG. 9c, the Clk terminal of the D flip-flop trg4 inputs the selection signal sel <2>, the Clk terminal inputs the clock signal ck _ p180, the Q terminal of the D flip-flop trg4 outputs the synchronization signal sel _ sync _ a <2>, the Clk terminal of the D flip-flop trg5 receives the clock signal ck _ p180, the D terminal is coupled to the Q terminal of the D flip-flop trg4 to receive the synchronization signal sel _ sync _ a <2>, and the Q terminal of the D flip-flop trg5 outputs the synchronization signal sel _ sync _ b <2 >.

Referring to fig. 10, the clock periods of sel <2>, sel _ sync _ a <2> and sel _ sync _ b <2> are all 5T, and the purpose of using two D flip-flops trg2 and trg3 is to cover the high level of sel _ sync _ b <2> to the correct rising edge of ck _180, so as to ensure that the two inputs (en and clk) of the subsequent clock gating cell gate3 can meet the timing requirement of the cell, and avoid timing errors.

In FIG. 9D, the Clk terminal of the D flip-flop trg6 inputs the selection signal sel <3>, the Clk terminal inputs the clock signal ck _ p270, the Q terminal of the D flip-flop trg6 outputs the synchronization signal sel _ sync _ a <3>, the Clk terminal of the D flip-flop trg7 receives the clock signal ck _ p270, the D terminal is coupled to the Q terminal of the D flip-flop trg6 to receive the synchronization signal sel _ sync _ a <3>, and the Q terminal of the D flip-flop trg7 outputs the synchronization signal sel _ sync _ b <3 >.

Referring to FIG. 10, the clock periods of sel <3>, sel _ sync _ a <3> and sel _ sync _ b <3> are all 5T (frequency is 1/T), and the purpose of using two D flip-flops trg6 and trg7 is to cover the high level of sel _ sync _ b <3> to the correct rising edge of ck _270, so as to ensure that the two inputs (en and clk) of the subsequent clock gating cell gate4 can meet the timing requirement of the cell, and avoid timing errors.

With continuing reference to FIGS. 9e-9h, in FIG. 9e, clock gating unit gate1 receives a sync signal sel _ sync <0> at enable en, a clock signal ck _ p0 at input Clk, and a cg _ out <0> at output, in FIG. 9f, clock gating unit gate2 receives a sync signal sel _ sync _ b <1> at enable en, a clock signal ck _ p90 at input Clk, and a cg _ out <1> at output, in FIG. 9g, clock gating unit gate3 receives a sync signal sel _ sync _ b <2> at enable en, a clock signal ck _ p180 at input Clk, and a cg _ out <2> at output, in FIG. 9h, clock gating unit gate4 receives a sync signal sel _ sync _ b <3> at enable en, and a clock signal ck _ p270, and a cg _ out <3> at output.

As an alternative embodiment, any one of the clock gating units gate 1-gate 4 is an AND gate, and in FIG. 9e, signals sel _ sync <0> and ck _ p0 are AND-operated, that is, when sel _ sync <0> and ck _ p0 are both high or low, corresponding to outputting high or low, and when one of sel _ sync <0> and ck _ p0 is high and the other is low, outputting low, so that the clock period of cg _ out <0> output is 5T, wherein high occupies 0.5T and low occupies 4.5T.

The clock cycles of cg _ out <1>, cg _ out <2> and cg _ out <3> obtained by the AND gate operation are also 5T, the high level occupies 0.5T, and the low level occupies 4.5T, but at the same time, the phase difference between two adjacent signals in cg _ out <0>, cg _ out <1>, cg _ out <2> and cg _ out <3> is 1.25T.

Referring to fig. 9i, cg _ out <0>, cg _ out <1>, cg _ out <2> and cg _ out <3> are input to an OR gate OR, and are subjected to an OR operation, so as to obtain a stretching clock signal ck _ out _ stretch _1p 25. Therefore, the cg _ out <0>, the cg _ out <1>, the cg _ out <2> and the cg _ out <3> are subjected to OR operation, and a stretched clock signal with a clock period of 1.25T is finally obtained.

Compared with the prior art, the embodiment does not use the DLL and the PLL, but constructs the clock control circuit, and the clock control circuit generates the clock signal with the clock period being 1.25 times of the input signal through the logic operations of frequency division, latching, gating and the like of the signal, thereby avoiding the technical problems generated by using the DLL and the PLL.

It should be understood that the circuit configurations of the latch, tri-state inverter and quadrature divider in this disclosure are exemplary and not required, and that one skilled in the art would be able to construct alternative circuits having the same functionality, knowing the functional requirements of the various circuits.

Frequency raising control method for clock signal

Fig. 11 is a flowchart of an up-conversion control method for a clock signal of a system embodying the present disclosure. The method comprises the following steps.

In step S01, a target clock signal is generated, the target clock signal having a target frequency.

In step S02, it is determined whether the gap between the target frequency and the current frequency exceeds a set threshold. If the gap between the target frequency and the current frequency exceeds the set threshold, step S03 is performed, otherwise step S04 is performed.

In step S03, the clock cycle corresponding to the target clock signal is stretched by 1.25 times and output.

In step S04, the target clock signal is directly output.

According to the embodiment, in the frequency boosting operation, whether the frequency is directly boosted to the target frequency depends on the difference between the current frequency and the target frequency, when the difference is larger than the set threshold, the frequency is boosted from the current frequency to 0.8 times (1/1.25) of the target frequency, and then the frequency is boosted from 0.8 times of the target frequency to the target frequency after the preset stable condition is reached. Therefore, the frequency increasing operation of the clock signal tends to be gentle, and the problem that the power consumption of the load is suddenly increased due to the steep frequency rise, so that the power supply voltage is pulled down is also avoided.

In a further embodiment, the reaching of the preset stable condition comprises: and raising the frequency of the processor from the current frequency to 0.8 time of the target frequency and then keeping the preset time length.

In a further embodiment, stretching the clock period of the target clock signal to 1.25 times of step S03 includes the steps of:

in step S031, four quadrature clock signals ck _ p0, ck _ p90, ck _ p180, and ck _ p270 having a target frequency are generated based on the target clock signal. In FIG. 10, the clock period is T and the target frequency is 1/T.

Step S032, five frequency division is performed based on the target clock signal to obtain four paths of selection signals sel <0> to sel <3>, and the clock period of the four paths of selection signals sel <0> to sel <3> is 5T.

In step S033, the four selection signals sel <0> to sel <3> and the four quadrature clock signals ck _ p0, ck _ p90, ck _ p180, and ck _ p270 are used to generate four synchronization signals sel _ sync <0>, sel _ sync _ b <1>, sel _ sync _ b <2>, and sel _ sync _ b <3 >. Four-way synchronizing signals sel _ sync <0>, sel _ sync _ b <1>, sel _ sync _ b <2> and sel _ sync _ b <3> respectively cover the rising edges of four-way orthogonal clock signals ck _ p0, ck _ p90, ck _ p180 and ck _ p270 (including the case of rising edge alignment), while the four-way synchronizing signals sel _ sync <0>, sel _ sync _ b <1>, sel _ sync _ b <2> and sel _ sync _ b <3> have a clock period of 5T, a high level of T, a low level of 4T and a delay value of 1.25T for the two adjacent signals.

In step S034, four channels of synchronization signals sel _ sync <0>, sel _ sync _ b <1>, sel _ sync _ b <2> and sel _ sync _ b <3> and four channels of quadrature clock signals ck _ p0, ck _ p90, ck _ p180 and ck _ p270 are gated to output gated output signals cg _ out <0> to cg _ out <3 >. The clock cycle of the gating output signals cg _ out <0> to cg _ out <3> is 5T, the high level is 0.5T, the low level is 4.5T, and the delay value of two adjacent signals is 1.25T.

In step S035, the gated output signals cg _ out <0> to cg _ out <3> are anded to obtain the stretching clock signal clk _ out _ stretch _1P 25. clk _ out _ stretch _1P25 is a clock signal with a clock period of 1.25T.

The frequency up-conversion control method for the clock signal provided in this embodiment may output the clock signal with the frequency 0.8 times of the target frequency when the difference between the target frequency and the current frequency is large, and output the clock signal with the target frequency after reaching the preset stable condition. Therefore, the frequency increasing operation of the clock signal tends to be gentle, and the problem that the power consumption of the load is suddenly increased due to the steep frequency rise, so that the power supply voltage is pulled down is also avoided.

Clock circuit and specific application of system on chip

FIG. 12 illustrates a general computer architecture to which embodiments of the disclosure may be applied. As shown, computer system 1200 may include one or more processors 12, and memory 14. In some embodiments, the clock circuit described above may be used in the computer architecture to provide a clock signal, and in other embodiments, the system-on-chip shown in FIG. 1 may be used directly as the processor 12 in this embodiment.

The memory 14 in the computer system 1200 may be a main memory (referred to simply as main memory or memory). For storing instruction information and/or data information represented by data signals, such as data provided by the processor 12 (e.g., operation results), and for implementing data exchange between the processor 12 and an external storage device 16 (or referred to as an auxiliary memory or an external memory).

In some cases, processor 12 may need to access memory 14 to retrieve data in memory 14 or to make modifications to data in memory 14. To alleviate the speed gap between processor 12 and memory 14 due to the slow access speed of memory 14, computer system 1200 also includes a cache memory 18 coupled to bus 11, cache memory 18 being used to cache some data in memory 14, such as program data or message data, that may be repeatedly called. The cache Memory 18 is implemented by a storage device such as a Static Random Access Memory (SRAM). The Cache memory 18 may have a multi-level structure, such as a three-level Cache structure having a first-level Cache (L1 Cache), a second-level Cache (L2 Cache), and a third-level Cache (L3 Cache), or may have a Cache structure with more than three levels or other types of Cache structures. In some embodiments, a portion of the cache memory 18 (e.g., a level one cache, or a level one cache and a level two cache) may be integrated within the processor 12 or in the same system on a chip as the processor 12.

In this regard, the processor 12 may include an instruction execution unit 121, a memory management unit 122, and so on. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory, where the write access request specifies write data and a corresponding physical address that need to be written into the memory; the memory management unit 122 is configured to translate the virtual addresses specified by the instructions into the physical addresses mapped by the virtual addresses, and the physical addresses specified by the write access request may be consistent with the physical addresses specified by the corresponding instructions.

The information exchange between the memory 14 and the cache 18 is typically organized in blocks. In some embodiments, the cache 18 and the memory 14 may be divided into data blocks by the same spatial size, and a data block may be the smallest unit of data exchange (including one or more data of a preset length) between the cache 18 and the memory 14. For the sake of brevity and clarity, each data block in the cache memory 18 will be referred to below simply as a cache block (which may be referred to as a cacheline or cache line), and different cache blocks have different cache block addresses; each data block in the memory 14 is referred to as a memory block, and different memory blocks have different memory block addresses. The cache block address comprises, for example, a physical address tag for locating the data block.

Due to space and resource constraints, the cache memory 18 cannot cache the entire contents of the memory 14, i.e., the storage capacity of the cache memory 18 is generally smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to the entire memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, firstly, the cache memory 18 is accessed through the bus 11 to judge whether the content to be accessed is stored in the cache memory 18, if so, the cache memory 18 hits, and at the moment, the processor 12 directly calls the content to be accessed from the cache memory 18; if the content that the processor 12 needs to access is not in the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to look up the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, the efficiency of the processor 12 can be significantly improved when the cache memory 18 hits, thereby also improving the performance and efficiency of the overall computer system 1200.

In addition, computer system 1200 may also include input/output devices such as storage device 16, display device 13, audio device 19, mouse/keyboard 15, and the like. The storage device 16 is a device for information access such as a hard disk, an optical disk, and a flash memory coupled to the bus 11 via corresponding interfaces. The display device 13 is coupled to the bus 11, for example via a corresponding graphics card, for displaying in accordance with display signals provided by the bus 11.

Computer system 1200 also typically includes a communication device 17 and thus may communicate with a network or other devices in a variety of ways. The communication device 17 may comprise, for example, one or more communication modules, by way of example, the communication device 17 may comprise a wireless communication module adapted for a particular wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing Wi-FiTM communication in compliance with the 902.11 standard established by the Institute of Electrical and Electronics Engineers (IEEE); the communication device 17 may also include a WWAN module for implementing wireless wide area communication conforming to a cellular or other wireless wide area protocol; the communication device 17 may also include a communication module using other protocols, such as a bluetooth module, or other custom type communication modules; the communication device 17 may also be a port for serial transmission of data.

Of course, the structure of different computer systems may vary depending on the motherboard, operating system, and instruction set architecture. For example, many computer systems today have an input/output control hub coupled between the bus 11 and various input/output devices, and the input/output control hub may be integrated within the processor 12 or separate from the processor 12.

Fig. 13 is a structural diagram of an embedded system to which the embodiment of the present disclosure is applied. In some embodiments, the clock circuit described above can be used in the present embedded system to provide a clock signal, and in other embodiments, the system on chip shown in fig. 1 can be directly used as the processor 951 in the present embodiment.

Although the embedded system has a high similarity to a computer system in terms of hardware structure, the application characteristics of the embedded system cause the embedded system to be greatly different from a general computer system in terms of the composition and implementation form of hardware.

First, in order to meet the requirements of the embedded system 950 on speed, size and power consumption, data that needs to be stored for a long time, such as an operating system, application software, and special data, is usually not used in a storage medium with a large capacity and a low speed, such as a magnetic disk, but a random access Memory 952 or a Flash Memory (Flash Memory)953 is mostly used.

In addition, in embedded system 950, a/D (analog/digital conversion) interface 955 and serial interface 956 are required for the needs of instrumentation, which is rarely used in general purpose computers. The a/D interface 955 mainly performs conversion of an analog signal to a digital signal and conversion of a digital signal to an analog signal required in the test. Embedded system 950 often requires testing when applied to industrial production. Since the single chip generates a digital signal and needs to be converted into an analog signal for testing during testing, unlike a general-purpose computer, an a/D (analog/digital conversion) interface 955 is required to perform a related conversion. In addition, the industry often requires multiple embedded systems to be connected in series to perform related functions, and therefore a serial interface 956 is required to connect multiple embedded systems in series, which is not required in many general purpose computers.

In addition, the embedded system 950 is a basic processing unit, and it is often necessary to connect a plurality of embedded systems 950 into a network in industrial design, and therefore, a network interface 957 for connecting the embedded system 950 into the network is required. This is also mostly not required in general purpose computers. In addition, some embedded systems 950 employ an external bus 954 depending on the application and size. With the rapid expansion of the application field of the embedded system 950, the embedded system 950 tends to be personalized more and more, and the types of buses adopted according to the characteristics of the embedded system 950 are more and more. In addition, boundary scan testing is commonly employed in processor chips to test the internal circuitry of embedded processor 951. To accommodate this testing, a debug interface 958 is employed.

With the rapid development of Very Large Scale integrated circuits (Very Large Scale Integration) and semiconductor processes, part or all of the embedded system can be implemented on a silicon chip, i.e., an embedded system on a chip (SoC).

Commercial value of the disclosed embodiments

The clock control circuit provided by the embodiment of the disclosure can be used for a clock circuit to avoid sudden increase of load power consumption caused by steep frequency rise and cause the power supply voltage to be pulled down. And the resulting clock circuit may then be applied in any electronic device including a system on a chip. The electronic device may be, for example, a cloud server with a large number of data centers, or may be various electronic devices used in daily life. Based on this, the clock control circuit, the clock circuit, the system on chip and the electronic device constructed by the system on chip of the embodiments of the present disclosure have commercial value and economic value.

It should be understood that the above description describes particular embodiments of the present specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

It should be understood that an element described herein in the singular or shown in the figures only represents that the element is limited in number to one. Furthermore, modules or elements described or illustrated herein as separate may be combined into a single module or element, and modules or elements described or illustrated herein as single may be split into multiple modules or elements.

It is also to be understood that the terms and expressions employed herein are used as terms of description and not of limitation, and that the embodiment or embodiments of the specification are not limited to those terms and expressions. The use of such terms and expressions is not intended to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications may be made within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be looked to in order to cover all such equivalents.