阅读说明：本技术 数字采样数据高速插值同步方法及系统 (Digital sampling data high-speed interpolation synchronization method and system ) 是由 李鹏 陈从靖 陈新之 霍银龙 李立浧 于杨 姚浩 习伟 于 2021-07-28 设计创作，主要内容包括：本发明公开了一种数字采样数据高速插值同步方法,包括：接收SV报文,提取SV报文中的各通道采样值信息以及时标信息；将各通道采样值信息与时标信息并行并行缓存；基于时间管理模块和SV报文时延信息计算需要插值的时刻；根据插值时刻同步读取各通道采样值信息；根据插值时刻和采样值信息算出插值,本发明能够充分利用FPGA器件并行处理数据能力,同步操作写入、读取多个RAM的地址,实现多端口多通道的并行插值,大幅减少了数据插值消耗的时间。(The invention discloses a high-speed interpolation synchronization method for digital sampling data, which comprises the following steps: receiving an SV message, and extracting sampling value information and time mark information of each channel in the SV message; parallelly caching the sampling value information and the time scale information of each channel; calculating the time needing interpolation based on the time management module and SV message time delay information; synchronously reading the information of the sampling values of all channels according to the interpolation time; the invention can fully utilize the parallel data processing capability of the FPGA device, synchronously operate and write and read the addresses of a plurality of RAMs, realize the parallel interpolation of multiple ports and multiple channels and greatly reduce the time consumed by data interpolation.)

1. A high-speed interpolation synchronization method for digital sampling data is characterized by comprising the following steps:

receiving an SV message, and extracting sampling value information and time mark information of each channel in the SV message;

parallelly caching the sampling value information and the time scale information of each channel;

calculating the time needing interpolation based on the time management module and SV message time delay information;

synchronously reading the information of the sampling values of all channels according to the interpolation time;

and calculating interpolation according to the interpolation time and the sampling value information.

2. The high-speed interpolation synchronization method for digital sample data according to claim 1, wherein: and multi-port parallel receiving processing is carried out when SV messages are received and received.

3. The high-speed interpolation synchronization method for digital sample data according to claim 2, wherein: each port stores time stamp information and a sample value at the same address.

4. A high-speed interpolation synchronization method for digital sample data according to claim 1, wherein the interpolation is calculated as follows:

when t is_i≤t_x≤t_i+1The interpolation is obtained by the calculation of the formula (1)

Wherein, t_i、t_xAnd t_i+1Respectively indicate the interpolation time points of the i, x and i +1 th sampling points, Y (t)_i+1)、Y(t_i) Respectively representing the sample values of the i +1 th and i-th sample points.

5. A digital sample data high speed interpolation synchronization system, comprising:

the message analysis and storage module is used for receiving the SV message and extracting the sampling value information and the time mark information of each channel in the SV message;

parallelly caching the sampling value information and the time scale information of each channel;

the interpolation module is used for calculating the time needing interpolation based on the time management module and the SV message time delay information;

synchronously reading the information of the sampling values of all channels according to the interpolation time;

and calculating interpolation according to the interpolation time and the sampling value information.

6. A high-speed interpolation synchronization system of digital sampling data is characterized by comprising a memory and a processor;

the memory is to store instructions;

the processor is configured to operate in accordance with the instructions to perform the steps of the method according to any one of claims 1 to 4.

Technical Field

The invention belongs to the technical field of power system protection and control, and particularly relates to a digital sampling data high-speed interpolation synchronization method and system.

Background

The digital sampling technology is widely applied to relay protection and automatic devices, and in an intelligent substation, three sampling value acquisition modes of direct sampling, merging unit point-to-point and SV (sampling value message) networking (via a switch) and a mixed mode thereof exist at present. The data processing is difficult due to different delays of the data, and the data synchronization is usually realized by an interpolation method, i.e., a resampling method.

In the current engineering application, the main scheme is that the FPGA completes the work of local sampling, SV message analysis, filtering and the like, the content of a sampling value message is directly sent to the CPU without processing, and the CPU completes the interpolation synchronization of the sampling value. The scheme is definite in work division, but occupies high CPU resources, and the processing capacity of the CPU limits the operation efficiency of the system in an application scene with large data volume. The other scheme is that the interpolation synchronization work is completed by the FPGA, namely after the FPGA completes the local sampling and the SV message receiving processing, the message is stored in an internal cache, and a new interpolation synchronization sequence is calculated according to the information of interpolation synchronization pulse, backspacing time and the like. However, in the scheme, interpolation needs to be calculated serially one by one, the completion efficiency of the interpolation is low by the FPGA, and when the number of channels is large, the protection performance is affected.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a high-speed interpolation synchronization method and system for digital sampling data, which can improve the interpolation efficiency.

The technical problem to be solved by the invention is realized by the following technical scheme:

in a first aspect, a method for synchronizing high-speed interpolation of digital sample data is provided, which includes:

receiving an SV message, and extracting sampling value information and time mark information of each channel in the SV message;

parallelly caching the sampling value information and the time scale information of each channel;

calculating the time needing interpolation based on the time management module and SV message time delay information;

synchronously reading the information of the sampling values of all channels according to the interpolation time;

and calculating interpolation according to the interpolation time and the sampling value information.

With reference to the first aspect, further, when receiving an SV packet, the multi-port parallel reception processing is performed.

With reference to the first aspect, further, each port stores the time stamp information and the sample value at the same address.

With reference to the first aspect, further, the calculation of the interpolation is as follows:

when t is_i≤t_x≤t_i+1The interpolation is obtained by the calculation of the formula (1)

Wherein, t_i、t_xAnd t_i+1Respectively indicate the interpolation time points of the i, x and i +1 th sampling points, Y (t)_i+1)、Y(t_i) Respectively representing the sample values of the i +1 th and i-th sample points.

In a second aspect, a high-speed interpolation synchronization system for digital sample data is provided, which includes:

the message analysis and storage module is used for receiving the SV message and extracting the sampling value information and the time mark information of each channel in the SV message;

parallelly caching the sampling value information and the time scale information of each channel;

the interpolation module is used for calculating the time needing interpolation based on the time management module and the SV message time delay information;

synchronously reading the information of the sampling values of all channels according to the interpolation time;

and calculating interpolation according to the interpolation time and the sampling value information.

In a third aspect, a high-speed interpolation synchronization system for digital sampling data is provided, which comprises a memory and a processor;

the memory is to store instructions;

the processor is configured to operate in accordance with the instructions to perform the steps of the method according to any one of the first aspect.

The invention has the beneficial effects that: aiming at the technical requirements of how to realize multiport receiving and high-speed interpolation of multi-channel sampling data, the invention stores time mark information into the RAM in sequence after SV message receiving and data extraction are finished, simultaneously, sampling values are put into different RAMs according to different channels, the storage addresses are kept consistent with the time mark storage addresses, after interpolation time is obtained by calculation, a time delay mark reversely searches an interpolation interval, at the moment, the RAM of the selected channel is synchronously read by the same address to obtain the sampling value data, and the sampling value of an interpolation point is obtained by calculation. The method can fully utilize the parallel data processing capacity of the FPGA device, synchronously operate and write and read the addresses of the plurality of RAMs, realize the parallel interpolation of multiple ports and multiple channels, greatly reduce the time consumed by data interpolation, and reduce the data processing burden for a CPU.

Drawings

FIG. 1 is a flow chart of the present invention;

FIG. 2 is a schematic diagram of data storage according to the present invention;

fig. 3 is a schematic diagram of the interpolation process of the present invention.

Detailed Description

To further describe the technical features and effects of the present invention, the present invention will be further described with reference to the accompanying drawings and detailed description.

Example 1

As shown in fig. 1-3, a high-speed interpolation synchronization method for digital sampling data mainly includes the following steps:

firstly, parallel receiving of SV messages of a plurality of ports is completed by an FPGA, filtering of repeated messages is completed, non-subscribed messages are discarded, and sampling value information and time mark information of each channel in the messages are extracted.

Step two, storing the time mark information (corresponding relation with the interpolation time) in the ASDU (application Service Data Unit) and the sampling value information of each channel in parallel into a double-port RAM (the cache depth is more than 2 ms) by the same address. The format of the data storage is shown in fig. 2. During interpolation, an interpolation point time scale interval is searched, the sampling values of all channels read data at the same address, and after the interpolation interval is obtained, the interpolation data are obtained through calculation according to the following formula, so that the parallel synchronous interpolation of multiple channels is completed, the calculation method is used for all the channels, and when the interpolation point x is positioned between the sampling point i and the point i +1, the interpolation time t is inserted_xSatisfies the following conditions: .

t_i≤t_x≤t_i+1

Then there are:

wherein, t_i、t_xAnd t_i+1Respectively indicate the interpolation time points of the i, x and i +1 th sampling points, Y (t)_i+1)、Y(t_i) Respectively representing the sample values of the i +1 th and i-th sample points.

As shown in FIG. 3, in the flow of processing data, t_kFor the time to be interpolated, the interpolation time t is calculated according to the information such as the message delay time and the like_xThe time delay axis is reversely searched one by one to find the first one smaller than t_xTime scale t of time_iTo obtain an interpolation interval [ t ]_i,t_i+1]Since the data in the read channel sample values are synchronized when the time stamp is read from the buffer, Y (t) is obtained at the same time_i) And Y (t)_i+1) At the moment, interpolation data is obtained by calculation of a formula (1) for the selected channel, interpolation under one synchronous pulse is completed, then a new pulse is waited, interpolation time is recalculated, and new interpolation is started.

Example 2

The invention also provides a digital sampling data high-speed interpolation synchronization system, which comprises:

the message analysis and storage module is used for receiving the SV message and extracting the sampling value information and the time mark information of each channel in the SV message;

parallelly caching the sampling value information and the time scale information of each channel;

the interpolation module is used for calculating the time needing interpolation based on the time management module and the SV message time delay information;

synchronously reading the information of the sampling values of all channels according to the interpolation time;

and calculating interpolation according to the interpolation time and the sampling value information.

Example 3

The invention also provides a digital sampling data high-speed interpolation synchronization system, which comprises a memory and a processor;

the memory is to store instructions;

the processor is configured to operate in accordance with the instructions to perform the steps of the method according to any one of the first aspect.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.