阅读说明：本技术 半导体检测器及其制造方法 (Semiconductor detector and method for manufacturing the same ) 是由 朴泽一幸 竹崎泰一 于 2021-03-17 设计创作，主要内容包括：本发明提供能够提高半导体检测器的性能的技术。在半导体检测器中,将在以倒装芯片的方式连接后的半导体芯片(CHP1)与半导体芯片(CHP2)之间的间隙填充底部填充物(40)作为前提,在读取电极焊盘(PD1)与栅极端子(20)的经由凸块电极(BMP1)的连接构造的周围不形成底部填充物(40)。(The invention provides a technique capable of improving the performance of a semiconductor detector. In a semiconductor detector, on the premise that an underfill (40) is filled in a gap between a flip-chip-connected semiconductor chip (CHP1) and a semiconductor chip (CHP2), the underfill (40) is not formed around a connection structure of a read electrode pad (PD1) and a gate terminal (20) via a bump electrode (BMP 1).)

1. A semiconductor detector for moving charge carriers generated by injecting an electromagnetic wave into a depletion layer to which a drift electric field is applied to a reading electrode in the drift electric field to collect an amount of charge, and measuring energy of the electromagnetic wave based on the amount of charge, the semiconductor detector comprising:

a first semiconductor chip on which the read electrode and a read electrode pad electrically connected to the read electrode are formed; and

a second semiconductor chip having an amplifier electrically connected to the read electrode pad and flip-chip connected to the first semiconductor chip,

an underfill is filled between the first semiconductor chip and the second semiconductor chip except for a first connection portion where the read electrode pad is connected to the amplifier.

2. The semiconductor detector of claim 1,

the first connection portion is surrounded by a void having a dielectric constant lower than that of the underfill.

3. The semiconductor detector of claim 1,

the amplifier comprises a field effect transistor having a gate electrode,

the second semiconductor chip has a gate terminal electrically connected to the gate electrode,

the first connection portion is constituted by a first connection structure of the read electrode pad and the gate terminal via a bump electrode.

4. The semiconductor detector of claim 3,

the first semiconductor chip is provided with a first guide portion for suppressing the first connection structure from being surrounded by the underfill.

5. The semiconductor detector of claim 4,

the first guide portion is composed of a pad portion and a protrusion portion formed on the pad portion.

6. The semiconductor detector of claim 5,

the protrusion is made of the same material as the bump electrode.

7. The semiconductor detector of claim 4,

the first guide portion is made of an insulating material.

8. The semiconductor detector of claim 1,

the second semiconductor chip has an output terminal for outputting the amplified signal amplified by the amplifier,

the first semiconductor chip has an output electrode pad electrically connected to the output terminal,

the underfill is filled between the first semiconductor chip and the second semiconductor chip except for a first connection portion where the read electrode pad is connected to the amplifier and a second connection portion where the output electrode pad is connected to the output terminal.

9. The semiconductor detector of claim 8,

the second connection portion is also surrounded by a void having a dielectric constant lower than that of the underfill.

10. The semiconductor detector of claim 8,

the second connection portion is constituted by a second connection structure of the output electrode pad and the output terminal via a bump electrode.

11. The semiconductor detector of claim 10,

the first semiconductor chip is provided with a second guide portion for suppressing the second connection structure from being surrounded by the underfill.

12. The semiconductor detector of claim 1,

the first semiconductor chip constitutes a silicon drift detector.

13. The semiconductor detector of claim 1,

the electromagnetic wave is an X-ray.

14. The semiconductor detector of claim 1,

the above-mentioned reading electrode is an anode electrode,

the charge carrier is an electron.

15. A method of manufacturing a semiconductor detector, wherein charge carriers generated by injecting an electromagnetic wave into a depletion layer to which a drift electric field is applied are moved to a reading electrode in the drift electric field to collect an amount of electric charge, the energy of the electromagnetic wave is measured based on the amount of electric charge,

the method for manufacturing a semiconductor detector is characterized by comprising the following steps:

(a) preparing a first semiconductor chip having the read electrode and a read electrode pad electrically connected to the read electrode formed thereon;

(b) preparing a second semiconductor chip having an amplifier;

(c) a step of connecting the first semiconductor chip and the second semiconductor chip in a flip chip manner so that the reading electrode pad is electrically connected to the amplifier; and

(d) and a step of filling an underfill material between the first semiconductor chip and the second semiconductor chip, except for a first connection portion where the read electrode pad is connected to the amplifier.

Technical Field

The present invention relates to a semiconductor detector and a manufacturing technique thereof, and for example, relates to a technique that is applied and effective in the following semiconductor detector and a manufacturing technique thereof: charge carriers generated by injecting an electromagnetic wave into a depletion layer to which a drift electric field is applied are moved to a reading electrode in the drift electric field to collect an electric charge amount, and the energy of the electromagnetic wave is measured based on the electric charge amount.

Background

Silicon drift detectors are widely used in X-ray fluorescence analyzers because they have high energy resolution even at low energy, and because peltier elements can be used instead of liquid nitrogen for cooling. In this silicon drift detector, charge carriers generated by the electromagnetic wave incident on the depletion layer are moved to the reading electrode in the drift electric field in a state where the depletion layer is expanded to the entire semiconductor substrate by applying a reverse bias voltage to the pn junction formed on the semiconductor substrate. Then, in the silicon drift detector, the energy of the electromagnetic wave is measured based on the amount of charge collected at the reading electrode.

In this silicon drift detector, since the size of the reading electrode is very small, there is an advantage that the electrostatic capacitance (parasitic capacitance) of the reading electrode is small. Therefore, the silicon drift detector can measure electromagnetic waves with low energy as a result of reducing noise due to parasitic capacitance, and can be used for measuring X-ray fluorescence, for example.

For example, japanese patent application laid-open No. 2019-190934 (patent document 1) describes a technique relating to a silicon drift detector.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2019-190934

Disclosure of Invention

Problems to be solved by the invention

The signal based on the amount of charge collected at the read electrode of the silicon drift detector is weak. Therefore, an amplifier is electrically connected to the read electrode, and an amplified signal is generated by the amplifier from a signal based on the amount of charge collected at the read electrode. Then, the energy of the electromagnetic wave is measured based on the generated amplified signal.

Here, the silicon drift detector including the reading electrode is formed on a first semiconductor chip, and the amplifier is formed on a second semiconductor chip independent from the first semiconductor chip. The read electrode formed on the first semiconductor chip and the amplifier formed on the second semiconductor chip are electrically connected to each other, for example, by a metal wire.

However, when the read electrode is connected to the metal line for the amplifier, the metal line inevitably includes a parasitic capacitance and a parasitic inductance. Thus, noise caused by parasitic capacitance and parasitic inductance overlaps with the signal output from the read electrode. In particular, since a signal based on the amount of charge collected in the reading electrode is weak, even a small noise has a large adverse effect. Therefore, from the viewpoint of improving the measurement sensitivity of electromagnetic wave energy of a semiconductor detector including a silicon drift detector and an amplifier, an electrical connection structure between a reading electrode and an amplifier that can suppress parasitic capacitance and parasitic inductance is desired.

The purpose of the present invention is to provide a technique capable of improving the performance of a semiconductor detector.

Other objects and novel features will become apparent from the description of the specification and the drawings.

Means for solving the problems

In the semiconductor detector according to one embodiment, charge carriers generated by injecting an electromagnetic wave into a depletion layer to which a drift electric field is applied are moved to a reading electrode in the drift electric field to collect an amount of electric charge, and the energy of the electromagnetic wave is measured based on the amount of electric charge.

Here, the semiconductor detector includes: a first semiconductor chip formed with a read electrode and a read electrode pad electrically connected to the read electrode; and a second semiconductor chip having an amplifier electrically connected to the read electrode pad and flip-chip connected to the first semiconductor chip. At this time, an underfill is filled between the first semiconductor chip and the second semiconductor chip except for the first connection portion where the read electrode pad is connected to the amplifier.

In one embodiment, a method for manufacturing a semiconductor detector includes the steps of: preparing a first semiconductor chip having a read electrode and a read electrode pad electrically connected to the read electrode formed thereon; preparing a second semiconductor chip having an amplifier; a step of connecting the first semiconductor chip and the second semiconductor chip in a flip chip manner in a manner that the reading electrode pad is electrically connected with the amplifier; and a process of filling an underfill between the first semiconductor chip and the second semiconductor chip except for the first connection portion where the reading electrode pad is connected to the amplifier.

The effects of the invention are as follows.

According to one embodiment, the performance of a semiconductor detector can be improved.

Drawings

Fig. 1 is a diagram showing a schematic structure of a semiconductor detector.

Fig. 2 is a plan view showing a mounting structure of a semiconductor detector in the first related art.

Fig. 3 is a sectional view showing a mounting structure of a semiconductor detector in the first related art.

Fig. 4 is a plan view showing a mounting structure of a semiconductor detector in a second related art.

Fig. 5 is a sectional view showing a mounting structure of a semiconductor detector in a second related art.

Fig. 6 is an enlarged view showing a connection structure of the first semiconductor chip and the second semiconductor chip.

Fig. 7 is a diagram for explaining the basic idea of embodiment 1.

Fig. 8 is a diagram illustrating ideas derived from basic ideas.

Fig. 9 is a plan view showing the structure of the first semiconductor chip.

Fig. 10 is a cross-sectional view showing a flip-chip configuration after the first semiconductor chip and the second semiconductor chip are connected.

Fig. 11 is a plan view showing the structure of the first semiconductor chip.

Fig. 12 is a cross-sectional view showing a flip-chip configuration after the first semiconductor chip and the second semiconductor chip are connected.

Fig. 13 is a plan view showing the structure of the first semiconductor chip.

Fig. 14 is a cross-sectional view showing a flip-chip configuration after the first semiconductor chip and the second semiconductor chip are connected.

Fig. 15 is a sectional view showing the structure of a semiconductor detector in embodiment 2.

Fig. 16 is a diagram for explaining the verification result.

Description of the symbols

10-silicon drift detector, 11-p-type semiconductor region, 12-read electrode, 15-amplifier, 20-gate terminal, 30-output terminal, 40-underfill, 50-adhesive, 60-adhesive, 100-semiconductor detector, 200-semiconductor detector, 300-semiconductor detector, 400-semiconductor detector, BC-back contact surface, BMP-bump electrode, BMP 1-bump electrode, BMP 2-bump electrode, BMP 3-bump, BMP 4-bump, CHP 1-semiconductor chip, CHP 2-semiconductor chip, GD 1-guide, GD 2-guide, GD 3-guide, OP 1-opening, PD-electrode pad, PD 1-read electrode pad, PD 2-output electrode pad, PD 3-pad, PD 4-pad, R1-internal electrode, RX-external electrode, SUB-semiconductor substrate, W-metal line, WB-wiring substrate.

Detailed Description

In all the drawings for explaining the embodiments, the same components are denoted by the same reference numerals in principle, and redundant explanations thereof are omitted. In addition, in order to easily understand the drawings, hatching may be added to the plan view.

(embodiment mode 1)

< Structure of semiconductor detector >

Fig. 1 is a diagram showing a schematic structure of a semiconductor detector.

In fig. 1, a semiconductor detector 100 includes a silicon drift detector 10 and an amplifier (power amplifier) 15 electrically connected to the silicon drift detector 10.

The silicon drift detector 10 has a semiconductor substrate SUB made of silicon to which n-type impurities (donors) are added, for example. The semiconductor substrate SUB, which is a constituent element of the silicon drift detector 10, has a front surface and a back surface, the front surface of the semiconductor substrate SUB being referred to as a "window surface", and the back surface of the semiconductor substrate SUB being referred to as a "ring surface".

As shown in fig. 1, a p-type semiconductor region 11 electrically connected to the back contact surface BC is formed on the front surface side of the semiconductor substrate SUB. Thereby, a pn junction is formed by the semiconductor substrate SUB to which the n-type impurity is added and the p-type semiconductor region 11. Then, by adjusting the voltage applied to the back contact BC, a reverse bias is applied to the pn junction. As a result, the depletion layer extends from the pn junction, and the semiconductor substrate SUB is depleted.

Next, as shown in fig. 1, n is formed at the center of the back surface of the semiconductor substrate SUB⁺And a read electrode 12 formed of a semiconductor region. For example, the reading electrode 12 functions as an anode electrode. A plurality of ring electrodes are formed so as to concentrically surround the read electrode 12. In particular, the ring electrode includes an inner electrode R1 formed at an inner periphery and an outer electrode RX formed at an outer periphery. Here, different voltages are applied to the inner electrode R1 and the outer electrode RX. Thereby, a drift electric field is applied to the semiconductor substrate SUB having the depleted depletion layer.

Next, as shown in fig. 1, the reading electrode 12 is electrically connected to an amplifier 15. In the amplifier 15, for example, a field effect transistor having a gate electrode, a source, and a drain is formed, and the gate electrode of the field effect transistor is electrically connected to the reading electrode 12.

< operation of semiconductor Detector >

Next, the operation of the semiconductor detector 100 will be explained.

First, when X-rays (electromagnetic waves) are incident from the "window surface" side of the silicon drift detector 10 into the semiconductor substrate SUB, X-rays are incident on the depletion layer existing on the depleted semiconductor substrate SUB. Thus, the depletion layer absorbs X-rays to form electron-hole pairs. That is, since the energy of the X-ray is larger than the band gap of silicon constituting the semiconductor substrate SUB, the energy of the X-ray is used as energy for exciting an electron existing in the valence band of silicon to the conduction band of silicon. As a result, a plurality of electrons are excited into the conduction band in accordance with the energy of the X-ray. That is, the larger the energy of the X-ray, the larger the amount of electrons (charge amount) excited to the conduction band. At this time, in the silicon drift detector 10, since a potential difference is applied between the inner electrode R1 and the outer electrode RX, electrons generated in the depletion layer move toward the read electrode 12 due to a drift electric field generated by the potential difference. Thereby, electrons are accumulated at the reading electrode 12. Here, the reading electrode 12 is an anode electrode, and electrons are assumed as charge carriers collected at the reading electrode 12. Then, a weak signal generated by the electrons collected in the reading electrode 12 is amplified by an amplifier 15 electrically connected to the reading electrode 12, and the amplified signal is output from the semiconductor detector 100.

Then, the energy of the X-ray is measured based on the amplified signal output from the semiconductor detector 100. For example, since the magnitude of the amplification signal is proportional to the charge amount of electrons and the amount of charge collected in the reading electrode 12 differs depending on the energy of the X-ray, the energy of the incident X-ray can be measured by analyzing the amplification signal proportional to the charge amount of electrons.

< description of the first related art >

The semiconductor detector 100 described above is mounted.

First, a first related art relating to a mounting structure of a semiconductor detector will be described below.

Here, the "related art" described in the present specification is not a known art, but a technology which has a problem found by the inventors and is a technology which is a premise of the invention of the present application.

Fig. 2 is a plan view schematically showing a mounting structure of a semiconductor detector in the first related art.

In fig. 2, a semiconductor detector 200 has a wiring substrate WB on which a plurality of wirings are formed. Here, fig. 2 is a plan view of the wiring substrate WB viewed from the lower surface side. A semiconductor chip CHP1 on which the silicon drift detector 10 is formed is mounted on the upper surface of the wiring substrate WB, and a semiconductor chip CHP2 is mounted on the lower surface of the wiring substrate WB. In fig. 2, the back surface ("loop surface") of the semiconductor chip CHP1 mounted on the upper surface side of the wiring substrate WB is visible from the opening OP1 formed in the wiring substrate WB.

The silicon drift detector 10 formed on the semiconductor chip CHP1 has a read electrode 12. On the other hand, an amplifier is formed in the semiconductor chip CHP 2. The amplifier includes, for example, a field effect transistor having a gate electrode, a source, and a drain, and the semiconductor chip CHP2 has a gate terminal 20 electrically connected to the gate electrode and an output terminal 30 for outputting an output signal generated by the amplifier. As shown in fig. 2, the read electrode 12 of the silicon drift detector 10 and the gate terminal 20 formed on the semiconductor chip CHP2 are electrically connected by a metal wire W. The semiconductor chip CHP2 also has a DC power supply terminal, a reset pulse terminal, and the like.

Fig. 3 is a sectional view schematically showing a mounting structure of a semiconductor detector in the first related art.

As shown in fig. 3, a semiconductor chip CHP1 on which the silicon drift detector 10 is formed is mounted on the upper surface of the wiring substrate. On the other hand, a semiconductor chip CHP2 on which an amplifier is formed is mounted on the lower surface of the wiring board WB. In the first related art, for example, the read electrode 12 formed on the semiconductor chip CHP1 and the gate terminal 20 formed on the semiconductor chip CHP2 are electrically connected by the wire W.

< room for improvement in the first related art >

However, when the read electrode 12 and the gate terminal 20 are electrically connected by the metal line W, the metal line W inevitably includes parasitic capacitance and parasitic inductance. Thus, noise caused by parasitic capacitance and parasitic inductance overlaps with the signal output from the read electrode 12. In particular, since a signal based on the amount of charge collected in the reading electrode 12 is weak, even a small noise has a large adverse effect. Therefore, from the viewpoint of improving the measurement sensitivity of the X-ray energy of the semiconductor detector 200 including the silicon drift detector 10 and the amplifier, an electrical connection structure between the reading electrode 12 and the gate terminal 20 that can suppress parasitic capacitance and parasitic inductance is desired.

< description of the second related art >

In this regard, there is a second related art shown below.

Fig. 4 is a plan view schematically showing a mounting structure of a semiconductor detector in the second related art.

In fig. 4, a semiconductor detector 300 has a wiring substrate WB on which a plurality of wirings are formed. Here, fig. 4 is a plan view seen from the lower surface side of the wiring substrate WB. A semiconductor chip CHP1 on which the silicon drift detector 10 is formed is mounted on the upper surface side of the wiring substrate WB. In fig. 4, the back surface ("loop surface") of the semiconductor chip CHP1 mounted on the upper surface side of the wiring substrate WB is visible from the opening OP1 formed in the wiring substrate WB.

In fig. 4, the semiconductor chip CHP2 is arranged to overlap the semiconductor chip CHP1 in plan view. Specifically, an interlayer insulating layer (not shown) is formed so as to cover the "ring-shaped surface" of the semiconductor chip CHP1, and a plurality of pads PD are formed on the interlayer insulating layer. The semiconductor chip CHP2 is disposed so as to overlap the pad layer on which the plurality of pads PD are formed in a planar manner. In this way, in the semiconductor detector 300 according to the second related art, the semiconductor chip CHP1 and the semiconductor chip CHP2 are stacked so as to overlap each other in a plane.

Fig. 5 is a sectional view schematically showing a mounting structure of a semiconductor detector in the second related art.

As shown in fig. 5, a semiconductor chip CHP1 on which the silicon drift detector 10 is formed is mounted on the upper surface of the wiring substrate WB. Further, on the lower surface of the semiconductor chip CHP1, the semiconductor chip CHP2 formed with an amplifier is disposed so as to overlap the semiconductor chip CHP1 in plan view. That is, in the second related art, the semiconductor chip CHP1 and the semiconductor chip CHP2 are connected in a flip-chip manner. Specifically, as shown in fig. 5, the read electrode pad PD1 formed on the semiconductor chip CHP1 and the gate terminal 20 formed on the semiconductor chip CHP2 are electrically connected via a bump electrode (bump electrode) BMP 1. Similarly, the output electrode pad PD2 formed in the semiconductor chip CHP1 and the output terminal 30 formed in the semiconductor chip CHP2 are electrically connected via the bump electrode BMP 2.

According to the semiconductor detector 300 in the second related art configured as such, the read electrode pad PD1 formed on the semiconductor chip CHP1 and the gate terminal 20 formed on the semiconductor chip CHP2 are electrically connected through the bump electrode BMP1 instead of the metal wire W. Therefore, an increase in noise due to parasitic capacitance and parasitic inductance caused by the metal wire W can be suppressed. That is, according to the second related art, the electrical connection configuration of the semiconductor chip CHP1 and the semiconductor chip CHP2 employs a flip-chip connection configuration instead of a metal wire connection configuration, whereby parasitic capacitance and parasitic inductance can be reduced.

< room for improvement in the second related art >

In this way, in the second related art, since the metal line W is not used for connection of the read electrode 12 and the gate terminal 20, it is considered that parasitic capacitance and parasitic inductance caused by the metal line W can be reduced. However, according to the study of the inventors, it was newly found that: even in the flip-chip connection structure, from the viewpoint of suppressing the generation of noise due to the connection structure of the read electrode pad PD1 and the gate terminal 20, it is not sufficient and improvement is required, and therefore, the following description will be made of the room for improvement of the second related art.

Fig. 6 is an enlarged view schematically showing a connection configuration of the semiconductor chip CHP1 and the semiconductor chip CHP 2. In fig. 6, the read electrode pad PD1 and the gate terminal 20 are electrically connected by a bump electrode BMP1, and the output electrode pad PD2 and the output terminal 30 are electrically connected by a bump electrode BMP 2. Thus, the semiconductor chip CHP1 and the semiconductor chip CHP2 are flip-chip connected. Here, as shown in fig. 6, the underfill 40 made of, for example, an insulating resin is filled in the gap between the flip-chip connected semiconductor chip CHP1 and the semiconductor chip CHP 2. This is to improve the connection strength of the semiconductor chip CHP1 and the semiconductor chip CHP 2.

However, the underfill 40 is made of an insulating resin, and the dielectric constant is high. Due to this situation, the inventors newly found that: if underfill 40 is filled so as to cover the periphery of the connection structure between read electrode pad PD1 and gate terminal 20 via bump electrode BMP1, the parasitic capacitance due to underfill 40 cannot be ignored, and this causes an increase in noise. That is, in the flip chip connection structure, although the parasitic capacitance and parasitic inductance due to the metal wire W can be reduced, it is difficult to suppress noise due to the parasitic capacitance due to the underfill 40 that is indispensable to the flip chip connection structure. This is a room for improvement in the second related art.

Therefore, in embodiment 1, the room for improvement of the second related art has been studied. The technical idea of the present embodiment 1 thus studied will be explained below.

< basic idea of embodiment 1 >

Fig. 7 is a diagram illustrating a basic idea of embodiment 1.

In fig. 7, the basic idea of embodiment 1 is to assume that the underfill 40 is filled in the gap between the semiconductor chip CHP1 and the semiconductor chip CHP2 after flip-chip connection, and the underfill 40 is not formed around the connection structure between the read electrode pad PD1 and the gate terminal 20 via the bump electrode BMP 1. In other words, the basic idea of embodiment 1 is an idea of filling the underfill 40 in the gap between the flip-chip connected semiconductor chip CHP1 and the semiconductor chip CHP2, except for the periphery of the connection structure of the read electrode pad PD1 and the gate terminal 20 via the bump electrode BMP 1. According to the basic idea of embodiment 1, the underfill 40 can secure the connection strength between the semiconductor chip CHP1 and the semiconductor chip CHP2 after the flip-chip connection, and on the other hand, since the underfill 40 is not present around the connection structure of the read electrode pad PD1 and the gate terminal 20 via the bump electrode BMP1, the increase in the parasitic capacitance due to the underfill 40 can be suppressed.

That is, according to embodiment 1, by making the periphery of the connection structure between read electrode pad PD1 and gate terminal 20 via bump electrode BMP1 vacuum with a low dielectric constant, it is possible to suppress an increase in parasitic capacitance due to underfill 40 with a high dielectric constant. As a result, according to embodiment 1, an increase in noise due to parasitic capacitance can be suppressed, and thus the measurement sensitivity of the semiconductor detector for X-ray energy can be improved.

Fig. 8 is a diagram illustrating ideas derived from the basic ideas.

As shown in fig. 8, the idea derived from the basic idea is the following idea: the underfill 40 is not present not only around the connection structure of the read electrode pad PD1 and the gate terminal 20 via the bump electrode BMP1, but also around the connection structure of the output electrode pad PD2 and the output terminal 30 via the bump electrode BMP 2.

According to this idea, it is possible to suppress not only the noise due to the parasitic capacitance from overlapping with a weak signal output from the read electrode pad PD1 but also the noise due to the parasitic capacitance from overlapping with an amplified signal amplified by an amplifier formed in the semiconductor chip CHP2 and output from the output terminal 30. Thus, the measurement sensitivity of the X-ray energy can be further improved based on the idea derived from the basic idea.

The basic idea of embodiment 1 can be realized as follows, for example.

First, a semiconductor chip CHP1 formed with the read electrode 12 and the read electrode pad PD1 electrically connected to the read electrode 12 is prepared, and a semiconductor chip CHP2 having an amplifier is prepared. Next, the semiconductor chip CHP1 and the semiconductor chip CHP2 are flip-chip connected in such a manner that the read electrode pad PD1 is electrically connected to the amplifier. Thereafter, the underfill 40 is filled between the semiconductor chip CHP1 and the semiconductor chip CHP2 except for the first connection portion where the read electrode pad PD1 is connected to the amplifier. Thus, the basic idea is realized that the underfill 40 is not formed around the first connection portion where the read electrode pad PD1 is connected to the amplifier.

Hereinafter, a specific study scheme for filling the underfill 40 between the semiconductor chip CHP1 and the semiconductor chip CHP2, except for the first connection portion where the read electrode pad PD1 is connected to the amplifier, will be described based on a plurality of specific schemes.

< embodiment 1 >

Next, a specific embodiment will be described which embodies the basic idea of embodiment 1 described above.

Fig. 9 is a plan view showing a schematic structure of the semiconductor chip CHP 1.

In fig. 9, a plurality of ring electrodes arranged concentrically are formed on the "ring surface" of the semiconductor chip CHP1 on which the silicon drift detector 10 is formed, and a plurality of pad electrodes PD are arranged on the upper layer of the layer on which the plurality of ring electrodes are formed. Further, the bump electrode BMP is mounted on each of the plurality of pad electrodes PD. Specifically, one of the plurality of pad electrodes PD is a read electrode pad PD1 electrically connected to the read electrode, and a bump electrode BMP1 is mounted on the read electrode pad PD 1. Further, another of the plurality of pad electrodes PD is an output electrode pad PD2, and a bump electrode BMP2 is mounted on the output electrode pad PD 2.

As shown in fig. 9, the semiconductor chip CHP1 is provided with a guide portion GD 1. The guide portion GD1 is composed of a pad portion PD3 and a protrusion portion BMP3 formed on the pad portion PD 3. At this time, the pad portion PD3 is formed on the pad layer where the plurality of pad electrodes PD are formed. Further, the projection BMP3 is made of the same material as the bump electrode BMP.

Next, fig. 10 is a sectional view schematically showing the flip chip configuration after the semiconductor chip CHP1 and the semiconductor chip CHP2 are connected.

In fig. 10, the read electrode pad PD1 formed in the semiconductor chip CHP1 is connected to the gate terminal 20 formed in the semiconductor chip CHP2 by the bump electrode BMP 1. Here, the connection structure of the read electrode pad PD1 and the gate terminal 20 via the bump electrode BMP1 is referred to as a "first connection structure".

In fig. 10, the output electrode pad PD2 formed in the semiconductor chip CHP1 is connected to the output terminal 30 formed in the semiconductor chip CHP2 by the bump electrode BMP 2. Here, the connection structure of the output electrode pad PD2 and the output terminal 30 via the bump electrode BMP2 is referred to as a "second connection structure".

In this way, flip-chip connection of the semiconductor chip CHP1 and the semiconductor chip CHP2 is achieved by the "first connection configuration" and the "second connection configuration". In embodiment 1, as shown in fig. 10, a guide portion GD1 is provided between the "first connection structure" and the "second connection structure". The guide portion GD1 is composed of a pad portion PD3 and a protrusion portion BMP 3. Further, by providing the guide portion GD1 between the semiconductor chip CHP1 and the semiconductor chip CHP2, the "first connection structure" can be suppressed from being surrounded by the underfill 40. That is, the guide portion GD1 is provided to suppress the "first connection structure" from being surrounded by the underfill 40. As a result, the "first connection structure" is surrounded by the void having a lower dielectric constant than the dielectric constant of the underfill 40.

From the above, the following basic ideas are embodied in embodiment 1: by providing the guide portion GD1 composed of the pad portion PD3 and the protrusion portion BMP3 between the "first connection structure" and the "second connection structure", the underfill 40 is not formed around the "first connection structure".

For example, the structure of embodiment 1 is implemented as follows.

First, a semiconductor chip CHP1 is prepared, in which a read electrode, a read electrode pad PD1 electrically connected to the read electrode, an output electrode pad PD2, and a pad portion PD3 are formed in the semiconductor chip CHP 1. Next, a semiconductor chip CHP2 is prepared, and an amplifier formed of, for example, a field effect transistor having a gate electrode, a source, and a drain is formed on the semiconductor chip CHP 2. At this time, the semiconductor chip CHP2 has the gate terminal 20 electrically connected to the gate electrode.

Next, the bump electrode BMP1 is disposed on the read electrode pad PD1, the bump electrode BMP2 is disposed on the output electrode pad PD2, and the bump BMP3 is disposed on the pad PD 3. Then, the semiconductor chip CHP1 and the semiconductor chip CHP2 are flip-chip connected in such a manner that the read electrode pad PD1 is connected to the gate terminal 20 via the bump electrode BMP1, and the output electrode pad PD2 is connected to the output terminal 30 via the bump electrode BMP 2. Thereby, the "first connection structure" and the "second connection structure" are formed between the semiconductor chip CHP1 and the semiconductor chip CHP2, and the guide portion GD1 composed of the pad portion PD3 and the bump portion BMP3 is formed.

Thereafter, the underfill 40 is filled between the semiconductor chip CHP1 and the semiconductor chip CHP 2. Here, the underfill 40 is injected between the semiconductor chip CHP1 and the semiconductor chip CHP2 from the direction of the arrow in fig. 10. In this case, the underfill 40 injected between the semiconductor chip CHP1 and the semiconductor chip CHP2 is intercepted by the guide portion GD1 so as not to reach the periphery of the "first connection configuration". Thereby, the structure of embodiment 1 can be realized.

< embodiment 2 >

The above-described embodiment 1 is an example in which the guide portion GD1 including the projection BMP3 is provided, and the projection BMP3 is made of the same conductive material as the bump electrode BMP. In contrast, embodiment 2 is an example in which the guide portion GD2 made of an insulating material typified by, for example, a resist material is provided.

Fig. 11 is a plan view showing a schematic structure of the semiconductor chip CHP 1. In fig. 11, a guide portion GD2 made of an insulating material such as a resist material is provided, and the configuration is the same as that of embodiment 1 except for this.

Fig. 12 is a sectional view schematically showing the flip chip configuration after the semiconductor chip CHP1 and the semiconductor chip CHP2 are connected.

In embodiment 2, as shown in fig. 12, a guide portion GD2 is provided between the "first connection structure" and the "second connection structure". The guide portion GD2 is made of an insulating material such as a resist material. In addition, in embodiment 2, the "first connection structure" can be suppressed from being surrounded by the underfill 40 by providing the guide portion GD2 between the semiconductor chip CHP1 and the semiconductor chip CHP 2. As a result, the "first connection structure" is surrounded by the void having a lower dielectric constant than the dielectric constant of the underfill 40.

From the above, the following basic ideas are embodied in the embodiment 2: by providing the guide portion GD2 made of an insulating material between the "first connection structure" and the "second connection structure", the underfill 40 is not formed around the "first connection structure".

For example, the structure of embodiment 2 is implemented as follows.

First, a semiconductor chip CHP1 is prepared, in which a read electrode, a read electrode pad PD1 electrically connected to the read electrode, an output electrode pad PD2, and a guide portion GD2 made of a resist material (resist film) are formed on the semiconductor chip CHP 1. At this time, for example, after a resist material is applied, a pattern is formed by using a photolithography technique, whereby the guide portion GD2 formed of a resist film can be formed.

Next, a semiconductor chip CHP2 is prepared, and an amplifier formed of, for example, a field effect transistor having a gate electrode, a source, and a drain is formed on the semiconductor chip CHP 2. At this time, the semiconductor chip CHP2 has the gate terminal 20 electrically connected to the gate electrode.

Next, the bump electrode BMP1 is disposed on the read electrode pad PD1, the bump electrode BMP2 is disposed on the output electrode pad PD2, and the bump BMP3 is disposed on the pad PD 3. Then, the semiconductor chip CHP1 and the semiconductor chip CHP2 are flip-chip connected in such a manner that the read electrode pad PD1 is connected to the gate terminal 20 via the bump electrode BMP1, and the output electrode pad PD2 is connected to the output terminal 30 via the bump electrode BMP 2. Thereby, the "first connection structure" and the "second connection structure" are formed between the semiconductor chip CHP1 and the semiconductor chip CHP2, and the guide portion GD2 made of a resist material is formed.

Thereafter, the underfill 40 is filled between the semiconductor chip CHP1 and the semiconductor chip CHP 2. Here, the underfill 40 is injected between the semiconductor chip CHP1 and the semiconductor chip CHP2 from the direction of the arrow in fig. 12. In this case, the underfill 40 injected between the semiconductor chip CHP1 and the semiconductor chip CHP2 is intercepted by the guide portion GD2 so as not to reach the periphery of the "first connection configuration". This enables the structure of embodiment 2 to be realized.

< embodiment 3 >

The above-described embodiments 1 and 2 are examples in which the guide portions GD1 (guide portions GD2) are provided so that the underfill 40 is not formed around the "first connection structure". In contrast, embodiment 3 is an example in which the guide portions GD1 are provided not only to form no underfill 40 around the "first connection structure", but also the guide portions GD3 are provided to form no underfill 40 also around the "second connection structure".

Fig. 13 is a plan view showing a schematic structure of the semiconductor chip CHP 1. In fig. 13, for example, the configuration is the same as that of embodiment 1 except that not only the guide portion GD1 but also the guide portion GD3 is provided.

Fig. 14 is a sectional view schematically showing the flip chip configuration after the semiconductor chip CHP1 and the semiconductor chip CHP2 are connected.

In embodiment 3, as shown in fig. 14, not only the guide portion GD1 but also the guide portion GD3 is provided between the "first connection structure" and the "second connection structure". The guide portion GD3 is composed of a pad portion PD4 and a protrusion portion BMP 4. In embodiment 3, the presence of the guide portions GD1 and GD3 between the semiconductor chip CHP1 and the semiconductor chip CHP2 can prevent both the "first connection structure" and the "second connection structure" from being surrounded by the underfill 40. As a result, each of the "first connection structure" and the "second connection structure" is surrounded by a void having a dielectric constant lower than that of the underfill 40.

From the above, the following basic idea is embodied in embodiment 3: by providing the guide portions GD1 and GD3 between the "first connection structure" and the "second connection structure", the underfill 40 is not formed around the "first connection structure", and a structure is realized in which the underfill 40 is not formed also around the "second connection structure".

For example, the structure of embodiment 3 is implemented as follows.

First, a semiconductor chip CHP1 is prepared, the semiconductor chip CHP1 being formed with a read electrode, a read electrode pad PD1 electrically connected to the read electrode, an output electrode pad PD2, a pad portion PD3, and a pad portion PD 4.

Next, a semiconductor chip CHP2 is prepared, and an amplifier formed of, for example, a field effect transistor having a gate electrode, a source, and a drain is formed on the semiconductor chip CHP 2. At this time, the semiconductor chip CHP2 has a gate terminal 20 electrically connected to the gate electrode and an output terminal 30 outputting an amplified signal.

Next, the bump electrode BMP1 is disposed on the read electrode pad PD1, the bump electrode BMP2 is disposed on the output electrode pad PD2, the protrusion BMP3 is disposed on the pad PD3, and the protrusion BMP4 is disposed on the pad PD 4.

Then, the semiconductor chip CHP1 and the semiconductor chip CHP2 are flip-chip connected in such a manner that the read electrode pad PD1 is connected to the gate terminal 20 via the bump electrode BMP1, and the output electrode pad PD2 is connected to the output terminal 30 via the bump electrode BMP 2. Thereby, the "first connection configuration" and the "second connection configuration" are formed between the semiconductor chip CHP1 and the semiconductor chip CHP 2. Further, a guide portion GD1 including a pad portion PD3 and a bump portion BMP3, and a guide portion GD3 including a pad portion PD4 and a bump portion BMP4 are formed between the semiconductor chip CHP1 and the semiconductor chip CHP 2.

Thereafter, the underfill 40 is filled between the semiconductor chip CHP1 and the semiconductor chip CHP 2. At this time, the underfill 40 injected between the semiconductor chip CHP1 and the semiconductor chip CHP2 is intercepted by the guide portion GD1 so as not to reach the periphery of the "first connection configuration", and is intercepted by the guide portion GD3 so as not to reach the periphery of the "second connection configuration". This enables the structure of embodiment 3 to be realized.

< feature of embodiment 1 >

Next, the characteristic points of embodiment 1 will be explained.

In order to embody the basic idea described above, embodiment 1 is characterized in that the guide portion GD1 is formed between the "first connection structure" and the "second connection structure" to suppress the "first connection structure" from being covered with the underfill 40. Thereby, the underfill 40 injected between the semiconductor chip CHP1 and the semiconductor chip CHP2 is intercepted by the guide portion GD1 before reaching the "first connection configuration". As a result, the "first connection structure" is surrounded by the void having a lower dielectric constant than the dielectric constant of the underfill 40 without being covered with the underfill 40. Thus, according to embodiment 1, an increase in parasitic capacitance due to the underfill 40 can be suppressed. That is, according to embodiment 1, by providing the periphery of the "first connection structure" of read electrode pad PD1 and gate terminal 20 via bump electrode BMP1 with a void having a low dielectric constant, it is possible to suppress an increase in parasitic capacitance due to underfill 40 having a high dielectric constant. Therefore, according to embodiment 1, an increase in noise due to parasitic capacitance can be suppressed, and thus the measurement sensitivity of the semiconductor detector 100 for X-ray energy can be improved.

In particular, the feature of embodiment 1 is of great technical significance to a structure in which the periphery of the "first connection structure" is a void. This is because the semiconductor detector 100 including the silicon drift detector 10 is used under vacuum. That is, in the semiconductor detector 100, making the periphery of the "first connection structure" a void means making the periphery of the "first connection structure" a vacuum, and the dielectric constant of the vacuum is the lowest, so it can be said that the vacuum is preferable from the viewpoint of effectively reducing the parasitic capacitance.

The reason why the semiconductor detector 100 is used under vacuum is as follows. In the semiconductor detector 100, it is necessary to reduce the dark current that causes noise, and the dark current increases as the temperature increases. Thus, the semiconductor detector 100 is cooled using, for example, a peltier element, and reduces dark current which becomes noise. At this time, if the semiconductor detector 100 is used in the air, the semiconductor detector 100 after cooling may cause corrosion of the semiconductor detector 100 or increase in dark current due to dew condensation of moisture in the air. For this reason, the semiconductor detector 100 including the silicon drift detector 10 is used in vacuum.

The feature of embodiment 1 is realized by, for example, the above-described embodiment 1, embodiment 2, and embodiment 3. For example, the following points can be mentioned as advantages of embodiment 1: since the protrusion portion BMP3 of the guide portion GD1 is made of the same conductive material as the bump electrode BMP, it is easy to adjust the height, and it is easy to incorporate the forming process of the guide portion GD1 into the forming process of the "first connection structure".

Further, as advantages of embodiment 2, the following can be mentioned: since the guide portion GD2 is made of an insulating material typified by a resist material, there is no fear of an electrical adverse effect on the "first connection structure" disposed in proximity thereto. Further, the following aspects and the like can be mentioned: the resist is effectively used to simultaneously form a plurality of fine patterns, and the resist does not electrically adversely affect other terminals (output terminal, DC power supply terminal, reset pulse terminal, etc.) other than the "first connection structure".

Further, as advantages of embodiment 3, the following can be mentioned: not only the periphery of the "first connection structure" can be made to have a low dielectric constant by the guide portions GD1, but also the periphery of the "second connection structure" can be made to have a low dielectric constant by the guide portions GD 3. According to embodiment 3, it is possible to reduce noise superimposed on a weak signal output from the read electrode pad PD1, and noise superimposed when an amplified signal obtained by amplifying the weak signal is output from the output terminal 30. Therefore, the measurement sensitivity of the semiconductor detector 100 for the X-ray energy can be further improved.

As an application of embodiment 3, a guide portion may be provided around the DC power supply terminal, the reset pulse terminal, and the like other than the gate terminal 20 and the output terminal 30 of the amplifier (power amplifier) 15 so that no underfill is present. This structure is effective from the viewpoint of further reducing noise superimposed on a weak signal.

(embodiment mode 2)

< basic idea of embodiment 2 >

The basic idea of embodiment 1 described above is to assume that the underfill 40 is filled in the gap between the flip-chip connected semiconductor chip CHP1 and the semiconductor chip CHP2, and the underfill 40 is not formed around the "first connection structure" of the read electrode pad PD1 and the gate terminal 20 via the bump electrode BMP 1.

In contrast, the basic idea of embodiment 2 is to fill the underfill 40 into the gap between the flip-chip connected semiconductor chip CHP1 and the semiconductor chip CHP 2. According to this basic idea, since the underfill 40 having a high dielectric constant is not interposed around the "first connection structure", an increase in parasitic capacitance due to the underfill 40 can be suppressed. As a result, according to embodiment 2, noise superimposed on a weak signal passing through the "first connection structure" can be reduced, and thus the measurement sensitivity of the semiconductor detector 100 for X-ray energy can be improved.

However, in the case where the gap between the semiconductor chip CHP1 and the semiconductor chip CHP2 after flip-chip connection is not filled with the underfill 40, the problem of the connection strength between the semiconductor chip CHP1 and the semiconductor chip CHP2 being reduced becomes apparent. That is, when the basic idea of embodiment 2 is realized, it is necessary to make an investigation to suppress a decrease in the connection strength between the semiconductor chip CHP1 and the semiconductor chip CHP 2.

Therefore, in embodiment 2, in order to suppress an increase in the parasitic capacitance due to the underfill 40, it is considered to suppress a decrease in the connection strength between the semiconductor chip CHP1 and the semiconductor chip CHP2 due to the basic idea that the underfill 40 is not filled in the gap between the semiconductor chip CHP1 and the semiconductor chip CHP2 after flip-chip connection, on the premise that the basic idea is adopted. The technical idea of the present embodiment 2 thus studied will be explained below.

< embodiment 2 >

Fig. 15 is a cross-sectional view showing a schematic structure of a semiconductor detector in embodiment 2.

In fig. 15, the semiconductor detector 400 has a semiconductor chip CHP1 formed with the silicon drift detector 10. A read electrode pad PD1 and an output electrode pad PD2 are formed on the semiconductor chip CHP 1. The semiconductor detector 400 includes a wiring board WB flip-chip connected to the semiconductor chip CHP1 and having an opening OP 2. The wiring board WB and the semiconductor chip CHP1 are connected to each other with an adhesive 50, for example. The semiconductor detector 400 includes an amplifier electrically connected to the read electrode pad PD1 formed in the semiconductor chip CHP1, and a semiconductor chip CHP2 disposed inside the opening OP2 and flip-chip connected to the semiconductor chip CHP 1. An amplifier including a field effect transistor including a gate electrode, a source, and a drain is formed in the semiconductor chip CHP 2. Here, the semiconductor chip CHP2 has a gate terminal 20 electrically connected to the gate electrode and an output terminal 30 outputting an amplified signal amplified by the amplifier.

Further, as shown in fig. 15, the read electrode pad PD1 formed on the semiconductor chip CHP1 and the gate terminal 20 formed on the semiconductor chip CHP2 are connected by the bump electrode BMP1 ("first connection configuration"). On the other hand, as shown in fig. 15, the output electrode pad PD2 formed in the semiconductor chip CHP1 and the output terminal 30 formed in the semiconductor chip CHP2 are connected by the bump electrode BMP2 ("second connection structure").

In this way, flip-chip connection of the semiconductor chip CHP1 and the semiconductor chip CHP2 is achieved by the "first connection configuration" and the "second connection configuration". From the above, in the semiconductor detector 400 of embodiment 2, the wiring substrate WB and the semiconductor chip CHP1 are flip-chip connected, and the semiconductor chip CHP1 and the semiconductor chip CHP2 are also flip-chip connected. However, in embodiment 2, no underfill is present between the semiconductor chip CHP1 and the semiconductor chip CHP2 including the "first connection configuration" of the read electrode pad PD1 and the gate terminal 20 via the bump electrode BMP1 and the "second connection configuration" of the output electrode pad PD2 and the output terminal 30 via the bump electrode BMP 2. Thus, according to embodiment 2, the underfill having a high dielectric constant is not present around the "first connection structure", and thus an increase in parasitic capacitance due to the underfill can be suppressed. As a result, according to embodiment 2, noise superimposed on a weak signal passing through the "first connection structure" can be reduced, and thus the measurement sensitivity of the semiconductor detector 400 for X-ray energy can be improved.

However, as shown in fig. 15, when the underfill is not filled in the gap between the flip-chip connected semiconductor chip CHP1 and the semiconductor chip CHP2, the connection strength between the semiconductor chip CHP1 and the semiconductor chip CHP2 may be reduced.

In this regard, in the semiconductor detector 400 according to embodiment 2, the following studies are made in order to suppress a decrease in the connection strength between the semiconductor chip CHP1 and the semiconductor chip CHP 2. That is, as shown in fig. 15, the semiconductor chip CHP2 is fixed by the adhesive 60 inside the opening OP2 provided in the wiring board WB. Thus, according to embodiment 2, the semiconductor chip CHP2 can be firmly fixed to the wiring board WB with the adhesive 60 without using an underfill, and the connection reliability between the semiconductor chip CHP1 and the semiconductor chip CHP2 can be improved.

As described above, according to the semiconductor detector 400 in embodiment 2, since the underfill is not filled between the semiconductor chip CHP1 and the semiconductor chip CHP2, an increase in parasitic capacitance due to the underfill can be suppressed. Further, even if the underfill is not used, it is considered that the bonding strength between the semiconductor chip CHP1 and the semiconductor chip CHP2 can be suppressed from being lowered by fixing the semiconductor chip CHP2 inside the opening OP2 provided in the wiring board WB with the adhesive 60. Therefore, it can be said that the semiconductor detector 400 in embodiment 2 is excellent in that both the increase in the parasitic capacitance and the decrease in the connection strength between the semiconductor chip CHP1 and the semiconductor chip CHP2 are suppressed.

< verification of Effect >

Finally, the following is explained: according to embodiment 1 and embodiment 2, for example, compared to the first related art and the second related art, noise included in the signal can be reduced, and as a result, the measurement sensitivity of the semiconductor detector for the X-ray energy can be improved.

Fig. 16 is a diagram for explaining the verification result.

In fig. 16, the first related art is a "wire bonding connection structure" in which the read electrode and the gate terminal are connected by a metal wire. In the first related art, "Mn-Ka half amplitude (eV)" is 130 to 135.

Here, "Mn — Ka half amplitude (eV)" shows a half amplitude of a peak value of the K α line (5890eV) of manganese (Mn), and the larger the noise, the larger the value. Therefore, the smaller the "Mn-Ka half amplitude (eV)", the higher the measurement sensitivity and the better the performance.

Next, a second related technique is a "flip chip connection configuration" in which the reading electrode pad and the gate terminal are connected by a bump electrode. However, in the second related art, the underfill is filled between the first semiconductor chip formed with the read electrode pad and the second semiconductor chip formed with the gate terminal. As a result, by using the bump electrode instead of the metal line, the influence of the parasitic capacitance and parasitic inductance of the metal line itself disappears, but the value of "Mn — Ka half amplitude (eV)" becomes larger in the second related art than in the first related art due to the parasitic capacitance caused by the underfill having a high dielectric constant.

In contrast, in embodiment 1 (embodiment 1), on the premise of the "flip-chip connection structure", a guide portion is provided on the reading electrode side. As a result, the "first connection structure" of the read electrode pad and the gate terminal via the bump electrode is surrounded by the void without being covered by the underfill. According to embodiment 1 (embodiment 1), "Mn — Ka half amplitude (eV)" is 127 to 132. This means that, according to embodiment 1 (embodiment 1), the influence of the parasitic capacitance due to the underfill is reduced, and the noise contained in the signal is reduced. Thus, it can be seen that: according to embodiment 1 (embodiment 1), the measurement sensitivity of the semiconductor detector for the X-ray energy can be improved as compared with the first related art and the second related art.

Next, in embodiment 1 (embodiment 3), on the premise of the "flip chip connection structure", a guide portion is provided on the reading electrode side, and a guide portion is also provided on the output terminal side. As a result, not only the "first connection structure" of the read electrode pad and the gate terminal via the bump electrode, but also the "second connection structure" of the output electrode pad and the output terminal via the bump electrode is surrounded by the void and is not covered by the underfill. According to embodiment 1 (embodiment 3), "Mn — Ka half amplitude (eV)" is 126 to 131. This means that not only the reduction of the parasitic capacitance in the "first connection configuration", but also the reduction of the parasitic capacitance in the "second connection configuration" effectively acts on the reduction of the noise. Thus, it can be seen that: according to embodiment 1 (embodiment 3), the measurement sensitivity of the semiconductor detector for the X-ray energy can be improved as compared with the first related art and the second related art.

Next, in embodiment 2, on the premise of the "flip-chip connection structure", no underfill is present between the first semiconductor chip on which the read electrode pad and the output electrode pad are formed and the second semiconductor chip on which the gate terminal and the output terminal are formed. As a result, in embodiment 2, the "first connection structure" and the "second connection structure" are also surrounded by the void and are not covered with the underfill. According to this embodiment 2, "Mn-Ka half amplitude (eV)" is 127 to 132. Therefore, it is understood that, according to embodiment 2, the measurement sensitivity of the semiconductor detector for the X-ray energy can be improved as compared with the first related art and the second related art.

From the above, it was confirmed that: according to embodiment 1 and embodiment 2, noise included in a signal can be reduced as compared with the first related art and the second related art, and as a result, the measurement sensitivity of the semiconductor detector for X-ray energy can be improved.

The invention made by the inventors has been specifically described above based on the above embodiments, but the invention is not limited to the above embodiments, and it goes without saying that various modifications can be made within the scope not departing from the gist thereof.

The above embodiment includes the following embodiments.

(attached note 1)

A semiconductor detector that moves charge carriers generated by entering an electromagnetic wave into a depletion layer to which a drift electric field is applied to a reading electrode in the drift electric field, collects a charge amount, and measures energy of the electromagnetic wave based on the charge amount, the semiconductor detector comprising:

a first semiconductor chip on which the read electrode and a read electrode pad electrically connected to the read electrode are formed;

a wiring board which is connected to the first semiconductor chip in a flip-chip manner and has an opening; and

a second semiconductor chip having an amplifier electrically connected to the read electrode pad, disposed in the opening, and flip-chip connected to the first semiconductor chip,

the second semiconductor chip is fixed inside the opening by an adhesive,

an underfill does not exist between the first semiconductor chip and the second semiconductor chip including the first connection portion where the read electrode pad is connected to the amplifier.