Pixel circuit, driving method thereof, display panel and display device

文档序号：1923507 发布日期：2021-12-03 浏览：24次中文

阅读说明：本技术 像素电路及其驱动方法、显示面板、显示装置 (Pixel circuit, driving method thereof, display panel and display device ) 是由陈腾孟维欣史大为王文涛蒋发明于 2021-09-02 设计创作，主要内容包括：本申请实施例提供了一种像素电路及其驱动方法、显示面板、显示装置,像素电路包括复位模块、数据写入模块、驱动模块、第一补偿子模块、第一存储子模块、第二补偿子模块、第三补偿子模块和发光控制模块。复位模块与第一节点电连接,被构造成与第一扫描信号线和第二电压端电连接；第二电压端与发光元件的阴极电连接；第三补偿子模块与第二节点电连接,被构造成与第三补偿控制信号线和第二电压端电连接；本申请实施例中第二电压端的电压可以参与到像素电路的补偿中,避免了与第二电压端电连接的电压线路上的电阻压降对发光元件寿命补偿产生影响,延长了发光元件的寿命,同时能够降低成本,提高对发光元件补偿的精度。(The embodiment of the application provides a pixel circuit and a driving method thereof, a display panel and a display device. The reset module is electrically connected with the first node and is configured to be electrically connected with the first scanning signal line and the second voltage end; the second voltage end is electrically connected with the cathode of the light-emitting element; the third compensation submodule is electrically connected with the second node and is configured to be electrically connected with a third compensation control signal line and a second voltage end; in the embodiment of the application, the voltage of the second voltage end can participate in the compensation of the pixel circuit, so that the influence of the resistance voltage drop on the voltage line electrically connected with the second voltage end on the service life compensation of the light-emitting element is avoided, the service life of the light-emitting element is prolonged, the cost can be reduced, and the compensation precision of the light-emitting element is improved.)

1. A pixel circuit, comprising:

the first end of the reset module is electrically connected with the first node, the control end of the reset module is electrically connected with the first scanning signal line, and the second end of the reset module is electrically connected with the second voltage end; the second voltage end is electrically connected with the cathode of the light-emitting element;

the first end of the data writing module is electrically connected with the third node, the second end of the data writing module is electrically connected with the data signal line, and the control end of the data writing module is electrically connected with the second scanning signal line;

the control end of the driving module is electrically connected with the first node, the first end of the driving module is electrically connected with the third node, and the second end of the driving module is electrically connected with the fourth node;

a first compensation submodule, a first end of which is electrically connected with the first node, a second end of which is electrically connected with the fourth node, and a control end of which is electrically connected with the second scanning signal line;

a first storage submodule having a first pole electrically connected to the first node and a second pole electrically connected to the second node;

a first end of the second compensation submodule is electrically connected with the second node, a control end of the second compensation submodule is electrically connected with the second scanning signal line, and a second end of the second compensation submodule is electrically connected with the anode of the light-emitting element;

a first end of the third compensation submodule is electrically connected with the second node, a control end of the third compensation submodule is electrically connected with a third compensation control signal line, and a second end of the third compensation submodule is electrically connected with a second voltage end;

and the first end of the light-emitting control module is electrically connected with the third node, the second end of the light-emitting control module is electrically connected with the fourth node, the third end of the light-emitting control module is electrically connected with the first voltage end, the first control end and the second control end of the light-emitting control module are electrically connected with the light-emitting control signal line, and the fourth end of the light-emitting control module is electrically connected with the anode of the light-emitting element.

2. The pixel circuit according to claim 1, wherein the third compensation control signal line comprises a light emission control signal line.

3. The pixel circuit according to claim 1, further comprising:

a first pole of the second storage submodule is electrically connected with the first voltage end, and a second pole of the second storage submodule is electrically connected with the second node;

the third compensation control signal line includes a third scanning signal line.

4. The pixel circuit according to claim 1, further comprising:

a first pole of the second storage submodule is electrically connected with the first voltage end, and a second pole of the second storage submodule is electrically connected with the first node;

the third compensation control signal line includes a light emission control signal line.

5. The pixel circuit according to claim 1, further comprising:

a first pole of the second storage submodule is electrically connected with the first voltage end, and a second pole of the second storage submodule is electrically connected with the first node;

the third compensation control signal line includes a third scanning signal line.

6. A display panel comprising a voltage transmission line, the pixel circuit according to any one of claims 1 to 5, and the light emitting element;

the voltage transmission line is electrically connected with the second voltage end;

the voltage transmission line, the pixel circuit and the light emitting element are all arranged on the same backboard.

7. A display device characterized by comprising the display panel according to claim 6.

8. A driving method of a pixel circuit, applied to the pixel circuit according to claim 1, the driving method comprising:

in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

in the second stage, the data writing module, the first compensation submodule and the second compensation submodule are conducted on the basis of a second scanning signal, and data voltage is transmitted to the first node;

in the third stage, the third compensation submodule is conducted based on a third compensation control signal; the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

9. The method for driving the pixel circuit according to claim 8, wherein the third compensation control signal line includes a light emission control signal line; in the third stage, the third compensation sub-module is turned on based on a third compensation control signal, and includes:

and in the third stage, the third compensation submodule is conducted based on the light-emitting control signal.

10. A driving method of a pixel circuit, applied to the pixel circuit according to claim 3, the driving method comprising:

in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

in the third stage, the third compensation submodule is conducted based on the third scanning signal;

and in the fourth stage, the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

11. A driving method of a pixel circuit, applied to the pixel circuit according to claim 4, the driving method comprising:

in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

in the third stage, the third compensation submodule is conducted based on the light-emitting control signal; the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

12. A driving method of a pixel circuit, applied to the pixel circuit according to claim 5, the driving method comprising:

in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

in the third stage, the third compensation submodule is conducted based on the third scanning signal;

and in the fourth stage, the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

Technical Field

The application relates to the technical field of display, in particular to a pixel circuit, a driving method thereof, a display panel and a display device.

Background

Light-Emitting elements (e.g., OLED) limit further applications of the Light-Emitting elements due to their lifetime, and thus limit application fields of display panels and display devices having the Light-Emitting elements, such as products with long life cycles like vehicle-mounted and notebook computers.

In the prior art, the method for prolonging the service life of the light-emitting element is mainly to compensate the data again after calculation in an external compensation mode, namely, by testing the current or voltage of each pixel light-emitting stage.

However, the above compensation method requires a new added IC (integrated Circuit), which greatly increases the cost, and in addition, since the current of a single light emitting device (e.g. OLED) is very small, the compensation method using external compensation method reduces the precision of compensation for the light emitting device.

Disclosure of Invention

The present application provides a pixel circuit, a driving method thereof, a display panel, and a display device, which are directed to overcome the disadvantages of the prior art, and are used to solve the technical problems that in the compensation method of the prior art, an IC needs to be added again, which can greatly increase the cost, and the accuracy of compensation for a light emitting element can be reduced by compensating the IC in an external compensation manner.

In a first aspect, an embodiment of the present application provides a pixel circuit, including:

the first end of the first compensation submodule is electrically connected with the first node, the second end of the first compensation submodule is electrically connected with the fourth node, and the control end of the first compensation submodule is electrically connected with the second scanning signal line;

the first pole of the first storage submodule is electrically connected with the first node, and the second pole of the first storage submodule is electrically connected with the second node;

the first end of the second compensation submodule is electrically connected with the second node, the control end of the second compensation submodule is electrically connected with the second scanning signal line, and the second end of the second compensation submodule is electrically connected with the anode of the light-emitting element;

the first end of the third compensation submodule is electrically connected with the second node, the control end of the third compensation submodule is electrically connected with the third compensation control signal line, and the second end of the third compensation submodule is electrically connected with the second voltage end;

and the first end of the light-emitting control module is electrically connected with the third node, the second end of the light-emitting control module is electrically connected with the fourth node, the third end of the light-emitting control module is electrically connected with the first voltage end, the first control end and the second control end are electrically connected with the light-emitting control signal line, and the fourth end of the light-emitting control module is electrically connected with the anode of the light-emitting element.

In one possible implementation, the third compensation control signal line includes a light emission control signal line.

In one possible implementation, the pixel circuit further includes:

a first electrode of the second storage submodule is electrically connected with the first voltage end, and a second electrode of the second storage submodule is electrically connected with the second node;

the third compensation control signal line includes a third scanning signal line.

In one possible implementation, the pixel circuit further includes:

the third compensation control signal line includes a light emission control signal line.

In one possible implementation, the pixel circuit further includes:

the third compensation control signal line includes a third scanning signal line.

In a second aspect, embodiments of the present application provide a display panel, including a voltage transmission line, the pixel circuit of the first aspect, and a light emitting element;

the voltage transmission line is electrically connected with the second voltage end;

the voltage transmission line, the pixel circuit and the light-emitting element are all arranged on the same back plate.

In a third aspect, an embodiment of the present application provides a display device, including the display panel of the second aspect.

In a fourth aspect, an embodiment of the present application provides a driving method for a pixel circuit, which is applied to the pixel circuit of the first aspect, and the driving method for the pixel circuit includes:

in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

In one possible implementation, the third compensation control signal line includes a light emission control signal line; in the third stage, the third compensation sub-module is turned on based on a third compensation control signal, and includes:

and in the third stage, the third compensation submodule is conducted based on the light-emitting control signal.

In a fifth aspect, an embodiment of the present application provides a driving method for a pixel circuit, where the driving method is applied to the pixel circuit of the first aspect, and the driving method includes:

in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

in the third stage, the third compensation submodule is conducted based on the third scanning signal;

and in the fourth stage, the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

In a sixth aspect, an embodiment of the present application provides a driving method for a pixel circuit, where the driving method is applied to the pixel circuit of the first aspect, and the driving method includes:

in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

In a seventh aspect, an embodiment of the present application provides a driving method for a pixel circuit, where the driving method is applied to the pixel circuit of the first aspect, and the driving method includes:

in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

in the third stage, the third compensation submodule is conducted based on the third scanning signal;

and in the fourth stage, the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:

(1) the pixel circuit provided by the embodiment of the application comprises: the device comprises a reset module, a data writing module, a driving module, a first compensation submodule, a first storage submodule, a second compensation submodule, a third compensation submodule and a light-emitting control module. Wherein the reset module is electrically connected to the first node and configured to be electrically connected to the first scan signal line and the second voltage terminal; the second voltage end is electrically connected with the cathode of the light-emitting element; a third compensation submodule is electrically connected to the second node and is configured to electrically connect to a third compensation control signal line and a second voltage terminal. Namely, the reset module and the third compensation submodule are both configured to be electrically connected with a second voltage terminal, and the second voltage terminal is electrically connected with the cathode of the light-emitting element; that is, the voltage of the second voltage terminal (hereinafter referred to as VSS voltage) can participate in the compensation of the pixel circuit, so that IR drop (resistance drop) on the VSS voltage line is prevented from affecting the lifetime compensation of the light emitting element, and the lifetime of the light emitting element is prolonged.

(2) Compared with an external compensation mode, the pixel circuit provided by the embodiment of the application adopts an internal compensation mode, an IC (integrated circuit) is not required to be added again, the cost is reduced, meanwhile, because the current of a single light-emitting element (such as an OLED) is very small, the internal compensation mode is adopted, the compensation precision of the light-emitting element can be improved, and the brightness of a picture displayed on the display device is more uniform.

(3) According to the embodiment of the application, the compensation of the pixel circuit can be completed only by adopting two scanning signal lines (namely, the first scanning signal line and the second scanning signal line) and one light-emitting control signal line, so that the number of the signal lines on the display panel is reduced, the display panel has a loose wiring space, and the design of the display panel is simplified.

(4) The second storage sub-module of the pixel circuit provided by the embodiment of the application is electrically connected between the first voltage terminal VDD and the second node N2, that is, during the light emitting phase of the light emitting device, the first node N1 is connected to the first voltage terminal VDD through the capacitors (i.e., the first capacitor C1 and the second capacitor C2), so that the influence of the voltage fluctuation of the first voltage terminal VDD on the light emitting brightness of the light emitting device is avoided, and the problem of non-uniform dynamic picture brightness is avoided.

(5) The second storage submodule of the pixel circuit provided by the embodiment of the present application is electrically connected between the first voltage terminal VDD and the first node N1, and compensates the threshold voltage Voled _ th of the light emitting element into the pixel circuit in a required ratio, so that the requirements of a plurality of EL devices (light emitting elements) can be met, that is, the compensation amount can be controlled by changing the capacitance ratio of the first capacitor C1 and the second capacitor C2, so that the pixel circuit can be applied to the materials of the plurality of EL devices, that is, the embodiment of the present application can provide a targeted compensation value for the characteristics of different EL devices.

(6) The display panel that this application embodiment provided, adopt the novel technology of present advanced supplementary negative pole, with voltage transmission line (VSS voltage line), pixel circuit and light emitting component all set up on same backplate, introduce voltage transmission line (VSS voltage line) in pixel circuit's wiring, whole face evaporation plating before having replaced, make VSS voltage can participate in pixel circuit's compensation, IR drop on the VSS voltage line has been avoided producing the influence to light emitting component life-span compensation, the life-span of light emitting component has been prolonged, and simultaneously, the length of voltage transmission line on the display panel has been reduced, make the display panel have more loose wiring space, thereby optimize display device's design space, be convenient for display device can realize higher resolution ratio.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a graph of the lifetime decay characteristic of an OLED;

fig. 2a is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 2b is a schematic diagram of a current path at each stage of the pixel circuit shown in FIG. 2 a;

FIG. 2c is a timing diagram of various stages of the pixel circuit shown in FIG. 2 a;

fig. 3a is a schematic circuit diagram of another pixel circuit according to an embodiment of the present disclosure;

FIG. 3b is a schematic diagram of a current path at each stage of the pixel circuit shown in FIG. 3 a;

FIG. 3c is a timing diagram of various stages of the pixel circuit shown in FIG. 3 a;

fig. 4a is a schematic circuit diagram of another pixel circuit provided in an embodiment of the present application;

FIG. 4b is a schematic diagram of a current path at each stage of the pixel circuit shown in FIG. 4 a;

FIG. 4c is a timing diagram of various stages of the pixel circuit shown in FIG. 4 a;

fig. 5a is a schematic circuit diagram of another pixel circuit provided in an embodiment of the present application;

FIG. 5b is a schematic diagram of a current path at each stage of the pixel circuit shown in FIG. 5 a;

FIG. 5c is a timing diagram of various stages of the pixel circuit shown in FIG. 5 a.

Reference numerals:

10-a reset module, 20-a data write-in module, 30-a drive module, 41-a first compensation sub-module, 42-a second compensation sub-module, 43-a third compensation sub-module, 50-a light-emitting control module, 51-a first light-emitting sub-module, 52-a second light-emitting sub-module, 61-a first storage sub-module, 62-a second storage sub-module;

100-light emitting element.

Detailed Description

Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

The inventors of the present application have conducted studies to find that a Light Emitting element, such as an OLED (Organic Light-Emitting Diode), limits further applications of the Light Emitting element due to its lifetime problem, as shown in fig. 1, in which the axis of abscissa indicates time in units of h (hours); the ordinate axis on the left represents the OLED anode surface voltage in V (volts); the ordinate axis on the right represents the percentage based on the lifetime of the OLED in% (percentage). The OLED anode surface voltage is measured using a constant current test, and it can be seen from the figure that as the lifetime of the OLED decreases, the resistance of the OLED and its threshold voltage increase, resulting in an increase in the voltage across the OLED (i.e., the OLED anode surface voltage). It follows that the lifetime of an OLED is inversely related to the threshold voltage of the OLED.

In addition, because the current of a single light emitting element (for example, OLED) is very small, the compensation is performed by adopting the external compensation method, and the compensation precision of the light emitting element is reduced.

The inventor also considers that the prior art uses the 8T2C circuit structure to compensate the OLED lifetime by the OLED threshold voltage. The problems of compensating the lifetime of the OELD are: as the lifetime of the OLED decreases, the threshold voltage Voled _ th of the OLED becomes larger, and thus Vdata-VSS-Voled _ th becomes more negative, which for a PMOS TFT (Thin Film Transistor) is the more negative the value, the larger the current of the OLED. The VSS voltage (namely, the voltage of the cathode of the OLED) is involved in the current calculation process of the OLED, and since the VSS voltage is input from the periphery of the Panel, under the influence of an IR drop (resistance drop) on a VSS voltage line, the VSS voltage in the middle of the Panel is slightly smaller, and the larger the size of the Panel is, the more obvious the phenomenon is.

In addition, in the previous process, the cathode (VSS) of the OLED is entirely evaporated above the EL (ELectroluminescence) device and cannot be in contact with the trace of the pixel circuit, so that it is difficult to eliminate the influence of the cathode (VSS) voltage of the OLED, i.e., the VSS voltage, on the compensation of the pixel circuit.

The application provides a pixel circuit, a driving method thereof, a display panel and a display device, and aims to solve the above technical problems in the prior art.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.

The embodiment of the present application provides a pixel circuit, as shown in fig. 2a, the pixel circuit may include a reset module 10, a data writing module 20, a driving module 30, a first compensation submodule 41, a first storage submodule 61, a second compensation submodule 42, a third compensation submodule 43, and a light emitting control module 50.

Specifically, a first end of the reset module 10 is electrically connected to the first node N1, a control end is electrically connected to the first scanning signal line S1, and a second end is electrically connected to the second voltage terminal VSS; the second voltage terminal VSS is electrically connected to the cathode of the light emitting element 100; the first node N1 is a node electrically connected to the control terminal of the driving module 30;

the first terminal of the data writing module 20 is electrically connected to the third node N3, the second terminal thereof is electrically connected to the data signal line S1, and the control terminal thereof is electrically connected to the second scan signal line S2; the third node N3 is a node electrically connected to the first end of the driving module 30;

the control terminal of the driving module 30 is electrically connected to the first node N1, the first terminal is electrically connected to the third node N3, and the second terminal is electrically connected to the fourth node N4; the fourth node is a node electrically connected to the second end of the driving module 30;

a first terminal of the first compensation submodule 41 is electrically connected to the first node N1, a second terminal thereof is electrically connected to the fourth node N4, and a control terminal thereof is electrically connected to the second scan signal line S2;

the first pole of the first storage submodule 61 is electrically connected to the first node N1, and the second pole is electrically connected to the second node N2; a second node N2 is a node electrically connected to a second pole of the first storage submodule;

a first terminal of the second compensation submodule 42 is electrically connected to the second node N2, a control terminal is electrically connected to the second scanning signal line S2, and a second terminal is electrically connected to the anode of the light emitting element 100;

a first terminal of the third compensation submodule 43 is electrically connected to the second node, a control terminal is electrically connected to a third compensation control signal line (for example, EM in fig. 2a or S3 in fig. 3 a), and a second terminal is electrically connected to the second voltage terminal VSS;

the light emission control module 50 has a first terminal electrically connected to the third node N3, a second terminal electrically connected to the fourth node N4, a third terminal electrically connected to the first voltage terminal VDD, a first control terminal and a second control terminal both electrically connected to the light emission control signal line EM, and a fourth terminal electrically connected to the anode of the light emitting device 100.

Optionally, the light emitting element 100 comprises an OLED.

The voltage of the second voltage terminal of the pixel circuit (hereinafter referred to as VSS voltage) provided in this embodiment of the application may participate in the compensation of the pixel circuit, thereby avoiding an IR drop (resistance drop) on the VSS voltage line from affecting the lifetime compensation of the light emitting element 100, and prolonging the lifetime of the light emitting element 100.

Compared with an external compensation mode, the pixel circuit provided by the embodiment of the application adopts an internal compensation mode, an IC does not need to be added again, the cost is reduced, and meanwhile, because the current of a single light-emitting element 100 (such as an OLED) is very small, the accuracy of compensation for the light-emitting element 100 can be improved by adopting the internal compensation mode, so that the brightness of a picture displayed on a display device is more uniform.

Meanwhile, in the embodiment of the present application, compensation of the pixel circuit can be completed only by using two scanning signal lines (i.e., the first scanning signal line S1 and the second scanning signal line S2) and one emission control signal line EM, so that the number of signal lines on the display Panel is reduced, the display Panel has a relatively loose wiring space, and the Panel design is simplified.

In some embodiments, as shown in fig. 2a, the lighting control module 50 comprises a first lighting control sub-module 51 and a second lighting control sub-module 52. The first emission control sub-module 51 is electrically connected to the third node N3, and is configured to be electrically connected to the first voltage terminal VDD and the emission control signal line EM; the second emission control sub-module 52 is electrically connected to the fourth node N4, and is configured to be electrically connected to the anode of the light emitting element 100 and the emission control signal line EM.

In some embodiments, as shown in fig. 2a, the third compensation control signal line includes a light emission control signal line EM.

Alternatively, as shown in fig. 2a, the reset module 10 includes a first transistor T1, a first pole of the first transistor T1 is electrically connected to the first node N1, a second pole of the first transistor T1 is electrically connected to the second voltage terminal VSS, and a control pole of the first transistor T1 is electrically connected to the first scan signal line S1; the second voltage terminal VSS is electrically connected to the cathode of the light emitting element 100;

the data writing module 20 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is electrically connected to the third node N3, a second electrode is electrically connected to the data signal line Vdata, and a control electrode is electrically connected to the second scan signal line S2;

the driving module 30 includes a third transistor T3, a control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode is electrically connected to the third node N3, and a second electrode is electrically connected to the fourth node N4;

the first compensation submodule 41 includes a second transistor T2, a first pole of the second transistor T2 is electrically connected to the first node N1, a second pole is electrically connected to the fourth node N4, and a control pole is electrically connected to the second scan signal line S2;

the first storage submodule 61 comprises a first capacitor C1, a first pole of the first capacitor C1 is electrically connected with a first node N1, and a second pole is electrically connected with a second node N2;

the second compensation submodule 42 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected to the second node N2, a control electrode is electrically connected to the second scan signal line S2, and a second electrode is electrically connected to the anode of the light emitting element 100;

the third compensation submodule 43 includes a sixth transistor T6, a first pole of the sixth transistor T6 is electrically connected to the second node N2, a control pole is electrically connected to the emission control signal line EM, and a second pole is electrically connected to the second voltage terminal VSS;

the first light emission control sub-module 51 includes a seventh transistor T7, a first pole of the seventh transistor T7 is electrically connected to the third node N3, a second pole is electrically connected to the first voltage terminal VDD, and a control pole is electrically connected to the light emission control signal line EM;

the second light emission control sub-module 52 includes an eighth transistor T8, a first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, a second electrode is electrically connected to the anode of the light emitting element 100, and a control electrode is electrically connected to the light emission control signal line EM.

In some embodiments, as shown in fig. 3a, the pixel circuit further comprises: a second storage submodule 62, a first pole of the second storage submodule 62 being electrically connected to the first voltage terminal VDD, and a second pole of the second storage submodule 62 being electrically connected to the second node N2;

the third compensation control signal line includes a third scan signal line S3.

The third compensation submodule 43 is electrically connected to both the third scan signal line S3 and the second voltage terminal VSS.

Optionally, as shown in fig. 3a, the second storage submodule 62 includes a second capacitor C2, a first pole of the second capacitor C2 is electrically connected to the first voltage terminal VDD, and a second pole is electrically connected to the second node N2.

The second storage sub-module 62 of the embodiment of the application is electrically connected between the first voltage terminal VDD and the second node N2, that is, when the light emitting device 100 emits light, the first node N1 is connected to the first voltage terminal VDD through capacitors (i.e., the first capacitor C1 and the second capacitor C2), so that the influence of the voltage fluctuation of the first voltage terminal VDD on the light emitting brightness of the light emitting device 100 is avoided, and the problem of uneven brightness of the dynamic image is avoided.

In some embodiments, as shown in fig. 4a, the pixel circuit further comprises: a second storage submodule 62, a first pole of the second storage submodule 62 is electrically connected to the first voltage terminal VDD, and a second pole of the second storage submodule 62 is electrically connected to the first node N1;

the third compensation control signal line includes the emission control signal line EM.

The third compensation control signal line includes a light emission control signal line EM, and the third compensation submodule 43 is electrically connected to the light emission control signal line EM and the second voltage terminal VSS.

Alternatively, as shown in fig. 4a, the second storage submodule 62 includes a second capacitor C2, a first pole of the second capacitor C2 is electrically connected to the first voltage terminal VDD, and a second pole is electrically connected to the first node N1.

The second storage submodule 62 in the embodiment of the present application is electrically connected between the first voltage terminal VDD and the first node N1, and compensates the threshold voltage Voled _ th of the light emitting element 100 into the pixel circuit in a required ratio, so that the requirements of a plurality of EL devices (light emitting elements 100) can be satisfied, that is, the compensation amount can be controlled by changing the capacitance ratio of the first capacitor C1 and the second capacitor C2, and thus the pixel circuit can be applied to a plurality of materials of the EL devices, that is, the embodiment of the present application can provide a targeted compensation value for different characteristics of the EL devices. And only two scanning signal lines (namely, the first scanning signal line S1 and the second scanning signal line S2) and one light-emitting control signal line EM are adopted, so that the compensation of the pixel circuit can be completed, the number of the signal lines on the display Panel is reduced, the display Panel has a looser wiring space, and the Panel design is simplified.

In some embodiments, as shown in fig. 5a, the pixel circuit further comprises: a second storage submodule 62, a first pole of the second storage submodule 62 is electrically connected to the first voltage terminal VDD, and a second pole of the second storage submodule 62 is electrically connected to the first node N1;

the third compensation control signal line includes a third scan signal line S3.

The third compensation control signal line includes a third scan signal line S3, and the third compensation submodule 43 is electrically connected to the third scan signal line S3 and the second voltage terminal VSS.

Alternatively, as shown in fig. 5a, the second storage submodule 62 includes a second capacitor C2, a first pole of the second capacitor C2 is electrically connected to the first voltage terminal VDD, and a second pole is electrically connected to the first node N1.

Based on the same inventive concept, the present application provides a display panel, including a voltage transmission line, the pixel circuit described in any of the above embodiments, and a light emitting element 100; the voltage transmission line is electrically connected with the second voltage end; the voltage transmission line, the pixel circuit and the light emitting element 100 are all disposed on the same backplane.

Optionally, the voltage transmission line comprises: and a VSS voltage line electrically connected to the second voltage terminal VSS.

The display panel that this application embodiment provided, adopt the novel technology of present advanced supplementary negative pole, with voltage transmission line (VSS voltage line), pixel circuit and light emitting component 100 all set up on same backplate, introduce voltage transmission line (VSS voltage line) in pixel circuit's wiring, whole face evaporation plating before having replaced, make VSS voltage can participate in pixel circuit's compensation, IR drop on the VSS voltage line has been avoided producing the influence to light emitting component 100 life-span compensation, the life-span of light emitting component 100 has been prolonged, and simultaneously, the length of voltage transmission line on the display panel has been reduced, make the display panel have more loose wiring space, thereby optimize display device's design space, be convenient for display device can realize higher resolution ratio.

Based on the same inventive concept, embodiments of the present application provide a display device, including the display panel described in any of the above embodiments.

The display device provided by the embodiment of the present application has the same inventive concept and the same advantageous effects as the embodiments described above, and the details not shown in the display device may refer to the embodiments described above, and are not repeated herein.

Based on the same inventive concept, the embodiment of the present application provides a driving method of a pixel circuit, which is applied to the pixel circuit provided by the embodiment of the present application, and the driving method of the pixel circuit includes the following steps S201 to S203:

step S201: in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

step S202: in the second stage, the data writing module, the first compensation submodule and the second compensation submodule are conducted on the basis of a second scanning signal, and data voltage is transmitted to the first node;

step S203: in the third stage, the third compensation submodule is conducted based on a third compensation control signal; the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

In some embodiments, the third compensation control signal line includes a light emission control signal line; and in the third stage, the third compensation submodule is conducted based on a third compensation control signal and comprises: and in the third stage, the third compensation submodule is conducted based on the light-emitting control signal.

Referring to fig. 2a, 2b and 2c, taking a case that each transistor is a P-type TFT and the light emitting element 100 is an OLED as an example, a driving method of a pixel circuit provided in the embodiment of the present application is specifically described as follows:

in fig. 2a, an 8T1C circuit structure is adopted, which saves one capacitor compared with the 8T2C circuit, and the 8T1C pixel circuit in fig. 2a only needs 3 gate signal lines, namely, the first scanning signal line S1, the second scanning signal line S2 and the light-emitting control signal line EM. Since the first scanning signal line S1 and the second scanning signal line S2 have the same logic low level width and only have a phase difference, the same GOA (Gate Driver On Array, Array substrate line Driver) signal can be used for output. The emission control signal line EM may be formed of an existing GOA.

In fig. 2a, the first transistor T1 is used for writing a second voltage (hereinafter referred to as VSS voltage) of the second voltage terminal VSS into the first node N1, and plays a reset role for the first capacitor C1; the third transistor T3 is a driving transistor; the second transistor T2 and the fourth transistor T4 are responsible for inputting the data voltage Vdata and performing compensation of the TFT Vth (i.e., the threshold voltage of the third transistor T3); the fifth transistor T5 is for electrically connecting the second node N2 with the anode of the OLED, and inputting the anode voltage of the OLED into Panel (display Panel); the sixth transistor T6 electrically connects the cathode voltage (i.e., VSS voltage) of the OLED to the second node N2, and functions to filter out the VSS voltage, only reserve Voled _ th (i.e., threshold voltage of the OLED), and write Voled _ th into the first node N1 by bootstrapping through the first capacitor C1, thereby completing the lifetime compensation of the OLED; the seventh transistor T7 and the eighth transistor T8 control the light emitting stage of the OLED.

Alternatively, referring to fig. 2a, 2b and 2c, in the pixel circuit shown in fig. 2a, the driving method of the pixel circuit is specifically described as follows:

first stage (i.e. stage t1 in fig. 2 c): reset phase (transmission path shown as dotted arrow e in FIG. 2 b)

The first scan signal line S1 is at a logic low level, the first transistor T1 is turned on based on the first scan signal, resets the first capacitor C1, and transmits the VSS voltage to the first node N1; the voltage at the second node N2 is temporarily floating, and the voltage at the first node N1 is VSS.

Second stage (i.e. stage t2 in fig. 2 c): TFT Vth compensation phase (transmission path is shown by dotted arrow f in FIG. 2 b)

The second scan signal line S2 is at a logic low level, the fourth transistor T4, the second transistor T2, and the fifth transistor T5 are turned on based on the second scan signal, the control electrode and the second electrode of the third transistor T3 are connected, the data voltage Vdata is transmitted to the first node N1 through the fourth transistor T4, the third transistor T3, and the second transistor T2, the voltage of the first node N1 is raised, and the voltage of the second node N2 is raised by bootstrap driving of the first capacitor C1; then, the second node N2 current flows into the OLED through the fifth transistor T5, so that the voltage of the second node N2 is the same as the anode voltage of the OLED. Finally, the voltage at the first node N1 is Vdata + Vth, and the voltage at the second node N2 is VSS + Voled _ th.

Third stage (i.e. stage t3 in fig. 2 c): voled _ th write and emission phases

Voled _ th write phase (transmission path shown as dashed arrow g in fig. 2 b): the light emission control signal line EM is at a logic low level, the sixth transistor T6 is turned on based on the light emission control signal, the voltage of the second node N2 is changed from VSS + Voled _ th to VSS, and the voltage of the second node N2 is changed by Voled _ th. Due to the bootstrap effect of the first capacitor C1, the voltage at the first node N1 varies by Voled _ th, and finally the voltage at the first node N1 is Vdata + Vth-Voled _ th.

Light emission phase (transmission path is shown by dashed arrow h in fig. 2 b): the light emission control signal line EM is at a logic low level, the seventh transistor T7 and the eighth transistor T8 are turned on based on the light emission control signal, the voltage of the first voltage terminal VDD is transmitted to the first pole of the third transistor T3 through the seventh transistor T7, the third transistor T3 outputs a driving current, and the driving current is transmitted to the light emitting element through the eighth transistor T8 to realize light emission. The voltages of the first node N1 and the second node N2 are the same as the voltage during the Voled _ th write phase. As shown in table one.

Optionally, there is also a stage (i.e., a stage t21 in fig. 2 c) between the second stage and the third stage in which the emission control signal line EM, the first scan signal line S1, and the second scan signal line S2 are all at a logic high level.

The above-mentioned t21 stage may or may not exist, and in actual operation, this stage is generally present.

Table one: voltages at nodes N1 and N2 at different stages of the pixel circuit shown in FIG. 2a

Phases	t1	t2	t3
				Function(s)	Reduction of position	TFT Vth compensation	Voled _ th write and light emission
N1	VSS	Vdata+Vth	Vdata+Vth-Voled_th
				N2	---	VSS+Voled_th	VSS

The driving method of the pixel circuit provided in the embodiment of the application can participate in the compensation of the pixel circuit with the VSS voltage, thereby avoiding the IR drop (resistance drop) on the VSS voltage line from affecting the lifetime compensation of the light emitting element 100, and prolonging the lifetime of the light emitting element 100.

Compared with an external compensation mode, the driving method of the pixel circuit provided by the embodiment of the application adopts an internal compensation mode, does not need to add an IC again, reduces the cost, and simultaneously can improve the compensation precision of the light-emitting element 100 due to the fact that the current of a single light-emitting element 100 (such as an OLED) is very small, and enables the brightness of a picture displayed on the display device to be more uniform by adopting the internal compensation mode.

step S301: in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

step S302: in the second stage, the data writing module, the first compensation submodule and the second compensation submodule are conducted on the basis of a second scanning signal, and data voltage is transmitted to the first node;

step S303: in the third stage, the third compensation submodule is conducted based on the third scanning signal;

step S304: and in the fourth stage, the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

Referring to fig. 3a, 3b and 3c, taking a case that each transistor is a P-type TFT and the light emitting element 100 is an OLED as an example, a driving method of a pixel circuit provided in the embodiment of the present application is specifically described as follows:

fig. 3a shows an 8T2C circuit structure, and the 8T2C pixel circuit in fig. 3a needs 4 gate signal lines, which are the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3 and the emission control signal line EM. Since the first scanning signal line S1, the second scanning signal line S2, and the third scanning signal line S3 have the same logic low level width and only differ by one phase, the same GOA (Gate Driver On Array) signal can be used for output. The emission control signal line EM may be formed of an existing GOA.

In fig. 3a, the first transistor T1 is used for writing a second voltage (hereinafter referred to as VSS voltage) of the second voltage terminal VSS into the first node N1, and plays a reset role for the first capacitor C1 and the second capacitor C2; the third transistor T3 is a driving transistor; the second transistor T2 and the fourth transistor T4 are responsible for inputting the data voltage Vdata and performing compensation of the TFT Vth (i.e., the threshold voltage of the third transistor T3); the fifth transistor T5 is for electrically connecting the second node N2 with the anode of the OLED, and inputting the anode voltage of the OLED into Panel (display Panel); the sixth transistor T6 electrically connects the cathode voltage (i.e., VSS voltage) of the OLED to the second node N2, and functions to filter out the VSS voltage, only reserve Voled _ th (i.e., threshold voltage of the OLED), and write Voled _ th into the first node N1 by bootstrapping through the first capacitor C1, thereby completing the lifetime compensation of the OLED; the seventh transistor T7 and the eighth transistor T8 control the light emitting stage of the OLED.

Alternatively, referring to fig. 3a, 3b and 3c, in the pixel circuit shown in fig. 3a, the driving method of the pixel circuit is specifically described as follows:

first stage (i.e. stage t1 in fig. 3 c): reset phase (transmission path shown as dotted arrow e in FIG. 3 b)

The first scan signal line S1 is at a logic low level, the first transistor T1 is turned on based on the first scan signal, resets the first capacitor C1 and the second capacitor C2, and transmits the VSS voltage to the first node N1; the voltage at the second node N2 is temporarily floating, and the voltage at the first node N1 is VSS.

Second stage (i.e. stage t2 in fig. 3 c): TFT Vth compensation phase (transmission path is shown by dotted arrow f in FIG. 3 b)

Third stage (i.e., stage t3 in fig. 3 c): voled _ th write (transmission path shown as dotted arrow g in FIG. 3 b)

Voled _ th write: the light emission control signal line EM is at a logic low level, the sixth transistor T6 is turned on based on the light emission control signal, the voltage of the second node N2 is changed from VSS + Voled _ th to VSS, and the voltage of the second node N2 is changed by Voled _ th. Due to the bootstrap effect of the first capacitor C1, the voltage at the first node N1 varies by Voled _ th, and finally the voltage at the first node N1 is Vdata + Vth-Voled _ th.

Fourth stage (i.e. stage t4 in fig. 3 c): light emission phase (transmission path is shown by dashed arrow h in fig. 3 b): the light emission control signal line EM is at a logic low level, the seventh transistor T7 and the eighth transistor T8 are turned on based on the light emission control signal, the voltage of the first voltage terminal VDD is transmitted to the first pole of the third transistor T3 through the seventh transistor T7, the third transistor T3 outputs a driving current, and the driving current is transmitted to the light emitting element through the eighth transistor T8 to realize light emission. The voltages of the first node N1 and the second node N2 are the same as the voltage of the T3 phase. As shown in table two.

Table two: voltages at nodes N1 and N2 at different stages of the pixel circuit shown in FIG. 3a

Phases	t1	t2	t3	t4
					Function(s)	Reduction of position	TFT Vth compensation	Voled _ th write	Luminescence
N1	VSS	Vdata+Vth	Vdata+Vth-Voled_th	Vdata+Vth-Voled_th
					N2	---	VSS+Voled_th	VSS	VSS

In the driving method of the pixel circuit provided in the embodiment of the application, during the light emitting phase of the light emitting device 100, the first node N1 is connected to the first voltage terminal VDD through the capacitors (i.e., the first capacitor C1 and the second capacitor C2), so that the influence of the voltage fluctuation of the first voltage terminal VDD on the light emitting luminance of the light emitting device 100 is avoided, and the problem of non-uniform dynamic picture luminance is avoided.

step S401: in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

step S402: in the second stage, the data writing module, the first compensation submodule and the second compensation submodule are conducted on the basis of a second scanning signal, and data voltage is transmitted to the first node;

step S403: in the third stage, the third compensation submodule is conducted based on the light-emitting control signal; the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

Referring to fig. 4a, 4b and 4c, taking a case that each transistor is a P-type TFT and the light emitting element 100 is an OLED as an example, a driving method of a pixel circuit provided in the embodiment of the present application is specifically described as follows:

in fig. 4a, an 8T2C circuit structure is adopted, and the 8T2C pixel circuit in fig. 4a only needs 3 gate signal lines, namely, the first scanning signal line S1, the second scanning signal line S2 and the emission control signal line EM. Since the first scanning signal line S1 and the second scanning signal line S2 have the same logic low level width and only have a phase difference, the same GOA (Gate Driver On Array, Array substrate line Driver) signal can be used for output. The emission control signal line EM may be formed of an existing GOA.

In fig. 4a, the first transistor T1 is used for writing a second voltage (hereinafter referred to as VSS voltage) of the second voltage terminal VSS into the first node N1, and plays a reset role for the first capacitor C1 and the second capacitor C2; the third transistor T3 is a driving transistor; the second transistor T2 and the fourth transistor T4 are responsible for inputting the data voltage Vdata and performing compensation of the TFT Vth (i.e., the threshold voltage of the third transistor T3); the fifth transistor T5 is for electrically connecting the second node N2 with the anode of the OLED, and inputting the anode voltage of the OLED into Panel (display Panel); the sixth transistor T6 electrically connects the cathode voltage (i.e., VSS voltage) of the OLED to the second node N2, and functions to filter out the VSS voltage, only reserve Voled _ th (i.e., threshold voltage of the OLED), and write Voled _ th into the first node N1 by bootstrapping through the first capacitor C1, thereby completing the lifetime compensation of the OLED; the seventh transistor T7 and the eighth transistor T8 control the light emitting stage of the OLED.

Alternatively, referring to fig. 4a, 4b and 4c, in the pixel circuit shown in fig. 4a, the driving method of the pixel circuit is specifically described as follows:

first stage (i.e. stage t1 in fig. 4 c): reset phase (transmission path shown as dotted arrow e in FIG. 4 b)

Second stage (i.e. stage t2 in fig. 4 c): TFT Vth compensation phase (transmission path is shown by dotted arrow f in FIG. 4 b)

Third stage (i.e., stage t3 in fig. 3 c): voled _ th write and emission phases

Voled _ th write phase (transmission path shown as dashed arrow g in fig. 4 b): the light emission control signal line EM is at a logic low level, the sixth transistor T6 is turned on based on the light emission control signal, the voltage of the second node N2 is changed from VSS + Voled _ th to VSS, and the voltage of the second node N2 is changed by Voled _ th. Due to the bootstrap effect of the first capacitor C1, the voltage of the first node N1 varies by Voled _ th · C1/(C1+ C2), and finally the voltage of the first node N1 is Vdata + Vth-Voled _ th · C1/(C1+ C2).

Light emission phase (transmission path is shown by dashed arrow h in fig. 4 b): the light emission control signal line EM is at a logic low level, the seventh transistor T7 and the eighth transistor T8 are turned on based on the light emission control signal, the voltage of the first voltage terminal VDD is transmitted to the first pole of the third transistor T3 through the seventh transistor T7, the third transistor T3 outputs a driving current, and the driving current is transmitted to the light emitting element through the eighth transistor T8 to realize light emission. The voltages of the first node N1 and the second node N2 are the same as the voltage during the Voled _ th write phase. As shown in table three.

Optionally, there is also a stage (i.e., a stage t21 in fig. 4 c) between the second stage and the third stage in which the emission control signal line EM, the first scan signal line S1, and the second scan signal line S2 are all at a logic high level.

The above-mentioned t21 stage may or may not exist, and in actual operation, this stage is generally present.

Table three: voltages at nodes N1 and N2 at different stages of the pixel circuit shown in FIG. 4a

Phases	t1	t2	t3
				Function(s)	Reduction of position	TFT Vth compensation	Voled _ th write and light emission
N1	VSS	Vdata+Vth	Vdata+Vth-Voled_th·C1/(C1+C2)
				N2	---	VSS+Voled_th	VSS

The driving method of the pixel circuit according to the embodiment of the present application compensates the threshold voltage Voled _ th of the light emitting element 100 into the pixel circuit in a required ratio, so that the requirements of a plurality of EL devices (light emitting elements 100) can be satisfied, that is, the compensation amount can be controlled by changing the capacitance ratio of the first capacitor C1 and the second capacitor C2, so that the pixel circuit can be applied to the materials of the plurality of EL devices, that is, the embodiment of the present application can provide a targeted compensation value for the characteristics of different EL devices. And only two scanning signal lines (namely, the first scanning signal line S1 and the second scanning signal line S2) and one light-emitting control signal line EM are adopted, so that the compensation of the pixel circuit can be completed, the number of the signal lines on the display Panel is reduced, the display Panel has a looser wiring space, and the Panel design is simplified.

step S501: in the first stage, the reset module is conducted based on a first scanning signal and transmits a second voltage of a second voltage end to a first node;

step S502: in the second stage, the data writing module, the first compensation submodule and the second compensation submodule are conducted on the basis of a second scanning signal, and data voltage is transmitted to the first node;

step S503: in the third stage, the third compensation submodule is conducted based on the third scanning signal;

step S504: and in the fourth stage, the light-emitting control module is conducted based on the light-emitting control signal, and the driving module outputs driving current to the light-emitting element.

Referring to fig. 5a, 5b and 5c, taking a case that each transistor is a P-type TFT and the light emitting element 100 is an OLED as an example, a driving method of a pixel circuit provided in the embodiment of the present application is specifically described as follows:

fig. 5a shows an 8T2C circuit structure, and the 8T2C pixel circuit in fig. 5a requires 4 gate signal lines, which are the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3, and the emission control signal line EM. Since the first scanning signal line S1, the second scanning signal line S2, and the third scanning signal line S3 have the same logic low level width and only differ by one phase, the same GOA (Gate Driver On Array) signal can be used for output. The emission control signal line EM may be formed of an existing GOA.

In fig. 5a, the first transistor T1 is used for writing a second voltage (hereinafter referred to as VSS voltage) of the second voltage terminal VSS into the first node N1, and plays a reset role for the first capacitor C1 and the second capacitor C2; the third transistor T3 is a driving transistor; the second transistor T2 and the fourth transistor T4 are responsible for inputting the data voltage Vdata and performing compensation of the TFT Vth (i.e., the threshold voltage of the third transistor T3); the fifth transistor T5 is for electrically connecting the second node N2 with the anode of the OLED, and inputting the anode voltage of the OLED into Panel (display Panel); the sixth transistor T6 electrically connects the cathode voltage (i.e., VSS voltage) of the OLED to the second node N2, and functions to filter out the VSS voltage, only reserve Voled _ th (i.e., threshold voltage of the OLED), and write Voled _ th into the first node N1 by bootstrapping through the first capacitor C1, thereby completing the lifetime compensation of the OLED; the seventh transistor T7 and the eighth transistor T8 control the light emitting stage of the OLED.

Alternatively, referring to fig. 5a, 5b and 5c, in the pixel circuit shown in fig. 5a, the driving method of the pixel circuit is specifically described as follows:

first stage (i.e. stage t1 in fig. 5 c): reset phase (transmission path shown as dotted arrow e in FIG. 5 b)

Second stage (i.e. stage t2 in fig. 5 c): TFT Vth compensation phase (transmission path is shown by dotted arrow f in FIG. 5 b)

Third stage (i.e., stage t3 in fig. 5 c): voled _ th write (transmission path shown by dotted arrow g in FIG. 5 b)

Voled _ th write: the light emission control signal line EM is at a logic low level, the sixth transistor T6 is turned on based on the light emission control signal, the voltage of the second node N2 is changed from VSS + Voled _ th to VSS, and the voltage of the second node N2 is changed by Voled _ th. Due to the bootstrap effect of the first capacitor C1, the voltage of the first node N1 varies by Voled _ th · C1/(C1+ C2), and finally the voltage of the first node N1 is Vdata + Vth-Voled _ th · C1/(C1+ C2).

Fourth stage (i.e. stage t4 in fig. 5 c): light emission phase (transmission path is shown by dashed arrow h in fig. 5 b): the light emission control signal line EM is at a logic low level, the seventh transistor T7 and the eighth transistor T8 are turned on based on the light emission control signal, the voltage of the first voltage terminal VDD is transmitted to the first pole of the third transistor T3 through the seventh transistor T7, the third transistor T3 outputs a driving current, and the driving current is transmitted to the light emitting element through the eighth transistor T8 to realize light emission. The voltages of the first node N1 and the second node N2 are the same as the voltage of the T3 phase. As shown in table four.

Table four: voltages at nodes N1 and N2 at different stages of the pixel circuit shown in FIG. 5a

Further, in the pixel circuit shown in fig. 5a, the current of the OLED is calculated as follows:

wherein, I_oledIs the current of the OLED, mu, C_oxW and L are fixed constants that are related to process parameters and geometric parameters of the driving transistor, i.e., the third transistor T3. In particular, mu, C_oxW and L are field effect mobility, gate insulating layer unit area capacitance, channel width and channel length of the driving transistor (i.e., the third transistor T3), respectively. V_gsIs the gate-source voltage difference of the driving transistor (i.e., the third transistor T3).

From the above calculation formula, as the light emitting time is prolonged, the Voled _ th of the OLED is increased, which causes Vgs to decrease, and the output current of the third transistor T3 as a PMOS transistor is increased, so that the luminance of the OLED is improved, and the OLED lifetime compensation effect is achieved. The voltage compensation is related to the proportional size of the first capacitor C1 and the second capacitor C2, and different proportions of the first capacitor C1 and the second capacitor C2 can be designed according to the characteristics of different EL devices.

Further, simulation verification is performed for the pixel circuit shown in fig. 5a as follows:

first, the OLED was simulated by an IV (current and voltage) curve, and after the simulation, the current was significantly increased after 1.2V, indicating that the voltage of the threshold voltage Voled _ th of the OLED is about 1.2V.

Next, the OLED model was introduced into the pixel circuit shown in fig. 5a and simulated. For example only, the voltage of the first voltage terminal VDD (hereinafter referred to as VDD voltage) is set to 4.6V, the VSS voltage is set to-3V, the Vdata voltage is set to 4V, the threshold voltage Vth of the third transistor T3 is set to-2.5V, and the capacitance values of the first capacitor C1 and the second capacitor C2 are set to be the same.

As can be seen from the above, in the second stage, the theoretical voltage value of the second node N2 is VSS + Voled _ th ═ 1.8V, which is close to the simulation result of-1.7V. In the third stage, the theoretical voltage value of the first node N1 is Vdata + Vth-1/2Voled _ th — 4-2.5-1/2 × 1.2 — 0.9V, which is almost the same as the simulation result.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

(1) with the pixel circuit and the driving method thereof provided by the embodiment of the application, the VSS voltage can participate in the compensation of the pixel circuit, so that an IR drop (resistance drop) on a VSS voltage line is prevented from affecting the life compensation of the light emitting element 100, and the life of the light emitting element 100 is prolonged.

(2) Compared with an external compensation mode, the pixel circuit provided by the embodiment of the application adopts an internal compensation mode, an IC does not need to be added again, the cost is reduced, and meanwhile, because the current of a single light-emitting element 100 (such as an OLED) is very small, the accuracy of compensation for the light-emitting element 100 can be improved by adopting the internal compensation mode, so that the brightness of a picture displayed on a display device is more uniform.

(3) The pixel circuit provided by the embodiment of the application can complete the compensation of the pixel circuit by only adopting two scanning signal lines (namely, the first scanning signal line S1 and the second scanning signal line S2) and one light-emitting control signal line EM, thereby reducing the number of the signal lines on the display Panel, leading the display Panel to have a looser wiring space and simplifying the design of Panel (display Panel).

(4) The second storage submodule 62 of the pixel circuit provided in the embodiment of the application is electrically connected between the first voltage terminal VDD and the second node N2, that is, during the light emitting phase of the light emitting device 100, the first node N1 is connected to the first voltage terminal VDD through capacitors (i.e., the first capacitor C1 and the second capacitor C2), so that the influence of the voltage fluctuation of the first voltage terminal VDD on the light emitting brightness of the light emitting device 100 is avoided, and the problem of non-uniform dynamic picture brightness is avoided.

(5) The second storage submodule 62 of the pixel circuit provided in the embodiment of the present application is electrically connected between the first voltage terminal VDD and the first node N1, and compensates the threshold voltage Voled _ th of the light emitting element 100 into the pixel circuit in a required ratio, so that the requirements of a plurality of EL devices (light emitting elements 100) can be satisfied, that is, the compensation amount can be controlled by changing the capacitance ratio of the first capacitor C1 and the second capacitor C2, so that the pixel circuit can be applied to a plurality of materials of the EL devices, that is, the embodiment of the present application can provide a targeted compensation value for different characteristics of the EL devices. And only two scanning signal lines (namely, the first scanning signal line S1 and the second scanning signal line S2) and one light-emitting control signal line EM are adopted, so that the compensation of the pixel circuit can be completed, the number of the signal lines on the display Panel is reduced, the display Panel has a looser wiring space, and the Panel design is simplified.

(6) The display panel that this application embodiment provided, adopt the novel technology of present advanced supplementary negative pole, with voltage transmission line (VSS voltage line), pixel circuit and light emitting component 100 all set up on same backplate, introduce voltage transmission line (VSS voltage line) in pixel circuit's wiring, whole face evaporation plating before having replaced, make VSS voltage can participate in pixel circuit's compensation, IR drop on the VSS voltage line has been avoided producing the influence to light emitting component 100 life-span compensation, the life-span of light emitting component 100 has been prolonged, and simultaneously, the length of voltage transmission line on the display panel has been reduced, make the display panel have more loose wiring space, thereby optimize display device's design space, be convenient for display device can realize higher resolution ratio.

Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

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Pixel circuit, driving method thereof, display panel and display device

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