阅读说明：本技术 一种sram型fpga用户寄存器单粒子翻转故障注入方法 (SRAM (static random Access memory) type FPGA (field programmable Gate array) user register single event upset fault injection method ) 是由 周东 汪路元 王翠莲 冯国平 刘崇华 曾连连 翟君武 吴伟 张溢 李珂 庞波 于 2021-07-27 设计创作，主要内容包括：本发明公开一种SRAM型FPGA用户寄存器单粒子翻转故障注入方法,能够对SRAM型FPGA用户寄存器中的暂存值进行直接的修改,实现SRAM型FPGA用户寄存器的单粒子翻转故障的模拟。包括：分析用户寄存器控制参数的真值表,获得将用户寄存器直接设置为“0”或“1”的控制参数的真值表项。通过FPGA Editor工具修改网表文件中控制参数设置值,对比修改前后的配置码流,获得FPGA寄存器控制参数在配置位流中的准确偏移量。结合XDL文件中的寄存器X、Y坐标信息,得到FPGA代码中感兴趣寄存器的准确偏移量。从而可以通过SelcetMap或JTAG接口对感兴趣寄存器进行快速故障注入。大幅度提高SRAM型FPGA单粒子翻转故障注入效率和准确度,更有效地识别FPGA中用户寄存器单粒子翻转防护中的隐患。(The invention discloses a single event upset fault injection method for an SRAM (static random access memory) type FPGA (field programmable gate array) user register, which can directly modify a temporary storage value in the SRAM type FPGA user register and realize the simulation of the single event upset fault of the SRAM type FPGA user register. The method comprises the following steps: and analyzing the truth table of the control parameters of the user register to obtain a truth table entry of the control parameters for directly setting the user register to be 0 or 1. And modifying the set value of the control parameter in the netlist file through an FPGA Editor tool, and comparing the modified configuration code stream to obtain the accurate offset of the control parameter of the FPGA register in the configuration bit stream. And combining the coordinate information of the register X, Y in the XDL file to obtain the accurate offset of the interested register in the FPGA code. So that fast fault injection can be performed on the register of interest through the SelcetMap or JTAG interface. The single event upset fault injection efficiency and accuracy of the SRAM type FPGA are greatly improved, and hidden dangers in single event upset protection of a user register in the FPGA are effectively identified.)

1. A single event upset fault injection method for an SRAM type FPGA user register is characterized by comprising the following steps:

analyzing a truth table of a reset initial value parameter and a reset polarity parameter in an FPGA user register to obtain a truth table entry which can directly set a temporary storage value of the user register to be 0 or 1;

acquiring the offset of the initial reset value parameter and the reset polarity parameter of the user register in the configuration bit stream data;

obtaining the fault bit stream offset of the interested register through X, Y coordinate information of the interested user register and the bit stream offset relation of the reset initial value parameter and the reset polarity parameter of the user register;

and performing single event upset fault injection on the user register according to the fault bit stream offset of the interested register.

2. The single event upset fault injection method for the SRAM type FPGA user register as claimed in claim 1, wherein the truth tables of the reset initial value parameter and the reset polarity parameter are specifically:

TABLE 1 user register truth table

3. The method for injecting the single event upset fault into the user register of the SRAM type FPGA as claimed in claim 1 or 2, wherein the offset of the reset initial value parameter in the configuration bit stream data is obtained by the following steps:

(a) compiling an original use case in an FPGA development environment ISE, generating original configuration bit stream data by using a BitGen tool, and marking the original configuration bit stream data as configuration data 1;

(b) in an FPGA development environment ISE, opening an FPGA Editor tool, browsing and finding a target register, and opening an internal structure diagram of the target register;

(c) setting the attribute of the FPGA Editor to be in an editable state;

(d) modifying the reset initial value parameter and setting the reset initial value parameter to be in a state opposite to the original state;

(e) saving the setting state, generating configuration bit stream data through an ISE BitGen tool, and marking the configuration bit stream data as configuration data 2;

(f) comparing the data of the configuration data 1 and the configuration data 2 bit by bit to obtain the offset of the initial reset value parameter in the configuration bit stream data, and marking the offset as SR _ offset;

(g) and (3) finding the user registers of adjacent lines and columns in the FPGA Editor, repeating the steps (a) to (f), and obtaining the offset of the initial reset parameter of the adjacent lines and columns in the configuration bit stream.

4. The single-event upset fault injection method for the SRAM type FPGA user register as claimed in claim 3, wherein the register offset values in four directions, i.e. SR _ offset _ Up, SR _ offset _ Down, SR _ offset _ Left, and SR _ offset _ Right, are adjacent, and the increment of the offset values of the adjacent row and column control parameters is obtained according to SR _ offset, SR _ offset _ Up, SR _ offset _ Down, SR _ offset _ Left, and SR _ offset _ Right, and then the offset values of the reset initial value parameters in the configuration bit stream data in all the user registers are calculated.

5. The method for injecting the single event upset fault into the user register of the SRAM type FPGA as claimed in claim 1 or 2, wherein the offset of the reset polarity parameter in the configuration bit stream data is obtained by the following steps:

(a) compiling an original use case in an FPGA development environment ISE, generating original configuration bit stream data by using a BitGen tool, and marking the original configuration bit stream data as configuration data 3;

(b) in an FPGA development environment ISE, opening an FPGA Editor tool, browsing and finding a target register, and opening an internal structure diagram of the target register;

(c) setting the attribute of the FPGA Editor to be in an editable state;

(d) modifying the reset polarity parameter and setting the reset polarity parameter to be in a state opposite to the original state; when the original setting value is SR, the SR is modified to SR _ B, and when the original setting value is SR _ B, the SR is modified to SR;

(e) saving the setting state, generating configuration bit stream data through an ISE BitGen tool, and marking the configuration bit stream data as configuration data 4;

(f) comparing the data of the configuration data 3 and the configuration data 4 bit by bit to obtain the offset of the reset polarity parameter in the configuration bit stream data, which is marked as POL _ offset;

(g) and (3) finding user registers of adjacent lines and columns in the FPGA Editor, repeating the steps (a) to (f), and obtaining the offset of the adjacent register reset polarity parameters in the configuration bit stream.

6. The method for injecting single event upset fault into the SRAM type FPGA user register as claimed in claim 5, wherein the adjacent register offset values in four directions of Up, Down, Left and Right are labeled as POL _ offset _ Up, POL _ offset _ Down, POL _ offset _ Left, POL _ offset _ Right; and obtaining the increment of the offset of the adjacent row and column control parameters according to POL _ offset, POL _ offset _ Up, POL _ offset _ Down, POL _ offset _ Left and POL _ offset _ Right, and then calculating the offset of the reset polarity parameter in the configuration bit stream data in all the user registers.

7. The method for injecting the single event upset fault into the user register of the SRAM type FPGA as claimed in claim 1 or 2, wherein the obtaining of the fault bit stream offset of the register of interest specifically comprises the following steps:

(a) acquiring the name of the register of the interested user from the source code;

(b) converting the FPGA engineering netlist ngc file into an XDL file format through an XDL.exe tool carried by the ISE;

(c) finding an XDL file in an engineering folder of an FPGA compiling environment, opening the XDL file through a text table editor, inquiring layout information in an interested user register in the XDL file, and obtaining X, Y coordinate information of the interested user register;

(d) and acquiring the fault bit stream offset required by fault injection of the user register of interest in the FPGA code according to the X, Y coordinate information of the user register of interest and the bit stream offset relation of the initial reset value parameter and the reset polarity parameter of the user register.

8. The method for injecting the single event upset fault into the user register of the SRAM type FPGA as claimed in claim 1 or 2, wherein the fault injection adopts a fault injector to inject the configuration data into the SRAM type FPGA through an injection interface.

9. The method of claim 8, wherein the injection configuration data comprises original configuration data and fault configuration data, and is used to compare the working state of the FPGA under normal conditions and abnormal conditions.

10. The method for single event upset fault injection into custom registers of an SRAM-type FPGA of claim 8 or 9, wherein the injection interface comprises a SelectMap and JTAG interface.

Technical Field

The invention belongs to the technical field of satellite electronic systems, and relates to a single event upset fault injection method for an SRAM (static random access memory) type FPGA (field programmable gate array) user register.

Background

In order to meet the requirements of large capacity, high speed, complex information processing, on-orbit reconfigurable and the like, a large number of SRAM type FPGAs are adopted in the conventional satellite electronic system. The SRAM type FPGA belongs to a single-particle sensitive device, and a single-particle effect protection measure must be taken.

Typical safeguards currently taken for SRAM type FPGAs in satellite electronics systems are timing refresh and triple modular redundancy. In the engineering implementation process, situations often occur in which the protective measures are not in place, such as: (1) the design of the refreshing function has hidden troubles, which causes the situations of non-refreshing, incomplete refreshing or error refreshing; (2) the triple modular redundancy design has defects, so that the triple modular redundancy design of an important register is incomplete; (3) the function requirements of the FPGA are more and more complex, but the FPGA resources are limited, and only part of important registers can be selected for carrying out triple modular redundancy design. And the important registers obtained by manual evaluation may have deviation, which results in omission of the important registers and causes a certain degree of hidden danger of single event upset.

And the potential design hazard can be identified by carrying out an SRAM type FPGA single-particle fault injection test. In the single-particle fault injection system in the prior art, a configuration data fault code stream is injected into an SRAM type FPGA sequentially or randomly mainly by means of a SelectMap or JTAG interface. The configuration data mainly corresponds to information such as a logic circuit and a communication state in the FPGA, and the temporary storage value of the user register cannot be accurately and quickly changed through a configuration data sequence or a random injection mode. No relevant information for directly carrying out fault injection on an SRAM type FPGA user register exists in the prior published documents.

Disclosure of Invention

The invention discloses a single event upset fault injection method for an SRAM (static random access memory) type FPGA (field programmable gate array) user register, which can directly modify a temporary storage value in the SRAM type FPGA user register and realize the simulation of the single event upset fault of the SRAM type FPGA user register.

The invention is realized by the following technical scheme.

A single event upset fault injection method for an SRAM type FPGA user register comprises the following steps:

analyzing a truth table of a reset initial value parameter and a reset polarity parameter in an FPGA user register to obtain a truth table entry which can directly set a temporary storage value of the user register to be 0 or 1;

acquiring the offset of the initial reset value parameter and the reset polarity parameter of the user register in the configuration bit stream data;

obtaining the fault bit stream offset of the interested register through X, Y coordinate information of the interested user register and the bit stream offset relation of the reset initial value parameter and the reset polarity parameter of the user register;

and performing single event upset fault injection on the user register according to the fault bit stream offset of the interested register.

The invention has the beneficial effects that:

the invention can obtain the control parameter truth value table entry which directly sets the user register to be 0 or 1. Accurate offsets of FPGA register control parameters in the configuration bit stream can be obtained. And combining the coordinate information of the register X, Y in the XDL file to obtain the accurate offset of the interested register in the FPGA code. So that fast fault injection can be performed on the register of interest through the SelcetMap or JTAG interface. The single event upset fault injection efficiency and accuracy of the SRAM type FPGA are greatly improved, and hidden dangers in single event upset protection of a user register in the FPGA are effectively identified.

Drawings

FIG. 1 is a flow chart of a single event upset fault injection method for an SRAM type FPGA user register of the present invention;

FIG. 2 is a diagram illustrating a basic structure of a user register in accordance with an embodiment of the present invention;

FIG. 3 is a flow chart of user register single event upset fault injection in an embodiment of the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

As shown in fig. 1, a method for injecting a single event upset fault into a user register of an SRAM-type FPGA of the present embodiment includes:

analyzing a truth table of a reset initial value parameter and a reset polarity parameter in an FPGA user register to obtain a truth table entry which can directly set a temporary storage value of the user register to be 0 or 1;

in specific implementation, the user registers in the SRAM-type FPGA are distributed in Slice, IOB, and other components in the FPGA. The basic structure of the user register is shown in fig. 2. The user register has a reset signal control terminal SR, and there is a reset signal polarity control element at the upstream of the SR control terminal for controlling the polarity of the SR signal, i.e. determining whether it is a high level reset or a low level reset, and the control parameter selectable setting value of the polarity control element is: SR, SR _ B, which parameter may be named reset polarity parameter. The user register comprises a reset initial value parameter for setting the default value of the user register during the reset, and the optional setting values of the control parameter are as follows: SRHIGH, SRLOW.

When the user register normally operates, the reset signal control end SR is in a non-reset state, and at the moment, the reset polarity parameter is inverted: (1) when the original set value is SR, it is modified to SR _ B, and (2) when the original set value is SR _ B, it is modified to SR, then the reset control end SR of the user register can be set to reset state. And then, SRLOW or SRHIGH is selected by modifying the reset initial value parameter. The user register may be set to a desired '0' or '1'.

Table 1 below shows a truth table of the user register with respect to the reset initial value parameter and the reset polarity parameter. The user register temporary value may be set to "0" by entries 3 and 4 of the table, and may be set to "1" by entries 7 and 8 of the table.

TABLE 1 user register truth table

Acquiring the offset of a reset initial value parameter and a reset polarity parameter of a user register in configuration bit stream data;

in this embodiment, the offset of the reset initial value parameter in the configuration bitstream is obtained by the following steps:

(a) compiling an original use case in an FPGA development environment ISE, generating original configuration bit stream data by using a BitGen tool, and marking the original configuration bit stream data as configuration data 1;

(b) in an FPGA development environment ISE, opening an FPGA Editor tool, browsing and finding a target register, and opening an internal structure diagram of the target register;

(c) setting the attribute of the FPGA Editor to be in an editable state;

(d) modifying the reset initial value parameter and setting the reset initial value parameter to be in a state opposite to the original state; that is, when it is originally SRHIGH, it is modified to SRLOW. When the original SRLOW is SRHIGH, the SRLOW is modified into SRHIGH;

(e) saving the setting state, generating configuration bit stream data through an ISE BitGen tool, and marking the configuration bit stream data as configuration data 2;

(f) comparing the data of the configuration data 1 and the configuration data 2 bit by bit to obtain the offset of the initial reset value parameter in the configuration bit stream data, and marking the offset as SR _ offset;

(g) and (3) finding the user registers of adjacent lines and columns in the FPGA Editor, repeating the steps (a) to (f), and obtaining the offset of the initial reset parameter of the adjacent lines and columns in the configuration bit stream.

In a specific implementation, the register offset amounts in the adjacent Up, Down, Left and Right directions are marked as SR _ offset _ Up, SR _ offset _ Down, SR _ offset _ Left and SR _ offset _ Right, and the offset amount of the adjacent row and column control parameter is obtained according to the SR _ offset, SR _ offset _ Up, SR _ offset _ Down, SR _ offset _ Left and SR _ offset _ Right, so as to calculate the offset amount of the reset initial value parameter in the configuration bit stream data in all the user registers.

In this embodiment, the offset of the reset polarity parameter in the configuration bitstream data is obtained by the following steps:

(a) compiling an original use case in an FPGA development environment ISE, generating original configuration bit stream data by using a BitGen tool, and marking the original configuration bit stream data as configuration data 3;

(b) in an FPGA development environment ISE, opening an FPGA Editor tool, browsing and finding a target register, and opening an internal structure diagram of the target register;

(c) setting the attribute of the FPGA Editor to be in an editable state;

(d) modifying the reset polarity parameter and setting the reset polarity parameter to be in a state opposite to the original state; namely, when the original setting value is SR, the SR is modified to SR _ B, and when the original setting value is SR _ B, the SR is modified to SR;

(e) saving the setting state, generating configuration bit stream data through an ISE BitGen tool, and marking the configuration bit stream data as configuration data 4;

(f) comparing the data of the configuration data 3 and 4 bit by bit, the offset of the reset polarity parameter in the configuration bit stream data, labeled POL _ offset, can be obtained.

(g) And (3) finding user registers of adjacent lines and columns in the FPGA Editor, repeating the steps (a) to (f), and obtaining the offset of the adjacent register reset polarity parameters in the configuration bit stream.

In a specific implementation, the register offset amounts in the adjacent Up, Down, Left, and Right directions are denoted by POL _ offset _ Up, POL _ offset _ Down, POL _ offset _ Left, and POL _ offset _ Right. And obtaining the increment of the offset of the adjacent row and column control parameters according to POL _ offset, POL _ offset _ Up, POL _ offset _ Down, POL _ offset _ Left and POL _ offset _ Right, and then calculating the offset of the reset polarity parameter in the configuration bit stream data in all the user registers.

And step three, obtaining the fault bit stream offset of the interested register through X, Y coordinate information of the interested user register and the bit stream offset relation of the user register reset initial value parameter and the reset polarity parameter.

In this embodiment, the method specifically includes the following steps:

(a) acquiring the name of an interested user register from an FPGA source code;

(b) converting the FPGA engineering netlist ngc file into an XDL file format through an XDL.exe tool carried by the ISE; an example of a transition command is: xdl-ncd2 xdlfiliname.ncdfiliname.xdl;

(c) finding an XDL file in an engineering folder of an FPGA compiling environment, opening the XDL file through a text table editor, inquiring layout information in an interested user register in the XDL file, and obtaining X, Y coordinate information of the interested user register; register coordinate information example in XDL file: inst ' reg ' slide ', place R20C36 slide _ X71Y88, which represents the reg coordinate information of the register as X:71 abscissa and Y:88 ordinate;

(d) and acquiring the fault bit stream offset required by fault injection of the user register of interest in the FPGA code according to the X, Y coordinate information of the user register of interest and the bit stream offset relation of the initial reset value parameter and the reset polarity parameter of the user register.

And fourthly, performing single event upset fault injection on the user register according to the fault bit stream offset of the interested register.

As shown in fig. 3, in the present embodiment, the fault injection uses a fault injector to inject configuration data into the SRAM-type FPGA through an injection interface.

The injection configuration data comprises original configuration data and fault configuration data and is used for comparing the working state of the FPGA under normal conditions and abnormal conditions; the inject interfaces include the SelectMap and JTAG interfaces.

In specific implementation, the first step and the second step are only carried out once, and the third step and the fourth step can be repeatedly carried out.

In summary, the above is merely a typical example of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.