IGBT device structure and process method
阅读说明：本技术 Igbt器件的结构及工艺方法 (IGBT device structure and process method ) 是由 王晓军 马庆海 胡杰 于 2021-08-31 设计创作，主要内容包括：本发明公开了一种IGBT器件结构及其工艺方法,所述器件的背面金属上方为集电区,集电区上方为场终止层,场终止层上方为基区；在所述衬底的上表面的浅层为体区,沟槽的底部位于基区中,沟槽内填充多晶硅层形成沟槽型栅极,所述衬底的上表面覆盖金属层；靠近体区的基区中具有一层正面缺陷区,靠近场终止层的基区中具有一层背面缺陷区。本发明通过正面及背面的可控深度制造缺陷,控制正面及背面载流子寿命；这样在关断的过程中,载流子寿命有限,电流很快就下降为零。注入缺陷后,正面部分区域的电阻偏小,电流很快就上升到饱和区域,开通时间变小,在开通和关断过程中损耗变少。(The invention discloses an IGBT device structure and a process method thereof, wherein a collector region is arranged above metal on the back surface of the device, a field stop layer is arranged above the collector region, and a base region is arranged above the field stop layer; the shallow layer on the upper surface of the substrate is a body region, the bottom of the trench is positioned in the base region, the trench is filled with a polycrystalline silicon layer to form a trench type grid, and the upper surface of the substrate is covered with a metal layer; the base region close to the body region is provided with a front defect region, and the base region close to the field stop layer is provided with a back defect region. The invention controls the service life of the front and back carriers by manufacturing the defects with controllable depth on the front and back; thus, during the turn-off process, the carrier lifetime is limited and the current quickly drops to zero. After defects are injected, the resistance of the front part area is smaller, the current quickly rises to a saturation area, the turn-on time is shortened, and the loss is reduced in the turn-on and turn-off processes.)
1. An IGBT device structure characterized in that: the device is formed in a semiconductor substrate, on a section plane of the semiconductor substrate, the substrate is defined to be provided with an upper surface and a lower bottom surface, and the horizontal direction vertical to the longitudinal direction of the upper surface and the lower bottom surface is the left side and the right side; in the longitudinal direction of the device, the lowest layer, namely the lower bottom surface, is back metal, a collector region is arranged above the back metal, a field stop layer is arranged above the collector region, and a base region is arranged above the field stop layer; the shallow layer on the upper surface of the substrate is a body region of a first conduction type, the body region comprises a plurality of second conduction type heavily doped regions which are arranged at equal intervals, and the second conduction type heavily doped regions are positioned on the shallow layer of the body region;
a plurality of parallel trenches respectively penetrate through the heavily doped region and the body region, the bottoms of the trenches are positioned in the base region, polysilicon layers are filled in the trenches to form trench type gates, and the upper surface of the substrate is covered with a metal layer;
in the substrate, a base region close to the body region is provided with a front defect region, and a base region close to the field stop layer is provided with a back defect region.
2. The IGBT device structure of claim 1, wherein: the base region is a second conductive type lightly doped region.
3. The IGBT device structure of claim 1, wherein: the front defect area is a hydrogen ion injection layer with controllable injection depth, the service life of front current carriers is controlled through the front defect area, the resistance is reduced, the current is accelerated to rise to a saturation area, and the turn-on time is shortened.
4. The IGBT device structure of claim 1, wherein: the back defect area is a hydrogen ion injection layer with controllable injection depth, the service life of a back carrier is controlled through the back defect area, and when the IGBT device is turned off, the current is rapidly reduced to zero.
5. The IGBT device structure of claim 1, wherein: the first conduction type is P type, and the second conduction type is N type; or the foregoing definitions may be altered to the opposite type.
6. The process method for manufacturing the IGBT device structure according to claim 1, characterized in that: comprises the following process steps:
the first step, providing a wafer, and forming a layer of silicon dioxide on the front surface of the wafer;
secondly, opening a region to be corroded by photoetching and etching processes;
thirdly, after the groove is etched, growing another layer of oxide film on the surface of the silicon;
fourthly, growing a layer of polycrystalline silicon layer on the surface of the oxide film;
fifthly, coating photoresist, exposing the polysilicon pattern, developing, carrying out etching with a photoetching plate, and forming a polysilicon gate;
sixthly, growing an insulating film on the surface of the wafer;
seventhly, carrying out photoresist exposure and etching processes to open an etching window of the contact hole region;
eighthly, after the insulating film is etched, removing the photoresist, further etching the contact hole, and etching the substrate;
ninth, impurity ion implantation is carried out to form a contact area;
tenth, carrying out a forming process of the interconnection metal to form a metal film layer of the interconnection metal;
step ten, carrying out a photoetching development process of the metal film layer, carrying out a wet or dry etching process with the photoresist, and forming metal interconnection;
a twelfth step of depositing a passivation layer;
step ten, performing polyimide coating, and forming a polyimide protective layer after exposure and development;
fourteenth, hydrogen ion implantation is carried out on the front surface of the wafer to form a front surface defect area;
fifteenth, thinning the back of the wafer;
sixthly, performing ion implantation on the back of the wafer, and activating to form a back anode;
seventeenth, hydrogen ion implantation is carried out on the back of the wafer to form a back defect area;
eighteen, performing furnace tube activation well pushing on the wafer completely to form a front defect area and a back defect area with controllable depths;
and nineteenth step, forming service life control on the front surface and the back surface local area.
7. The process method of the IGBT device structure of claim 6, characterized in that: in the first step, the silicon dioxide layer is used as a barrier layer for etching the groove, the thickness of the silicon oxide layer is 1-2 um, and the silicon oxide layer is formed by adopting a field oxygen process.
8. The process method of the IGBT device structure of claim 6, characterized in that: in the third step, the oxide film is used as a gate oxide film and is formed by adopting a high-temperature furnace tube process at the temperature of more than 1000 ℃, and the thickness of the oxide film is 800-1500A.
9. The process method of the IGBT device structure of claim 6, characterized in that: in the fourth step, the thickness of the polycrystalline silicon is 8000-15000A.
10. The process method of the IGBT device structure of claim 6, characterized in that: in the fifth step, the width of the polysilicon formed by etching is 1-4 um.
11. The process method of the IGBT device structure of claim 6, characterized in that: in the sixth step, a furnace tube process and a CVD process are adopted in the insulating film forming process, and the thickness of the formed insulating film is 1-2 um.
12. The process method of the IGBT device structure according to claim 11, characterized in that: the insulating film is a silicon oxide film or a silicon nitride film.
13. The process method of the IGBT device structure of claim 6, characterized in that: and in the eighth step, the silicon substrate is continuously etched downwards in the contact hole window opened by the insulating film, and the etching depth of the silicon substrate is 0.2-0.5 um.
14. The process method of the IGBT device structure of claim 6, characterized in that: in the ninth step, the implanted impurity of the contact region is arsenic, and the doping concentration is 1E 19-5E 20CM-3(ii) a The depth of the contact region in the silicon substrate is 0.2-0.5 um.
15. The process method of the IGBT device structure of claim 6, characterized in that: in the tenth step, the thickness of the metal film layer is 1-5 um, and the metal film layer is formed by adopting a sputtering process.
16. The process method of the IGBT device structure of claim 6, characterized in that: in the tenth step, after the metal sputtering reaches the designed thickness, the photoetching development and etching process is carried out, and the photoresist is carried to carry out the wet or dry etching process to pattern the metal so as to form the metal interconnection.
17. The process method of the IGBT device structure of claim 6, characterized in that: in the tenth step, the passivation layer is a silicon nitride layer, and the thickness of the passivation layer is 100-1000A.
18. The process method of the IGBT device structure of claim 6, characterized in that: in the fourteenth step, the energy of hydrogen ion implantation is 1-3 MEV, and the dose is 1E 11-2E 12CM-2In the meantime.
19. The process method of the IGBT device structure of claim 6, characterized in that: in the fifteenth step, the thinning thickness of the back of the wafer is 50-120 um.
20. The process method of the IGBT device structure of claim 6, characterized in that: and in the sixteenth step, boron ion implantation is carried out on the back surface of the wafer, and then a laser activation process is carried out.
21. The process method of the IGBT device structure of claim 6, characterized in that: in the seventeenth step, the energy of the implantation of the hydrogen ions is 1-3 MEV, and the dosage is 1E 11-2E 12CM-2In the meantime.
Technical Field
The invention relates to the field of semiconductor devices, in particular to a structure of an IGBT device.
The invention also relates to a process method of the IGBT device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a darlington structure semiconductor power electronic device integrating the Gate voltage control characteristic of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a Bipolar Junction Transistor (BJT), has the characteristics of voltage control, large input impedance, small driving power, small on resistance, low switching loss, high working frequency and the like, is an ideal semiconductor power switching device, has a switching frequency of between 10K and 100K hertz, and has wide development and application prospects. In the function of the IGBT power device, the speed of switching and the corresponding switching loss are important indexes for evaluating the performance of the IGBT. At present, phosphorus or hydrogen ions are injected into the back surface, and a back surface field stop layer is formed through high-temperature long-time well pushing to reduce turn-off loss, but the static index on-state voltage is inevitably larger due to the fact that the back surface field stop layer is thicker and thicker. In addition, the turn-on loss of the front side of the IGBT needs to be further reduced, and no better method exists.
At present, with the higher and higher current density requirement of the IGBT, the on-state current of the device is also larger and larger. The losses of the device are increasing. The difficulty of balancing the dynamic loss and the static loss is higher and higher. In order to improve the dynamic loss, it is common practice to inject phosphorus ions or hydrogen ions into the back surface of the IGBT, and then form a field stop layer with a certain depth after the phosphorus ions or hydrogen ions pass through the high-temperature drive-in well, so as to combine holes emitted from the back surface when the IGBT is turned off, reduce the back surface emission efficiency, and achieve the purpose of reducing turn-off loss.
The existing semiconductor device, especially for products with more than 100A of large current, has large on-loss and off-loss due to large current, and is difficult to be compromised with the on-loss. Since there is a problem that only the back surface is less than one tenth of the entire length in the process of passing a current through the entire substrate from the back surface to the front surface, the back surface emission efficiency is reduced by the field stop layer, and the turn-off loss is reduced. This approach has a limited compromise and tends to increase Vcesat (saturated pressure drop). In the aspect of turn-on loss, no better method is provided in the process, and the turn-on loss can be reduced only by reducing the input resistance in the design, but turn-on current overshoot is easily caused, so that the use safety of the device is influenced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an IGBT device with lower switching loss.
The invention also provides a process method of the IGBT device.
The IGBT device structure is formed in a semiconductor substrate, the substrate is defined to be provided with an upper surface and a lower bottom surface on a section plane of the semiconductor substrate, and the horizontal direction vertical to the longitudinal direction of the upper surface and the lower bottom surface is the left side and the right side; in the longitudinal direction of the device, the lowest layer, namely the lower bottom surface, is back metal, a collector region is arranged above the back metal, a field stop layer is arranged above the collector region, and a base region is arranged above the field stop layer; the shallow layer on the upper surface of the substrate is a body region of a first conduction type, the body region comprises a plurality of second conduction type heavily doped regions which are arranged at equal intervals, and the second conduction type heavily doped regions are located on the shallow surface layer of the body region.
And a plurality of parallel grooves respectively penetrate through the heavily doped region and the body region, the bottoms of the grooves are positioned in the base region, polycrystalline silicon layers are filled in the grooves to form groove type grid electrodes, and the upper surface of the substrate is covered with a metal layer.
In the substrate, a base region close to the body region is provided with a front defect region, and a base region close to the field stop layer is provided with a back defect region.
In a further improvement, the base region is a second conductive type lightly doped region.
The further improvement is that the front defect area is a hydrogen ion injection layer with controllable injection depth, the service life of front carriers is controlled through the front defect area, the resistance is reduced, the current is accelerated to rise to a saturation area, and the turn-on time is reduced.
The further improvement is that the back defect area is a hydrogen ion injection layer with controllable injection depth, the back carrier service life is controlled by the back defect area, and when the IGBT device is turned off, the current is rapidly reduced to zero.
The further improvement is that the first conductive type is P type, and the second conductive type is N type; or the foregoing definitions may be altered to the opposite type.
The process method of the IGBT device structure comprises the following process steps:
the first step, providing a wafer, and forming a layer of silicon dioxide on the front surface of the wafer;
secondly, opening a region to be corroded by photoetching and etching processes;
thirdly, after the groove is etched, growing another layer of oxide film on the surface of the silicon;
fourthly, growing a layer of polycrystalline silicon layer on the surface of the oxide film;
fifthly, coating photoresist, exposing the polysilicon pattern, developing, carrying out etching with a photoetching plate, and forming a polysilicon gate;
sixthly, growing an insulating film on the surface of the wafer;
seventhly, carrying out photoresist exposure and etching processes to open an etching window of the contact hole region;
eighthly, after the insulating film is etched, removing the photoresist, further etching the contact hole, and etching the substrate;
ninth, impurity ion implantation is carried out to form a contact area;
tenth, carrying out a forming process of the interconnection metal to form a metal film layer of the interconnection metal;
step ten, carrying out a photoetching development process of the metal film layer, carrying out a wet or dry etching process with the photoresist, and forming metal interconnection;
a twelfth step of depositing a passivation layer;
step ten, performing polyimide coating, and forming a polyimide protective layer after exposure and development;
fourteenth, hydrogen ion implantation is carried out on the front surface of the wafer to form a front surface defect area;
fifteenth, thinning the back of the wafer;
sixthly, performing ion implantation on the back of the wafer, and activating to form a back anode;
seventeenth, hydrogen ion implantation is carried out on the back of the wafer to form a back defect area;
eighteen, performing furnace tube activation well pushing on the wafer completely to form a front defect area and a back defect area with controllable depths;
and nineteenth step, forming service life control on the front surface and the back surface local area.
The further improvement is that in the first step, the silicon dioxide layer is used as a barrier layer for groove etching, the thickness of the silicon oxide layer is 1-2 um, and the silicon oxide layer is formed by adopting a field oxygen process.
In a further improvement, in the third step, the oxide film is used as a gate oxide film and is formed by a high-temperature furnace tube process at a temperature of more than 1000 ℃, and the thickness of the oxide film is 800-1500A.
In a further improvement, in the fourth step, the thickness of the polycrystalline silicon is 8000-15000A.
In a further improvement, in the fifth step, the width of the polysilicon formed by etching is 1-4 um.
The further improvement is that, in the sixth step, the furnace tube process and the CVD process are adopted in the insulating film forming process, and the thickness of the formed insulating film is 1-2 um.
In a further improvement, the insulating film is a silicon oxide film or a silicon nitride film.
The further improvement is that, in the eighth step, the silicon substrate is continuously etched downwards in the contact hole window opened by the insulating film, and the etching depth of the silicon substrate is 0.2-0.5 um.
In a further improvement, in the ninth step, the implantation impurity of the contact region is arsenic, and the doping concentration is 1E 19-5E 20CM-3(ii) a The depth of the contact region in the silicon substrate is 0.2-0.5 um.
The further improvement is that, in the tenth step, the thickness of the metal film layer is 1-5 um, and the metal film layer is formed by adopting a sputtering process.
In the tenth step, after the metal sputtering reaches the designed thickness, the photoetching development and etching process is carried out, and the metal is patterned by carrying out the wet or dry etching process with the photoresist to form the metal interconnection.
In a further improvement, in the tenth step, the passivation layer is a silicon nitride layer with a thickness of 100-1000A.
In a further improvement, in the fourteenth step, the energy of the hydrogen ion implantation is 1-3 MEV, and the dose is 1E 11-2E 12CM-2In the meantime.
In a further improvement, in the fifteenth step, the thinning thickness of the back surface of the wafer is 50-120 um.
In a further improvement, in the sixteenth step, boron ion implantation is performed on the back surface of the wafer, and then a laser activation process is performed.
In a further improvement, in the seventeenth step, the energy of implantation of hydrogen ions is 1-3 MEV, and the dosage is 1E 11-2E 12CM-2In the meantime.
The invention has the advantages that the defect can be manufactured in a controllable depth on the front side and the service life of a front carrier can be controlled by implanting hydrogen ions with controllable distance on the front side and implanting hydrogen ions with controllable distance on the back side; defects are made at a controlled depth on the back surface to control the back carrier lifetime. Thus, during the turn-off process, the carrier lifetime is limited and the current quickly drops to zero. After defects are injected, the resistance of the front part area is smaller, the current quickly rises to a saturation area, the turn-on time is shortened, and the loss is reduced in the turn-on and turn-off processes. The process method has less influence on the whole resistance of the substrate from the front surface to the back surface, so the process method has less influence on the whole on-state voltage and has less influence on the on-off loss.
Drawings
Fig. 1 is a sectional structure view of a trench gate insulated gate bipolar transistor IGBT according to the present invention.
FIG. 2 is a flow chart of the process steps of the present invention.
Description of the reference numerals
1 is the back metal, 2 is the collector region (P-type), 3 is the field stop layer (N +), 4 is the base region (N-), 5 is the second P-type body region, 6 is the polysilicon gate, 7 is the heavily doped region, 8 is the metal, 9 is the front defect region, and 10 is the back defect region.
Detailed Description
The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
The existing IGBT device has the problems that in the process that current passes through the whole substrate from the back surface to the front surface, only the back surface is less than one tenth of the whole length, the back surface emission efficiency is reduced through the field stop layer, and the turn-off loss is reduced. This approach has a limited compromise and tends to increase Vcesat. In the aspect of turn-on loss, no better method is provided in the process, and the turn-on loss can be reduced only by reducing the input resistance in the design, but turn-on current overshoot is easily caused, so that the use safety of the device is influenced.
The invention provides an IGBT device, as shown in FIG. 1, on a cross-sectional plane of a semiconductor substrate, the substrate has an upper surface and a lower bottom surface in a longitudinal direction. The bottom layer, namely the bottom surface is a back metal 1, a collector region 2 is arranged above the back metal 1, a field stop layer 3 is arranged above the collector region, and an N-type base region 4 is arranged above the field stop layer 3; the shallow layer on the upper surface of the substrate is a P-type body region 5, the body region 5 comprises a plurality of N-type heavily doped regions 7 which are arranged at equal intervals, and the N-type heavily doped regions 7 are positioned on the shallow layer of the body region 5 and close to the surface.
And a plurality of parallel grooves respectively penetrate through the heavily doped region and the body region, the bottoms of the grooves are positioned in the base region, the grooves are filled with a polycrystalline silicon layer to form groove type grid electrodes 6, and the upper surface of the substrate is covered with a metal layer 8.
In the substrate, a front defect region 9 is arranged in the base region 4 close to the body region 5, and a back defect region 10 is arranged in the base region close to the field stop layer. The depth of the front side defect region and the depth of the back side defect region can be controlled through a push-in trap process.
In the structure, the defects can be manufactured in a front-surface controllable depth manner by implanting hydrogen ions with controllable front-surface implantation distance and hydrogen ions with controllable back-surface implantation distance, and the service life of front-surface carriers is controlled; defects are made at a controlled depth on the backside to control backside carrier lifetime. After defects are injected, the resistance of the front part area is smaller, the current quickly rises to a saturation area, the turn-on time is shortened, and the loss is reduced in the turn-on and turn-off processes. During the turn-off process, the carrier lifetime is limited and the current drops quickly to zero.
The device is manufactured by adopting the following process method:
the method comprises the steps of firstly, providing a wafer, and forming a layer of silicon dioxide on the front surface of the wafer by adopting a field oxygen process; when the groove used for forming the grid electrode is etched, the silicon dioxide layer is used as a barrier layer for etching the groove, and the thickness of the silicon dioxide layer is 1-2 um.
And secondly, opening the area to be etched through photoetching and etching processes.
Thirdly, after the groove is etched, growing another layer of oxide film on the surface of the silicon; the oxide film is used as a gate oxide film of a grid electrode in the groove and is formed by adopting a high-temperature furnace tube process at the temperature of more than 1000 ℃, and the forming thickness of the oxide film is 800-1500A. In this embodiment, 1000 a or 1300 a may be formed and determined according to device performance requirements.
Fourthly, growing a layer of polycrystalline silicon layer on the surface of the oxide film; the thickness of the polycrystalline silicon is 8000-15000A, the groove is filled with the polycrystalline silicon, and the polycrystalline silicon is subsequently used for forming a grid electrode.
Fifthly, coating photoresist, exposing the polysilicon pattern, developing, carrying out etching with a photoetching plate, and forming a polysilicon gate; the width of the polysilicon formed by etching is 1-4 um.
Sixthly, growing an insulating film on the surface of the wafer by adopting a furnace tube process and a CVD process; the insulating film can be a silicon oxide film or a silicon nitride film, and the thickness of the formed insulating film is 1-2 um.
And seventhly, carrying out photoresist exposure and etching processes to open the etching window of the contact hole region.
And eighthly, removing the photoresist after the insulating film is etched, further etching the contact hole, and continuously etching the silicon substrate downwards in the contact hole window opened by the insulating film, wherein the etching depth of the silicon substrate is 0.2-0.5 um.
A ninth step of performing doping implantation of N-type impurity ions, such as arsenic, to form a contact region; the doping concentration is 1E 19-5E 20CM-3(ii) a The depth of the contact region in the silicon substrate is 0.2-0.5 um.
Step ten, carrying out a sputtering forming process of the interconnection metal to form a metal film layer of the interconnection metal; the thickness of the metal film layer is 1-5 um.
And the tenth step, carrying out a photoetching development process on the metal film layer, carrying out a wet or dry etching process with the photoresist, and forming metal interconnection.
A twelfth step of depositing a passivation layer; the passivation layer is a silicon nitride layer, and the thickness of the passivation layer is 100-1000A.
And step ten, performing polyimide coating, and forming a polyimide protective layer after exposure and development.
Fourteenth, hydrogen ion implantation is carried out on the front surface of the wafer to form a front surface defect area; the energy of hydrogen ion implantation is 1-3 MEV, and the dose is 1E 11-2E 12CM-2In the meantime.
Fifteenth, thinning the back of the wafer; the thinning thickness of the back of the wafer is 50-120 um.
Sixthly, injecting boron ions into the back of the wafer, and then activating by a laser activation process to form a back anode.
Seventeenth, hydrogen ion implantation is carried out on the back of the wafer to form a back defect area; the energy of hydrogen ion implantation is 1-3 MEV, and the dose is 1E 11-2E 12CM-2In the meantime.
Eighteen, performing furnace tube activation well pushing on the wafer completely to push the front defect area and the back defect area to the expected depth to form the front defect area and the back defect area with controllable depth.
And nineteenth step, forming service life control on the local areas of the front surface and the back surface of the wafer.
The process method has less influence on the whole resistance of the substrate from the front surface to the back surface, so the process method has less influence on the whole on-state voltage and can not increase the on-state voltage by a certain amount. The front defect area has less influence on the turn-on loss, is a hydrogen ion injection layer with controllable injection depth, controls the service life of front carriers through the front defect area, reduces the resistance, accelerates the current to rise to a saturation area, and reduces the turn-on time.
While there have been shown and described what are at present considered to be the fundamental principles of the invention and its essential features and advantages, it will be understood by those skilled in the art that the invention is not limited by the embodiments described above, which are merely illustrative of the principles of the invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.