阅读说明：本技术 高灵敏度矩阵图像传感器 (High sensitivity matrix image sensor ) 是由 倪扬 于 2021-05-28 设计创作，主要内容包括：一种光电传感器,包括一组像素,每个所述像素包括结式光电转换元件和读出电路,所述读出电路包括电容跨阻放大器(CTIA),所述电容跨阻放大器包括一对连接到光电转换元件端子上的N-MOS P-MOS晶体管(C-MOS),以便通过产生输出电压来累积所述光电转换产生的电流,根据本发明,该传感器包括读出电路中每个放大器的控制装置,用于在累积模式下对所述控制装置进行操作,所述控制装置能够在光转换电流累积期间依次启用和禁用,并结合放大器极化电压交替控制和放大器电源电压交替控制,从而降低闪烁噪声并提供高灵敏度。(A photosensor comprising a set of pixels each comprising a junction photoelectric conversion element and a readout circuit comprising a capacitive transimpedance amplifier (CTIA) comprising a pair of N-MOS P-MOS transistors (C-MOS) connected to terminals of the photoelectric conversion element for accumulating a current generated by said photoelectric conversion by generating an output voltage, according to the invention, the sensor comprises control means of each amplifier in the readout circuit for operating said control means in an accumulation mode, said control means being capable of being sequentially enabled and disabled during accumulation of a photoelectric conversion current and combining amplifier polarization voltage alternation control and amplifier supply voltage alternation control, thereby reducing flicker noise and providing high sensitivity.)

1. A photosensor comprising a set of pixels each comprising a junction photoelectric conversion element and a readout circuit comprising a capacitive transimpedance amplifier (CTIA) comprising a pair of N-MOS P-MOS transistors (C-MOS) connected to terminals of the photoelectric conversion element for accumulating a current generated by said photoelectric conversion by generating an output voltage, characterized in that the photosensor comprises control means of each amplifier in the readout circuit for operating the control means in an accumulation mode, the control means being capable of being sequentially enabled and disabled during accumulation of a photoelectric conversion current and combining amplifier polarization voltage alternation control and amplifier supply voltage alternation control, thereby reducing flicker noise and providing high sensitivity.

2. The sensor of claim 1, further comprising a charging capacitor common to a group of pixel readout circuits and external to a pixel, and a switching circuit capable of sequentially connecting the outputs of the group of readout circuits to the common charging capacitor during respective amplifier enable phases.

3. A sensor as claimed in claim 2 in the form of a matrix of rows and columns of pixels, wherein the sensor comprises a charge capacitor common to the readout circuits of the same row or column.

4. A sensor according to any one of claims 1 to 3, further comprising a correlated double sampling Circuit (CDS) connected to each readout circuit output.

Technical Field

The present invention relates generally to hybrid image sensors with Capacitive TransImpedance amplifiers (CTIAs, the english term "Capacitive transfer Amplifier").

And more generally to the basic readout circuitry (e.g., pixel readout circuitry) of such sensors.

Background

It is to be noted that the hybrid image sensor is a detector in which a photoelectric conversion element and a readout circuit are located on two substrates connected together by a conductive micro-bump (english term "micro-bumps").

As shown in fig. 1, the CTIA readout circuit is an active load transfer apparatus using a high-gain voltage amplifier. It comprises an amplifier AMP, an integrating capacitor CINT connected between the amplifier input and output, and a reset transistor RST connected in parallel with the capacitor CINT. The anode of the associated photodiode PD is connected to the input of the amplifier AMP and the cathode is connected to the polarization voltage VSUB.

The photon source current in the diode is denoted by Iph and the output voltage of the amplifier AMP is denoted by Vout.

The transistor RST connects the input and output terminals of the amplifier AMP together before image capturing. This operation eliminates the charge in the integration capacitor CINT. The image capturing is started after the transistor RST is turned off. With the high voltage gain of the amplifier AMP, the input voltage of the AMP is kept substantially constant, and the optical charge generated by the photodiode PD is transferred to the capacitor CINT. At the end of exposure, the output voltage Vout is read out as an image signal.

The read-out circuitry for hybrid Sensors is well outlined in the article written by Eric Fossum and Bedabrata Pain A Review of the Infrared read-out Electronics for Space Science Sensors, State of the Art and Future directives (Review of the Infrared read-out circuitry for Space Science Sensors: recent technology and Future Directions), 1993 in Infrared technologies, Proceedings SPIE 2020. Of all readout circuits, CTIA-based readout circuits are the best choice to implement a high-sensitivity sensor that can operate at low light conditions at real-time video frame rates.

The main reason is that the parasitic capacitance of the photodiode is isolated from the integrating capacitor. High conversion gain can be obtained when the CINT integration capacitance is extremely low. When the voltage gain of the amplifier AMP is sufficiently large, the output voltage of the CTIA can be expressed by the following equation (1):

Vout＝Iph*Texp/CINT

where Texp is the exposure time and Iph is the current generated by the photodiode.

With such a high gain of the amplifier AMP, all the charges generated by the photo-conversion migrate into the capacitor CINT.

As can be seen from equation (1) above, high sensitivity can be obtained with a small capacitance CINT. For example, the value of the capacitance CINT, which makes the voltage of each received elementary charge 160 μ V, can be set to 1fF, which is defined as the pixel conversion gain.

However, if the AMP output noise cannot be reduced, high conversion gain cannot always achieve high sensitivity. This noise at the output of the amplifier AMP is one of the largest limiting factors for the sensitivity of the CTIA pixel. The CTIA pixel detection threshold given in conventional applications is 50 electrons and it is difficult to reduce this threshold below 10-20 electrons. This threshold of 15 μm pixel pitch provides performance that is not satisfactory for demanding applications. If it is desired to reduce the pitch to 5 μm to produce a more economical or higher resolution sensor, it is necessary to reduce this threshold by a factor of 10 to maintain the existing performance. This indicates the importance of reducing the noise at the output of the amplifier AMP.

Disclosure of Invention

The invention aims to improve the sensitivity of a hybrid sensor in CTIA technology by reducing the noise of a readout circuit.

To this end, a photosensor is proposed, which comprises a group of pixels, each pixel comprising a junction-type photoelectric conversion element and a readout circuit, the readout circuit includes a capacitive transimpedance amplifier (CTIA) including a pair of N-MOS P-MOS transistors (C-MOS) connected to terminals of the photoelectric conversion elements so as to accumulate a current generated by the photoelectric conversion by generating an output voltage, characterized in that the photosensor comprises control means for each amplifier in the readout circuit for operating these control means in accumulation mode, these control means are capable of being sequentially enabled and disabled during the accumulation of the photoconversion current in combination with amplifier polarization voltage alternation control and amplifier supply voltage alternation control, thereby reducing flicker noise and providing high sensitivity.

Non-limiting advantageous aspects of such a sensor are as follows:

the sensor further comprises a charging capacitor common to a group of pixel readout circuits and located outside the pixels, and a switching circuit capable of connecting in sequence the outputs of the group of readout circuits to the common charging capacitor during the respective amplifier enabling phase.

The sensor is in the form of a matrix of rows and columns of pixels and comprises a charging capacitor common to the read-out circuits of the same row or column.

-the sensor further comprises a correlated double sampling Circuit (CDS) connected to each readout circuit output.

Drawings

Further aspects, objects and advantages of the invention will be elucidated in the following by means of a preferred embodiment of the invention, given as a non-limitative example, in conjunction with the accompanying drawings. The attached drawings are as follows:

figure 1 is a schematic diagram of a CTIA-type pixel readout circuit of a matrix sensor,

figure 2 is an equivalent diagram of such a sensor with a noisy sound source,

FIG. 3 shows the matrix principle of the CTIA readout circuit of a matrix sensor according to the invention, in which each column shares a charge capacitor,

figure 4 shows a CTIA readout circuit with amplifier enable and disable control functions,

figure 5 shows an example of a circuit for performing enable and disable control,

FIG. 6A is a schematic diagram of a CTIA readout circuit including a disable control modification,

FIG. 6B is a timing diagram of the enable/disable control signals of the circuit of FIG. 6A,

FIG. 7 is a schematic diagram of the CTIA readout circuit of FIG. 6A, additionally having a connection control function to connect the common charge capacitor,

FIG. 8A is a schematic diagram of the readout circuit of FIG. 7, supplemented by a correlated double sampling circuit,

FIG. 8B is a timing diagram of the control signals of the circuit of FIG. 8A,

Detailed Description

The CTIA readout circuit in its simplest form, corresponding to the schematic already described in fig. 1, can be modelled using the equivalent circuit shown in fig. 2. The effect of the transistor RST is to create switching noise in the output in the form of an offset. In practice, this offset can be eliminated by Correlated Double Sampling (CDS) in practical applications. It is assumed that all well-behaved applications include the CDS function, so this offset noise can be ignored in practical applications.

The noise generated by the amplifier transistor is itself represented by the generator NS.

For analyzing noise In CTIA pixels, reference may be made to the article "CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager" (a CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager), published In IEEE Trans Biomed Circuits Syst 10.2011.

According to this article, the role of the amplifying transistor in the output can be calculated by the following equation (2):

in this equation, CPD is the parasitic capacitance on the photodiode and at the intersection of the photodiode and the input terminal of the amplifier AMP, CINT is the integration capacitance value, and CL is the capacitance value of the charging capacitor at the output terminal of the amplifier AMP. In addition, α is a constant between 2/3 and 2, depending on the design of the amplifier. Finally, k and T are the Boltzmann constant and the absolute temperature, respectively.

Here, only high conversion gain configurations are of interest, i.e. CPD > > CINT. In this case, equation (2) is simplified as follows (equation (3)):

this equation shows that very low noise can be obtained by using a large value of the charging capacitor CL at the output of the amplifier AMP. We cite a very practical example, where CPD-25 fF and CINT-1 fF. In this case, when the capacitance CL is 100fF and the constant α is 2, the noise is 1430 μ V when the detection threshold is 8.94 electrons. However, if the value of CL is increased to 2500fF, the noise will drop to 286 μ V with a detection threshold of 1.8 electrons.

Thus, a realistic set of design parameters can be used to determine the noise performance, which is much better than that obtained with a real circuit. The main reason is that, in the above-described equations (2) and (3), only the thermal noise of the amplification transistor included in the amplifier AMP is considered.

On the other hand, in this inference, another source of noise is ignored, the so-called flicker or "flicker" noise. This flicker noise is considered to be caused by surface defects of the amplifying transistor of the amplifier AMP. The noise is characterized by an amplitude that is inversely proportional to frequency. For low illumination CTIA pixels, the operating frequency is very low, and this noise becomes very large and is almost impossible to reduce by increasing the CL value.

The article "Analysis and differentiation of Low-Frequency Noise Reduction in MOSFET Circuits Using variable Duty Cycle Switched Biasing" (Analysis and verification of Low Frequency Noise in MOSFET Circuits Using variable Duty Cycle switch Biasing) is published in the IEEE institute of electronics, 2018, volume 6, page 420 and 431, and shows that if the transistors are periodically polarized (turned on) and depolarized (turned off) during operation, flicker Noise can be greatly reduced. According to the authors, this improvement is due to the suppression of defects in the transistor channel during the depolarization phase. When a MOS transistor depolarizes, the channel surface is completely occupied by majority carriers, which make up for these defects and de-energize them. When the transistor is re-polarized, these defects become active again after a certain time. If the rate of alternation between polarization and depolarization is fast enough, the number of active defects will be greatly reduced and the flicker noise will also decrease in the same proportion. Another benefit of this alternating polarization is that the integration time of the noise decreases in proportion to the AMP polarization duty cycle in the readout circuit.

According to one aspect of the present description, it has been found that such dynamic polarization alternation can be advantageously implemented in CTIA sensors.

As can be understood from fig. 1, if the amplifier AMP is temporarily disabled, the photo charge generated by the photodiode can be stored in the parasitic capacitance CPD of the photodiode PD. When the amplifier AMP is polarized again, the stored charge may be transferred to the capacitance CINT. The only condition is that the photodiode remains reverse polarized to avoid partial charge loss in its PN junction. This condition is, however, particularly ensured in low light conditions, where each photodiode produces little charge during exposure.

Here, a CTIA readout circuit is proposed in which the amplifier AMP is periodically disabled, thereby significantly reducing the effect of flicker noise of the pixel amplification transistor by reducing its integration in the capacitance CINT.

Returning now to equation (3), this equation shows that in a CTIA readout circuit, noise can be reduced by increasing the value of the charge capacitor CL (as shown in the equivalent diagram of fig. 2).

As an estimate, the capacitance CL has a value of a few picofarads, which can significantly reduce the effect of transistor thermal noise. However, the increasingly stringent requirements in terms of pixel minimization do not allow the integration of this value capacitance into one pixel for two-dimensional matrix detection, where the available space is not sufficient.

It has also been found that the charge capacitor CL only plays its role during the amplifier AMP enable phase when the pixel amplifier AMP is periodically enabled and disabled. Since it is known that the enable can have a very low duty cycle, according to one aspect of the present description, this capacitance can be placed outside the pixels so as to be shared by a group of pixels; this capacitance will connect the output of the amplifier AMP for a given pixel in the group when the amplifier is enabled. At the same time, the enablement of the set of pixels is ordered so as to connect the outputs of the various readout circuits in sequence according to a calling order defined by appropriate control signals. The capacitance then becomes common to the group of pixels in a predefined order, which is predefined in accordance with the activation of the group of pixels.

For a two-dimensional sensor matrix, a capacitance CL common to all pixels of the same column may be provided. Then, pixel enable is applied to all pixels of the same row in a uniform manner by sequencing row by row. Thus, at each instant in a column, only one pixel is connected to the associated capacitance CL of the column. Activation may be performed row-by-row in any order, but is preferably performed in order for simplicity.

Fig. 3 shows this implementation structure, in which all pixel readout circuits RC (i, j) are organized in rows and columns, and the charging capacitors CLEX0, CLEX1, CLEX2, …, CLEXi are associated with the columns COL0, COL1, COL2, …, coi, respectively. The readout circuits on the same row can be connected to their respective charge capacitors simultaneously by control buses a0, a1, a2, A3, etc., with control being performed sequentially row by row.

Therefore, two approaches are proposed here to improve the sensitivity of CTIA pixels. The first method is to alternately power the CTIA pixel amplifier. This scheme can reduce low frequency flicker noise. Such alternate powering may be performed in any order for the pixels in a one-or two-dimensional matrix. The second approach may reduce transistor thermal noise in the CTIA pixel when alternately powered according to the first approach. This solution consists in connecting the readout circuit output to a charging capacitor external to the pixel during the power supply enable. The charging capacitor may be shared by a group of pixels in the 2D matrix, or even by all pixels in the matrix, taking into account that the duty cycle of the pixel enable is low.

Examples

Referring to fig. 4, an implementation of CMOS technology in the CTIA readout circuit of fig. 1 is shown, supplemented with enable/disable alternate control of the amplifier AMP. Here, the amplifier AMP is composed of a pair of transistors using CMOS technology. To achieve an alternate enabling/disabling of the amplifier AMP, the simplest method consists in applying a variable polarization voltage VBIAS. When the value of the polarization voltage VBIAS is lower than the threshold value of the N-MOS transistor of the AMP circuit, the power supply of the circuit is thus turned off. When this voltage recovers its value corresponding to the normal operating polarization, the AMP circuit will be powered again. Therefore, by applying an alternating voltage between two potentials, it is possible to supply an alternating current to the AMP circuit, and achieve a desired reduction in flicker noise.

Fig. 5 shows a simple circuit for generating such an alternating VBIAS control voltage. It comprises a polarization current generator IBIAS, a current/voltage converter MBIAS providing a polarization voltage VBIAS, a transistor MC having an input connected to the VOFF signal and connected between VBIAS node and ground. When the VOFF signal is activated, transistor MC grounds the VBIAS node, thereby turning off the polarization voltage of amplifier AMP. The output voltage of the amplifier AMP rises and turns off the P-MOS transistor, thereby disabling the amplifier.

A modification of this circuit will now be described. The aforementioned article "Analysis and differentiation of Low-Frequency Noise Reduction in MOSFET Circuits Using variable Duty Cycle Switched Biasing" (Analysis and verification of Low Frequency Noise in MOSFET Circuits Using variable Duty Cycle switch Biasing) suggests that flicker Noise will be further reduced if the transistors making up the amplifier AMP can operate in accumulation mode. It is to be noted herein that when the voltage between the gate and the source/drain of the transistor MOS of the N-type channel is negative and the voltage between the gate and the source/drain of the transistor MOS of the P-type channel is positive, the transistor MOS is in the accumulation mode during the activation.

To this end, and referring to fig. 6A and 6B, another embodiment of a readout circuit is presented in which the transistors NMOS and PMOS of the amplifier are in accumulation mode when the amplifier is disabled. For this reason, the supply voltage ALIMX of the amplifier is also changed.

When turned off, the power supply ALIMX is first zeroed, and then the polarization voltage VBIAS is changed to a negative value with a short delay Td (see fig. 6B), so that the output voltage of the AMP during the disable period is 0 volt, thereby bringing the transistor PMOS of the AMP circuit into the accumulation mode.

Fig. 7 shows the circuit in fig. 6A, supplemented with a circuit for selectively connecting the readout circuit output to a common charge capacitor CL located outside the pixel. The signal CL _ ON drives a switching transistor CT connected between the circuit output and the charging capacitor CL terminal. The readout circuit may be integrated into a matrix as shown in fig. 3.

Referring to fig. 8A and 8B, a readout circuit such as that of fig. 7 is shown, supplemented with a correlated double sampling circuit CDS function, for suppressing reset noise of the amplifier AMP circuit. This function is realized by a capacitor CDSC connected between the output terminal VOUT of the amplifier AMP and the output terminal of the readout circuit CDSOUT, and a transistor CDST installed between a reference voltage source CDSREF and said output terminal CDSOUT, which is controlled by a CDS reset signal denoted CDSRST.

Referring to the timing diagram of fig. 8B, during startup of the ALIMX power supply, resetting of the amplifier AMP and CDS circuits is performed. Between times T1 and T2, amplifier reset is performed by RST gate pulse, while between longer times T1 and T3, CDS circuit reset is performed by CDSRST gate pulse. Therefore, after the reset of the AMP circuit is ended, the CDS circuit reset is released, and so-called "kTC" load noise generated during the reset is absorbed by the capacitor CDSC, and the output voltage CDSOUT approaches the reference voltage CDSREF.

CDS circuit reset also produces kTC type noise in the CDS capacitor, but the value of this capacitor is much larger than the value of the integrating capacitor CINT, so the equivalent reset noise on CINT is much lower.

With the gate pulse CL _ ON between T1 and the time after T3, the common charging capacitor CL is connected to the output terminal of the amplifier AMP throughout these operations.

The amplifier AMP is enabled by the gate pulse VBIAS between times T1 and T4, and is powered by the gate pulse ALIMX between times T1 and intermediate times T3-T4 to achieve the accumulation mode described above.

The gating pulses CL _ ON, VBIAS and ALIMX between times T5 and T6 ensure that the amplifier AMP is re-enabled after the disable phase. This re-enabling is performed periodically during exposure, according to a predefined control sequence of the pixel matrix management.

The pixel readout, i.e. the voltage CDSOUT, is performed during the period when the amplifier AMP is activated and the charging capacitor CL is switched in. At the end of the exposure phase, the pixel readout circuit is in the prior art and will not be described in detail here.

Of course, many variations and modifications are possible.

In particular, as a variant, the alternate enabling/disabling of the amplifier AMP can be achieved by changing only its polarization voltage, or by changing its supply voltage, or by changing both.

In addition, the structure of the transimpedance amplifier may be more complex than a pair of simple P-MOS and N-MOS transistors.