阅读说明：本技术 存储器装置的高速缓存架构 (Cache architecture for memory devices ) 是由 N·德尔加托 于 2021-05-24 设计创作，主要内容包括：本申请涉及存储器装置的高速缓存架构。例如,一种存储器装置可包含：主阵列,其具有第一组存储器单元；高速缓存,其具有第二组存储器单元；和高速缓存延迟寄存器,其配置成存储与最近执行的存取操作相关联的高速缓存地址的指示。在一些实例中,所述高速缓存延迟寄存器可以作为高速缓存地址的先进先出FIFO寄存器操作,其中与所执行存取操作相关联的高速缓存地址可以添加到所述FIFO寄存器的起点中,并且在所述FIFO寄存器的末尾的高速缓存地址可被清除。与所述主阵列上的存取操作相关联的信息可以维持在所述高速缓存中,并被直接存取(例如,无需对所述主阵列进行另一存取),至少持续所述高速缓存地址存在于高速缓存延迟寄存器中的时间。(The present application relates to cache architectures for memory devices. For example, a memory device may include: a main array having a first set of memory cells; a cache having a second set of memory cells; and a cache delay register configured to store an indication of a cache address associated with a most recently performed access operation. In some examples, the cache delay register may operate as a first-in-first-out FIFO register of cache addresses, where the cache address associated with the executed access operation may be added to the beginning of the FIFO register and the cache address at the end of the FIFO register may be cleared. Information associated with an access operation on the primary array may be maintained in the cache and accessed directly (e.g., without another access to the primary array), at least for the time that the cache address is present in the cache delay register.)

1. An apparatus, comprising:

a memory array comprising a first plurality of memory cells;

a cache comprising a second plurality of memory cells;

a first-in first-out (FIFO) register; and

a control component coupled with the memory array, the cache, and the FIFO register, the control component configured to cause the apparatus to:

receiving a command to write information to the device;

based at least in part on receiving the command, writing the information to an address of the cache;

storing, in the FIFO register, an indication of the address of the cache based at least in part on writing the information to the cache; and

performing an operation based at least in part on the indication to store the address of the cache in the FIFO register.

2. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to:

writing the information to the memory array based at least in part on the command.

3. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to:

based at least in part on writing the information to the cache, storing an indication that the information stored at the address of the cache is to be maintained in the cache.

4. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to:

receiving a second command to write second information to the device; and

removing the indication of the address from the FIFO register based at least in part on receiving the second command.

5. The apparatus of claim 4, wherein the control component is further configured to cause the apparatus to:

storing an indication that the address of the cache is available for eviction based, at least in part, on the indication to remove the address from the FIFO register.

6. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to:

receiving a third command to read third information from the device, wherein to perform the operation, the control component is configured to cause the device to determine whether to access the third information from the cache or the memory array (e.g., based at least in part on the FIFO register, based at least in part on an address map or tag of the cache).

7. The apparatus of claim 6, wherein to determine whether to access the third information from the cache or the memory array, the control component is configured to cause the apparatus to:

determining to access the third information from the memory array based at least in part on an address associated with the third command not being included in the FIFO register.

8. The apparatus of claim 7, wherein the control component is further configured to cause the apparatus to:

writing the third information from the memory array to a second address of the cache; and

storing, in a second FIFO register of the apparatus, an indication of the second address of the cache based at least in part on writing the third information from the memory array to the second address of the cache.

9. The apparatus of claim 6, wherein the control component is further configured to cause the apparatus to:

determining to access the third information from the cache based at least in part on an address associated with the third command being included in the FIFO register.

10. The apparatus of claim 9, wherein the control component is further configured to cause the apparatus to:

removing the indication of the address from the FIFO register based at least in part on determining to access the third information from the cache.

11. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to:

receiving a fourth command to write fourth information to the device;

identifying a third address of the cache for eviction of the cache based at least in part on the fourth command and the FIFO register; and

writing the fourth information to the cache based at least in part on identifying the third address.

12. The apparatus of claim 11, wherein the control component is further configured to cause the apparatus to:

determining to perform the eviction based at least in part on an amount of entries in the FIFO register and an amount indicating cache lines available for eviction; and

identifying the third address of the cache for the eviction based at least in part on determining to perform the eviction.

13. The apparatus of claim 11, wherein the control component is further configured to cause the apparatus to:

writing fifth information from the third address of the cache to the memory array based at least in part on identifying the third address of the cache for the eviction.

14. The apparatus of claim 13, wherein the control component is further configured to cause the apparatus to:

storing, in the FIFO register, an indication of the third address of the cache based at least in part on writing the fifth information to the memory array.

15. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to:

operating the FIFO register with an amount of entries based at least in part on a target duration between successive accesses of addresses of the memory array and an access command interval of the apparatus.

16. The apparatus of claim 1, wherein:

the first plurality of memory cells comprises non-volatile storage elements; and is

The second plurality of memory cells includes volatile storage elements.

17. An apparatus, comprising:

a memory array comprising a first plurality of memory cells;

a cache comprising a second plurality of memory cells;

a first-in first-out (FIFO) register; and

a control component coupled with the memory array, the cache, and the FIFO register, the control component configured to cause the apparatus to:

receiving a command to read information in the device;

based at least in part on receiving the command, writing the information from the memory array to an address of the cache;

storing, in the FIFO register, an indication of the address of the cache based at least in part on writing the information from the memory array to the address of the cache; and

performing an operation based at least in part on the indication to store the address of the cache in the FIFO register.

18. The apparatus of claim 17, wherein the control component is further configured to cause the apparatus to:

transmitting the information to a host device coupled with the apparatus based at least in part on the command.

19. The apparatus of claim 17, wherein the control component is further configured to cause the apparatus to:

based at least in part on writing the information from the memory array to the address of the cache, storing an indication that the information stored at the address of the cache is to be maintained in the cache.

20. The apparatus of claim 17, wherein the control component is further configured to cause the apparatus to:

receiving a second command to read second information from the device; and

removing the indication of the address from the FIFO register based at least in part on receiving the second command.

21. The apparatus of claim 20, wherein the control component is further configured to cause the apparatus to:

storing an indication that the address of the cache is available for eviction based, at least in part, on the indication to remove the address from the FIFO register.

22. The apparatus of claim 17, wherein:

the first plurality of memory cells comprises non-volatile storage elements; and is

The second plurality of memory cells includes volatile storage elements.

23. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to:

receiving a command to write information to the electronic device;

based at least in part on receiving the command, writing the information to an address of a cache of the electronic device;

storing, in a first-in, first-out (FIFO) register of the electronic device, an indication of the address of the cache based at least in part on writing the information to the cache; and

performing an operation of the electronic device based at least in part on the indication to store the address of the cache in the FIFO register.

24. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

writing the information to a memory array of the electronic device based at least in part on the command.

25. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

based at least in part on writing the information to the cache, storing an indication that the information stored at the address of the cache is to be maintained in the cache.

26. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

receiving a second command for writing second information to the electronic device; and

removing the indication of the address from the FIFO register based at least in part on receiving the second command.

27. The non-transitory computer-readable medium of claim 26, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

storing an indication that the address of the cache is available for eviction based, at least in part, on the indication to remove the address from the FIFO register.

28. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

receiving a third command to read third information from the electronic device, wherein performing the operation of the electronic device comprises determining whether to access the third information from the cache based at least in part on the FIFO register.

29. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

receiving a fourth command to write fourth information to the electronic device;

identifying a third address of the cache for eviction of the cache based at least in part on the fourth command and the FIFO register; and

writing the fourth information to the cache based at least in part on identifying the third address.

30. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to:

receiving a command to read information from the electronic device;

based at least in part on receiving the command, writing the information from a memory array of the electronic device to an address of a cache of the electronic device;

storing, in a first-in-first-out (FIFO) register, an indication of the address of the cache based at least in part on writing the information from the memory array to the address of the cache; and

performing an operation of the electronic device based at least in part on the indication to store the address of the cache in the FIFO register.

31. The non-transitory computer-readable medium of claim 30, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

transmitting the information to a host device coupled with the electronic device based at least in part on the command.

32. The non-transitory computer-readable medium of claim 30, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

based at least in part on writing the information from the memory array to the address of the cache, storing an indication that the information stored at the address of the cache is to be maintained in the cache.

33. The non-transitory computer-readable medium of claim 30, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

receiving a second command to read second information from the electronic device; and

removing the indication of the address from the FIFO register based at least in part on receiving the second command.

34. The non-transitory computer-readable medium of claim 33, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

storing an indication that the address of the cache is available for eviction based, at least in part, on the indication to remove the address from the FIFO register.

35. An apparatus, comprising:

a memory array comprising a first plurality of memory cells;

a cache comprising a second plurality of memory cells;

a first-in first-out (FIFO) register; and

a control component coupled with the memory array, the cache, and the FIFO register, the control component operable to store an indication of an address of the cache based at least in part on accessing the memory array.

Technical Field

The technical field relates to cache architectures for memory devices.

Background

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells can be programmed to one of two support states, often represented by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, either of which may be stored. To access the stored information, the component may read or sense at least one stored state in the memory device. To store information, a component may write or program a state in a memory device.

There are various types of memory devices and memory units, including magnetic hard disks, Random Access Memory (RAM), Read Only Memory (ROM), dynamic RAM (dram), synchronous dynamic RAM (sdram), ferroelectric RAM (feram), magnetic RAM (mram), resistive RAM (rram), flash memory, Phase Change Memory (PCM), self-selected memory, chalcogenide memory technology, and the like. The memory cells may be volatile or nonvolatile.

Disclosure of Invention

An apparatus is described. The apparatus may include: a memory array comprising a first plurality of memory cells; a cache comprising a second plurality of memory cells; a first-in-first-out (FIFO) register; and a control component coupled with the memory array, the cache, and the FIFO register. The control component may be configured to cause the apparatus to: receiving a command to write information to the device; based at least in part on receiving the command, writing the information to an address of the cache; storing, in the FIFO register, an indication of the address of the cache based at least in part on writing the information to the cache; and performing an operation based at least in part on the indication to store the address of the cache in the FIFO register.

An apparatus is described. The apparatus may include: a memory array comprising a first plurality of memory cells; a cache comprising a second plurality of memory cells; a FIFO register; and a control component coupled with the memory array, the cache, and the FIFO register. The control component may be configured to cause the apparatus to: receiving a command to read information in the device; based at least in part on receiving the command, writing the information from the memory array to an address of the cache; storing, in the FIFO register, an indication of the address of the cache based at least in part on writing the information from the memory array to the address of the cache; and performing an operation based at least in part on the indication to store the address of the cache in the FIFO register.

A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a command to write information to the electronic device; based at least in part on receiving the command, writing the information to an address of a cache of the electronic device; storing, in a FIFO register of the electronic device, an indication of the address of the cache based at least in part on writing the information to the cache; and performing an operation of the electronic device based at least in part on the indication to store the address of the cache in the FIFO register.

A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a command to read information from the electronic device; based at least in part on receiving the command, writing the information from a memory array of the electronic device to an address of a cache of the electronic device; storing, in the FIFO register, an indication of the address of the cache based at least in part on writing the information from the memory array to the address of the cache; and performing an operation of the electronic device based at least in part on the indication to store the address of the cache in the FIFO register.

An apparatus is described. The apparatus may include: a memory array comprising a first plurality of memory cells; a cache comprising a second plurality of memory cells; a FIFO register; and a control component coupled with the memory array, the cache, and the FIFO register. The control component may be operative to store an indication of an address of the cache based at least in part on accessing the memory array.

Drawings

Fig. 1 illustrates an example of a system supporting a cache architecture of a memory device in accordance with examples disclosed herein.

Fig. 2 illustrates an example of an architecture that supports a cache architecture of a memory device in accordance with examples disclosed herein.

Fig. 3-5 illustrate examples of architectures to operate a cache architecture supporting a memory device in accordance with examples disclosed herein.

Fig. 6 illustrates an example of a process flow to support a cache architecture of a memory device in accordance with examples disclosed herein.

FIG. 7 illustrates a block diagram of a memory device that supports a cache architecture for the memory device, in accordance with aspects of the present disclosure.

Fig. 8 and 9 illustrate flow diagrams showing one or more methods of supporting a cache architecture of a memory device, according to examples disclosed herein.

Detailed Description

In some memory architectures, it may be beneficial to provide a delay between access operations on the same memory cells of the memory array, such as a minimum read-after-write delay or other type of delay between access operations. For example, some memory cells or accompanying circuitry may accumulate heat, charge, or some other characteristic or instability when accessed, and it may be beneficial to allow such a characteristic to dissipate or otherwise stabilize before another access operation is performed on the same memory cells (e.g., at least some of the same memory cells). To support such delays between successive access operations without incurring undue latency, information (e.g., data) associated with accessing memory cells of the main array may be maintained in memory cells of the cache for a period of time so as to be accessible from the cache, which may be an alternative to performing another access operation on the same memory cells of the main array.

According to examples disclosed herein, a memory device may include: a main array having a first set (e.g., one or more) of memory cells; a cache having a second set (e.g., one or more) of memory cells; and one or more cache delay registers configured to store an indication of one or more cache addresses associated with a most recently performed access operation. The cache delay register may operate in a manner that supports maintaining a threshold duration between successive operations on the same memory cell or the same address of the main array. For example, the cache delay register may operate as a first-in-first-out (FIFO) register of cache addresses, where the cache address associated with the access operation performed (e.g., on the main array, associated with the address of the main array) may be added into the beginning of the FIFO register and the cache address at the end of the FIFO register may be cleared. Information associated with the access operation may be maintained in the cache, for example, at least for the time that the cache address is present in the cache delay register, and after receiving another access command, the associated information may be retrieved from the cache instead of the main array if the information is available in the cache. The threshold duration between successive access operations may be maintained by operating a cache delay register having a capacity related to the rate of access operations performed on the memory device. In some examples, providing such cache delay registers may support reduced power consumption, improved scalability, or both, or other benefits compared to other techniques of delaying operations on memory cells of a memory array.

Features of the present disclosure are first described in the context of the memory systems, architectures, and associated techniques described with reference to fig. 1-6. These and other features of the present disclosure are further illustrated by, and described with reference to, the apparatus diagrams and flowcharts associated with the cache architecture of the memory device described with reference to fig. 7-9.

Fig. 1 illustrates an example of a system 100 that supports a cache architecture of a memory device in accordance with examples disclosed herein. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices, although aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

The system 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 may show aspects of a computer, laptop, tablet, smart phone, mobile phone, wearable device, internet-connected device, vehicle controller, and so forth. Memory device 110 may be a component of a system that may be used to store data for one or more other components of system 100.

At least part of the system 100 may be an instance of the host device 105. Host device 105 may be an example of other circuitry within a processor or device that uses memory to perform a process, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet, a smartphone, a mobile phone, a wearable device, an internet-connected device, a vehicle controller, or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof, that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

Memory device 110 may be a stand-alone device or component that may be used to provide physical memory addresses/spaces that may be used or referenced by system 100. In some examples, memory device 110 may be configured to function with one or more different types of host devices 105. Signaling between the host device 105 and the memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for communicating signals, various physical dimensions of physical packaging for the host device 105 and the memory device 110, clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other factors.

Memory device 110 may be used to store data for components of host device 105. In some examples, the memory device 110 may act as a slave to the host device 105 (e.g., by the external memory controller 120 responding to and executing commands provided by the host device 105). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

Host device 105 may include an external memory controller 120, a processor 125, one or more of basic input/output system (BIOS) components 130, or other components such as one or more peripheral components or one or more input/output controllers. Components of the host device may be coupled to each other using a bus 135.

The processor 125 may be used to provide control or other functionality to at least part of the system 100 or at least part of the host device 105. The processor 125 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 may be an example of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a general purpose GPU (gpgpu), or a system on a chip (SoC), among other examples. In some examples, external memory controller 120 may be implemented by, or may be part of, processor 125.

The BIOS component 130 may be a software component that includes a BIOS operating as firmware that may initialize and run various hardware components of the system 100 or the host device 105. The BIOS component 130 may also manage the flow of data between the processor 125 and various components of the system 100 or host device 105. The BIOS component 130 may include programs or software stored in one or more of Read Only Memory (ROM), flash memory, or other non-volatile memory.

Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired capacity or a specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sectors) where each memory cell may be used to store at least one bit of data. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or multi-die package or a multi-chip memory or multi-chip package.

Device memory controller 155 may include circuitry, logic, or components that may be used to control the operation of memory device 110. Device memory controller 155 may include hardware, firmware, or instructions that enable memory device 110 to perform various operations and may be used to receive, transmit, or execute commands, data, or control information related to the components of memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some examples, device memory controller 155 can control the operation of memory device 110 described herein in conjunction with local memory controller 165 of memory die 160.

A local memory controller 165 (e.g., local to the memory die 160) may be used to control the operation of the memory die 160. In some examples, local memory controller 165 may be used to communicate (e.g., receive or transmit data or commands or both) with device memory controller 155. In some examples, memory device 110 may not include device memory controller 155, and local memory controller 165 or external memory controller 120 may perform the various functions described herein. As such, local memory controller 165 may be used to communicate with device memory controller 155, other local memory controllers 165, or directly with external memory controllers 120 or processor 125, or a combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165, or both, may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers that may be used to support the described operations of device memory controller 155 or local memory controller 165, or both.

In some examples, a component such as memory device 110 (e.g., device memory controller 155, local memory controller 165) may be or may include a non-transitory computer-readable medium storing instructions (e.g., firmware) for performing techniques associated with a cache architecture of a memory device in accordance with examples disclosed herein. For example, such instructions, when executed by a component such as device memory controller 155 or local memory controller 165, may cause the controller to perform the techniques in accordance with the architectures and techniques described with reference to fig. 2-9.

The external memory controller 120 may be used to enable one or more of information, data, or commands to be communicated between components (e.g., the processor 125) of the system 100 or host device 105 and the memory device 110. The external memory controller 120 may translate or translate communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or the host device 105 or functions described herein may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100, or the host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some examples, external memory controller 120 or the functions described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channel 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an instance of a transmission medium that carries information between host device 105 and a memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path that may be used to carry a signal. For example, the channel 115 may include a first terminal including one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be used to act as part of a channel.

The channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, the channels 115 may include one or more Command and Address (CA) channels 186, one or more clock signal (CK) channels 188, one or more Data (DQ) channels 190, one or more other channels 192, or a combination thereof.

Memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command indicating that memory device 110 is to store data for host device 105. In some examples, the local memory controller 165 may be used to perform a write operation (e.g., a programming operation) on one or more memory cells of the associated memory array 170. During a write operation, the memory cells of the memory die 160 can be programmed to store a desired logic state. In some examples, local memory controller 165 may identify a target memory cell to perform a write operation.

In some examples, memory device 110 may receive a read command indicating that memory device 110 is to provide stored data to host device 105, and local memory controller 165 may be used to perform a read operation (e.g., a sense operation) on one or more memory cells of associated memory array 170. During a read operation, the logic state stored in the memory cells of the memory array 170 may be determined. In some examples, local memory controller 165 may identify a target memory cell to perform a read operation.

In some examples, the one or more memory arrays 170 of the memory device 110 can include non-volatile memory cells for storing information (e.g., logical values, logical states). For example, the memory array 170 may include NAND (e.g., NAND flash) memory, Read Only Memory (ROM), Phase Change Memory (PCM), self-selected memory, 3D cross point (3DXP) memory, other chalcogenide-based memory, ferroelectric ram (feram), Magnetic Ram (MRAM), NOR (e.g., NOR flash) memory, Spin Transfer Torque (STT) -MRAM, conductive bridge ram (cbram), Resistive Random Access Memory (RRAM), oxide-based RRAM (oxram), and electrically erasable programmable ROM (eeprom), among other types of non-volatile memory cells.

In a NAND memory architecture, each memory cell may include a transistor having a floating gate or dielectric material for storing an amount of charge representing a logical value. The transistor may include a control gate and a floating gate, where the floating gate may be sandwiched between two portions of dielectric material. A logical value may be stored in a transistor by placing (e.g., writing, storing) an amount of electrons (e.g., an amount of charge) on a floating gate. The amount of charge to be stored on the floating gate may depend on the logic value to be stored. The charge stored on the floating gate may affect the threshold voltage of the transistor, thereby affecting the amount of current flowing through the transistor when the transistor is activated (e.g., when a voltage is applied to the control gate). The logic value stored in the transistor may be sensed (e.g., as part of a read operation) by applying a voltage to the control gate to activate the transistor and measuring the resulting amount of current flowing through the transistor.

In some examples, memory cells of the memory array 170 may store logic states using configurable materials, which may be referred to as memory elements, memory storage elements, material memory elements, material portions, or polarity written material portions, among others. The configurable material of a memory cell may refer to a chalcogenide-based storage component, such as a Phase Change Memory (PCM) cell, a threshold memory cell, or a self-selected memory cell.

In a phase change architecture, a memory cell may exhibit an observable difference between the resistance of a crystalline state and an amorphous state in a phase change material, which may be a chalcogenide material. Writing a material in a crystalline state may result in a relatively low resistance, while writing a material in an amorphous state may result in a relatively high resistance. The difference in resistance of the material of the storage element that depends on the logic state written to the material of the storage element may correspond to the read window of the storage element.

In a threshold or optional architecture, some or all of a set of logic states supported by a memory cell may be associated with an amorphous state of a chalcogenide material (e.g., a single material state of material may be used to store different logic states). In some examples, the storage elements may be instances of a self-selected memory cell, where the material for the storage elements is operable to change to a different physical state during normal operation of the memory cell. For example, a selected memory cell may have a high threshold voltage state and a low threshold voltage state. The threshold voltage difference of the material of the storage element may correspond to a read window of the storage element.

In a FeRAM architecture, a memory cell may store a state (e.g., a polarization state or dielectric charge) representing a programmable state in a capacitor that includes a ferroelectric material to store charge and/or a polarization representing a programmable state. Ferroelectric materials are characterized as being electrically polarized, wherein the material can maintain a non-zero charge in the absence of an electric field. By applying a net voltage difference across the ferroelectric capacitor, a logic 0 or 1 can be written to the memory cell by controlling the electrical polarization of the ferroelectric material and thus the charge on the capacitor terminals. To read or sense the stored state of the ferroelectric capacitor, a voltage may be applied across the ferroelectric capacitor and the charge stored by the ferroelectric capacitor may be detected. The degree of change may depend on the initial polarization state, applied voltages, intrinsic or other capacitance on the access lines, and other factors.

In some memory architectures, it may be beneficial to ensure a delay between access operations on the same memory cells of the memory array 170. For example, some memory cells or accompanying circuitry may accumulate heat, charge, or some other characteristic or instability when accessed. The accumulation of disturbances due to relatively rapid sequential access of the same memory cell may, for example, result in degradation of the logic state stored by the accessed memory cell or adjacent memory cells, degradation of the ability of the memory cell to write with a logic state, degradation of the ability of the memory cell to maintain a written logic state, degradation or fatigue of the material or material interface of the memory cell or isolation breakdown between components, and other degradation or other adverse performance, or any combination thereof. Thus, after an access operation is performed, it may be beneficial to allow various characteristics of the memory cell or accompanying circuitry to stabilize or dissipate before another access operation is performed on the same memory cell.

To support a delay between consecutive access operations without incurring undue latency, information (e.g., data, logic state) associated with accessing memory cells of a main array (e.g., of the memory array 170) may be maintained in memory cells of a cache for a period of time such that it may be accessed (e.g., directly) from the cache, rather than performing another access operation to the same memory cells of the main array. In various examples, such caches may be included in or otherwise associated with device memory controller 155 or local memory controller 165, and may include memory cells having a different architecture (e.g., cell architecture, storage architecture) than the memory cells of the main array. For example, the main array (e.g., memory array 170) may be configured with non-volatile memory cells, including one or more of the examples described herein, and the cache may be configured with volatile memory cells or storage components, such as DRAM memory cells or other capacitive storage components. In some examples, memory device 110 (e.g., device memory controller 155, local memory controller 165) may also include a cache latency register configured to store an indication of a cache address associated with a most recently executed access operation, and the cache latency register may be operated in a manner that supports maintaining a threshold duration between successive operations on the same memory cell of the main array.

Fig. 2 illustrates an example of an architecture 200 that supports a cache architecture of a memory device in accordance with examples disclosed herein. The architecture 200 may be included in, or may refer to components of, the memory device 110 described with reference to FIG. 1. Architecture 200 includes a main array 210, a cache 220, and a cache delay register 240. The architecture also includes a control component 260 that may be coupled with the main array 210, the cache 220, and the cache delay register 240 via one or more buses (e.g., bus 265). Control component 260 may include circuitry, components (e.g., a processor, a non-transitory computer-readable medium), or various combinations thereof configured to perform one or more techniques described herein.

The main array 210 may include a first array of memory cells that may be used to store information (e.g., data) in the form of logic states. In some examples, the memory cells in the main array 210 may be non-volatile memory cells or other types of emerging memory cells, such as NAND memory cells, phase change memory cells, threshold memory cells, FeRAM memory cells, and the like. Cache 220 may include a second array of memory cells, which may have a different architecture than the memory cells in main array 210. For example, the memory cells in cache 220 may be volatile memory cells, such as capacitive memory cells or DRAM memory cells. In some examples, the memory cells in the cache 220 may support a relatively lower latency, a relatively shorter access duration, or a relatively faster access rate than the memory cells in the main array 210. In some instances, data stored in an address of cache 220 may be associated with an address in primary array 210 (e.g., according to a mapping or data synchronization between cache 220 and primary array 210), which may be tracked using a logical-to-physical (L2P) pointer or other mapping (e.g., a mapping by or to control component 260).

Data may be written to the primary array 210 in response to a write command (e.g., from the host device 105, which may be received by or otherwise interpreted by the control component 260). In some examples, data associated with the write command may be written directly to the main array 210 (e.g., without first writing to the cache 220). In some examples, data associated with the write command may be written first to cache 220, then may be passed to the main array (e.g., according to cache line synchronization 272), or may be written in parallel (e.g., concurrently, simultaneously) to cache 220 and main array 210.

In some examples, data may be read from the main array 210 in response to a read command. Additionally or alternatively, data may be read from cache 220 in response to a read command. For example, in response to a read command under some conditions, data may be transferred from main array 210 to cache 220 (e.g., according to cache line load 271), and from cache 220 to host device 105 (e.g., via control component 260). In response to a read command under some conditions, data already available in the cache 220 may be transferred (e.g., directly) to the host device 105 without accessing the main array 210.

In some examples, it may be advantageous to provide or impose a delay between consecutive access operations on the same memory cells (e.g., same addresses) of the main array 210, such as a delay between a write operation and a subsequent read or write operation, or a delay between a read operation and a subsequent read or write operation, or both. To support such delays between successive access operations without incurring undue latency, information associated with accessing the main array 210 may be maintained in the cache 220 for a period of time (e.g., by delaying evictions from the cache 220) so that it may be accessed (e.g., directly) from the cache 220, rather than performing another access operation to the same memory location or address of the main array 210. For example, after CL synchronization 272, the associated information may be maintained in cache slot 230 until the hold time expires, thereby supporting a delay of eviction from cache 220.

In some examples, cache 220 may include or otherwise be associated with a set of cache slots 230, where each cache slot may include or be referred to as a Cache Line (CL). Each cache slot 230 may be associated with an address of the cache 220 (e.g., CL address, CL index, CL _ ID) and may be associated with a set of fields configured to support various operations of the cache 220. For example, the cache slot 230 may be associated with a first field 231 containing cached information (e.g., according to a set of N CL bits, where N may be any amount or one bit or more than one bit). In some examples, the cache slot 230 may be associated with a second field 232 (e.g., a "cache line allocated" flag CL _ a) that indicates whether the cache slot 230 is allocated to an address of the main array 210. For example, the second field 232 holding a logical 0 may indicate that the cache line (e.g., the first field 231, the cache slot 230) is empty or unallocated. In some examples, cache slot 230 may be associated with a third field 233 (e.g., a "cache line invalid" flag CL _ D) that indicates whether cache slot 230 is synchronized with main array 210. For example, a third field 233 holding a logical 1 may indicate that the cache line (e.g., first field 231, cache slot 230) "invalid," which may indicate that cache slot 230 needs to be synchronized with main array 210 prior to eviction. In some examples, the cache slot 230 may be associated with a fourth field 234 (e.g., a "cache line hold" flag CL _ H) that indicates whether the cache slot 230 is available for eviction. For example, the fourth field 234 holding a logical 1 may indicate that the cache line (e.g., the first field 231, the cache slot 230) is synchronized with the main array 210, but is to be maintained or otherwise not evicted.

In some examples, cache slots 230 may include counters that support providing or imposing a delay between consecutive access operations on the same memory cells of main array 210. For example, when cache slots 230 are used to support the transfer of information into or out of main array 210, such counters may be used to track the duration of time since information was written to or read from main array 210. However, this approach may be accompanied by power consumption associated with incrementing a counter at each cache slot 230, and the inclusion of such a counter at each cache slot 230 may be associated with adjusting limits to support various sizes of cache 220.

In the architecture 200, the cache delay register 240 may operate in a manner that supports maintaining a threshold duration between successive operations on the same memory cell or memory address of the main array 210. For example, the cache latency register 240 may include a plurality of entries 245 that serve as a first-in-first-out (FIFO) register for cache addresses, where a cache address associated with an executed access operation on the main array 210 (e.g., including a CL load 271 or a CL sync 272) is added into the beginning of the FIFO register (e.g., according to a CL register 273), and a cache address at the end of the FIFO register is flushed (e.g., associated with a evicted or reclaimable cache line, an Empty Cache Line (ECL)). Although illustrated in the context of a FIFO register storing cache addresses that move from a start point to an end, similar functionality, such as FIFO functionality, may be supported by various other techniques, such as statically storing cache addresses in a given slot or location of the cache delay register 240 and tracking which slot in the cache delay register 240 refers to the most recently or least recently added cache address (e.g., for adding a new cache address to the cache delay register 240 in place of the least recently added cache address). The use of the cache delay register 240 may replace the corresponding counter for each cache slot 230, which may support more efficient use of cache regions or reduced power consumption, among other benefits.

Information associated with an access of main array 210 may be maintained in cache 220 for a period of time, e.g., at least for the time that the associated cache address is present in cache delay register 240, which may include maintaining a cache line hold value (e.g., of fourth field 234) or otherwise delaying eviction of cache slot 230, at least for the time that the cache address is present in cache delay register 240. After a sequential access command (e.g., a read or write command received by control component 260), if associated information is available in cache 220 (e.g., as indicated by a cache line allocated indicator, as indicated by a cache line hold indicator, as indicated by a mapping between an address of main array 210 and an address of cache 220), the information may be retrieved from cache 220 without accessing main array 210, thereby preventing or mitigating access disturbance to the memory cells or associated circuitry to be held or stabilized.

The threshold duration between successive access operations may be maintained by operating the cache delay register 240 with a capacity N _ CDR that is related to the rate of access operations supported by the architecture 200. For example, capacity may be defined by the following equation:

n _ CDR ═ (hold time)/(minimum request time)

Where the hold time may refer to a configured delay (e.g., a minimum delay) between successive access operations on the same memory unit or address, and the minimum request time may refer to a duration between control component 260 receiving an access command, a minimum time between successive accesses of cache 220, a clock rate associated with operation of architecture 200, or some other operational timing. In some examples, the N _ CDR may refer to the total manufacturing capacity of the cache delay register 240 defined based on a known hold time and a minimum request time. In some instances, the N _ CDR may vary and may refer to all or a subset of the manufacturing capacity of the cache delay register 240. For example, the N _ CDR may be selected or configured based on a desired retention time, which may be based on an operating condition or mode of the memory device (e.g., according to a variable retention time), and may also be selected or configured based on a variable time between access operations, such as a variable clock time or access frequency (e.g., according to a variable minimum request time).

In some examples, architecture 200 may support selection of a victim cache line (e.g., a cache line to be evicted, emptied, or replaced with different information). For example, to support eviction of a cache slot 230, the control component 260 may be configured to select or identify one or more allocated cache slots 230 that are available for eviction, which may include one or more cache slots 230 having a value CL _ a ═ 1 and a value CL _ H ═ 0. In some instances, control component 260 may be configured to return an index or address of cache slot 230 that meets such requirements, which may be referred to as a victim CL _ ID or VCL _ ID.

In some examples, victim cache slot 230 may be included or added to cache delay register 240. For example, an address of the victim cache slot 230 (e.g., VCL _ ID) may be received as an input parameter, and the control component 260 may determine whether the cache slot 230 is invalid (e.g., whether the cache slot is associated with a value CL _ D ═ 1, whether the cache line needs to be synchronized with the main array 210 before eviction). If the cache slot 230 is invalid, the information of the cache slot 230 (e.g., of the first field 231) may be synchronized with the main array 210 (e.g., according to the CL sync 272), and if not, the CL sync 272 may be omitted. The control component 260 may add the VCL _ ID to the cache delay register 240, which may delay accessing the address of the main array 210 associated with the newly added information in the victim cache slot 230.

In some examples, control component 260 may be configured to perform cache latency registry checking. For example, the control component 260 may determine whether the cache delay register 240 is full, and if so, the control component 260 may flush or remove the index of the evicted cache slot 230 from the cache delay register 240. In some examples, after evicted cache slot 230 is cleared from cache delay register 240, evicted cache slot 230 may undergo a hold flag reset (e.g., set CL _ H to 0) and an allocate flag reset (e.g., set CL _ a to 0).

In some examples, control component 260 may be configured to remove the address of cache slot 230 (e.g., CL _ ID) from cache delay register 240. For example, when accessing information from the cache 220, rather than by accessing the main array 210, the control component 260 may remove the CL _ ID from the cache delay register 240 and move the remaining entries to the head (e.g., FIFO head) of the cache delay register 240.

Although the architecture 200 is shown with a single cache delay register 240, an architecture according to examples disclosed herein may include any number of one or more cache delay registers 240. In some examples, different cache delay registers 240 may be associated with different types of access operations. For example, to support a target or threshold delay between write operations on the main array 210, or more generally a threshold delay between a write operation and a consecutive access operation (e.g., a read or a write), a first cache delay register 240 may be associated with tracking an address of a cache slot 230 associated with a write operation on the main array 210. Additionally or alternatively, to support a target or threshold delay between read operations on the main array 210, or more generally a threshold delay between a read operation and a consecutive access operation (e.g., a read or a write), a second cache delay register 240 may be associated with tracking an address of a cache slot 230 associated with a read operation on the main array 210. In some examples, different cache delay registers 240 may be used to track or maintain read-after-write delays, read-after-read delays, write-after-write delays, and other delays between various types of access operations.

In some examples, after performing the CL load 271, the address of the associated cache slot 230 (e.g., CL _ IDX) may be stored in a Cache Read Registry (CRR), which may be an instance of the cache delay register 240. In some examples, a synchronization process (e.g., CL sync 272) may be selected from any cache slot 230 that is not in the CRR and, where applicable, another cache delay register 240 (e.g., the cache delay register 240 associated with the synchronization delay). To support such techniques, the cache slot 230 may also contain a fifth field (not shown) for tracking the presence of a cache line address or index (e.g., CL _ R tag) in the CRR.

The components of architecture 200 may correspond to various components of memory device 110. For example, main array 210 may refer to one memory array 170 in memory device 110 or some number of memory arrays 170 of memory device 110 (e.g., a subset or all of memory arrays 170). In some examples, each memory die 160 in memory device 110 may include its own cache 220, and in other examples, cache 220 may be shared among multiple memory dies 160. In some examples, each memory die 160 in memory device 110 may include its own cache delay register 240, and in other examples, one or more cache delay registers 240 may be located external to memory die 160 or the memory device, such as being a component of device memory controller 155 or otherwise associated with device memory controller 155. In various examples, the operations described with reference to control component 260 may be performed by one or more local memory controllers 165 of memory device 110 or device memory controller 155 of memory device 110, or distributed between device memory controller 155 and one or more local memory controllers 165.

In some examples, the operations supported by architecture 200 may be performed (e.g., by control component 260) based on a relationship between the amount of empty or available cache slots 230 of cache 220 and the capacity of cache delay register 240. For example, the operation may consider a "nearly full" condition of cache 220, which may be true when the amount of empty or unallocated cache slots 230 of cache 220 is less than or equal to (N _ CDR + 1). Various operations may be performed based on whether cache 220 is full, nearly full, or not full (e.g., empty, not "nearly full"). Further, various operations of the architecture 200 may be performed based on whether information associated with an access command (e.g., received by the control component 260) is available in the cache 220, the available and unavailable situations may be referred to as a "cache hit" or a "cache miss", respectively.

In some examples, the control component 260 may be configured to operate the architecture 200 on a "not nearly full" condition with a cache hit. In such examples, control component 260 may receive an access request (e.g., a read request, from host device 105), which may be associated with an address of cache slot 230. For example, control component 260 may contain a mapping of information between main array 210 and cache 220, and based at least in part on receiving an access request, control component 260 may identify cache slot 230 containing the requested information. In various examples, a read or write request may cause control component 260 to generate a cache line read (e.g., read from an associated cache slot 230 to provide information to the requesting host device 105, read from an associated cache slot 230 to write information to the main array 210) without accessing the main array 210 (e.g., due to a "cache hit" condition). In some instances, the latency or duration of performing such operations may be referred to as a "hit duration" or a "hit penalty".

In some examples, control component 260 may be configured to operate architecture 200 with a cache miss under "not nearly full" conditions. In such examples, control component 260 may receive an access request (e.g., a read request, from host device 105), which may not be associated with the address of cache slot 230. For example, control component 260 may contain a mapping of information between main array 210 and cache 220, and based at least in part on receiving the access request, control component 260 may identify that no cache slot 230 contains the requested information. In various examples, the CL read or write request may cause the control component 260 to perform a CL load 271 (e.g., for an empty or unallocated cache slot 230), or otherwise read directly from the main array 210. In some examples, the latency or duration for performing such operations may be referred to as a "miss duration" or "miss penalty," which may be longer than a hit duration or hit penalty.

Fig. 3 illustrates an example of an architecture 300 that supports a cache architecture of a memory device in accordance with the operations of the examples disclosed herein. Architecture 300 includes a main array 210-a, a cache 220-a, a cache latency register 240-a, a control component 260-a, and a bus 265-a, each of which may be an example of a corresponding component described with reference to architecture 200 of FIG. 2. In the example of fig. 3, control component 260-a may be configured to operate architecture 300 with a cache miss under a "nearly full" condition, which may include one or more of operations 301-305.

In some examples, operation 301 may include control component 260-a receiving an access request (e.g., a read request, a CL read, or a write request from host device 105). The received request may include or otherwise refer to an address 215-a-1 of one or more memory cells in the main array 210-a. Control component 260-a may identify that information associated with the received request is not present in cache 220-a, and may identify that cache 220-a is operating in a nearly full condition (e.g., identify a condition that the amount of empty cache slots 230 in cache 220-a is less than or equal to (N _ CDR + 1)).

In some examples, operation 302 may include control component 260-a selecting a "non-empty" cache slot 230 as a victim CL (e.g., VCL) for eviction. For example, the controlling component 260-a may identify the cache slot 230-a-1 having a cache line assigned value CL _ a ═ 1 cache line holding value CL _ H ═ 0, where the cache slot 230-a-1 may be associated with the address 215-a-2 of the primary array 210-a (e.g., by the address mapping resources of the controlling component 260-a).

In some examples, operation 303 may include control component 260-a passing the index of cache slot 230-a-1 (e.g., VCL _ IDX1) to cache delay register 240-a. For example, if a CL-sync 272-a between cache slot 230-a-1 and address 215-a-2 of main array 210-a is performed, passing the index of cache slot 230-a-1 to cache delay register 240-a may delay or suppress subsequent access operations on address 215-a-2 (e.g., after a write to address 215-a-2 associated with CL-sync 272-a). In some examples (e.g., if CL synchronization 272-a is not performed), operation 303 may be omitted.

In some examples (e.g., if the cache slot 230-a-1 is invalid, e.g., associated with a cache line invalid value CL _ D ═ 1), the operations 304 may include the control component 260-a performing a synchronization (e.g., CL synchronization 272-a) between the cache slot 230-a-1 and the main array 210-a (e.g., the addresses 215-a-2 of one or more memory cells in the main array 210-a). In some examples (e.g., if the cache slot 230-a-1 associated with VCL _ IDX1 is not invalid, e.g., associated with a cache line invalid value CL _ D ═ 0), operation 304 may be omitted.

In some examples, operation 305 may include control component 260-a loading data associated with the request of 301 from the primary array 210-a. Operation 305 may be associated with a CL load 271-a, which may include loading information from address 215-a-1 of primary array 210-a into cache slot 230-a-2 associated with the address or index of the CL _ IDX. Control component 260-a may identify cache slot 230-a-2 based at least in part on cache slot 230-a-2 being empty or unallocated (e.g., having a cache slot allocated value CL _ a ═ 0). In various examples, the requested data (e.g., from address 215-a-1) may be provided from cache slot 230-a-2 to the requestor (e.g., after the CL load 271-a), or directly from the main array 210-a (e.g., before, after, concurrently, or in parallel with the CL load 271-a). In some examples, architecture 300 may include a cache read register (not shown), and the index of cache slot 230-a-2 may be passed to the cache read register to delay or suppress subsequent access operations on address 215-a-1 (e.g., after a read of address 215-a-1 associated with CL load 271-a).

Fig. 4 illustrates an example of an architecture 400 that supports a cache architecture of a memory device in accordance with the operations of the examples disclosed herein. Architecture 400 includes a main array 210-b, a cache 220-b, a cache latency register 240-b, a control component 260-b, and a bus 265-b, each of which may be an example of a corresponding component described with reference to architecture 200 of FIG. 2. In the example of fig. 4, control component 260-b may be configured to operate architecture 400 with a cache miss under a "full" condition, which may include one or more of operations 401-405.

In some examples, operation 401 may include the control component 260-b receiving an access request (e.g., a read request, a CL read, or a write request from the host device 105). The received request may include or otherwise refer to an address 215-b-1 of one or more memory cells in the main array 210-b. Control component 260-b may identify that information associated with the received request is not present in cache 220-b and may identify that cache 220-b is operating in a fully full condition (e.g., identify a condition that an empty cache slot 230 is not present in cache 220-b).

In some examples, operation 402 may include control component 260-b clearing the cache slot index from cache delay register 240-b (e.g., containing the index or address of cache slot 230 numbered 1-8 because cache delay register 240-b is full). For example, VCL _ IDX1 may refer to cache slot 230-b-1, which may be cache slot 230 that has been synchronized with main array 210-b for at least a threshold duration (e.g., at least before a hold time). Thus, cache slot 230-b-1, identified by VCL _ IDX1, may be evicted from cache 220-b or otherwise made available, and cache slot 230-b-1 may be reused to accommodate 401 requests. In other words, the control component 260-b may identify or return the VCL _ IDX1 in response to the access request 401.

In some examples, operation 403 may include the control component 260-b loading data associated with the request of 401 from the primary array 210-b. Operation 403 may be associated with a CL load 271-b, which may include loading information from the address 215-b-1 of the primary array 210-b into the evicted cache slot 230-b-1. In various examples, the requested data (e.g., from address 215-b-1) may be provided from cache slot 230-b-1 to the requestor (e.g., after the CL load 271-b), or directly from the main array 210-b (e.g., before, after, concurrent, or in parallel with the CL load 271-b). In some examples, the architecture 400 may include a cache read register (not shown), and the index of the cache slot 230-b-1 may be passed to the cache read register to delay or suppress subsequent access operations on the address 215-b-1 (e.g., after a read of the address 215-b-1 associated with the CL load 271-b).

In some examples (e.g., to make a cache slot 230 available in the cache 220-b), the operation 404 may include the control component 260-b performing a synchronization (e.g., CL synchronization 272-b) between the cache slot 230-b-2 and the main array 210-b (e.g., the address 215-b-2 of one or more memory cells in the main array 210-b).

In some examples, operation 405 may include control component 260-b passing the index of cache slot 230-b-2 (e.g., VCL IDX9) to cache delay register 240-b. Passing the index of cache slot 230-b-2 to cache delay register 240-b may delay or suppress subsequent access operations on address 215-b-2 (e.g., after a write to address 215-b-2 associated with CL sync 272-b).

Fig. 5 illustrates an example of an architecture 500 that supports a cache architecture of a memory device in accordance with the operations of the examples disclosed herein. Architecture 500 includes a main array 210-c, a cache 220-c, a cache latency register 240-c, a control component 260-c, and a bus 265-c, each of which may be an example of a corresponding component described with reference to architecture 200 of FIG. 2. In the example of fig. 5, the control component 260-c may be configured to operate the architecture 500 on a "full" or "nearly full" condition with a cache hit, which may include one or more of operations 501-504.

In some examples, operation 501 may include control component 260-c receiving an access request (e.g., a read request, a CL read, or a write request from host device 105). The received request may include or otherwise refer to an address 215-c-1 of one or more memory cells in the main array 210-c. Control component 260-c may identify that information associated with the received request is present in cache 220-c (e.g., at cache slot 230-c-1, resources are mapped based on the address of control component 260-c), and may identify that cache 220-c is operating at a full or nearly full condition (e.g., identify that no empty cache slot 230 is present in cache 220-c, identify a condition that the amount of empty cache slots 230 in cache 220-c is less than or equal to (N CDR + 1)). The requested data (e.g., associated with address 215-c-1 and cache slot 230-c-1) may be provided from cache slot 230-c-1 to the requestor.

In some examples, operation 502 may include control component 260-c clearing the cache slot index from cache latency register 240-c (e.g., containing the index or address of cache slot 230 numbered 1-8 because cache latency register 240-c is full). In some examples, the controlling component 260-c may clear the earliest address or index of the cache delay register 240-c (e.g., clear VCL _ IDX 1). However, in some examples, based at least in part on the "hit" condition identified in operation 501, the control component 260-c may clear the index (e.g., VCL _ IDX6) of the cache slot 230-c-1 associated with the hit.

In other words, if a cache slot 230 is accessed before the associated time expires, the hold time may be stopped. For example, the control component 260-c may identify that the cache slot 230-c-1 indicates or is included in the cache delay register 240-c (e.g., based at least in part on the cache slot 230-c-1 having a cache line holding value CL _ H ═ 1), which may be accompanied by the control component 260-c performing a search (e.g., from beginning to end) of the index associated with the cache slot 230-c-1 on the cache delay register 240-c. In some examples, clearing the index of cache slot 230-c-1 (e.g., from a middle position of cache delay register 240-c) may entail shifting other indices (e.g., VCL _ IDX1 through VCL _ IDX5) up one position in cache delay register 240-c.

In some examples (e.g., to make a cache slot 230 available in the cache 220-c), the operations 503 may include the control component 260-c performing a synchronization (e.g., CL synchronization 272-c) between the cache slot 230-c-2 and the main array 210-c (e.g., the address 215-c-2 of one or more memory cells in the main array 210-c).

In some examples, operation 504 may include control component 260-c passing the index of cache slot 230-c-2 (e.g., VCL _ IDX10) to cache delay register 240-c. Passing the index of cache slot 230-c-2 to cache delay register 240-c may delay or suppress subsequent access operations on address 215-c-2 (e.g., after a write to address 215-c-2 associated with CL sync 272-c).

Fig. 6 illustrates an example of a process flow 600 to support a cache architecture of a memory device in accordance with examples disclosed herein. The process flow may be performed by the memory device 110, such as a process flow including the control component 260 described with reference to fig. 2-5.

At 605, the process flow 600 may begin. In various examples, operation 605 may initiate or otherwise be based at least in part on an access command (e.g., received at control component 260, received from host device 105). In some examples, the access command may include a memory address, such as an address of the main array 210, an address of the cache 220, or some other indication of information targeted by the access command.

At 610, the process flow 600 may include performing a cache delay registry check. For example, at 610, the control component 260 may determine whether the address of the cache 220 associated with the access command is included in the cache delay register 240, or otherwise determine whether the information targeted by the access command is associated with the address of the indirectly accessed main array 210 (e.g., according to the cache line hold flag CL _ H).

At 615, the process flow 600 may include determining whether information associated with the access command is available in the cache 220. For example, control component 260 may determine whether a cache line address included in the access command is included in the cache, or whether a cache line address (e.g., an address of main array 210) otherwise associated with the access command maps to cache 220. If so, the process flow 600 may proceed to 655, and if not, the process flow 600 may proceed to 620.

At 620, process flow 600 may include evaluating cache 220 against a nearly full condition. For example, control component 260 may determine whether the amount of empty cache slots 230 in cache 220 is less than or equal to (N _ CDR + 1). If so, process flow may proceed to 625, and if not, process flow may proceed to 640.

At 625, process flow 600 may include selecting a victim cache line (e.g., a cache slot 230 that can be evicted). For example, the control component 625 may select a cache slot 230 having a cache line assigned value CL _ a ═ 1 and a cache line hold value CL _ H ═ 0.

At 630, after the victim cache line is selected, process flow 600 may include setting the cache line hold value of the selected cache slot 230 to CL _ H-0 (e.g., prior to writing new information to the selected cache slot 230). At 635, the process flow may include inserting an address of an index of the selected victim cache line into the cache delay register 240 (e.g., to delay subsequent access operations after accessing the main array 210 in response to an access command associated with starting the process flow 600).

At 640, process flow 640 may include allocating the evicted cache line. For example, regardless of whether the associated cache slot 230 is empty or selected as a victim cache line, the control component 625 can allocate the cache slot 230 to hold information associated with the access command. At 645, process flow 600 may include reading a storage element (e.g., main array 210) and populating the evicted cache line with read information. At 650, the process flow 600 may include returning the address or index of the evicted cache line, and the process flow 600 may proceed to completion at 675.

At 655, where information associated with the access command is present in the cache, the process flow may include an address or index (e.g., CL _ ID) to return the associated cache line.

At 660, the process flow 600 may include evaluating whether an address of an associated cache line is present in the cache delay register 240 (e.g., whether the cache line hold flag is set to CL _ H-0 or CL _ H-1). If so, the process flow 600 may proceed to 665, and if not, the process flow 600 may proceed to 675 for completion.

At 665, when the associated cache line containing information of the access command is also identified in the cache delay register 240, the indication (e.g., CL _ ID) may be removed from the cache delay register 240. At 670, the cache line hold flag for the associated cache line may be set to CL _ H ═ 0, and process flow may proceed to completion at 675.

Fig. 7 illustrates a block diagram 700 of a memory device 705 that supports a cache architecture of the memory device, according to an example disclosed herein. The memory device 705 may be an example of aspects of the memory devices described with reference to fig. 1-6. Memory device 705 may include a memory array 710, an access command receiver component 715, a cache component 720, a cache register component 725, an access operation component 730, a cache element hold indication component 735, an access location determination component 740, an eviction determination component 745, and a data transmitter component 750. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

The access command receiver component 715 may be configured to receive an access command. In some examples, access command receiver component 715 may receive a command to write information to a memory device. In some examples, access command receiver component 715 may receive a command to read information from a memory device.

Cache component 720 may be configured to write information to the cached address based on the command received by access command receiver component 715. In some examples, cache component 720 may be configured to write information from memory array 710 to an address of the cache based on access command receiver component 715 receiving the command. In some examples, cache component 720 may be configured to write information to the cache based on the address of the cache being identified for eviction. In some examples, cache component 720 may be configured to support writing information from an address to memory array 710 based on the address identifying the cache for eviction.

In some examples, the cache register component 725 may store an indication of the address of the cache in a FIFO register or otherwise configured cache address register based on writing information to the cache. In some examples, the cache register component 725 may store an indication of the address of the cache in a FIFO register or otherwise configured cache address register based on writing information from the memory array 710 to the cache. In some examples, the cache register component 725 may store an indication of the address of the cache in a FIFO register or otherwise configured cache address register based on writing information to the memory array 710.

In some examples, the cache register component 725 may store an indication of the address of the cache in a second FIFO register or otherwise configured cache address register based on the address at which information is written from the memory array 710 to the cache.

In some examples, the cache register component 725 may remove the indication of the address from the register based on the access command receiver component 715 receiving a command (e.g., write information, read information). In some examples, cache register component 725 may remove the indication of the address from the register based on determining to access information from the cache.

The access operation component 730 may perform operations based on indications of cache addresses stored in registers of the cache register component 725. In some examples, access operation component 730 may write information to memory array 710 based on a command received by access command receiver component 715. In some examples, access operation component 730 may be configured to write information from memory array 710 to cache component 720. In some examples, access operation component 730 may be configured to write information from cache component 720 to memory array 710.

The cache element hold indication component 735 may store (e.g., based on writing information to the cache, based on writing information from the memory array 710 to an address of the cache) an indication that information stored at an address of the cache is to be maintained in the cache. In some examples, cache element hold indication component 735 may store (e.g., based on an indication of removal of an address from a register of cache register component 725) an indication that an address of the cache is available for eviction.

Access location determining component 740 may be configured to determine whether to access information from cache component 720 or memory array 710 (e.g., based on a register of cache register component 725, based on cache component 720 or a cache element holding an address map or flag of indicating component 735). In some examples, access location determining component 740 may determine to access information from memory array 710 based on an address associated with a command not included in a register of cache register component 725. In some examples, access location determining component 740 may determine to access information from cache component 720 based on an address associated with a command contained in a register of cache register component 725.

In some examples, the eviction determining component 745 may identify the address of the cache used for the eviction (e.g., based on the register of the cache register component 725 based on the command received by the access command receiver component 715). In some examples, eviction determining component 745 may determine to perform an eviction based on the amount of entries in the registers of cache register component 725.

In some examples, data transmitter component 750 may be configured to transmit information to a host device coupled with memory device 705 (e.g., based on a command received by access command receiver component 715).

Fig. 8 illustrates a flow diagram showing one or more methods 800 of supporting a cache architecture of a memory device, in accordance with aspects of the present disclosure. The operations of method 800 may be implemented by a memory device described herein or components thereof. For example, the operations of method 800 may be performed by the memory device described with reference to FIG. 7. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware.

At 805, the method 800 can include receiving a command to write information (e.g., to a memory device). 805 may be performed according to the methods described herein. In some examples, aspects of the operations of 805 may be performed by the access command receiver component described with reference to fig. 7.

At 810, the method 800 may include writing information to an address of a cache (e.g., of a memory device) based on receiving the command. The operations of 810 may be performed according to the methods described herein. In some examples, aspects of the operations of 810 may be performed by the cache component described with reference to fig. 7.

At 815, the method 800 may include storing, in a FIFO register (e.g., of a memory device), an indication of an address of the cache based on writing the information to the cache. 815 may be performed according to the methods described herein. In some examples, aspects of the operation of 815 may be performed by the cache register component described with reference to fig. 7.

At 820, the method 800 may include performing an operation (e.g., of a memory device) based on an indication to store an address of a cache in a FIFO register. 820 may be performed according to the methods described herein. In some examples, aspects of the operations of 820 may be performed by the access operation component described with reference to fig. 7.

In some examples, an apparatus described herein may perform one or more methods, such as method 800. The apparatus may include features, means, circuitry, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a command to write information to the device; based on receiving the command, writing the information to an address of a cache of the device; based on writing the information to the cache, storing an indication of the address of the cache in a FIFO register of the device; and performing an operation (e.g., an access operation) based on the indication to store the address of the cache in the FIFO register.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: based on the command, the information is written to a memory array (e.g., of a memory device, of the apparatus).

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: based on writing the information to the cache, storing an indication that the information stored at the address of the cache is to be maintained in the cache.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: a second command to write second information (e.g., to the memory device, to the apparatus) is received (e.g., at the memory device, at the apparatus) and the indication of the address is removed from the FIFO register based on receiving the second command.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: storing an indication that the address of the cache is available for eviction based on the indication to remove the address from the FIFO register.

Some examples of the method 800 and apparatus described herein may further include an operation, feature, means, circuitry, or instruction for receiving (e.g., at the memory device, at the apparatus) a third command to read third information (e.g., from the memory device, from the apparatus), and performing the operation may include determining whether to access the third information from the cache or from a memory array (e.g., based on the FIFO register, based on an address map or flag of the cache).

In some examples of the method 800 and apparatus described herein, determining whether to access the third information from the cache or the memory array may include an operation, feature, means, circuitry, or instruction for determining to access the third information from the memory array based on an address associated with the third command not being included in the FIFO register.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: writing the third information from the memory array to a second address of the cache, and storing an indication of the second address of the cache in a second FIFO register of the memory device based on the second address at which the information is written from the memory array to the cache.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: determining to access the third information from the cache based on an address associated with the third command being included in the FIFO register.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: based on determining to access the third information from the cache, removing the indication of the address from the FIFO register.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: receiving (e.g., at the memory device, at the apparatus) a fourth command to write fourth information (e.g., to the memory device, to the apparatus), identifying a third address of the cache for eviction of the cache based on the fourth command and the FIFO register, and writing the fourth information to the cache based on identifying the third address.

Some examples of the method 800 and apparatus described herein may further include an operation, feature, means, circuitry, or instruction for determining to perform the eviction based on an amount of entries in the FIFO register and an amount indicating cache lines available for eviction, and the third address identifying the cache for the eviction may be based on determining to perform the eviction.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: based on identifying the third address of the cache for the eviction, writing fifth information from the third address of the cache to a memory array.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: storing, in the FIFO register, an indication of the third address of the cache based on writing the fifth information to the memory array.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: receiving (e.g., at the memory device, at the apparatus) a fifth command to write sixth information (e.g., to the memory device, to the apparatus), identifying a fourth address of the cache for eviction of the cache based on the fifth command and the FIFO register, and writing the sixth information to the cache based on identifying the fourth address.

Fig. 9 illustrates a flow diagram showing one or more methods 900 to support a cache architecture of a memory device, in accordance with aspects of the present disclosure. The operations of method 900 may be implemented by a memory device described herein or components thereof. For example, the operations of method 900 may be performed by the memory device described with reference to fig. 7. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware.

At 905, the method 900 can include receiving a command to read information (e.g., from a memory device). 905 operations may be performed according to methods described herein. In some examples, aspects of the operations of 905 may be performed by the access command receiver component described with reference to fig. 7.

At 910, method 900 can include, based on receiving the command, writing information from a memory array (e.g., of the memory device) to an address of a cache (e.g., of the memory device). 910 may be performed according to the methods described herein. In some examples, aspects of the operations of 910 may be performed by the cache component described with reference to fig. 7.

At 915, the method 900 may include storing an indication of an address of the cache in a FIFO register (e.g., of the memory device) based on writing information from the memory array to the cache. 915 may be performed according to the methods described herein. In some examples, aspects of the operations of 915 may be performed by the cache register component described with reference to fig. 7.

At 920, the method 900 may include performing an operation (e.g., of a memory device) based on the FIFO register. The operations of 920 may be performed according to the methods described herein. In some examples, aspects of the operations of 920 may be performed by the access operation component described with reference to fig. 7.

In some examples, an apparatus described herein may perform one or more methods, such as method 900. The apparatus may include features, means, circuitry, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a command to read information from the device; based on receiving the command, writing the information from a memory array of the device to an address of a cache of the device; based on writing the information from the memory array to the cache, storing an indication of the address of the cache in a FIFO register of the device; and performing an operation based on the FIFO register.

Some examples of the method 900 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: based on the command, the information is transmitted to a host device (e.g., coupled with the memory device, coupled with the apparatus).

Some examples of the method 900 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: based on the address at which the information is written from the memory array to the cache, storing an indication that the information stored at the address of the cache is to be maintained in the cache.

Some examples of the method 900 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: a second command to read second information (e.g., from the memory device, from the apparatus) is received, and the indication of the address is removed from the FIFO register based on receiving the second command.

Some examples of the method 900 and apparatus described herein may further include operations, features, means, circuitry, or instructions for: storing an indication that the address of the cache is available for eviction based on the indication to remove the address from the FIFO register.

It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or modified, and that other embodiments are possible. Further, portions from two or more methods may be combined.

An apparatus is described. The apparatus may include: a memory array including a first set of memory cells; a cache including a second set of memory cells; a FIFO register; and a control component coupled with the memory array, the cache, and the FIFO register. The control component may be configured to cause the apparatus to: receiving a command to write information to the device; based on receiving the command, writing the information to an address of the cache; based on writing the information to the cache, storing an indication of the address of the cache in the FIFO register; and performing an operation based on the indication to store the address of the cache in the FIFO register.

In some examples, the control component may be further configured to cause the apparatus to write the information to the memory array based on the command.

In some examples, the control component may be further configured to cause the apparatus to store an indication that the information stored at the address of the cache is to be maintained in the cache based on writing the information to the cache.

In some examples, the control component may be further configured to cause the apparatus to receive a second command to write second information to the apparatus, and based on receiving the second command, remove the indication of the address from the FIFO register.

In some examples, the control component may be further configured to cause the apparatus to store an indication that the address of the cache is available for eviction based on the indication to remove the address from the FIFO register.

In some examples, the control component may be further configured to cause the apparatus to receive a third command to read third information from the apparatus, and to perform the operation, the control component may be configured to cause the apparatus to determine whether to access the third information from the cache or from the memory array (e.g., FIFO register based, cache based address map or flag).

In some examples, to determine whether to access the third information from the cache or the memory array, the control component may be configured to cause the apparatus to determine to access the third information from the memory array based on an address associated with the third command not being included in the FIFO register.

In some examples, the control component may be further configured to cause the apparatus to write the third information from the memory array to a second address of the cache, and store an indication of the second address of the cache in a second FIFO register of the apparatus based on the second address at which the third information is written from the memory array to the cache.

In some examples, to determine whether to access the third information from the cache or the memory array, the control component may be configured to cause the apparatus to determine to access the third information from the cache based on an address associated with the third command being included in the FIFO register.

In some examples, the control component may be further configured to cause the apparatus to remove the indication of the address from the FIFO register based on determining to access the third information from the cache.

In some examples, the control component may be further configured to cause the apparatus to receive a fourth command to write fourth information to the apparatus, identify a third address of the cache for eviction of the cache based on the fourth command and the FIFO register, and write the fourth information to the cache based on identifying the third address.

In some examples, the control component may be further configured to cause the apparatus to determine to perform the eviction based on an amount of entries in the FIFO register and an amount indicating cache lines available for eviction, and identify the third address of the cache for the eviction based on determining to perform the eviction.

In some examples, the control component may be further configured to cause the apparatus to write fifth information from the third address of the cache to the memory array based on identifying the third address of the cache for the eviction.

In some examples, the control component may be further configured to cause the apparatus to store an indication of the third address of the cache in the FIFO register based on writing the fifth information to the memory array.

In some examples, the control component may be further configured to cause the apparatus to operate the FIFO register with an amount of entries based on a target duration between successive accesses of addresses of the memory array and an access command interval of the apparatus.

In some examples, the first set of memory cells includes non-volatile storage elements and the second set of memory cells includes volatile storage elements.

Another apparatus is described. The apparatus may include: a memory array including a first set of memory cells; a cache including a second set of memory cells; a FIFO register; and a control component coupled with the memory array, the cache, and the FIFO register. The control component may be configured to cause the apparatus to: receiving a command to read information in the device; based on receiving the command, writing the information from the memory array to an address of the cache; storing, in the FIFO register, an indication of the address of the cache based on the address at which the information is written from the memory array to the cache; and performing an operation based on the indication to store the address of the cache in the FIFO register.

In some examples, the control component may be further configured to cause the apparatus to transmit the information to a host device coupled with the apparatus based on the command.

In some examples, the control component may be further configured to cause the apparatus to store an indication that the information stored at the address of the cache is to be maintained in the cache based on writing the information from the memory array to the address of the cache.

In some examples, the control component may be further configured to cause the apparatus to receive a second command to read second information from the apparatus, and based on receiving the second command, remove the indication of the address from the FIFO register.

In some examples, the control component may be further configured to cause the apparatus to store an indication that the address of the cache is available for eviction based on the indication to remove the address from the FIFO register.

In some examples, the first set of memory cells includes non-volatile storage elements and the second set of memory cells includes volatile storage elements.

Another apparatus is described. The apparatus may include: a memory array including a first set of memory cells; a cache including a second set of memory cells; a FIFO register; and a control component coupled with the memory array, the cache, and the FIFO register. The control component may be used to store an indication of an address of the cache based on accessing the memory array.

A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a command to write information to the electronic device; based at least in part on receiving the command, writing the information to an address of a cache of the electronic device; storing, in a FIFO register of the electronic device, an indication of the address of the cache based at least in part on writing the information to the cache; and performing an operation of the electronic device based at least in part on the indication to store the address of the cache in the FIFO register.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to write the information to a memory array of the electronic device based at least in part on the command.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to store an indication that the information stored at the address of the cache is to be maintained in the cache based at least in part on writing the information to the cache.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to receive a second command to write second information to the electronic device, and remove the indication of the address from the FIFO register based at least in part on receiving the second command.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to store an indication that the address of the cache is available for eviction based at least in part on the indication to remove the address from the FIFO register.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to receive a third command to read third information from the electronic device. In some examples, to perform operations of the electronic device, the instructions, when executed by the processor of the electronic device, cause the electronic device to determine whether to access the third information from the cache based at least in part on the FIFO register.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to receive a fourth command to write fourth information to the electronic device, identify a third address of the cache for eviction of the cache based at least in part on the fourth command and the FIFO register, and write the fourth information to the cache based at least in part on identifying the third address.

A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a command to read information from the electronic device; based at least in part on receiving the command, writing the information from a memory array of the electronic device to an address of a cache of the electronic device; storing, in the FIFO register, an indication of the address of the cache based at least in part on writing the information from the memory array to the address of the cache; and performing an operation of the electronic device based at least in part on the indication to store the address of the cache in the FIFO register.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to transmit the information to a host device coupled with the electronic device based at least in part on the command.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to store an indication that the information stored at the address of the cache is to be maintained in the cache based at least in part on writing the information from the memory array to the address of the cache.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to receive a second command to read second information from the electronic device, and remove the indication of the address from the FIFO register based at least in part on receiving the second command.

In some examples of the non-transitory computer-readable medium, the instructions, when executed by the processor of the electronic device, further cause the electronic device to store an indication that the address of the cache is available for eviction based at least in part on the indication to remove the address from the FIFO register.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may show the signals as a single signal; however, one of ordinary skill in the art will appreciate that the signals may represent a signal bus, where the bus may have a variety of bit widths.

The terms "in electrical communication," "in conductive contact," "in connection with," and "in coupling with" may refer to a relationship between components that enables a signal to flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there are any conductive paths between the components that can support a signal flowing between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed based on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

The term "coupled" refers to a condition that moves from an open circuit relationship between components, in which a signal cannot currently be transmitted between the components through a conductive path, to a closed circuit relationship between the components, in which a signal can be transmitted between the components through a conductive path. When a component, such as a controller, couples other components together, then the component causes a change that allows signals to flow between the other components through a conductive path that previously did not allow signals to flow.

The term "isolation" refers to the relationship between components where signals cannot currently flow between components. If there is an open circuit between the components, they are isolated from each other. For example, components that are spaced apart by a switch positioned between two components are isolated from each other when the switch is open. When the controller isolates the two components, the controller implements the following changes: signals are prevented from flowing between components using conductive paths that previously permitted signal flow.

Devices including memory arrays discussed herein may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-Sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping using various chemistries including, but not limited to, phosphorous, boron, or arsenic. The doping may be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping method.

The switching components or transistors discussed herein may represent Field Effect Transistors (FETs) and include three terminal devices including a source, a drain and a gate. The terminals may be connected to other electronic components through conductive materials (e.g., metals). The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The description set forth herein in connection with the appended drawings describes example configurations and is not intended to represent all examples that may be practiced or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," and is not "preferred" or "advantageous" over other examples. The detailed description includes specific details in order to provide an understanding of the described technology. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software for execution by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that perform a function may also be physically located at various positions, including being distributed such that portions of the function are performed at different physical locations. Also, as used herein (including in the claims), a "or" as used in a list of items (e.g., a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Also, as used herein, the phrase "based on" should not be construed as referring to a set of closed conditions. For example, exemplary steps described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, the phrase "based on" as used herein should likewise be construed as the phrase "based at least in part on".

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, a non-transitory computer-readable medium may comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), Compact Disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the present invention is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.