阅读说明：本技术 一种时域量化的高速流水线adc电路 (High-speed assembly line ADC circuit of time domain quantization ) 是由 石春琦 朱晓剑 张润曦 申家齐 于 2021-08-20 设计创作，主要内容包括：本发明公开了一种时域量化的高速流水线ADC电路,所述电路主要包括2级子ADC,第一级为4比特量化,第二级为5比特量化,两级之间包含1比特冗余,每一级均通过电压时间转换电路VTC将输入电压转化为时间以脉宽的形式输出给时间数字转换器TDC进行时域上的量化,两级之间采用高速动态残差放大器RA快速对第一级子ADC输出残差电压放大2倍。相对于传统电压域量化的高速ADC,本发明避免了使用传统的运算放大器,降低了电路的功耗。时域量化具有4ps的时间分辨率,可实现高速量化,并支持工艺演进。本发明高速ADC采样频率为800MS/s,在奈奎斯特输入下,有效位数ENOB为7.64Bit,无杂散动态范围SFDR为58.3dB,功耗仅为8.05mW。(The invention discloses a high-speed pipeline ADC circuit with time domain quantization, which mainly comprises 2 levels of sub ADCs, wherein the first level is 4-bit quantization, the second level is 5-bit quantization, 1-bit redundancy is included between the two levels, each level converts input voltage into time through a voltage time conversion circuit VTC and outputs the time to a time digital converter TDC in a pulse width mode for the time domain quantization, and a high-speed dynamic residual error amplifier RA is adopted between the two levels to quickly amplify the residual error voltage output by the first level of sub ADC by 2 times. Compared with the traditional high-speed ADC with voltage domain quantization, the invention avoids the use of the traditional operational amplifier and reduces the power consumption of the circuit. The time domain quantization has a time resolution of 4ps, can realize high-speed quantization, and supports process evolution. The sampling frequency of the high-speed ADC is 800MS/s, the effective digit ENOB is 7.64 bits under Nyquist input, the spurious-free dynamic range SFDR is 58.3dB, and the power consumption is only 8.05 mW.)

1. The high-speed pipeline ADC circuit with the time domain quantization function is characterized by comprising a gate voltage Bootstrap switch circuit Bootstrap, a clock generation circuit CLK _ GEN and a first voltage time conversion circuit VTC₁TDC of a first time-to-digital converter₁First time comparator TCMP₁A capacitive digital-to-analog conversion circuit CDAC, a first Decoder1, an inter-stage residual voltage amplifier RA, and a second voltage-time conversion circuit VTC₂A second time-to-digital converter TDC₂A second time comparator TCMP₂The second decoding circuit Decoder2 and the data alignment circuit Encoder have the following specific forms:

the input ends of the clock generation circuit CLK _ GEN are respectively connected with an input clock phi_CLKSum residual amplifier operation flag signal phi_SIGNThe clock generation circuit CLK _ GEN outputs reset clock signals phi_RSTResidual voltage amplification clock signal phi_AMPFirst stage circuit operating clock phi₁Second stage circuit operating clock phi₂And a sampling clock phi_S(ii) a The input end of the gate voltage bootstrapped switch circuit Bootstrap is respectively connected with input signals Signal _ VIP and Signal _ VIN; the clock port of the grid voltage bootstrapped switch circuit Bootstrap is connected with a sampling clock phi_SThe output end of the gate voltage Bootstrap switch circuit Bootstrap is a first sampling signal VCMN and a second sampling signal VCMP; first voltage-time conversion circuit VTC₁The input end of the first voltage-time conversion circuit is respectively connected with a first sampling signal VCMN and a second sampling signal VCMP, and the first voltage-time conversion circuit VTC₁Respectively are VOP_VTC1And VON_VTC1First stage circuit operating clock phi₁Is connected with a first voltage time conversion circuit VTC₁The clock control port of (a); first time comparator TCMP₁Is inputtedThe ends are respectively connected with a first voltage time conversion circuit VTC₁Output VOP of_VTC1And VON_VTC1First time comparator TCMP₁Is D1<8>(ii) a TDC of first time digital converter₁The input ends of the first and second voltage-time conversion circuits are respectively connected with the VTC₁Output VOP of_VTC1And VON_VTC1First stage circuit operating clock phi₁Connecting a first time-to-digital converter TDC₁The first time comparator TCMP₁Output D1<8>Connecting a first time-to-digital converter TDC₁A polarity control terminal of, a first time to digital converter TDC₁The output being bus D1<7:1>(ii) a Logic control ends of the capacitive digital-to-analog conversion circuit CDAC are respectively connected to the first time comparator TCMP₁Output D1<8>And a first time-to-digital converter TDC₁The output of (D) bus D1<7:1>The output end of the capacitive D/A conversion circuit CDAC is respectively connected to a first sampling signal VCMN and a second sampling signal VCMP, and the working clock phi of the first-stage circuit₁A clock control port connected to the capacitive digital-to-analog conversion circuit CDAC; the input terminals of the first Decoder circuit Decoder1 are respectively connected to the first time comparator TCMP₁Output D1<8>And a first time-to-digital converter TDC₁The output of (D) bus D1<7:1>The output end of the first Decoder1 is a bus D<8:5>(ii) a The input ends of the inter-stage residual voltage amplifier RA are respectively connected with the first sampling signal VCMN and the second sampling signal VCMP, and the output ends of the inter-stage residual voltage amplifier RA are respectively VOP_RA、VON_RASum residual amplifier operation flag signal phi_SIGNThe reset end of the interstage residual error voltage amplifier RA is connected with a reset clock signal phi_RSTThe clock control end of the interstage residual voltage amplifier RA is connected with a residual voltage amplification clock signal phi_AMP(ii) a Second voltage-time conversion circuit VTC₂Are respectively connected with the output port VOP of the inter-stage residual voltage amplifier RA_RAAnd VON_RASecond voltage-time conversion circuit VTC₂Respectively are VOP_VTC2And VON_VTC2Second voltage-time conversion circuit VTC₂Clock control ofEnd connected second stage circuit working clock phi₂(ii) a Second time comparator TCMP₂The input ends of the first and second voltage time conversion circuits are respectively connected with a VTC₂Output VOP of_VTC2And VON_VTC2Second time comparator TCMP₂Is D2<16>(ii) a Second time-to-digital converter TDC₂The input ends of the first and second voltage time conversion circuits are respectively connected with a VTC₂Output VOP of_VTC2And VON_VTC2Second time-to-digital converter TDC₂The clock control end of the second stage circuit is connected with a working clock phi of the second stage circuit₂Second time-to-digital converter TDC₂The polarity control end of the first time comparator is connected with the first time comparator TCMP₂Output D2<16>Second time-to-digital converter TDC₂The output being bus D2<15:1>(ii) a The input terminals of the second decoding circuit Decoder2 are respectively connected to the second time comparator TCMP₁Output D2<16>And a second time-to-digital converter TDC₂The output of (D) bus D2<15:1>The output end of the second Decoder2 is a bus D<4:0>(ii) a The output of the first Decoder circuit Decoder1 being bus D<8:5>And an output terminal of the second decoding circuit Decoder2, i.e., a bus D<4:0>Respectively connected to the input terminal of the data alignment circuit Encoder and the sampling clock phi_SThe output end of the data alignment circuit Encoder is an output code word B<7:0>。

Technical Field

The invention belongs to the technical field of integrated circuit design, and relates to a high-speed pipeline ADC circuit based on a 40nm CMOS process and used for time domain quantization in a wireless communication system.

Background

The analog-to-digital converter is used as an interface circuit of an analog signal and a digital signal, and is widely applied to high-speed wireless receivers, mobile phones, data acquisition systems and the like. Most of the applications need high-speed and low-power-consumption analog-to-digital converters, and although the traditional flash and Pipeline ADCs can realize high-speed applications, the power consumption is too large, and part of application scenarios are unacceptable.

With the continuous development of the CMOS process of the integrated circuit, the intrinsic gain of the transistor is continuously reduced, and the design difficulty of the operational amplifier in the traditional Pipeline ADC is increased. This requires that the ADC structure mostly adopts digital circuits to develop the features of advanced CMOS processes and achieve high-speed and low-power design.

Disclosure of Invention

The invention aims to provide a high-speed pipeline ADC circuit for time domain quantization.

The specific technical scheme for realizing the purpose of the invention is as follows:

a high-speed pipeline ADC circuit with quantized time domain is characterized in that the circuit comprises a gate voltage Bootstrap switch circuit Bootstrap, a clock generation circuit CLK _ GEN and a first voltage time conversion circuit VTC₁TDC of a first time-to-digital converter₁First time comparator TCMP₁A capacitive digital-to-analog conversion circuit CDAC, a first Decoder1, an inter-stage residual voltage amplifier RA, and a second voltage-time conversion circuit VTC₂A second time-to-digital converter TDC₂A second time comparator TCMP₂The second decoding circuit Decoder2 and the data alignment circuit Encoder have the following specific forms:

the input ends of the clock generation circuit CLK _ GEN are respectively connected with an input clock phi_CLKSum residual amplifier operation flag signal phi_SIGNThe clock generation circuit CLK _ GEN outputs reset clock signals phi_RSTResidual voltage amplification clock signal phi_AMPFirst stage circuit operating clock phi₁Second stage circuit operating clock phi₂And a sampling clock phi_S(ii) a The input end of the gate voltage bootstrapped switch circuit Bootstrap is respectively connected with input signals Signal _ VIP and Signal _ VIN; the clock port of the grid voltage bootstrapped switch circuit Bootstrap is connected with a sampling clock phi_SThe output end of the gate voltage Bootstrap switch circuit Bootstrap is a first sampling signal VCMN and a second sampling signal VCMP; first voltage-time conversion circuit VTC₁The input end of the first voltage-time conversion circuit is respectively connected with a first sampling signal VCMN and a second sampling signal VCMP, and the first voltage-time conversion circuit VTC₁Respectively are VOP_VTC1And VON_VTC1First stage circuit operating clock phi₁Is connected with a first voltage time conversion circuit VTC₁The clock control port of (a); first time comparator TCMP₁The input ends of the first and second voltage-time conversion circuits are respectively connected with the VTC₁Output VOP of_VTC1And VON_VTC1First time comparator TCMP₁Is D1<8>(ii) a TDC of first time digital converter₁The input ends of the first and second voltage-time conversion circuits are respectively connected with the VTC₁Output VOP of_VTC1And VON_VTC1First stage circuit operating clock phi₁Connecting a first time-to-digital converter TDC₁The first time comparator TCMP₁Output D1<8>Connecting a first time-to-digital converter TDC₁A polarity control terminal of, a first time to digital converter TDC₁The output being bus D1<7:1>(ii) a Logic control ends of the capacitive digital-to-analog conversion circuit CDAC are respectively connected to the first time comparator TCMP₁Output D1<8>And a first time-to-digital converter TDC₁The output of (D) bus D1<7:1>The output end of the capacitive D/A conversion circuit CDAC is respectively connected to a first sampling signal VCMN and a second sampling signal VCMP, and the working clock phi of the first-stage circuit₁A clock control port connected to the capacitive digital-to-analog conversion circuit CDAC; the input terminals of the first Decoder circuit Decoder1 are respectively connected to the first time comparator TCMP₁Output D1<8>And a first time-to-digital converter TDC₁The output of (D) bus D1<7:1>The output end of the first Decoder1 is a bus D<8:5>(ii) a The input ends of the inter-stage residual error voltage amplifier RA are respectively connected with the first sampling signal VCMN and a second sampling signal VCMP, the output of the inter-stage residual voltage amplifier RA is VOP_RA、VON_RASum residual amplifier operation flag signal phi_SIGNThe reset end of the interstage residual error voltage amplifier RA is connected with a reset clock signal phi_RSTThe clock control end of the interstage residual voltage amplifier RA is connected with a residual voltage amplification clock signal phi_AMP(ii) a Second voltage-time conversion circuit VTC₂Are respectively connected with the output port VOP of the inter-stage residual voltage amplifier RA_RAAnd VON_RASecond voltage-time conversion circuit VTC₂Respectively are VOP_VTC2And VON_VTC2Second voltage-time conversion circuit VTC₂The clock control end of the first stage circuit is connected with a working clock phi of the second stage circuit₂(ii) a Second time comparator TCMP₂The input ends of the first and second voltage time conversion circuits are respectively connected with a VTC₂Output VOP of_VTC2And VON_VTC2Second time comparator TCMP₂Is D2<16>(ii) a Second time-to-digital converter TDC₂The input ends of the first and second voltage time conversion circuits are respectively connected with a VTC₂Output VOP of_VTC2And VON_VTC2Second time-to-digital converter TDC₂The clock control end of the first stage circuit is connected with a working clock phi of the second stage circuit₂Second time-to-digital converter TDC₂The polarity control end of the first time comparator is connected with the first time comparator TCMP₂Output D2<16>Second time-to-digital converter TDC₂The output being bus D2<15:1>(ii) a The input terminals of the second decoding circuit Decoder2 are respectively connected to the second time comparator TCMP₁Output D2<16>And a second time-to-digital converter TDC₂The output of (D) bus D2<15:1>The output end of the second Decoder2 is a bus D<4:0>(ii) a The output of the first Decoder circuit Decoder1 being bus D<8:5>And an output terminal of the second decoding circuit Decoder2, i.e., a bus D<4:0>Respectively connected to the input end of the data alignment circuit Encoder, and a sampling clock phi_SThe output end of the data alignment circuit Encoder is an output code word B<7:0>。

The invention has the advantages that:

1. the invention provides a novel high-speed ADC structure quantized on a time domain, which has the characteristic of obvious low power consumption compared with the traditional Flash structure for realizing the high-speed ADC, and the power consumption of the high-speed ADC quantized in the time domain of 800MS/s 8Bit is only 8.05 mW.

2. The high-speed pipeline structure ADC based on time domain quantization supports the process evolution, wherein a first time digital converter TDC1, a second time digital converter TDC2, a first decoder Encoder1 and a second decoder Encoder2 are digital circuits, can be digitally integrated and conveniently transplanted to different processes, and have good compatibility with a high-speed digital system.

Drawings

FIG. 1 is a block diagram of a time-domain quantization high-speed pipeline ADC circuit of the present invention;

fig. 2 is a timing diagram illustrating operation of the present invention.

Detailed Description

The invention is described in detail below with reference to the figures and examples.

The invention relates to a high-speed pipeline ADC (analog-to-digital converter) circuit with quantized time domain, which comprises a gate voltage Bootstrap switch circuit Bootstrap, a clock generation circuit CLK _ GEN and a first voltage time conversion circuit VTC₁TDC of a first time-to-digital converter₁First time comparator TCMP₁A capacitive digital-to-analog conversion circuit CDAC, a first Decoder1, an inter-stage residual voltage amplifier RA, and a second voltage-time conversion circuit VTC₂A second time-to-digital converter TDC₂A second time comparator TCMP₂A second Decoder2 and a data alignment circuit Encode.

Referring to fig. 1, the working process of the present invention is as follows:

the grid voltage bootstrapped switch circuit Bootstrap is controlled by a sampling clock phi_SThe control outputs the input signals Signal _ VIP and Signal _ VIN as a first sampling Signal VCMN and a second sampling Signal VCMP through the sampling of a capacitive digital-to-analog conversion circuit CDAC, and then the first sampling Signal VCMN and the second sampling Signal VCMP are connectedThe first stage circuit then begins operation. First voltage-time conversion circuit VTC₁Operating clock phi from first stage circuit₁The control operation converts the voltage difference between the first sampling signal VCMN and the second sampling signal VCMP into a time difference and outputs the time difference as VOP_VTC1And VON_VTC1. First time comparator TCMP₁Time-converting the first voltage to the circuit VTC₁Output VOP of_VTC1And VON_VTC1Carry out 1Bit quantization and output binary D1<8>And controlling the TDC of the first time-to-digital converter₁And (4) outputting the data. TDC of first time digital converter₁Operating clock phi from first stage circuit₁And a first time comparator TCMP₁Output D1<8>Controlling the first voltage-to-time conversion circuit VTC₁Output VOP of_VTC1And VON_VTC1Quantized in the time domain and output as a thermometer code as bus D1<7:1>. The first Decoder circuit Decoder1 inputs the bus D1 in the form of thermometer code<7:1>And 1Bit binary signal D1<8>Bus D converted into binary and output as 4Bit in bus form<8:5>. Capacitive analog-to-digital converter CDAC with first-stage circuit working clock phi₁Control according to input bus D1<7:1>And a first time comparator TCMP₁Output D1<8>The switching of the capacitance is performed, and the residual voltage is output on the first sampling signal VCMN and the second sampling signal VCMP. Residual error amplifier RA amplifies clock signal phi from residual voltage_AMPAnd reset clock signal phi_RSTControlling the input residual voltage to be amplified by 2 times and output as VOP_RAAnd VON_RAResidual error amplifier working flag signal phi at the completion of amplification_SIGNWill change from high to low. Second voltage-time conversion circuit VTC₂From a second stage operating clock phi₂Control of VOP_RAAnd VON_RAThe voltage difference between the two is converted into time difference and output as VOP_VTC2And VON_VTC2. Second time comparator TCMP₂Time-converting the second voltage to the circuit VTC₂Output VOP of_VTC2And VON_VTC2Carry out 1Bit quantization and output binary D2<16>And controlling the second time-to-digital converter TDC₂And (4) outputting the data.

Second time-to-digital converter TDC₂By operating the second stage circuit with a clock phi₂And a second time comparator TCMP₂Output D2<16>Control, time-conversion of voltage circuit VTC₂Output VOP of_VTC2And VON_VTC2The quantization of the time domain is performed and output as a thermometer code as a bus D2<15:1>. The second Decoder circuit Decoder2 inputs thermometer code bus D2<15:1>And 1Bit binary signal D2<16>Bus D converted into binary and output as 5Bit in bus form<4:0>. Bus D<8:5>And bus D<4:0>By a sampling clock phi through a data alignment circuit Encoder_SControl alignment of data and data D containing 1-bit redundancy<8:0>Into binary code word B finally output by ADC<7:0>。

Examples

Referring to fig. 1, the invention comprises a gate voltage Bootstrap switch circuit Bootstrap, a clock generation circuit CLK _ GEN, a first voltage time conversion circuit VTC₁TDC of a first time-to-digital converter₁First time comparator TCMP₁A capacitor array CDAC, a first Decoder1, an inter-stage residual voltage amplifier RA, and a second voltage-time conversion circuit VTC₂A second time-to-digital converter TDC₂A second time comparator TCMP₂A second Decoder2, and a data alignment circuit Encode. Firstly, according to the swing of a first-stage input signal of 400mV, a first time digital converter TDC is obtained through simulation₁Is 43.049ps to determine the first voltage-to-time conversion circuit VTC₁The gain of (A) should be 107.623 ps/V. According to the first stage output D1<8>And D1<7:0>The differential signal after 2 times of amplification can be calculated to be 0-50mV, the full swing of the second-stage circuit design is determined to be 100mV by considering the nonlinearity of the residual error amplifier and the redundancy range of the system, and the TDC of the second time-to-digital converter is obtained by simulation₂Is 95.6ps, thereby determining the second voltage-to-time conversion circuit VTC₂The gain of (A) should be 956.07 ps/V.

Referring to FIG. 2, the operation sequence of the present invention is shownFigure (a). First of all an external input clock phi_CLKThe sampling clock phi is generated by the clock generation circuit CLK _ GEN_S。

The method comprises the following steps: when sampling clock phi_SWhen the low level is converted into the high level, the grid voltage Bootstrap switch circuit Bootstrap is conducted, the capacitor array CDAC is used for sampling, and meanwhile, the working clock phi of the second-stage circuit is triggered₂And when the voltage level is changed from the low level to the high level, the second-stage circuit quantizes the residual voltage output in the last period.

Secondly, the step of: second stage circuit operating clock phi₂The conversion from low level to high level triggers the residual voltage amplification clock signal phi at the same time_AMPTransitioning from a low level to a high level.

③: when sampling clock phi_SWhen the high level is converted into the low level, the sampling is finished to obtain a first sampling signal VCMN and a second sampling signal VCMP, the grid voltage bootstrap switch is disconnected to enter a holding state, and simultaneously, the working clock phi of the first-stage circuit is triggered₁And when the low level is changed into the high level, the first-stage circuit starts to work and quantize.

Fourthly, the method comprises the following steps: when the second stage circuit finishes working, the second stage circuit works with a clock phi₂Changing from high to low level and simultaneously triggering a reset clock signal phi_RSTThe residual amplifier RA is reset from high to low.

Fifthly: when the residual error amplifier RA is reset, the working flag signal phi of the residual error amplifier is reset_SIGNIt will change from a low level to a high level,

sixthly, the method comprises the following steps: residual amplifier operation flag signal phi_SIGNAfter the low level is converted into the high level, the residual error amplifier is reset, and a reset clock signal phi is triggered after the delay of the circuit_RSTChanging from low to high ends the reset.

Seventh, the method comprises the following steps: reset clock signal phi_RSTThe delay from low level to high level through the logic circuit triggers the residual voltage amplified clock signal phi_AMPFrom high to low, the residual amplifier starts amplifying.

And (v): after the amplification of the residual error amplifier is completed, the working flag signal phi of the residual error amplifier_SIGNThe delay through the logic circuit which will change from high to low triggers the first stage circuit operating clock phi₁And changing from high level to low level, and enabling the first stage to enter a reset state and wait for sampling in the next period. The first-stage circuit and the second-stage circuit work in a pipeline mode, and the working speed of the ADC is improved.