阅读说明：本技术 处理电路 (Processing circuit ) 是由 J·P·莱索 M·J·麦克洛史蒂文斯 于 2019-07-29 设计创作，主要内容包括：本申请涉及用于信号的相乘的设备和方法。乘法电路(100)具有第一时间编码调制器(103a)和第二时间编码调制器(103b),第一时间编码调制器(103a)和第二时间编码调制器(103b)被配置来分别接收第一组合信号(S_(C1))和第二组合信号(S_(C2))并且生成各自所具有的循环频率基本上取决于所输入组合信号的值的平方的相应第一PWM信号(S_(PWM1))和第二PWM信号(S_(PWM2))。第一组合信号(S_(C1))对应于第一输入信号(S_1)与第二输入信号(S_2)之和,并且第二组合信号(S_(C2))对应于第一输入信号(S_1)与第二输入信号(S_2)之间的差。第一时间解码转换器(104a)和第二时间解码转换器(104b)接收第一PWM信号和第二PWM信号并且基于与相应的第一PWM信号或第二PWM信号的频率相关的参数来提供相应的第一计数值(D_1)和第二计数值(D_2)。减法器(105)确定第一计数值(D_1)与第二计数值(D_2)之间的差并且基于此差提供输出信号(D_(OUT))。(The present application relates to an apparatus and a method for multiplication of signals. The multiplication circuit (100) has a first time-coded modulator (103a) and a second time-coded modulator (103b), the first time-coded modulator (103a) and the second time-coded modulator (103b) being configured to receive the first combined signal (S), respectively C1 ) And a second combined signal (S) C2 ) And generating respective first PWM signals (S) each having a cycle frequency substantially dependent on the square of the value of the input combined signal PWM1 ) And a second PWM signal (S) PWM2 ). First combined signal (S) C1 ) Corresponding to the first input signal (S) 1 ) And a second input signal (S) 2 ) And a second combined signal (S) C2 ) Corresponding to the first input signal (S) 1 ) And a second input signal (S) 2 ) The difference between them. A first time decode converter (104a) and a second time decode converter (104b) receive the first PWM signal and the second PWM signal and provide a respective first count value (D) based on a parameter related to a frequency of the respective first PWM signal or second PWM signal 1 ) And a second count value (D) 2 ). A subtractor (105) determines a first count value (D) 1 ) And a second count value (D) 2 ) And providing an output signal (D) based on the difference between OUT )。)