阅读说明：本技术 开关电路、栅极驱动器和操作晶体管器件的方法 (Switching circuit, gate driver and method of operating transistor device ) 是由 金炯男 A·查理斯 M·伊马姆 雷琴 刘春晖 于 2021-04-30 设计创作，主要内容包括：公开了开关电路、栅极驱动器和操作晶体管器件的方法。在实施例中,提供了一种开关电路,其包括基于III族氮化物的半导体本体,该半导体本体包括第一单片集成的基于III族氮化物的晶体管器件和第二单片集成的基于III族氮化物的晶体管器件,第一单片集成的基于III族氮化物的晶体管器件和第二单片集成的基于III族氮化物的晶体管器件被耦合以形成半桥电路并且被布置在包括公共掺杂水平的公共异质衬底上。开关电路被配置为在至少300V的电压下操作半桥电路。(Switching circuits, gate drivers, and methods of operating transistor devices are disclosed. In an embodiment, a switching circuit is provided that includes a group III-nitride based semiconductor body including a first monolithically integrated group III-nitride based transistor device and a second monolithically integrated group III-nitride based transistor device coupled to form a half-bridge circuit and disposed on a common foreign substrate including a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300V.)

1. A multi-level gate driver for a group III-nitride based enhancement mode transistor device including a source, a gate, and a drain,

wherein during an on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to:

supplying a first gate voltage to the gate during a first time period to apply a first gate current Ig during the first time period sufficient to turn on the gate and to maintain the gate in an on state₁And an

Supplying a second gate voltage to the gate during a second period after the first period to apply a second gate current Ig to the gate during the second period₂To keep the gate in an on-state, where Ig₁>5Ig₂Or Ig or₁>10Ig₂Either the first or the second substrate is, alternatively,

wherein during an on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to:

supplying a first gate current Ig to the gate during a first time period₁Wherein Ig is₁Is sufficient to turn on the gate and to keep the gate in a conductive state, an

Supplying a second gate current Ig to the gate during a second time period after the first time period₂Wherein Ig is₂The gate is held in a conducting state,

wherein Ig is₁＞5Ig₂Or Ig or₁＞10Ig₂。

2. The gate driver as set forth in claim 1,

wherein, during a further on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to:

a single gate voltage is supplied to the gate during the entire period of the on-period, or

Wherein, during a further on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to:

a single gate current is supplied to the gate during the entire period of the on-period.

3. The gate driver of claim 1 or 2,

wherein the gate driver is further configured to supply a third gate voltage to turn off the gate, or

Wherein the gate driver is further configured to supply a third gate current to turn off the gate.

4. The gate driver of claim 1 or 2, wherein the gate driver is further configured to supply a third gate voltage to turn off the gate, wherein the third gate voltage is 0, or wherein the third gate voltage is negative and is followed by a fourth gate voltage of about 0, or wherein the third gate voltage is negative and is followed by a negative fourth gate voltage.

5. The gate driver of one of claims 1 to 4,

wherein the gate driver is further configured to:

applying a fifth gate voltage to the gate for an initial period of time prior to the first period of time, thereby applying an initial gate current Ig₀To turn on the gate and to keep the gate in the on-state, where Ig₀＜Ig₁Or is or

Wherein the gate driver is further configured to:

supplying an initial gate current Ig to the gate during an initial period prior to the first period₀To turn on the gate and to keep the gate in the on-state, where Ig₀＜Ig₁。

6. The gate driver of one of claims 1 to 4,

wherein a first gate voltage is supplied to the gate during a first time period such that a first gate current Ig₁Turn on the gate and keep the gate in a conducting state, or

Wherein a first gate current Ig is supplied to the gate during a first time period₁To turn on the gate and to keep the gate in a conductive state.

7. A power switching circuit, comprising:

a group III nitride based semiconductor body comprising:

a first monolithically integrated group III-nitride based enhancement mode transistor device, and

a second monolithically integrated group III-nitride based enhancement mode transistor device,

the gate driver of one of claims 1 to 6,

wherein the first and second monolithically integrated group III-nitride based enhancement mode transistor devices are coupled to form a circuit having a load path and are disposed on a common substrate.

8. The power switching circuit of claim 7,

wherein a drain of the first monolithically integrated group III-nitride based enhancement mode transistor device is coupled to a source of the second monolithically integrated group III-nitride based enhancement mode transistor device to form a half bridge circuit, or

Wherein a drain of the first monolithically integrated group III-nitride based enhancement mode transistor device and a drain of the second monolithically integrated group III-nitride based enhancement mode transistor device are coupled to form a bidirectional switch.

9. The power switching circuit of claim 7 or 8, further comprising a diode comprising an anode and a cathode, wherein the anode is coupled to the node having the lowest potential and the cathode is coupled to the common substrate.

10. The power switching circuit of claim 9, wherein the diode is integrated into a common substrate.

11. The power switching circuit of claim 10, wherein:

the common substrate is a p-doped substrate and includes an n-doped island on the p-doped substrate to form a diode, the III-nitride semiconductor body is disposed on the n-doped island, or

The common substrate is a p-doped substrate and includes an n-doped well in the p-doped substrate to form a diode, the III-nitride semiconductor body is disposed on the n-doped well, or

The common substrate is a p-doped substrate and comprises an n-doped well in the p-doped substrate and a p-doped layer arranged on the n-doped well to form a diode, wherein the p-doped layer is further arranged on the p-doped substrate, the p-doped layer comprises a trench completely interrupting the p-doped layer adjacent to the n-doped well, the group III nitride semiconductor body is arranged on the p-doped layer, or

The common substrate is a p-doped substrate and includes an n-doped well in the p-doped substrate to form a diode, and a p-doped ring disposed in the p-doped substrate, the p-doped ring laterally spaced apart from the n-doped well, the group III-nitride semiconductor body disposed on the n-doped well.

12. A method of switching a group III-nitride based enhancement mode transistor device comprising a source, a gate, and a drain, the method comprising:

during an on-period of a group III-nitride based enhancement mode transistor device:

supplying a first gate voltage to the gate during a first time period to apply a first gate current Ig during the first time period sufficient to turn on the gate and to maintain the gate in an on state₁And an

Supplying a second gate voltage to the gate during a second period after the first period to apply a second gate current Ig to the gate during the second period₂To keep the gate in an on-state, where Ig₁>5Ig₂Preferably Ig₁>10Ig₂Or the method comprises:

during an on-period of a group III-nitride based enhancement mode transistor device:

supplying a first gate current Ig to the gate during the first period of time sufficient to turn on the gate and to maintain the gate in an on state₁And an

Supplying a second gate current Ig to the gate during a second time period after the first time period₂To keep the gate in a conductive state,

wherein Ig is₁＞5Ig₂Or Ig or₁＞10Ig₂。

13. The method of claim 12, wherein during a further turn-on cycle of the group III-nitride based enhancement mode transistor device, the method comprises:

a single gate voltage is supplied to the gate during the entire period of the on-period, or

A single gate current is supplied to the gate during the entire period of the on-period.

14. The method of claim 12 or 13, wherein

Supplying a first gate voltage to the gate during a first time period such that a first gate current Ig₁Turn on the gate and keep the gate in a conducting state, or

Supplying a first gate current Ig to the gate during a first time period₁To turn on the gate and to turn the gate onThe poles are kept in a conducting state, or

The method further comprises:

applying a fifth gate voltage to the gate for an initial period of time prior to the first period of time to apply an initial gate current Ig₀To turn on the gate and to keep the gate in the on-state, where Ig₀<Ig₁Or is or

The method further comprises:

supplying an initial gate current Ig to the gate during an initial period prior to the first period₀To turn on the gate and to keep the gate in the on-state, where Ig₀<Ig₁。

15. The method of one of claims 12 to 14, wherein the group III-nitride based enhancement mode transistor device is a high side switch of a half bridge circuit, wherein the half bridge circuit further comprises a further group III-nitride based enhancement mode transistor device configured to provide a low side switch of the half bridge circuit, wherein the method further comprises:

supplying a single gate voltage or a single gate current to a gate of a further group III-nitride based enhancement mode transistor device during an on-period of the low side switch.

Background

To date, transistors used in power electronics applications have typically been fabricated using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS ®, Si power MOSFETs and Si Insulated Gate Bipolar Transistors (IGBTs). Group III nitride based semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates to carry large currents, support high voltages, and provide very low on-resistance and fast switching times.

Two or more group III nitride based semiconductor devices may be formed in the group III nitride based body. US 2017/0154885a1 discloses a nitride semiconductor layer on a conductive substrate comprising two lateral transistor devices. The substrate includes isolation regions in the form of trenches in the substrate so that each device is located above a region of the substrate whose potential can be independently controlled. An isolation structure is also provided inside the nitride semiconductor layer to electrically isolate the transistor devices from each other.

However, the following devices are desirable: having two or more monolithically integrated group III-nitride based devices with improved operational reliability.

Disclosure of Invention

In an embodiment, a switching circuit is provided that includes a group III-nitride based semiconductor body including a first monolithically integrated group III-nitride based transistor device and a second monolithically integrated group III-nitride based transistor device coupled to form a half-bridge circuit and disposed on a common substrate including a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300V. In some embodiments, the common substrate is a foreign substrate formed from a material other than a group III nitride.

In accordance with the present invention, a multilevel gate driver for a group III-nitride based enhancement mode transistor device including a source, a gate, and a drain is provided. During an on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to: supplying a first gate voltage to the gate during a first time period to apply a first gate current Ig during the first time period sufficient to turn on the gate and to maintain the gate in an on state₁(ii) a And supplying a second gate voltage to the gate during a second period of time after the first period of time to apply a second gate current Ig to the gate during the second period of time₂To keep the gate in an on-state, where Ig₁>5Ig₂Or Ig or₁>10Ig₂。

The first gate voltage is greater than the second gate voltage so as to achieve a greater than second gate current Ig₂First gate current Ig of₁. The ratio between the first gate voltage and the second gate voltage may be equal to the first gate current Ig₁And a second gate current Ig₂The desired ratio is the same or substantially similar.

In accordance with the present invention, a multilevel gate driver for a group III-nitride based enhancement mode transistor device including a source, a gate, and a drain is provided. During an on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to: supplying a first gate current Ig to the gate during a first time period₁Wherein Ig is₁Sufficient to turn on the gate and to maintain the gate in an on state; and supplying a second gate current Ig to the gate during a second time period after the first time period₂Wherein Ig is₂Keeping the gate in a conducting state, where Ig₁＞5Ig₂Or Ig₁＞10Ig₂。

The gate may be an ohmic gate or a schottky gate.

An alternative method for driving a gate, namely a gate driver configured to supply a desired gate current or a gate voltage suitable for generating a desired gate current to the gate, enables a group III-nitride based enhancement mode transistor device to operate at a voltage of at least 300V, enables a half-bridge circuit including the group III-nitride based enhancement mode transistor device as a high-side switch of the half-bridge circuit to operate at least 300V, and enables a bidirectional switch including the group III-nitride based enhancement mode transistor device as a high-side switch of the half-bridge circuit to operate at least 300V.

For both alternative methods for driving the gate, i.e. for a gate driver configured to supply a desired gate current to the gate or for a gate driver configured to supply a gate voltage suitable for generating a desired gate current, the first gate current Ig₁And a second gate current Ig₂Unlike the initial spike in transient current, as may be observed during hard switching, for example, because the first gate current is a steady state current that can be distinguished from transient current.

First gate current Ig used in the gate driver described herein₁And a second gate current Ig₂The difference in the ratio between such transient current and the subsequent steady state gate current is much smaller than the minimum difference 5 between. For example, the difference in the ratio between such transient current and the subsequent steady state gate current is typically less than 2.

Further, since the first gate current is a steady state current, the first gate current is applied during a first time period, whereby the first time period is greater than a time period of the transient current. The first time period is also greater than an initial time period over which the transient gate current is observed, for example, within a range of 10ns to 3 mus, or 50ns to 3 mus, or 100ns to 3 mus, or 500ns to 3 mus, or 1 mus to 3 mus at the first time period.

A group III nitride based enhancement mode transistor driven using a gate driver according to one of the embodiments described herein may also have a first steady state gate current Ig₁It has previously been shown that the transient gate current has a higher first gate current Ig₁Large and largeThe value is obtained.

In some embodiments in which the gate driver supplies the gate voltage to the gate, in a further on-cycle of the group III-nitride based enhancement mode transistor device, the gate driver is configured to supply a single gate voltage to the gate during an entire period of the on-cycle.

In some embodiments in which the gate driver supplies the gate current to the gate, in a further on-cycle of the group III-nitride based enhancement mode transistor device, the gate driver is configured to supply a single gate current to the gate during an entire period of the on-cycle.

Thus, the gate driver may drive the gate during one or more subsequent conduction periods using a different driver scheme than one or more previous conduction periods. These embodiments may be used to exploit any so-called memory effect to simplify the drive scheme by using a single gate voltage level or gate current level for one or more subsequent conduction periods, after using a multi-level pattern comprising two or more steady-state gate voltage levels or gate current levels in a single conduction period.

In some embodiments, wherein the gate driver supplies the gate voltage to the gate, the gate driver is further configured to supply a third gate voltage to turn off the gate.

In some embodiments, wherein the gate driver supplies the gate current to the gate, the gate driver is further configured to supply a third gate current to turn off the gate.

In some embodiments, wherein the gate driver supplies the gate voltage to the gate, the gate driver is further configured to supply a third gate voltage to turn off the gate, wherein the third gate voltage is 0.

In some embodiments, wherein the gate driver supplies the gate voltage to the gate, the gate driver is further configured to supply a third gate voltage to turn off the gate, wherein the third gate voltage is negative, and followed by a fourth gate voltage of about 0. This gate driver scheme may be used to ensure that the gate is completely turned off.

In some embodiments, wherein the gate driver supplies the gate voltage to the gate, the gate driver is further configured to supply a third gate voltage to turn off the gate, followed by a fourth gate voltage, wherein the third gate voltage is negative and the fourth gate voltage is negative and greater than the third gate voltage. These gate driver schemes may be used to ensure that the gates are completely turned off.

In some embodiments, the gate driver is further configured to apply a fifth gate voltage to the gate for an initial period of time prior to the first period of time, thereby applying the initial gate current Ig₀To turn on the gate and to keep the gate in the on-state, where Ig₀＜Ig₁。

In some embodiments, the gate driver is further configured to supply an initial gate current Ig to the gate during an initial time period prior to the first time period₀To turn on the gate, wherein Ig₀＜Ig₁。

In these embodiments, the first gate current Ig₁Is sufficient to turn on the gate but is not used to turn on the gate. Instead, less than the first gate current Ig is used₁Initial gate current Ig of₀To turn on the gate and to keep the gate in a conductive state, and then to thereafter pass a first gate current Ig₁Is applied to the gate.

In some embodiments in which the gate driver supplies the gate voltage to the gate, the first gate voltage is supplied to the gate during the first period of time, such that the first gate current Ig₁The gate is turned on and held in a conductive state. In some embodiments in which the gate driver supplies the gate current to the gate, the first gate current Ig is supplied to the gate during the first period of time₁To turn on the gate and to keep the gate in a conductive state. In these embodiments, the first gate current Ig₁Is used to turn on the gate without applying the previous smaller gate current.

In accordance with the present invention, a power switching circuit is provided that includes a group III-nitride based semiconductor body including a first monolithically integrated group III-nitride based enhancement mode transistor device and a second monolithically integrated group III-nitride based enhancement mode transistor device. The power switching circuit further comprises a gate driver according to one of the embodiments described herein. The first and second monolithically integrated group III-nitride based enhancement mode transistor devices are coupled to form a circuit having a load path and are disposed on a common substrate.

By using a multi-level gate drive scheme according to one of the embodiments described herein, the power switching circuit can operate at least 300V.

In some embodiments, a drain of the first monolithically integrated group III-nitride based enhancement mode transistor device is coupled to a source of the second monolithically integrated group III-nitride based enhancement mode transistor device to form a half bridge circuit.

In some embodiments, a drain of the first monolithically integrated group III-nitride based enhancement mode transistor device and a drain of the second monolithically integrated group III-nitride based enhancement mode transistor device are coupled to form a bidirectional switch.

In some embodiments, the power switching circuit further comprises a diode comprising an anode and a cathode, wherein the anode is coupled to the node having the lowest potential and the cathode is coupled to the common substrate.

In some embodiments, the diodes are integrated into a common substrate.

In some embodiments, the common substrate is a p-doped substrate and includes an n-doped island on the p-doped substrate and a p-doped layer on the n-doped island to form the diode, the III-nitride semiconductor body being disposed on the p-doped layer.

In some embodiments, the p-doped layer is omitted such that the diode is formed from a p-doped substrate and n-doped islands on the p-doped substrate. A p-doped layer on the n-doped islands can be used to improve performance.

In some embodiments, the common substrate is a p-doped substrate and includes an n-doped well in the p-doped substrate and a p-doped layer disposed on the n-doped well and on the p-doped substrate to form the diode, the p-doped layer including a trench completely interrupting the p-doped layer adjacent to the n-doped well, the group III nitride semiconductor body being disposed on the p-doped layer.

In some embodiments, the p-doped layer may be omitted, such that the diode is formed by the p-doped substrate and an n-doped well in the p-doped substrate.

In some embodiments, the common substrate is a p-doped substrate and includes an n-doped well in the p-doped substrate, a p-doped well in the n-doped well to form the diode, and a p-doped ring disposed in the p-doped substrate laterally spaced apart from the n-doped well, the III-nitride semiconductor body being disposed on the p-doped well.

In some embodiments, the p-doped well is omitted such that the common substrate is a p-doped substrate and the n-doped well is included in the p-doped substrate to form the diode. A p-doped ring is disposed in the p-doped substrate laterally spaced from the n-doped well, and a III-nitride semiconductor body is disposed on the n-doped well.

According to the present invention there is provided a method of switching a group III-nitride based enhancement mode transistor device comprising a source, a gate and a drain, the method comprising: during an on-period of a group III-nitride based enhancement mode transistor device, a first gate voltage is supplied to a gate during a first time period to apply a first gate current Ig during the first time period sufficient to turn on the gate and maintain the gate in an on-state₁(ii) a And supplying a second gate voltage to the gate during a second period of time after the first period of time to supply a second gate current Ig to the gate during the second period of time₂To keep the gate in an on-state, where Ig₁>5Ig₂Or Ig₁>10Ig₂。

According to the present invention, there is provided a group III based semiconductor device comprising a source, a gate and a drainA method of switching a nitride enhancement mode transistor device, the method comprising: during an on-period of a group III-nitride based enhancement mode transistor device, a first gate current Ig sufficient to turn on and hold a gate in an on state is supplied to the gate during a first time period₁(ii) a And supplying a second gate current Ig to the gate during a second time period after the first time period₂To keep the gate in an on-state, where Ig₁>5Ig₂Or Ig₁>10Ig₂。

In some embodiments in which the gate is supplied with a gate voltage, in a further on-cycle of the group III-nitride based enhancement mode transistor device, the method includes supplying a single gate voltage to the gate during an entire period of the on-cycle.

In some embodiments in which the gate is supplied with a gate current, in a further on-cycle of the group III-nitride based enhancement mode transistor device, the method includes supplying a single gate current to the gate during an entire period of the on-cycle.

In some embodiments, the gate is supplied with a gate voltage during the first time period such that the first gate current Ig is equal to or greater than the first gate voltage₁The gate is turned on and held in a conductive state.

In some embodiments in which the gate is supplied with the gate current, the gate is supplied with the first gate current Ig during the first period of time₁To turn on the gate and to keep the gate in a conductive state.

In some embodiments, wherein the gate is supplied with the gate voltage, the method further comprises applying a fifth gate voltage to the gate for an initial time period prior to the first time period to apply the initial gate current Ig₀To turn on the gate and to keep the gate in the on-state, where Ig₀＜Ig₁。

In some embodiments, the method further comprises supplying an initial supply of gate current to the gate during an initial time period prior to the first time periodGate current Ig₀To turn on the gate and to keep the gate in the on-state, where Ig₀＜Ig₁。

In some embodiments, the group III-nitride based enhancement mode transistor device is a high side switch of a half bridge circuit, wherein the half bridge circuit further comprises a further group III-nitride based enhancement mode transistor device configured to provide a low side switch of the half bridge circuit. The high side switch is driven by the method of any of the embodiments described herein. The method further includes supplying a single gate voltage or a single gate current to a gate of a further group III-nitride based enhancement mode transistor device during an on-period of the low-side switch.

Thus, the high-side switch is driven using two or more steady-state levels, while the low-side switch is driven using a single steady-state level.

Drawings

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the drawings and are detailed in the following description.

Fig. 1 illustrates a cross-sectional view of a semiconductor device according to an embodiment.

Fig. 2A illustrates a diagram of voltage waveforms applied to the gates of the high-side switches of a monolithically integrated half-bridge circuit according to various embodiments.

Fig. 2B illustrates a power switching circuit with a three-level gate driver, according to an embodiment.

FIG. 2C illustrates the switch node voltage V as a function of time for three gate drive schemes_SWLine graph of (c).

FIG. 2D illustrates V for the high side switch_SWA descending line graph.

Fig. 2E illustrates a two-level gate drive scheme according to two embodiments.

Fig. 2F illustrates a three-level gate drive scheme according to an embodiment.

Fig. 2G illustrates a four-level gate drive scheme according to an embodiment.

Fig. 3A illustrates a schematic diagram of a switching circuit according to an embodiment.

FIG. 3B illustrates V for VDC of 400V for a three-level driver_SWA descending line graph.

FIG. 3C illustrates V for VDC of 600V for a three-level driver_SWA descending line graph.

Fig. 3D illustrates a line graph of Vds for the high-side switch under three different gate drive schemes.

Fig. 4A illustrates a diode structure according to an embodiment.

Fig. 4B illustrates a diode structure according to an embodiment.

Fig. 4C illustrates a diode structure according to an embodiment.

Fig. 5A illustrates a group III-nitride based enhancement mode transistor device, according to an embodiment.

Fig. 5B illustrates a line graph of gate-source voltage VGS versus time and a line graph of VSW versus time for a half bridge circuit for a High Side Switch (HSS) and a Low Side Switch (LSS).

Fig. 5C illustrates a circuit diagram of the device of fig. 5A during soft switching.

Fig. 5D illustrates a circuit diagram of the device of fig. 5A during a first period of the on-state of the high-side switch.

Fig. 5E illustrates a schematic diagram of the high-side switch during a first period of its on-state.

Fig. 6 illustrates a schematic diagram of a bidirectional switch according to an embodiment.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "front," "end," etc., is used with reference to the orientation of the figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description of the invention is not to be taken in a limiting sense, and the scope of the invention is defined by the appended claims.

A number of exemplary embodiments will be explained below. In this case, the same structural features are identified by the same or similar reference numerals in the respective drawings. In the context of the present description, "lateral" or "lateral direction" should be understood to mean a direction or extension running generally parallel to the lateral extension of the semiconductor material or semiconductor carrier. The transverse direction thus extends generally parallel to these surfaces or sides. In contrast, the terms "vertical" or "vertical direction" are understood to mean a direction running generally perpendicular to these surfaces or sides and therefore to the transverse direction. The vertical direction thus runs in the thickness direction of the semiconductor material or semiconductor carrier.

As used in this specification, when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present.

As used in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

A depletion mode device, such as a normally-on transistor, has a negative threshold voltage, meaning that it can conduct current at zero gate voltage. These devices are typically on. An enhancement mode device, such as a normally off transistor, has a positive threshold voltage, meaning that it cannot conduct current at zero gate voltage and is normally off. The operation of both depletion mode and enhancement mode devices is not limited to high voltages and may also be low voltages.

As used herein, a "high voltage device," such as a high voltage transistor, is an electronic device optimized for high voltage switching applications. That is, when a transistor is off, it is capable of blocking high voltages, such as about 300V or more, about 600V or more, or about 1200V or more, and when the transistor is on, the transistor has a sufficiently low on-Resistance (RON) for the application in which it is used, i.e., it experiences sufficiently low conduction losses when significant current passes through the device. The high voltage device may be at least capable of blocking a voltage equal to the high voltage supply or maximum voltage in the circuit in which it is used. The high voltage device may be capable of blocking 300V, 600V, 1200V or other suitable blocking voltage required by the application.

As used herein, the term "group III nitride" refers to a compound semiconductor that includes nitrogen (N) and at least one group III element, including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including, but not limited to, any of its alloys, such as, for example, aluminum gallium nitride (Al) and/or aluminum gallium nitride (Al)_xGa_(1-x)N), indium gallium nitride (In)_yGa_(1-y)N), aluminum indium gallium nitride (Al)_xIn_yGa_(1-x-y)N), gallium arsenic phosphorus nitride (GaAs)_aP_bN_(1-a-b)) And aluminum indium gallium arsenic phosphorus (Al) nitride_xIn_yGa_(1-x-y)As_aP_bN_(1-a-b)). Aluminum gallium nitride and AlGaN are denoted by the expression Al_xGa_(1-x)N, wherein 0 < x < 1.

For example, in GaN on Si technology, multiple GaN devices on a common Si substrate may be implemented using laterally conducting device structures. However, monolithically integrated GaN devices on a common Si substrate for half bridges may suffer from instability of the High Side Switch (HSS) during switching beyond a certain DC bus voltage, which may cause HSS failures. One explanation for this instability may be the capacitive effect of GaN-based epitaxial layers in dynamic operation, which results in depletion of the two-dimensional electron gas (2DEG) forming the channel and an increase in Rdson. One approach to improve stability is to include additional electrical isolation in the substrate at locations laterally between the GaN devices and between the GaN devices.

Fig. 1 illustrates a cross-sectional view of a semiconductor device 20 according to an embodiment. The semiconductor device 20 comprises a III-V semiconductor body 21 in which a plurality of devices are monolithically integrated. A plurality of devices are monolithically integrated into a III-V semiconductor body formed on a common substrate. The semiconductor device may be a switchable device comprising a gate (such as a transistor device) or may be a bidirectional switch which may comprise a single or multiple gates. For example, two transistor devices may be coupled to form a half-bridge configuration. In some embodiments, semiconductor body 21 may comprise a group III nitride based semiconductor body.

In the embodiment illustrated in fig. 1, the semiconductor body 21 comprises a multilayered group III-nitride based semiconductor structure comprising a channel layer 22 and a barrier layer 23 arranged on the channel layer 22 such that a heterojunction 24 is formed at an interface between the barrier layer 23 and the channel layer 22. The heterojunction 24 is capable of supporting a two-dimensional charge gas, such as a two-dimensional electron gas (2 DEG). A group III-nitride based semiconductor body 21 having a plurality of group III-nitride based devices formed therein is disposed on a common substrate 25. Common substrate 25 includes an upper or growth surface 44 capable of supporting epitaxial growth of one or more group III-nitride based layers.

In some embodiments, the common substrate is a foreign substrate and is formed of a material other than a group III-nitride material, which includes an upper or growth surface 44 capable of supporting epitaxial growth of one or more group III-nitride based layers. The common foreign substrate 25 may be formed of silicon, and may be formed of, for example, single crystal silicon or an epitaxial silicon layer.

The group III-nitride based semiconductor body 21 may include a transition or buffer structure 26 disposed between the common foreign substrate 25 and the group III-nitride based device layer 27. In the illustrated embodiment, the group III-nitride based device layer 27 includes a channel layer 22 and a barrier layer 23. The transition structure 26 may include one or more group III nitrides and have a multilayer structure.

In some embodiments not shown, the group III-nitride based semiconductor body 21 may further include a backside barrier layer. The channel layer 22 is formed on the back-side barrier layer and forms a heterojunction with the back-side barrier layer, and the barrier layer 23 is formed on the channel layer 22. The backside barrier layer has a different bandgap than the channel layer and may include, for example, AlGaN. The composition of AlGaN for the back side barrier layer may be different from that for the barrier layer 23.

A typical transition or buffer structure 26 for a silicon substrate comprises an AlN starting layer on a silicon substrate, which may have a thickness of several hundred nanometers, followed by Al_xGa_(1-x)The N-layer sequence, again a few hundred nanometers thick for each layer, whereby the Al content of about 50-75% is reduced to 10-25% before the growth of the GaN-or AlGaN-back barrier (if present). Alternatively, a superlattice buffer may be used. Again, an AlN start layer on a silicon substrate was used. Growing AlN and Al depending on the selected superlattice_xGa_(1-x)Sequence of N pairs, in which AlN layer and Al_xGa_(1-x)The thickness of N is in the range of 2-25 nm. The superlattice may comprise between 20 and 100 logarithms depending on the desired breakdown voltage. Alternatively, Al as described above_xGa_(1-x)The N-layer sequence may be used in combination with the superlattices mentioned above.

In the embodiment illustrated in fig. 1, the semiconductor device 20 comprises two transistor devices 28, 29 monolithically integrated in the semiconductor body 21. In some embodiments, the first monolithically integrated device 28 is a switchable device comprising a gate, and may comprise a group III-nitride based transistor device. The first monolithically integrated transistor device 28 may be an enhancement mode device, which is typically off. In other not illustrated embodiments, the first monolithically integrated transistor device 28 may be a depletion mode device, which is normally on. The second monolithically integrated device 29 is also a switchable device comprising a gate and may comprise a group III-nitride based transistor device. The second monolithically integrated group III-nitride based semiconductor device 29 may be an enhancement mode device as illustrated in fig. 1, or a depletion mode device. The first monolithically integrated transistor device 28 and the second monolithically integrated transistor device 29 may be HEMTs (high electron mobility transistors).

In some embodiments, two monolithically integrated semiconductor devices 28, 29 may be coupled to form a half bridge circuit 30, as in the embodiment illustrated in fig. 1. In other embodiments, two monolithically integrated semiconductor devices 28, 29 may be coupled to form or be configured as a bidirectional switch.

The first monolithically integrated group III-nitride based transistor device 28 provides a Low Side Switch (LSS) of the half bridge circuit 30 and comprises a source 31, a drain 32 and a gate 33 arranged on a first main surface 34 of the semiconductor body 21. The gate electrode 33 is disposed laterally between the source electrode 31 and the drain electrode 32. In the illustrated embodiment, gate 33 includes a p-doped group III-nitride region 35 between metal gate 36 and barrier layer 23 such that first monolithically integrated group III-nitride based transistor device 28 is an enhancement mode device. The gate 33 may be an ohmic gate or a schottky gate. The gate 33 may have a recessed gate structure.

The second monolithically integrated group III-nitride based base transistor device 29 provides a High Side Switch (HSS) of the half bridge circuit 30 and includes a source 37, a drain 38 and a gate 39 arranged on the first main surface 34 of the semiconductor body 21. Gate 39 is disposed laterally between source 37 and drain 38 and, in the illustrated embodiment, further includes a p-doped region 41 between metal gate 42 and barrier layer 23 so that second monolithically integrated ill-nitride based transistor device 29 is also an enhancement mode device. The gate 39 may be an ohmic gate or a schottky gate. The gate 39 may have a recessed gate structure.

The second monolithically integrated group III-nitride based transistor device 29 is arranged laterally adjacent to the first monolithically integrated group III-nitride based transistor device 28 such that the single conductive region 40 extends between the source 37 of the second monolithically integrated group III-nitride based transistor device 29 and the drain 32 of the first monolithically integrated group III-nitride based transistor device 28 and provides an output node of the half bridge circuit 30. The semiconductor device 20 further includes a source electrode 45 coupled to the source 31 of the first monolithically integrated group III-nitride based base transistor device 28 and a drain electrode 46 coupled to the drain 38 of the second monolithically integrated group III-nitride based base transistor device 29.

Both of these group III-nitride based semiconductor devices 28, 29 are monolithically integrated in a common group III-nitride based semiconductor body 21 located on a common foreign substrate 25. In the embodiment described herein, no electrical insulation is provided between the two group III-nitride based semiconductor devices 28, 29, e.g. no isolation trenches are located in the semiconductor body 21 between the devices 28, 29. Additionally, no electrical insulation, such as trenches or doped regions, is provided in the common foreign substrate 25 between the locations of the two semiconductor devices 28, 29, and no discrete doped regions are provided in the substrate 25. The common foreign substrate 25 extends continuously and uninterruptedly under the devices 28, 29 monolithically integrated into a single common semiconductor body 21, so that the potential of the common foreign substrate 25 is the same over its entire area. The common foreign substrate 25 may also have a common doping level.

Monolithically integrated III-V devices on a common foreign substrate may suffer from instability. As discussed above, monolithically integrated GaN devices forming half-bridge circuits on a common Si substrate may suffer from high-side switching instability during switching beyond the critical DC bus voltage. When operating with conventional gate drivers, conventional monolithically integrated GaN half-bridges may fail at DC link voltages of about 250V.

According to embodiments described herein, a plurality of group III-nitride based devices (such as GaN FETs) monolithically integrated on a common Si substrate are driven by a multi-level (tri-level or higher) gate driver in order to allow operation above 300V and even above 600V without difficulty. Still further, monolithic integration of GaN half-bridge circuits on a single chip with reliable operation in excess of 600V can be achieved, which also has the benefits of small footprint and low cost, and can be used in applications such as power factor correction and motor drive. Additionally, there are chip-level benefits, including cost reduction by reducing die area and overall chip size, and benefits on application systems with higher efficiency due to minimal parasitic inductance achieved.

Multilevel gate drivers may also be used to drive III-V devices, including III-V devices monolithically integrated on a common substrate, as well as devices other than transistor devices, such as III-V bidirectional devices and GaN bidirectional devices.

The multi-level gate driver may also be used to drive a single III-V semiconductor device, for example, a single III-nitride transistor device, such as a single HEMT that is not monolithically integrated with other devices. A multilevel gate driver and method of driving a gate using multiple levels according to any of the embodiments described herein may be used to mitigate, for example, dynamic R in a single III-V semiconductor device_DSonHas a positive effect and helps to mitigate, for example, dynamic R in a single III-V semiconductor device_DSonThe dynamic effect of (2).

According to embodiments described herein, a gate driver is provided for driving a gate by applying a plurality of gate voltage levels or a plurality of gate current levels to the gate during an on-period of a switch (i.e., a transistor device). Multiple gate voltage levels or gate current levels may be applied to the gates of the high side switches of the half bridge circuit. Surprisingly, this enables the monolithically integrated group III-nitride half bridge to operate above 600V without difficulty, while at the same time it can be observed that driving the monolithically integrated group III-nitride half bridge with the conventional two-level driving scheme leads to device failure even at DC link voltages of-250V.

The proposed three-level or more gate drive scheme is believed to supply a sufficiently large number of holes from the gate to the channel when the high-side switch (HSS) is turned on to prevent the 2DEG from being depleted when the HSS is turned on. A sufficiently large number of holes are supplied from the gate to the channel in a controlled manner. These holes compensate for the negative effects on the capacitive action of the GaN epitaxial structure as a capacitor. When HSS is turned on, the GaN capacitor will be charged.

One explanation for the observed increase in operating voltage is that the top of the epitaxial region, i.e., the GaN channel, will be positively charged and the bottom of the epitaxial region, i.e., the Si substrate, will be negatively charged. When it is said that the GaN channel is positively charged, the channel will lose the 2DEG without any hole supply to keep the charge neutral. One explanation is therefore that the multilevel gate drive method feeds a sufficient number of holes into the channel to positively charge the channel, while maintaining the 2DEG and its good conductivity.

To reduce the capacitive effect of the group III-nitride epitaxial layer, embodiments aim to reduce the effective voltage difference between the top channel (i.e. the two-dimensional charge gas of the transistor, in particular the high-side switch of a monolithically integrated half-bridge circuit) and the bottom Si substrate, resulting in a reduced capacitive effect.

In further embodiments, a substrate diode and/or a p-doped GaN region coupled to the source may be used in addition to or instead of a multi-level gate driver having a minimum of three levels.

The diode-forming Si substrate prior to GaN epitaxial growth can be used to provide additional voltage drop to reduce the actual voltage drop across the GaN epitaxial capacitor. The addition of a p-GaN region coupled to the source is believed to function in a similar manner to a p-GaN region coupled to the drain to provide additional holes during soft switching.

One possible explanation for the observed effect of a p-doped group III nitride region coupled to the source is that when Low Side Switch (LSS) is off and HSS is on with soft switching, the p-GaN region coupled to the source can be on because there is a sufficiently large current flowing from the source towards the drain during the first half of the switching and HSS on periods. This is the same principle as in the p-GaN region coupled to the drain, where the current direction is from the drain toward the gate during hard switching. Once the p-GaN region coupled to the source is turned on, holes are injected into the channel from the source toward the gate. Thus, when HSS is turned on, the intrinsic GaN capacitor will be charged. For example, the top of the epitaxial region, i.e., the GaN channel, will be positively charged, while the bottom of the epitaxial region, i.e., the Si substrate, will be negatively charged. When it is said that the GaN channel is positively charged, the channel will lose the 2DEG without any hole supply to keep the charge neutral. Thus, the integrated substrate diode will suppress 2DEG depletion and the integrated source-pGaN will feed a sufficient number of holes to the channel. Thus, the monolithically integrated GaN half-bridge works well at 600V or above.

The arrangement illustrated in fig. 1 may suffer from the fact that the drain-source current of the high-side switch 29 is in practice less than expected. One explanation for this observation is that when the high-side switch 29 changes from an off-state to an on-state, a parasitic resistance (designated Rs in fig. 1) in the high-side switch 29 occurs between the source 37 and the gate 39 of the high-side switch. This parasitic resistance Rs may increase due to the capacitive effect of the group III-nitride based epitaxial structure of the semiconductor body 21, which effectively acts as a capacitor, wherein the two-dimensional electron gas forms the top electrode, the substrate 25 forms the bottom electrode, and the group III-nitride based epitaxial structure between the two-dimensional electron gas and the substrate 25 forms the dielectric of the capacitor structure. When the high-side switch 29 is turned on, the top electrode of the parasitic capacitor is positively charged due to depletion of the two-dimensional electron gas, thus causing an increase in the parasitic resistance Rs. Intrinsic gate voltage gate source voltage V_GSBecomes small so that ID becomes small and drain-source voltage V_DSAnd (4) increasing. In other words, the switching voltage V_SWLowered and the high side switch 29 may fail due to thermal runaway. The parasitic resistance RD between the gate and the drain also increases, but this is mitigated in the design illustrated in fig. 1 by the presence of the p-doped region 43 which is coupled to the drain and injects holes.

As a result of this capacitive effect,

V_GSintrinsic=V_GS-I_DS x Rs<V_GSextursinc

and the actual drain-source current Ids of the high-side switch 29 is less than expected.

Surprisingly, the inventors have found that this problem can be overcome by a specific method as follows: the gates of the high-side switches of the monolithically integrated group III-nitride based half-bridge circuits are driven using three or more levels, including two or more levels in an on state.

Fig. 2A illustrates a graph 50 of a voltage waveform VGS applied to the gate of a high-side switch of a monolithically integrated half-bridge circuit, such as the second monolithically integrated group III-nitride based transistor device 29 of the semiconductor device 20 illustrated in fig. 1.

Fig. 2A illustrates a diagram 50 of the on-cycle of a group III-nitride based transistor device, where the high-side switch is first turned off (period 51), turned on (period 52), and then turned off again (period 53). As illustrated in fig. 2A, a multi-level gate driver concept including three or more levels is used. During the on period 52, for a predetermined period of time T₁The gate of the high-side switch is supplied with a first gate voltage V, indicated by level 54 in FIG. 2A_GSSo as to make the first gate current I_G1Is applied to turn on the gate. During a first time period T of the on-period 52₁Followed by a second period of time T₂During this time, a second gate voltage having a level 55 is applied to the gate of the high-side switch, so that a second gate current I_G2Is applied to the gate to maintain the gate in an on state. The second gate voltage 55 is less than the first gate voltage 54. A second time period T₂May correspond to the first time period T₁And (4) continuous. First gate current I_G1At least a second gate current I_G25 times or more than 10 times of I_G2. For example, in some embodiments, I_G1Can be at 1.68 muA/mum²To 4.81 muA/mum²In a range of (A) and I_G2Is at 48.1 nA/mum²To 0.24 muA/mum²Within the range of (1). In some embodiments, the first period of time T₁May be about 300 ns. In a time period T₂After the end, the gate is supplied with a voltage at the third level 56, which third level 56 is zero or a negative voltage in this embodiment, and the high-side switch is turned off in the period 53. Thus, the gate driver scheme 50 illustrated in fig. 2A includes three levels, such as using two gate levels during the on period 52, and for a second time period T₂The gate voltage or current at the third level supplied to the gate of the high-side switch then causes it to be in an off state.

The signal applied to the gate may be a gate voltage, or it may be a gate current. In both cases, during a first time period T₁During which a first gate voltage or a first gate current applied to the gate causes a first gate current I_G1Is in a second period T when a second gate voltage or a second gate current is applied to the gate of the high-side switch₂During which the applied gate current I_G2At least 5 times higher.

For both alternative methods for driving the gate, i.e. for a gate driver configured to supply a desired gate current to the gate or for a gate driver configured to supply a gate voltage suitable for generating a desired gate current, the first gate current Ig₁And a second gate current Ig₂Unlike the initial spike of the transient current, as may be observed during hard switching using a single gate voltage or a single gate current during the on-period, for example, because the first gate current Ig₁And a second gate current Ig₂Are steady state currents that can be distinguished from transient currents.

The difference in the ratio of such transient current and the subsequent steady state gate current is much smaller than the first gate current Ig used in the gate driver described herein₁And a second gate current Ig₂With a minimum difference of 5. Such transient currents and subsequent steady-state observed in conventional gate drive schemes that supply a single gate voltage or a single gate current over an on-period, for exampleThe difference in the ratio between the gate currents is typically less than 2.

Further, due to the first gate current Ig₁Is a steady state current and is therefore in a first time period T which is greater than the time period of the transient current₁During which a first gate current Ig is applied₁. A first time period T₁Also larger than the initial period of time over which the transient gate current is observed in a conventional gate drive scheme supplying a single gate voltage or a single gate current over a turn-on period, e.g. in the range of 10ns to 3 μ s (or 50ns to 3 μ s; or 100ns to 3 μ s; or 500ns to 3 μ s; or 1 μ s to 3 μ s) at the first period of time.

In the gate drive scheme illustrated in fig. 2A, the gate driver supplies V of two levels during the on period of the high-side switch_GSAnd supplies one level during the off period of the high-side switch. In other embodiments, the gate driver supplies V of a level during the on period of the high-side switch_GSAnd supplying two levels during the off period of the high-side switch to, for example, turn off the high-side switch, the gate driver may supply a negative level followed by a zero level.

In some embodiments, the gate driver is configured to apply three or more levels during the on period and to apply one or more levels during the off period.

In the embodiment illustrated in FIG. 2A, during a first time period T₁During which a first gate voltage is supplied to the gate and thus a first gate current Ig₁Turn on the gate and maintain the gate in a conductive state, or may be in a first time period T₁During which a first gate current Ig is supplied to the gate₁To turn on the gate and to keep the gate in a conductive state.

In some embodiments, the gate current I_G1Is not used to turn on the gate but is still high enough to turn on the gate. In some embodiments, during the first time period T₁Previous initial time period T₀Applying an initial gate voltage to the gate, thereby applying an initial gate current Ig₀To turn on the gateAnd maintaining the gate in an on state, where Ig₀＜Ig₁. Then, a gate voltage is subsequently applied to the gate for a first time period T₁Middle generation of gate current Ig₁At a second time period T₂Gate current Ig used in₂At least 5 times higher.

In some embodiments, during the first time period T₁Previous initial time period T₀During which an initial gate current Ig is supplied to the gate₀To turn on the gate and to keep the gate in a conducting state, where Ig₀＜Ig₁. Then, subsequently during a first time period T₁Middle applied gate current Ig₁At a subsequent second time period T₂Middle applied gate current Ig₂At least 5 times higher.

One possible explanation for the effect of such a gate driver scheme with three or more levels may be as follows.

As an initial use of a higher gate-source current I_GS1As a result, additional holes are injected from the p-doped region 35 of the gate 33, which is sufficient to prevent depletion of the two-dimensional electron gas and maintain good conductivity within the channel. As a result, an increase in parasitic resistance RS between the source and the gate is suppressed, and the inherent gate-source voltage V of the high-side switch_GSAn applied extrinsic voltage gate-source voltage similar to the high-side switch, so that the drain-source current I of the high-side switch_DSAnd does not deteriorate. Thus, the total RDSon of the high-side switches is kept at a desired level, and the V of the high-side switches_SWAnd V_DSIs not affected. As a result, the monolithically integrated group III-nitride based half-bridge circuits work well at higher voltages, such as voltages of 400V and above.

Fig. 2B illustrates an example of a power switch circuit 60 including a gate driver 61 and a semiconductor device 20 including a monolithically integrated group III-nitride based half-bridge circuit 30, the half-bridge circuit 30 including a low-side switch 28 and a high-side switch 29 arranged in a common group III-nitride based semiconductor body 21 on a common foreign substrate 25. In this embodiment, the common foreign substrate 25 is a common silicon substrate coupled to ground potential.

As illustrated in fig. 2B, the current supplied to the gate of the high-side switch 29 has three levels: in a first time period T₁First level I of the period_G1(ii) a In a second time period T₂During less than the first level I_G1Second level I of_G2(ii) a And in a second time period T₂Followed by a third level during a third time period T3, which in this embodiment is zero or negligible. A first time period T₁And a second time period T₂During the on period of the high-side switch 29, and a third period T₃Equal to the off period of the high-side switch 29, so that the gate driver 61 supplies two on levels and one off level.

Fig. 2B also illustrates an exemplary gate driver 61 for providing the three level supplies to the gate of the high-side switch 29. In the embodiment illustrated in fig. 2B, this same three-level gate driver may be used to drive the gate of the low-side switch 28. However, the low-side switch 28 may be driven by a two-level gate driver or a three-level gate driver having a different circuit than that illustrated for the high-side switch 29.

The gate driver 61 for the high-side switch 29 includes a first linear voltage regulator (LDO)62 and a second LDO 63. A first Low Drop Out (LDO) regulator 62 is electrically coupled between the high voltage node 64 and an intermediate node 72. First LDO 62 is electrically coupled in parallel with second LDO 63, with second LDO 63 also being coupled between high voltage node 64 and intermediate node 72. The output of the first LDO 62 is coupled in series with a switch 66, e.g., a transistor device, the switch 66 being coupled to an output node 67 of the gate driver circuit 61. The output of first LDO 62 is also coupled to capacitor 68, and capacitor 68 is coupled to the output of second LDO 63. The output of second LDO 63 is also coupled to a bidirectional switch 69, bidirectional switch 69 being coupled to output node 67. Second capacitor 70 is electrically coupled between the output of second LDO 63 and low voltage node 65. Transistor 71 is electrically coupled between low voltage node 65 and output node 67.

When the switch 66 is turned on, a high voltage is appliedIs applied to an output node 67, and a first gate current I is applied to the output node 67_G1To the gate of the high-side switch 29. When the bidirectional switch 69 is turned on, a low voltage is supplied to the output node 67 to make a lower current I_G2Is supplied to the gate of the high-side switch 29. When both switch 66 and bidirectional switch 69 are turned off and switch 71 is turned on, a low voltage (i.e., 0V or-4V) is applied to output node 67 and high-side switch 29 is turned off.

FIG. 2C illustrates the switch node voltage V as a function of time for three gate drive schemes 80, 81 and 82_SWLine graph of (c). In this embodiment the voltage V_DCIs 400V. FIG. 2D illustrates the actual V of the high-side switch after a period of 50ns for the gate drive schemes 80, 81, 82_SWCompared with the desired V_SWDecrease of or V_SWAnd (4) descending.

Fig. 2E illustrates a two-level gate drive scheme in which the gate current is held at a single level of 80 mA or 100mA during the on period, corresponding to schemes 80 and 81 in the line graphs illustrated in fig. 2C and 2D, respectively.

Fig. 2F illustrates a three-level gate drive scheme corresponding to scheme 82, where a gate current of 700mA is applied during a first time period of 300 ns, a current of 20mA is applied during a second time period after the first time period, followed by zero current during the off period.

After a period of 50ns, indicated by dashed line 83 in the line graph of fig. 2C, fig. 2D illustrates that V is for a two-level gate drive scheme_SWThe voltage drop compared to 400V is greater than 200V for a gate driver current of 80 mA (scheme 80) and between 200 and 150 for a gate driver current of 100mA (scheme 81). For a three-level gate drive scheme 82 that uses an initial gate current of 700mA for a period of 300 ns and then a gate current of 20mA, V after 50ns_SWThe drop above compared to the desired value of 400V has been reduced to just above 50.

Fig. 2G illustrates a four-level gate drive scheme 50' for the gate of a high-side switch of a monolithically integrated half-bridge circuit, such as the second monolithically integrated group III-nitride based transistor device 29 of the semiconductor device 20 illustrated in fig. 1, according to an embodiment.

In the gate drive scheme 50' illustrated in fig. 2G, similar to the scheme 50 illustrated in fig. 2A. However, in the scheme 50' illustrated in fig. 2G, the gate driver supplies three levels of gate voltage V during the on period 52 of the high-side switch_GAnd one level is supplied during the off period 53 of the high-side switch.

During the on period 52, at a time period T₁A predetermined initial period of time T before₀To the gate of the high-side switch, an initial gate voltage, indicated by level 57 in fig. 2G, is supplied, so that an initial gate-source current I is applied_GS0To turn on the gate. Then, at the initial gate current I_G0Thereafter for a predetermined period of time T₁Internally applying a first gate voltage, indicated by level 54 in fig. 2G, such that a first gate current I_G1Is applied to the gate. First gate current I_G1Greater than the initial gate current I_G0. Similar to the embodiment illustrated in FIG. 2A, during the first time period T of the conduction period 52₁Followed by a second period of time T₂During which a second gate voltage having a level 55 is applied to the gate of the high-side switch, so that a second gate current I_G2Is applied to the gate to maintain the gate in an on state. The second gate voltage 55 is less than the first gate voltage 54. A second time period T₂May correspond to the first time period T₁And (4) continuous. First gate current I_G1Is the second gate current I_G2At least 5 times or more than 10 times of I_G2. For example, in some embodiments, I_G1Can be at 1.68 muA/mum²To 4.81 muA/mum²In a range of (A) and I_G2Can be at 48.1 nA/mum²To 0.24 muA/mum²Within the range of (1). In a time period T₂After the end, the voltage at the third level 56, which in this embodiment is zero or a negative voltage, is supplied to the gate and the high-side switch is turned off in period 53.

Thus, the gate driver scheme 50' illustrated in fig. 2G includes four levels, such as using three gate levels 57, 54, 55 during the on period 52, and using the fourth level to turn off the gates. The signal applied to the gate may be a gate voltage or it may be a gate current. In both cases, during a first time period T₁During which a first gate voltage or a first gate current applied to the gate causes a first gate current I_G1Is a second period T when a second gate voltage or a second gate current is applied to the gate of the high-side switch₂During which a second gate current I is applied_G2At least 5 times higher.

When operating one or more switches of a transistor or switching circuit, multiple gate current levels or gate voltage levels used in the conduction period may be used in all conduction periods.

However, in some embodiments, in the further conduction period, the gate driver is configured to supply a single gate voltage to the gate during the entire period of the further conduction period, or to supply a single gate current to the gate during the entire period of the further conduction period. This embodiment can be used in the following cases: one or more switches or circuits exhibit a so-called memory effect, in which after driving with two or more gate levels in one or more conduction periods, a desired drain-source current is obtained in one or more subsequent conduction periods when the one or more switches or circuits are driven with a single gate level for the entire duration of the subsequent conduction period(s). This embodiment may be used to reduce the power consumption of the gate driver.

There is also provided a method of switching a group III-nitride based enhancement mode transistor device comprising a source, a gate and a drain using embodiments described herein with reference to a gate driver and a semiconductor device according to any of the embodiments described herein.

Fig. 3A illustrates a schematic diagram of a switching circuit 60', the switching circuit 60' comprising a tri-level gate driver 61 for the high-side switches and a tri-level gate driver 61 for the low-side switches of the half-bridge circuit 30 provided by the semiconductor device 20. The switching circuit 60' includes an additional diode 84 coupled between the common foreign substrate 25 and ground. The anode of diode 84 is coupled to the source of low side switch 28 and the cathode is coupled to common foreign substrate 25.

FIG. 3B illustrates V for VDC of 400V for the three-level driver 61 of FIG. 2C_SWFalling line diagram, three-level driver 61 drives semiconductor device 20 including diode 84 shown in fig. 3B by scheme 85. For comparison, V for scenarios 80, 81 and 82 shown in FIG. 2C_SWThe values are also shown in fig. 3B.

As can be seen in fig. 3B, V of the high-side switch 29 at a time period of 50ns is achieved by scheme 85 compared to scheme 82 for a three-level driver (but without diodes)_SWIs further improved because there is no effective V_SWDrop, thus avoiding the reduction in RDSon.

Fig. 3C illustrates a further embodiment as follows: a two-level driver (scheme 81) is compared to a three-level driver (scheme 82) and the three-level driver and diode combination of scheme 85 for VDC 600V.

Fig. 3D illustrates V for the high-side switch 29 after periods of 330 ns and 5 μ s for a two-level driver (scheme 81), a three-level driver without a diode (scheme 82), and a three-level driver with a diode (scheme 85)_SWThe voltage of (2) drops. Fig. 3D shows that the three-level driver circuit combined with the diode (scheme 85) causes minimal losses after both 330 ns and 5 μ s. At 330 ns and 5 μ s, the voltage drop seen when using the three-level driver alone (scheme 82) is greater than for the embodiment with three-level driver and diode (scheme 85), but significantly less than when using the two-level gate driver (scheme 81). This illustrates that a switching circuit with a three-level driver (comprising a diode coupled between a heterogeneous common substrate and ground) can also be used to implement V at 600V or above_dcA lower switch.

The diode 84 may be provided as a separate discrete component or as part of the semiconductor device 20.

In some embodiments, a semiconductor device according to any of the embodiments described herein further comprises a diode structure electrically coupled between the substrate and ground to form the diode 84 and the circuit illustrated in fig. 3A. The diode structures may be integrated into a common foreign substrate 25. If the common foreign substrate 25 is formed of silicon, for example, a single crystal silicon wafer or an epitaxial silicon layer, the diode structure may be formed by forming one or more n-doped regions and one or more p-doped regions in the substrate 25. The diode structure may have various structures, of which three possible structures are illustrated in fig. 4A to 4C.

In fig. 4A to 4C, a half-bridge circuit 30 provided by a low-side switch 28 and a high-side switch 29 monolithically integrated in a semiconductor body is schematically illustrated by means of circuit diagrams. The semiconductor body in which both the low-side switch 28 and the high-side switch 29 are monolithically integrated may be formed directly on top of the diode structure illustrated in fig. 4A to 4C. In some embodiments, no vertical connections (e.g., conductive vias) are provided in the semiconductor body between the diode structure 90 (which is located in the substrate 25) and the upper surface of the semiconductor body or the source of the low side switch 28. The diode structure may be used in a semiconductor device comprising a monolithically integrated half-bridge circuit based on group III nitrides on a common foreign substrate, for example in the semiconductor device 20.

In the embodiment illustrated in fig. 4A to 4C, the common foreign substrate 25 is a silicon substrate lightly doped with the second conductivity type, e.g., the substrate 25 is lightly p-doped.

In the embodiment illustrated in fig. 4A, the diode structure 90 includes a substrate 25, and islands 91 formed of silicon doped with a first conductivity type (e.g., n-type if the substrate is p-doped) are formed on the lightly doped silicon substrate 25. The islands 91 may be formed by implanting n-type dopants into the substrate 25 or may be formed by epitaxial deposition of a substantially planar layer doped with the first conductivity type. The diode structure 90 further includes an island 92 of the second conductivity type on the island 91 of the first conductivity type. The islands 92 of the second conductivity type may be formed by implantation or by epitaxial growth of a further layer doped with the second conductivity type. The islands 92 are heavily doped with the second conductivity type. The upper island 91 of the second conductivity type is laterally smaller than the lower island 91 of the first conductivity type.

Fig. 4B illustrates a diode structure 90' that may be used in the semiconductor device 20 according to an embodiment. The diode 90' is formed in a common foreign substrate 25, the common foreign substrate 25 being formed as in the embodiment illustrated in fig. 4a by a silicon substrate 25 that is lightly doped with a second conductivity type (which in this embodiment is p-type). In diode 90', a well 93 doped with a first conductivity type (n-type if substrate 25 is p-type) is formed in upper surface 44 of substrate 25. The well 93 may be formed by selectively implanting n-type dopants into the upper surface 44 of the lightly p-doped substrate 25. A layer 94 heavily doped with the second conductivity type (p-type if substrate 25 is p-type) is formed on upper surface 44 of substrate 25 and on well 93.

In this embodiment, a trench 95 is formed, the trench 95 extending through the layer 94 and into the upper surface 44 to laterally define the extension of the layer 94 and form an island, while leaving a ring 96 of material of the layer 94 on the upper surface 44 of the substrate 25 laterally surrounding and spaced apart from the island of the upper layer 93. This heavily doped ring 96 of heavily p-doped material forms the p-doped edge termination structure for the diode 90'. In some embodiments, n-doped well 93 is exposed in the bottom of trench 95 such that a ring-shaped region of upper surface 44 of substrate 25 surrounds island 93, and the ring-shaped region of the upper surface of island 93 is positioned laterally adjacent to the bottom of layer 94.

Fig. 4C illustrates an embodiment of a diode structure 90 ", the diode structure 90" comprising a well 93' doped with a first conductivity type (e.g., n-type if the substrate 25 is p-type) located in the upper surface 44 of the silicon substrate 25 that is lightly doped with a second conductivity type (e.g., p-type). A well 97 heavily doped with a second conductivity type is formed laterally within the well 93' doped with the opposite conductivity type. The well 97 has a lateral extension which is smaller than the lateral extension of the well 93', such that an outer circumferential region of the well 93' laterally surrounds the well 97.

The diode 90 "further includes a ring 96' doped with the second conductivity type and laterally surrounding the well 93' doped with the opposite conductivity type and spaced apart from the well 93' by a portion of the upper surface 44 of the common foreign substrate 25. In this embodiment, the ring 96' is formed by an implanted ring region formed in the upper surface 44 of the common substrate 25. Ring 96' is formed in substrate 25 rather than on upper surface 44 of substrate 25 as in the embodiment illustrated in fig. 4B. The rings 96' may be formed using the same process as the wells 97 because they may comprise the same conductivity type and doping. The ring 96' provides an edge termination structure for the diode structure 90 ".

Fig. 5A illustrates a group III-nitride based enhancement mode transistor device 100 that may be used in a half bridge circuit according to any of the embodiments described herein, and may also be used in a semiconductor device that includes two or more gate devices monolithically integrated into a common group III-nitride based semiconductor body located on a common foreign substrate.

Transistor device 100 includes a III-nitride body 101 including a transition/nucleation region 102 disposed on a foreign substrate 103 and a device region 104 disposed on the transition region 102. The device region 104 includes a channel layer 105 and a barrier layer 106 on the channel layer 105 and a heterojunction 107 is formed between the channel layer 105 and the barrier layer 106. In the case of some transistor devices, such as HEMTs, the heterojunction 107 is capable of supporting a two-dimensional charge gas (e.g., a two-dimensional electron gas), which is formed by spontaneous and piezoelectric polarization.

Transistor device 100 includes a source 108, a gate 109, and a drain 110 disposed on barrier layer 106. The gate 109 is laterally positioned between the source 108 and the drain 110. The gate 109 may include a p-doped region 111 between the barrier layer 106 and the metal gate 112 so that the transistor device 100 is an enhancement mode device.

In some embodiments, the drain 110 includes a p-doped region 113 that is electrically coupled to the metal drain 110 to form a so-called hybrid drain arrangement. The p-doped region 113 may be disposed laterally between the gate 109 and the drain 110 and spaced apart from the p-doped region 111 underlying the gate metal 112.

In the transistor device 100 illustrated in fig. 5A, a p-doped region 114 is provided that is electrically coupled to the metal source 108 such that the source has a hybrid source arrangement. The p-doped region 114 acts as a hole injector that is electrically coupled to the source 108 and laterally between the source 108 and the gate 109. The source 108 is typically connected to an overlying source contact 115 that has a lateral extent greater than the source 108, and in some embodiments extends over the gate 109 and is electrically insulated from the gate 109 by one or more electrically insulating layers 116. The gate 109 is covered by an electrically insulating layer 116, which electrically insulating layer 116 may also be arranged between the p-doped region 110 of the gate 109 and the source contact 108. The transistor device further comprises a drain electrode 117 arranged on the drain 110. The transistor device 100 may be used as a high-side switch in a monolithically integrated half-bridge circuit, such as the high-side switch 29 of the half-bridge circuit 30.

Fig. 5B illustrates a line graph of gate-source voltage VGS versus time and a line graph of VSW versus time for a half bridge circuit for a High Side Switch (HSS) and a Low Side Switch (LSS). Both the low-side switch and the high-side switch have a hybrid source structure including a p-doped source region 114 electrically coupled to the source.

In a time period 120 the gate-source voltage of the low-side switch is lowered, in this embodiment to-4V, to turn off the low-side switch, and thereafter, in a time period 121, a voltage is applied to the gate of the high-side switch to turn on the high-side switch. The voltage is then removed from the gate of the high-side switch to turn off the high-side switch. Subsequently, in a time period 122, a voltage is applied to the low-side switch to turn on the low-side switch again. In a time period 123 between time periods 120 and 121, both the low-side switch and the high-side switch are turned off and a positive voltage is not applied to the gate of the low-side switch or the high-side switch. Fig. 5B illustrates soft switching of the half-bridge circuit.

In time period 123, it is believed that the diode formed between p-doped region 114 coupled to source 108 and the channel region turns on and injects holes, preventing depletion of the two-dimensional electron gas. This is caused by the current I through the high side switch illustrated in FIG. 5A_L2And the equivalent circuit diagram illustration of fig. 5C. During this time period 123, the current I_L1Also through the low side switch as shown in fig. 5C.

Fig. 5D illustrates the circuit during the first period 124 of the on-state of the high-side switch (i.e., period 121 of fig. 5A), and illustrates that the p-doped region 114 coupled to the source 108 can still inject holes, preventing depletion of the two-dimensional electron gas. The total current I flowing through the high-side switch is indicated in the equivalent circuit diagram of fig. 5D and the schematic diagram of the high-side switch in fig. 5E_L. Thus, as shown in fig. 5B, during the initial conduction period 124 of the high-side switch, a desired value V is agreed_BUSIs smaller than that existing at V_SWIncrease (if any). V in this period for soft switching_SWHigher than V_BUS. If there is no depletion of the 2DEG in the channel as desired, then at V_SWThe increase in the above is small. On the other hand, if there is some 2DEG depletion, then V is compared to the case without 2DEG depletion_SWBecomes higher.

In other embodiments, a transistor device including a p-doped source region electrically coupled to a source, such as the transistor device 100 illustrated in fig. 5A, is driven using a multi-level gate drive scheme including at least three levels according to any of the embodiments described herein.

Fig. 6 illustrates a schematic representation of a bidirectional switch 130 comprising a III-V semiconductor body 131 disposed on a substrate 132. For example, the III-V semiconductor body 131 may include a multi-layer III-nitride structure and the substrate may include silicon. The bidirectional switch 130 comprises a first input/output contact 133 and a second input/output contact 134 arranged on an upper surface 135 of the semiconductor body 131. The bidirectional switch 130 further comprises two gate contacts 136, 137 arranged on the upper surface 135, laterally between and spaced apart from the first and second input/output contacts 133, 134, and spaced apart from each other. In some embodiments, a single gate contact is provided. A gate driver according to one of the embodiments described herein may be used to drive one or both of the gate contacts 136, 137.

The bidirectional switch 130 may be formed in a semiconductor body 131 having a multi-layer III-nitride structure according to any of the embodiments described herein.

The bidirectional switch 130 may have a common drain structure in which one input/output contact is shared by two adjacent devices, whereby a single gate electrode is disposed on opposite sides of the shared or common input/output contact.

In some embodiments of the bidirectional switch 130, the p-doped group III nitride region coupled to the first input/output contact 133 and/or the p-doped group III nitride region coupled to the second input/output contact 134 may be omitted as a charge source or a hole injector, and the second gate may be used as a hole injector.

As discussed above, a III-V semiconductor body, such as the III-nitride based epitaxial structure of semiconductor body 21 of semiconductor device 20 illustrated in fig. 1, may have a capacitive effect in which the semiconductor body effectively acts as a capacitor in which the two-dimensional electron gas forms a top electrode, substrate 25 forms a bottom electrode and the III-nitride based epitaxial structure between the two-dimensional electron gas and substrate 25 forms the dielectric of the capacitor structure, which results in depletion of the 2DEG and an increase in parasitic resistance Rs when the top electrode of the capacitor is at a high positive potential relative to the bottom electrode, such that the actual drain-source current Ids of the device, such as the high-side switch of a monolithically integrated half-bridge, is less than expected.

It is believed that this capacitive effect is reduced or eliminated by the embodiments described herein so that this can be exploited to increase the voltage at which the switching circuit can be operated. In some embodiments, a switching circuit is provided that includes a group III-nitride based semiconductor body including a first and a monolithically integrated group III-nitride based transistor devices coupled to form a half-bridge circuit disposed on a common foreign substrate including a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300V, for example at least 450V.

In some embodiments, the switching circuit includes a hole injector operable to periodically inject holes into a buried layer located vertically between the two-dimensional electron gas and the common foreign substrate. Thus, the hole injector may be switchable. The buried layer may for example be formed by a portion of the channel layer or by a buffer structure of the group III-nitride based semiconductor body, so that the term "buried layer" does not necessarily indicate an additional structure.

The buried layer may be arranged in a second monolithically integrated group III-nitride based transistor device providing a high-side switch of the half-bridge circuit, since the formation of parasitic resistances in the high-side switch may cause the drain-source current to be reduced.

In some embodiments, the switchable hole injector is vertically above and spaced apart from the two-dimensional charge gas, e.g., the switchable hole injector may be located on the channel layer. In some embodiments, the switchable hole injector is a doped region of the second conductivity type coupled to the source contact or provided by a gate driver coupled to and operating the gate.

In some embodiments, this capacitive effect of the semiconductor body is reduced or eliminated by a method of operating a transistor device as follows: wherein the two-dimensional charge gas is periodically shielded from the substrate by periodically injecting charges of the second conductivity type from the charge source. The charge source may be a p-doped region coupled to a source or gate driver.

The method may be used to operate a transistor device, such as transistor device 29 of semiconductor device 20 illustrated in fig. 1 or transistor device 100 illustrated in fig. 5A.

The transistor device 100 may include a group III-nitride based body 101 including a transition region 102 disposed on a foreign substrate 103 and a device region 104 disposed on the transition region 102, the device region 104 including: a barrier layer 106 disposed on the channel layer 105, forming a heterojunction 107 therebetween capable of supporting a two-dimensional charge gas of the first conductivity type; a source contact 115, a gate 109, and a drain contact 117 disposed on the barrier layer 106.

Transistor device 100 typically has a charge breakdown density that can be determined. In some embodiments, an amount of charge of at least half the breakdown density is periodically injected to provide periodic shielding of the two-dimensional charge gas from the substrate 102.

The second conductivity type of charge injected from the charge source may be used to increase the second conductivity type of charge density in a region of the group III-nitride based body vertically disposed between the two-dimensional charge gas of the first conductivity type and the foreign substrate 102 for a predetermined period of time, and after the predetermined period of time ends, the method includes stopping the injection of the second conductivity type of charge from the charge source.

The charge source may be vertically above and spaced apart from the two-dimensional charge gas, such as on the barrier layer 106.

The region of the group III-nitride based body in which the charge density of the second conductivity type is increased may be vertically spaced from the two-dimensional charge gas of the first conductivity type from the heterojunction 107 and vertically spaced from the foreign substrate 102. The region may extend continuously from the source contact 115 to the drain contact 117 and laterally under the source contact 115 and under the drain contact 117.

In some embodiments, the charge of the second conductivity type is injected during an initial period of the on-cycle of the transistor device 100.

In some embodiments, the charge density of the region capacitively decouples the foreign substrate 102 from the two-dimensional charge gas during a predetermined period of time.

In some embodiments, the transistor device 100 is coupled with a further transistor device (e.g. the low-side switch 28 illustrated in fig. 1) to form a half-bridge circuit, and the transistor device and the further transistor device are monolithically integrated in a common semiconductor body arranged on a common foreign substrate.

In embodiments in which the transistor device 100 provides a high side switch of a half bridge circuit and the further transistor device 28 provides a low side switch of the half bridge circuit, the method may further comprise ceasing injection of charge of the second conductivity type from the charge source during the conduction period of the low side switch 28, and injecting charge of the second conductivity type from the charge source 114 during a first time period when the gate 109 is turned on during the conduction period of the high side switch 100, and ceasing injection of charge of the second conductivity type from the charge source 114 during a second time period after the first time period when the gate 109 is held in a conducting state.

The gate driver scheme according to any of the embodiments described herein may also be used for discrete III-nitride transistor devices (such as discrete III-nitride enhancement mode HEMTs) and is not limited to use for devices comprising two or more III-nitride devices monolithically integrated in a common substrate.

A gate driver and method for switching according to any of the embodiments described herein is not limited to use with group III-nitride enhancement mode transistor devices and may be used with other transistor devices. In a further embodiment, the principles of a gate driver and method according to any of the embodiments described herein are used to switch normally-on III-nitride depletion mode transistor devices. The III-nitride depletion mode transistor device may be a discrete device or monolithically integrated with one or more further III-nitride devices in a common substrate.

In some embodiments, a depletion mode ill-nitride transistor device (e.g., a depletion mode ill-nitride HEMT) includes a gate including a p-doped ill-nitride layer under a metal gate. However, the distance between the gate p-doped group III nitride layer and the two-dimensional electron gas is large enough that the two-dimensional electron gas is fully depleted and the device is normally on.

In some embodiments, a gate voltage is used to drive the III-nitride depletion transistor device instead of a gate current.

In the off-state, a negative voltage less than the negative threshold voltage (e.g., -3V or less) of the group III-nitride depletion mode transistor device is supplied to the gate of the device. To turn on the group III-nitride depletion transistor device, a voltage V is applied_g1Supplied to the grid with the voltage V_g1It is sufficient to turn on a diode formed between the gate including the p-doped layer and the two-dimensional electron gas so as to inject holes. The voltage V_g1And may be greater than +3V or greater than + 4V. The voltage may be applied as a short pulse, similar to that used for enhancement mode III-nitride transistor devices, to generate a gate current Ig for a first period of time₁。

Then, a voltage V of about 0 at the next level of the multi-level gate driver_g2Is supplied to the gate to generate a gate current Ig₂And maintains the on state of the device, whereby the voltage may be slightly greater or less than 0V. For enhanced III-nitride devices, Ig₁＞5Ig₂Or Ig or₁＞10Ig₂Thus, there are additional conditions: v_g1≧ 3V or V_g1≧3V。

In an embodiment, there is provided a multilevel gate driver for a group III nitride based depletion mode transistor device comprising a source, a gate and a drain, wherein during an on-period of the group III nitride based depletion mode transistor device, the gate driver is configured to supply a first gate voltage Vg1 to the gate during a first time period to apply a first gate current Ig during the first time period₁First gate current Ig₁Is sufficient to turn on and maintain the gate in a conductive state, and to supply a second gate voltage V to the gate during a second time period after the first time period_g2Thereby applying a second gate current Ig to the gate during a second time period₂To keep the gate in a conducting state, where V_g1≧ 3V or V_g13V and Ig₁＞5Ig₂Or Ig or₁＞10Ig₂。V_g2About 0V.

In order to turn off and maintain the group III nitride based depletion mode transistor device in an off state, e.g., after a second period of time, the gate driver is configured to supply a voltage V to the gate_offIn which V is_off<0V, e.g. V_off<-3V。

The following examples are also provided:

example 1. a multi-level gate driver for a group III-nitride based enhancement mode transistor device including a source, a gate, and a drain,

wherein during an on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to:

supplying a first gate voltage to the gate during a first time period to apply a first gate current Ig during the first time period sufficient to turn on the gate and to maintain the gate in an on state₁And an

Supplying a second gate voltage to the gate during a second period after the first period to apply a second gate current Ig to the gate during the second period₂To keep the gate in an on-state, where Ig₁>5Ig₂Or Ig or₁>10Ig₂The amount of the oxygen present, or alternatively,

during an on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to:

supplying a first gate current Ig to the gate during a first time period₁Wherein Ig is₁Is sufficient to turn on the gate and to keep the gate in a conductive state, an

Supplying a second gate current Ig to the gate during a second time period after the first time period₂Wherein Ig is₂The gate is held in a conducting state,

wherein Ig is₁＞5Ig₂Or Ig or₁＞10Ig₂。

Example 2. the gate driver according to example 1, wherein the second period of time is consecutive to the first period of time.

Example 3. the gate driver according to example 1 or example 2, wherein 0.24 muA/mum²≤Ig1≤7.21µA/µm²And/or 2.4 nA/mum²≤Ig2≤0.24µA/µm²And/or the first time period is in the range of 10ns to 3 μ s, or 50ns to 3 μ s, or 100ns to 3 μ s, or 500ns to 3 μ s, or 1 μ s to 3 μ s.

Example 4. the gate driver according to one of examples 1 to 3, wherein during the further on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to:

a single gate voltage is supplied to the gate during the entire period of the on-period, or

Wherein, during a further on-period of the group III-nitride based enhancement mode transistor device, the gate driver is configured to:

a single gate current is supplied to the gate during the entire period of the on-period.

Example 5 the gate driver according to one of examples 1 to 4, wherein the gate driver is further configured to supply a third gate voltage to turn off the gate, or the gate driver is further configured to supply a third gate current to turn off the gate.

Example 6 the gate driver according to example 5, wherein the gate driver is further configured to supply a third gate voltage to turn off the gate, the third gate voltage being negative, followed by a fourth gate voltage of about 0.

Example 7. the gate driver according to one of examples 1 to 6, wherein

Applying a fifth gate voltage to the gate for an initial period of time prior to the first period of time, thereby applying an initial gate current Ig₀To turn on the gate and to keep the gate in the on-state, where Ig₀＜Ig₁Or is or

Supplying an initial gate current Ig to the gate during an initial period prior to the first period₀To turn on the gate, wherein Ig₀＜Ig₁。

Example 8. the gate driver according to one of examples 1 to 6, wherein

Supplying a first gate voltage to the gate during a first time period such that a first gate current Ig₁Turn on the gate, or

Supplying a first gate current Ig to the gate during a first time period₁To turn on the gate.

Example 9. the gate driver according to one of examples 1 to 8, wherein the gate driver includes:

a first linear voltage regulator (LDO) coupled in parallel with a second LDO,

an output of the first LDO coupled in series with a switch coupled to an output node,

an output of the second LDO coupled in series with a bidirectional switch coupled to the output node,

a first capacitor coupled between an output of the first LDO and an output of the second LDO,

a second capacitor coupled between an output of the second LDO and a low voltage node,

a switch coupled between the second capacitor and the output node,

wherein a first voltage is supplied to the output node when a switch coupled between an output of the first LDO and the output node is turned on, and wherein a second voltage is supplied to the output node when the bidirectional switch is turned on, wherein the first voltage is greater than the second voltage.

Example 10. the gate driver according to one of examples 1 to 9, wherein the transistor device is an enhancement mode device and is monolithically integrated in a group III nitride based semiconductor body, the semiconductor body comprising a further monolithically integrated group III nitride based enhancement mode transistor device,

wherein a source of the transistor device is coupled to a drain of the further monolithically integrated group III-nitride based enhancement mode transistor device to form a half-bridge configuration, the transistor device and the further monolithically integrated group III-nitride based enhancement mode transistor device being arranged on a common substrate.

Example 11. the gate driver according to one of examples 1 to 9, wherein the transistor device is an enhancement mode device and is monolithically integrated in a group III nitride based semiconductor body, the semiconductor body comprising a further monolithically integrated group III nitride based enhancement mode transistor device,

wherein the transistor device and the further monolithically integrated group III-nitride based enhancement mode transistor device are coupled to form a bidirectional switch and are disposed on a common foreign substrate.

Example 12 the gate driver according to example 10 or example 11, wherein the common substrate is coupled to a ground potential.

Example 13. a power switching circuit, comprising:

a group III nitride based semiconductor body comprising:

a first monolithically integrated group III-nitride based enhancement mode transistor device, and

a second monolithically integrated group III-nitride based enhancement mode transistor device,

according to the gate driver of one of examples 1 to 8,

wherein the first and second monolithically integrated group III-nitride based enhancement mode transistor devices are coupled to form a circuit having a load path and are disposed on a common substrate.

Example 14. the power switching circuit of example 13, wherein a drain of the first monolithically integrated group III-nitride based enhancement mode transistor device is coupled to a source of the second monolithically integrated group III-nitride based enhancement mode transistor device to form a half bridge circuit.

Example 15 the power switching circuit of example 13, wherein the first monolithically integrated group III-nitride based enhancement mode transistor device and the second monolithically integrated group III-nitride based enhancement mode transistor device are coupled to form a bidirectional switch.

Example 16 the power switching circuit of one of examples 13 to 15, further comprising a diode comprising an anode and a cathode, wherein the anode is coupled to the node having the lowest potential and the cathode is coupled to the common substrate.

Example 17 the power switching circuit of example 16, wherein the diode is integrated into a common substrate.

Example 18. the power switching circuit of example 17, wherein:

the common substrate is a p-doped substrate and includes an n-doped island on the p-doped substrate to form a diode, the III-nitride semiconductor body is disposed on the n-doped island, or

The common substrate is a p-doped substrate, and includes an n-doped island on the p-doped substrate and a p-doped layer on the n-doped island to form a diode, the III-nitride semiconductor body being disposed on the p-doped layer, or

The common substrate is a p-doped substrate and comprises an n-doped well in the p-doped substrate and a p-doped layer arranged on the n-doped well to form the diode, wherein the p-doped layer is further arranged on the p-doped substrate, the p-doped layer comprises a trench completely interrupting the p-doped layer adjacent to the n-doped well, the group III nitride semiconductor body is arranged on the p-doped layer, or

The common substrate is a p-doped substrate and includes an n-doped well in the p-doped substrate to form a diode and a p-doped ring disposed in the p-doped substrate, the p-doped ring being laterally spaced from the n-doped well, the group III-nitride semiconductor body being disposed on the n-doped well, or

The common substrate is a p-doped substrate and includes an n-doped well in the p-doped substrate and a p-doped well in the n-doped well to form a diode and a p-doped ring disposed in the p-doped substrate, the p-doped ring being laterally spaced apart from the n-doped well, the group III nitride semiconductor body being disposed on the p-doped well.

Example 19. a group III-nitride based enhancement mode transistor device, comprising:

a group III-nitride based body including a transition region disposed on a foreign substrate and a device region disposed on the transition region, the device region including a barrier layer on a channel layer and forming a heterojunction capable of supporting a two-dimensional charge gas,

a source and a gate disposed on the barrier layer, and a drain, the gate being disposed laterally between the source and the drain, wherein the source comprises at least one hole-injecting body region electrically coupled to the source and laterally between the source and the gate.

Example 20 the group III-nitride based enhancement mode transistor device of example 19, wherein the hole injection body region comprises a p-doped group III-nitride region disposed on the barrier layer.

Example 21 the group III nitride-based enhancement mode transistor device of example 19 or example 20, wherein the drain includes at least one hole injector body region electrically coupled to the drain and laterally between the drain and the gate of the second transistor device.

Example 22 the group III-nitride based enhancement mode transistor device of one of examples 19 to 21, wherein the gate further comprises a p-doped group III-nitride region disposed between the metal gate and the barrier layer.

Example 23 a monolithically integrated group III nitride-based circuit, comprising two or more switching devices, wherein two of the switching devices are coupled to form a half bridge comprising a low side switch and a high side switch, wherein the high side switch comprises a group III nitride-based enhancement mode transistor according to any of examples 19 to 22.

Example 24. the monolithically integrated group III-nitride based circuit of example 19, wherein the two or more switching devices are formed on a common group III-nitride based body, the common group III-nitride based body being formed on a common foreign substrate.

Example 25 the monolithically integrated group III nitride based circuit of example 23 or example 24, further comprising a gate driver according to one of examples 1 to 14.

Example 26. a monolithically integrated group III-nitride based circuit, comprising two or more switching devices, wherein two of the switching devices are coupled to form an bidirectional switch, wherein the bidirectional switch comprises two group III-nitride based enhancement mode transistors according to any of examples 19 to 22.

Example 27. the monolithically integrated group III-nitride based circuit of example 26, wherein the two group III-nitride based enhancement mode transistors share a common drain.

Example 28. the monolithically integrated group III-nitride based circuit of example 26 or example 27, wherein the two or more switching devices are formed in a common group III-nitride based body formed on a common foreign substrate.

Example 29 the monolithically integrated group III nitride based circuit of any of examples 26 to 28, further comprising a gate driver according to one of examples 1 to 14.

Example 30 a method of switching a group III-nitride based enhancement mode transistor device including a source, a gate, and a drain, the method comprising:

during an on-period of a group III-nitride based enhancement mode transistor device:

supplying a first gate voltage to the gate during a first time period to apply a first gate current Ig during the first time period sufficient to turn on the gate and to maintain the gate in an on state₁And an

Supplying a second gate voltage to the gate during a second period after the first period to apply a second gate current Ig to the gate during the second period₂To keep the gate in an on-state, where Ig₁>5Ig₂Or Ig or₁>10Ig₂Or the method comprises:

supplying a first gate current Ig to the gate during the first period of time sufficient to turn on the gate and to maintain the gate in an on state₁And an

Supplying a second gate current Ig to the gate during a second time period after the first time period₂To keep the gate in a conductive state,

wherein Ig is₁＞5Ig₂Or Ig or₁＞10Ig₂。

Example 31 the method of example 30, wherein the second time period is consecutive to the first time period.

Example 32. the method of example 30 or example 31, wherein 700mA ≦ Ig₁Less than or equal to 2A and less than or equal to 20mA and less than or equal to Ig₂Less than or equal to 100mA, or

Wherein 0.24 muA/mum²≤Ig₁≤7.21µA/µm²And/or 2.4 nA/mum²≤Ig₂≤0.24µA/µm²And/or in the range of 10ns to 3 μ s at the first time period.

Example 33 the method of one of examples 30 to 32, wherein during the further turn-on cycle of the group III-nitride based enhancement mode transistor device, the method comprises:

a single gate voltage is supplied to the gate during the entire period of the on-period, or

In a further on-cycle of the group III-nitride based enhancement mode transistor device, the method comprises:

a single gate current is supplied to the gate during the entire period of the on-period.

Example 34 the method of one of examples 30 to 33, further comprising supplying a third gate voltage to turn off the gate.

Example 35 the method of example 34, wherein the third gate voltage is negative, or the third gate voltage is negative and followed by a fourth gate voltage of about 0.

Example 36. the method of one of examples 30 to 35, further comprising:

applying a fifth gate voltage to the gate for an initial period of time prior to the first period of time to apply an initial gate current Ig₀To turn on the gate and to keep the gate in the on-state, where Ig₀<Ig₁Or is or

Further comprising:

supplying an initial gate current Ig to the gate during an initial period prior to the first period₀To turn on the gate and to keep the gate in the on-state, where Ig₀<Ig₁。

Example 37. the method according to one of examples 30 to 36, wherein

Supplying a first gate voltage to a gate during a first time periodSo that the first gate current Ig₁Turn on the gate and keep the gate in a conducting state, or

Supplying a first gate current Ig to the gate during a first time period₁To turn on the gate and to keep the gate in a conductive state.

Example 38. the method of one of examples 30 to 37, wherein the group III-nitride based enhancement mode transistor device is a high-side switch of a half-bridge circuit.

Example 39 the method of example 38, wherein the half-bridge circuit further comprises a further ill-nitride based enhancement mode transistor device configured to provide a low side switch of the half-bridge circuit, the method further comprising:

supplying a single gate voltage or a single gate current to the gate of a further group III-nitride based enhancement mode transistor device during an on-period of the low side switch, an

Supplying a first gate voltage to a gate of a group III-nitride based enhancement mode transistor device during a first time period during an on-period of a high-side switch such that a first gate-source current Igs₁Is applied to turn on the gate and to maintain the gate in a conductive state, an

Supplying a second gate voltage to a gate of a group III-nitride based enhancement mode transistor device during a second time period after the first time period such that a second gate-source current Igs₂Is applied to the gate to maintain the gate in a conductive state, wherein Igs₁＞5Igs₂Preferably Igs₁＞10Igs₂。

Example 40 a method of operating a transistor device, the transistor device including a group III-nitride based body, the group III-nitride based body including a transition region disposed on a substrate and a device region disposed on the transition region, the device region including a barrier layer disposed on a channel layer, a source contact, a gate, and a drain contact disposed on the barrier layer, the channel layer and the barrier layer forming a heterojunction therebetween capable of supporting a two-dimensional charge gas of a first conductivity type, the method comprising:

the two-dimensional charge gas is periodically shielded from the substrate by periodically injecting charges of the second conductivity type from the charge source.

Example 41 the method of operating a transistor device of example 40, wherein the transistor device has a charge breakdown density, and the amount of charge of at least half the breakdown density is periodically injected to provide periodic shielding of the two-dimensional charge gas from the substrate.

Example 42. the method of example 40 or example 41, wherein the second conductivity type of the charge injected from the charge source increases a charge density of the second conductivity type in a region of the group III nitride based body vertically arranged between the two-dimensional charge gas of the first conductivity type and the foreign substrate for a predetermined period of time, an

After the predetermined period of time has elapsed, the method includes stopping the injection of charges of the second conductivity type from the charge source.

Example 43. the method of one of examples 40 to 42, wherein the charge source is vertically above and spaced apart from the two-dimensional charge gas.

Example 44. the method of one of examples 40 to 43, wherein the charge source is located on the channel layer.

Example 45. the method of one of examples 40 to 44, wherein the charge source is a doped region of the second conductivity type coupled to the source contact.

Example 46. the method of one of examples 40 to 45, wherein the charge source is provided by a gate driver coupled to the gate.

Example 47. the method of one of examples 40 to 46, wherein the charge is periodically injected from the charge source into a region of the group III-nitride based body disposed between and vertically spaced from the two-dimensional charge gas and the foreign substrate.

Example 48 the method of example 47, wherein the region extends continuously from the source contact to the drain contact.

Example 49 the method of example 48, wherein the region extends laterally under the source contact and under the drain contact.

Example 50 the method of one of examples 40 to 49, wherein the second conductivity type of charge is injected during an initial period of an on cycle of the transistor device.

Example 51 the method of one of examples 40 to 50, wherein the charge density of the region capacitively decouples the foreign substrate from the two-dimensional charge during the predetermined period of time.

Example 52. the method of one of examples 40 to 51, wherein the transistor is a group III nitride based transistor device.

Example 53. the method according to one of examples 40 to 52, wherein the transistor device is coupled with the further transistor device to form a half bridge circuit, and the transistor device and the further transistor device are monolithically integrated in a common semiconductor body arranged on a common substrate.

Example 54 the method of example 53, wherein the common semiconductor body comprises an epitaxial multilayer structure.

Example 55 the method of one of examples 40 to 54, wherein the transistor device provides a high-side switch of the half-bridge circuit and the further transistor device provides a low-side switch of the half-bridge circuit, the method further comprising:

stopping injection of charge of the second conductivity type from the charge source into the transistor device providing the high-side switch during an on-period of the low-side switch, an

During an on-period of the high-side switch, injecting charge of the second conductivity type from the charge source during a first period of time when the gate is turned on and holds the gate in an on-state, an

During a second time period after the first time period when the gate is held in an on-state, injection of charge of the second conductivity type from the charge source into the transistor device providing the high-side switch is stopped.

Example 56. a switching circuit, comprising:

a group III nitride based semiconductor body comprising:

a first monolithically integrated group III-nitride based transistor device;

a second monolithically integrated group III-nitride based transistor device,

wherein the first and second monolithically integrated group III-nitride based transistor devices are coupled to form a half-bridge circuit and are disposed on a common substrate comprising a common doping level,

wherein the switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300V.

Example 57 the switching circuit of example 56, wherein the group III nitride based semiconductor body comprises:

a transition region disposed on the substrate and a device region disposed on the transition region, the device region including a barrier layer disposed on the channel layer, a heterojunction capable of supporting a two-dimensional charge gas of the first conductivity type being formed between the channel layer and the barrier layer;

a first monolithically integrated group III-nitride based transistor device and a second monolithically integrated group III-nitride based transistor device are formed in the device region.

Example 58. the switching circuit of example 56 or example 57, wherein the switching circuit further comprises a hole injector operable to periodically inject holes into a buried layer vertically between the two-dimensional electron gas and the common substrate.

Example 59. the switching circuit of example 58, wherein the buried layer is disposed in the second monolithically integrated group III-nitride based transistor device or in the first monolithically integrated group III-nitride based transistor device.

Example 60. the switching circuit of example 58 or example 59, wherein the hole injector is vertically above and spaced apart from the two-dimensional charge gas.

Example 61 the switching circuit of one of examples 58 to 60, wherein the hole injector is located on the channel layer.

Example 62. the switching circuit of one of examples 58 to 61, wherein the switchable hole injector is a doped region of the second conductivity type coupled to the source contact.

Example 63. the switching circuit of one of examples 58 to 61, wherein the hole injector is provided by a gate driver coupled to the gate.

Example 64 the switching circuit of one of examples 56-63, wherein the first monolithically integrated group III-nitride based transistor device and the second monolithically integrated group III-nitride based transistor device are coupled to form a half-bridge circuit, and the first monolithically integrated group III-nitride based transistor device provides a low-side switch of the half-bridge circuit and the second monolithically integrated group III-nitride based transistor device provides a high-side switch of the half-bridge circuit.

Example 65. the switching circuit of one of examples 56 to 64, wherein the first and second monolithically integrated group III-nitride based transistor devices are enhancement mode devices or depletion mode devices.

Example 66. the switching circuit of one of examples 56-65, wherein each of the first and second monolithically integrated group III-nitride based transistor devices includes a p-doped region between the metal gate and the barrier layer.

Spatially relative terms, such as "lower," "above," and "upper," are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as "first," "second," and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

As used herein, the terms "having," "including," and "comprising," and the like, are open-ended terms that indicate the presence of the stated elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It is to be understood that features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.