阅读说明：本技术 一种超低功耗并具有上电复位和掉电复位功能的电路 (Circuit with ultralow power consumption and power-on reset and power-off reset functions ) 是由 张永生 王彬 徐凯 程银 陆会会 王中杰 于 2021-06-16 设计创作，主要内容包括：本发明公开了一种超低功耗并具有上电复位和掉电复位功能的电路,将上电复位电路和掉电复位电路的功能集成在一起,利用比较器输出的高低电平来实现复位功能。电源电压的变化会引起电容的充放电效应,以此改变比较器两端输入电压大小,得到不同的输出电平,实现复位功能。合理调整各MOS管的尺寸、电容大小,可以满足不同的上电、下电需求,包括上电、下电电压以及时长,以及在不同的电压域下工作,将上电复位和掉电复位功能巧妙结合起来,同时还能实现纳安级别的超低待机功耗。(The invention discloses a circuit with ultra-low power consumption and power-on reset and power-off reset functions, which integrates the functions of a power-on reset circuit and a power-off reset circuit and realizes the reset function by using high and low levels output by a comparator. The change of the power supply voltage can cause the charge-discharge effect of the capacitor, so that the input voltage at two ends of the comparator is changed to obtain different output levels, and the reset function is realized. The sizes of the MOS tubes and the sizes of the capacitors are reasonably adjusted, different power-on and power-off requirements including power-on and power-off voltages and time lengths can be met, the MOS tube works in different voltage domains, the power-on reset function and the power-off reset function are ingeniously combined, and meanwhile, the ultralow standby power consumption of the nanoampere level can be realized.)

1. A circuit with ultra-low power consumption and power-on reset and power-off reset functions is characterized in that the charge-discharge effect of a capacitor is caused by the change of power supply voltage, when the power supply voltage gradually rises or falls, two input ends of a differential comparator show different size relations, and high and low levels are output according to a comparison result, so that the reset function of the circuit is realized.

2. The ultra-low power consumption circuit with power-on reset and power-off reset functions as claimed in claim 1, wherein the circuit comprises PMOS transistors PMB 1-PMB 6, PMOS transistors PM 1-PM 7, NMOS transistors NM 0-NM 11, a capacitor C1 and a capacitor C2;

PMOS tubes PMB 1-PMB 6 are sequentially connected in series, the gates of the PMOS tubes PMB 1-PMB 6 are all connected with VSS, the source of the PMOS tube PMB1 is connected with VDD, and the drain of the PMOS tube PMB6 is connected with the drain of an NMOS tube NM 0; the source electrodes of the PMOS tubes PM1 and PM2 are connected with VDD, the drain electrode of the PMOS tube PM1 is connected with the drain electrode of the NMOS tube NM1, and the grid electrode and the drain electrode of the PMOS tube PM1 are connected with the grid electrode of the PMOS tube PM 2; the grid electrode and the drain electrode of the NMOS tube NM0 are connected with the grid electrode of the NMOS tube NM1, and the source electrodes of the NMOS tubes NM0 and NM1 are connected with VSS; the drain of the PMOS tube PM2 is connected with the first end of a capacitor C2 and the drain of an NMOS tube NM4, the second end of the capacitor C2 and the source of the NMOS tube NM4 are connected with VSS, the drain of the NMOS tube NM2 is connected with VDD, the source of the NMOS tube NM2 is connected with the first end of the capacitor C1 and the source of the PMOS tube PM7, the gate of the NMOS tube NM2 is connected with the drain, the drain of the PMOS tube PM7 is connected with the drain of the NMOS tube NM3 and the gate of the NMOS tube NM4, and the sources of the NMOS tubes NM3 and NM4 and the second end of the capacitor C1 are connected with VSS; the source electrodes of the PMOS tubes PM3 and PM4 are connected with VDD, the drain electrode of the PMOS tube PM3 is connected with the drain electrode of the NMOS tube NM9, the drain electrode of the PMOS tube PM4 is connected with the drain electrode of the NMOS tube NM10, the grid electrode of the PMOS tube PM3 is connected with the drain electrode and is connected with the grid electrode of the PMOS tube PM4, the source electrodes of the NMOS tubes NM9 and NM10 are connected with the drain electrode of the NMOS tube NM5, the grid electrode of the NMOS tube NM5 is connected with VSS, and the grid electrode of the NMOS tube NM9 is connected with the common end of the PMOS tube PM2 and the capacitor C2; the source electrode of the PMOS tube PM5 is connected with VDD, the drain electrode of the PMOS tube PM5 is connected with the drain electrode of the NMOS tube NM6, the source electrode of the NMOS tube NM6 is connected with VSS, and the grid electrode of the PMOS tube PM5 is connected with the common end of the PMOS tube PM4 and the NMOS tube NM 10; the drain and the gate of the NMOS tube NM11 are connected with VDD, the source of the NMOS tube NM11 is connected with the drain of the NMOS tube NM7, the source of the NMOS tube NM7 is connected with VSS, and the gate of the NMOS tube NM10 is connected with the common end of the NMOS tube NM11 and the NMOS tube NM 7; the source electrode of the PMOS tube PM6 is connected with VDD, the drain electrode of the PMOS tube PM6 is connected with the drain electrode of an NMOS tube NM8, the source electrode of the NMOS tube NM8 is connected with VSS, the grid electrode of the PMOS tube PM6 is connected with the NMOS tube NM8 and connected with the common end of the PMOS tube PM5 and the NMOS tube NM6, and the common end of the PMOS tube PM6 and the NMOS tube NM8 serves as output; the gates of the NMOS transistors NM3, NM5, NM6, and NM7 are connected to the gate of the NMOS transistor NM 1.

Technical Field

The invention relates to a circuit with ultralow power consumption and simultaneously with power-on reset and power-off reset functions.

Background

Many integrated circuits include power-on reset circuitry and power-down reset circuitry that operate to ensure that the analog and digital blocks are initialized to a known state upon application of power. However, a common reset circuit, such as an RC reset circuit, can complete reset when powered on, but cannot effectively reset when powered off, and also occupies a large layout area. Although other types of reset circuits can perform power-on reset and power-off reset, the power-on and power-off reset circuits cannot well give consideration to the requirements of power-on and power-off voltages and time lengths and adapt to different voltage domains, and even generate larger standby power consumption. The current circuits are all combined, so that the area and the power consumption are further increased. At present, the size of an integrated circuit chip and the power supply voltage are continuously reduced and reduced, so that the requirement on a reset circuit is higher and higher, a circuit with ultralow power consumption and functions of power-on reset and power-off reset is required to be provided, and the requirements on functions, layout area and power consumption are met.

Disclosure of Invention

The purpose of the invention is as follows: aiming at the prior art, the circuit with ultralow power consumption and the power-on reset and power-off reset functions is provided.

The technical scheme is as follows: a circuit with ultra-low power consumption and power-on reset and power-off reset functions is characterized in that the charge-discharge effect of a capacitor is caused by the change of power supply voltage, when the power supply voltage is gradually increased or decreased, two input ends of a differential comparator show different size relations, and high and low levels are output according to a comparison result, so that the reset function of the circuit is realized.

Further, the device comprises PMOS tubes PMB 1-PMB 6, PMOS tubes PM 1-PM 7, NMOS tubes NM 0-NM 11, a capacitor C1 and a capacitor C2;

PMOS tubes PMB 1-PMB 6 are sequentially connected in series, the gates of the PMOS tubes PMB 1-PMB 6 are all connected with VSS, the source of the PMOS tube PMB1 is connected with VDD, and the drain of the PMOS tube PMB6 is connected with the drain of an NMOS tube NM 0; the source electrodes of the PMOS tubes PM1 and PM2 are connected with VDD, the drain electrode of the PMOS tube PM1 is connected with the drain electrode of the NMOS tube NM1, and the grid electrode and the drain electrode of the PMOS tube PM1 are connected with the grid electrode of the PMOS tube PM 2; the grid electrode and the drain electrode of the NMOS tube NM0 are connected with the grid electrode of the NMOS tube NM1, and the source electrodes of the NMOS tubes NM0 and NM1 are connected with VSS; the drain of the PMOS tube PM2 is connected with the first end of a capacitor C2 and the drain of an NMOS tube NM4, the second end of the capacitor C2 and the source of the NMOS tube NM4 are connected with VSS, the drain of the NMOS tube NM2 is connected with VDD, the source of the NMOS tube NM2 is connected with the first end of the capacitor C1 and the source of the PMOS tube PM7, the gate of the NMOS tube NM2 is connected with the drain, the drain of the PMOS tube PM7 is connected with the drain of the NMOS tube NM3 and the gate of the NMOS tube NM4, and the sources of the NMOS tubes NM3 and NM4 and the second end of the capacitor C1 are connected with VSS; the source electrodes of the PMOS tubes PM3 and PM4 are connected with VDD, the drain electrode of the PMOS tube PM3 is connected with the drain electrode of the NMOS tube NM9, the drain electrode of the PMOS tube PM4 is connected with the drain electrode of the NMOS tube NM10, the grid electrode of the PMOS tube PM3 is connected with the drain electrode and is connected with the grid electrode of the PMOS tube PM4, the source electrodes of the NMOS tubes NM9 and NM10 are connected with the drain electrode of the NMOS tube NM5, the grid electrode of the NMOS tube NM5 is connected with VSS, and the grid electrode of the NMOS tube NM9 is connected with the common end of the PMOS tube PM2 and the capacitor C2; the source electrode of the PMOS tube PM5 is connected with VDD, the drain electrode of the PMOS tube PM5 is connected with the drain electrode of the NMOS tube NM6, the source electrode of the NMOS tube NM6 is connected with VSS, and the grid electrode of the PMOS tube PM5 is connected with the common end of the PMOS tube PM4 and the NMOS tube NM 10; the drain and the gate of the NMOS tube NM11 are connected with VDD, the source of the NMOS tube NM11 is connected with the drain of the NMOS tube NM7, the source of the NMOS tube NM7 is connected with VSS, and the gate of the NMOS tube NM10 is connected with the common end of the NMOS tube NM11 and the NMOS tube NM 7; the source electrode of the PMOS tube PM6 is connected with VDD, the drain electrode of the PMOS tube PM6 is connected with the drain electrode of an NMOS tube NM8, the source electrode of the NMOS tube NM8 is connected with VSS, the grid electrode of the PMOS tube PM6 is connected with the NMOS tube NM8 and connected with the common end of the PMOS tube PM5 and the NMOS tube NM6, and the common end of the PMOS tube PM6 and the NMOS tube NM8 serves as output; the gates of the NMOS transistors NM3, NM5, NM6, and NM7 are connected to the gate of the NMOS transistor NM 1.

Has the advantages that: the circuit of the invention skillfully combines the power-on reset function and the power-off reset function, can realize nA-level ultra-low standby power consumption, simultaneously occupies extremely low chip area, reasonably adjusts the size and the capacitance of each MOS tube, can realize different power-on and power-off requirements including power-on and power-off voltage and time length, and can also work in different voltage domains.

Drawings

FIG. 1 is a circuit diagram of the present invention;

FIG. 2 is a simulation of the present invention.

Detailed Description

The invention is further explained below with reference to the drawings.

A circuit with ultra-low power consumption and power-on reset and power-off reset functions is characterized in that the charge-discharge effect of a capacitor is caused by the change of power supply voltage, when the power supply voltage is gradually increased or decreased, two input ends of a differential comparator show different size relations, and high and low levels are output according to a comparison result, so that the reset function of the circuit is realized.

As shown in FIG. 1, the circuit specifically includes PMOS transistors PMB 1-PMB 6, PMOS transistors PM 1-PM 7, NMOS transistors NM 0-NM 11, a capacitor C1, and a capacitor C2.

PMOS tubes PMB 1-PMB 6 are sequentially connected in series, the gates of the PMOS tubes PMB 1-PMB 6 are all connected with VSS, the source of the PMOS tube PMB1 is connected with VDD, and the drain of the PMOS tube PMB6 is connected with the drain of an NMOS tube NM 0; the source electrodes of the PMOS tubes PM1 and PM2 are connected with VDD, the drain electrode of the PMOS tube PM1 is connected with the drain electrode of the NMOS tube NM1, and the grid electrode and the drain electrode of the PMOS tube PM1 are connected with the grid electrode of the PMOS tube PM 2; the grid electrode and the drain electrode of the NMOS tube NM0 are connected with the grid electrode of the NMOS tube NM1, and the source electrodes of the NMOS tubes NM0 and NM1 are connected with VSS; the drain of the PMOS tube PM2 is connected with the first end of a capacitor C2 and the drain of an NMOS tube NM4, the second end of the capacitor C2 and the source of the NMOS tube NM4 are connected with VSS, the drain of the NMOS tube NM2 is connected with VDD, the source of the NMOS tube NM2 is connected with the first end of the capacitor C1 and the source of the PMOS tube PM7, the gate of the NMOS tube NM2 is connected with the drain, the drain of the PMOS tube PM7 is connected with the drain of the NMOS tube NM3 and the gate of the NMOS tube NM4, and the sources of the NMOS tubes NM3 and NM4 and the second end of the capacitor C1 are connected with VSS; the source electrodes of the PMOS tubes PM3 and PM4 are connected with VDD, the drain electrode of the PMOS tube PM3 is connected with the drain electrode of the NMOS tube NM9, the drain electrode of the PMOS tube PM4 is connected with the drain electrode of the NMOS tube NM10, the grid electrode of the PMOS tube PM3 is connected with the drain electrode and is connected with the grid electrode of the PMOS tube PM4, the source electrodes of the NMOS tubes NM9 and NM10 are connected with the drain electrode of the NMOS tube NM5, the grid electrode of the NMOS tube NM5 is connected with VSS, and the grid electrode of the NMOS tube NM9 is connected with the common end of the PMOS tube PM2 and the capacitor C2; the source electrode of the PMOS tube PM5 is connected with VDD, the drain electrode of the PMOS tube PM5 is connected with the drain electrode of the NMOS tube NM6, the source electrode of the NMOS tube NM6 is connected with VSS, and the grid electrode of the PMOS tube PM5 is connected with the common end VO of the PMOS tube PM4 and the NMOS tube NM 10; the drain and the gate of the NMOS tube NM11 are connected with VDD, the source of the NMOS tube NM11 is connected with the drain of the NMOS tube NM7, the source of the NMOS tube NM7 is connected with VSS, and the gate of the NMOS tube NM10 is connected with the common end of the NMOS tube NM11 and the NMOS tube NM 7; the source electrode of the PMOS tube PM6 is connected with VDD, the drain electrode of the PMOS tube PM6 is connected with the drain electrode of the NMOS tube NM8, the source electrode of the NMOS tube NM8 is connected with VSS, the grid electrode of the PMOS tube PM6 is connected with the NMOS tube NM8 and connected with the common end VO1 of the PMOS tube PM5 and the NMOS tube NM6, and the common end of the PMOS tube PM6 and the NMOS tube NM8 is used as output; the gates of the NMOS transistors NM3, NM5, NM6, and NM7 are connected to the gate of the NMOS transistor NM 1.

The PMOS tubes PMB 1-PMB 6 are used as resistors and act with the NMOS tube NM0 to generate bias current, and the NMOS tubes NM1, NM3 and NMOS tubes NM 5-NM 7 are current mirrors and mirror the current generated by the NMOS tube NM 0; the PMOS tubes PM1 and PM2 form a PMOS current mirror, and mirror the current of the NMOS tube NM 1; the PMOS tubes PM3 and PM4 and the NMOS tubes NM9, NM10 and NM5 form an N-type five-tube differential pair with double ends, input and single end output, the NMOS tubes NM9 and NM10 are used as input pair tubes of the comparator, and the PMOS tubes PM3 and PM4 are active loads of the input pair tubes; the output stage of the differential tube is connected with a common source amplifier which takes a constant current source consisting of a PMOS tube PM5 and an NMOS tube NM6 as a load, the output end of the differential tube is connected into a phase inverter consisting of a PMOS tube PM6 and an NMOS tube NM8, and finally an output result POR is obtained; the PMOS transistor PM5 is a second stage of the comparator, VO is a first stage output, and VO1 is a second stage output.

The reset circuit of the invention, its power-on reset, power-off reset principle are at power-on, VDD rises gradually, after reaching certain voltage, NMOS tube NM0 has current to flow through, the input VIN of the comparator follows the mains voltage change, after VDD voltage is stabilized, VIN voltage is stabilized too, and input VIP connects the electric capacity C2, PMOS tube PM2 charges the electric capacity C2 slowly, VIP rises the speed to be slower than VIN, after VIP > VIN (and keep the state all the time during VDD stabilizes), the comparator reverses, output POR is higher, the electric capacity C2 charges the speed to control VIP's rising speed. In the power-on process, the NMOS transistor NM2 is diode-connected, the capacitor C1 is charged through the NMOS transistor NM2 after VDD exceeds a certain voltage, and finally VA is maintained at a stable voltage. The gate of the PMOS transistor PM7 is connected to VDD, and as VDD rises, PM7 gradually turns off, so that VB is maintained at a very low voltage, and NMOS transistor NM4 is in a turned off state, so that the charge on the capacitor C2 is maintained, and VIP is finally charged to VDD. There is some reason to cause a sudden drop in VDD and a drop in VIN. At this time, the NMOS transistor NM2 is turned off rapidly and the PMOS transistor PM7 is turned on rapidly, VA = VB is provided, even VDD =0 can be maintained for a long time, so that the NMOS transistor NM4 is turned on, the charge on C2 is released rapidly, the VIP potential is pulled low, VIP < VIN exists before VDD =0, POR outputs low level, and power-down reset is realized, as shown in fig. 2.

In the circuit, the number of the PMB 1-PMB 6 used as the resistors can be adjusted according to the requirement, and the larger the resistor is, the smaller the current is, so as to realize ultra-low power consumption. The sizes of the MOS tubes and the sizes of the capacitors are reasonably adjusted, different power-on and power-off requirements including power-on and power-off voltages and durations can be met, the MOS tube works in different voltage domains, and meanwhile ultralow standby power consumption of nA (nanoampere) level can be achieved. If the current flowing through NM0 is set to be 20nA, and the current mirrors such as NM1, NM3, NM 5-NM 7, PM1, PM2 and the like are set at nA level, the whole power consumption can be maintained at nA level.

Furthermore, the capacitor in the circuit can be replaced by an MOS tube, so that the chip area occupied by the whole circuit is further reduced.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.