阅读说明：本技术 能够检测故障的led背光部 (LED backlight capable of detecting failure ) 是由 金钟善 李龙云 尹炳震 于 2021-03-29 设计创作，主要内容包括：根据本技术的LED背光部包括：发光器件；数据控制部,其接收输入的将发光数据、时钟信号和激活信号以不同电平嵌入的控制信号之后,输出用于控制亮度的亮度控制信号和亮度时间的发光时间控制信号；发光控制部,其接收输入的亮度控制信号和发光时间控制信号,并且在与发光时间控制信号相应的发光时间内,驱动发光器件以具有与亮度控制信号相应的亮度而发光；以及故障检测部,其检测连接到发光控制部和发光器件的节点处的电压并输出与发光器件的是否故障相应的故障信号,其中,数据控制部将由故障检测部检测到的故障作为故障检测信号而输出。(The LED backlight section according to the present technology includes: a light emitting device; a data control part which receives the input control signal embedding the light-emitting data, the clock signal and the activation signal in different levels and then outputs a brightness control signal for controlling brightness and a light-emitting time control signal for controlling brightness time; a light emission control part receiving the input luminance control signal and light emission time control signal and driving the light emitting device to emit light with luminance corresponding to the luminance control signal for a light emission time corresponding to the light emission time control signal; and a failure detection section that detects a voltage at a node connected to the light emission control section and the light emitting device and outputs a failure signal corresponding to whether the light emitting device is failed, wherein the data control section outputs the failure detected by the failure detection section as the failure detection signal.)

1. An LED backlight, comprising:

a light emitting device;

a data control part which receives the input control signal embedding the light-emitting data, the clock signal and the activation signal in different levels and then outputs a brightness control signal for controlling brightness and a light-emitting time control signal for controlling brightness time;

a light emission control part receiving the input luminance control signal and light emission time control signal and driving the light emitting device to emit light with luminance corresponding to the luminance control signal for a light emission time corresponding to the light emission time control signal; and

a failure detection section which detects a voltage at a node connected to the light emission control section and the light emitting device and outputs a failure signal corresponding to whether the light emitting device is failed or not,

the data control unit outputs the failure detected by the failure detection unit as a failure detection signal.

2. The LED backlight of claim 1,

the data control unit includes:

a signal separating unit that receives the control signal as an input, and separates and outputs the clock signal and the activation signal from the control signal;

a data input/output control part which is controlled according to an input/output control signal and receives the supplied light emission data or outputs the failure signal to the outside; and

and a data processing part which provides the input/output of the control signal, receives the supplied activation signal, the clock signal and the data, and forms and outputs the luminance control signal and the light emission time control signal.

3. The LED backlight of claim 2,

the control signal is embedded with:

the activation signal swings (swing) between the first level and a second level greater than the first level; and

the clock signal comprising a plurality of pulses that swing between the second level and a third level that is greater than the second level,

wherein the signal separating part includes: an activation signal isolation circuit that separates an activation signal by including a transistor having a threshold voltage between the first level and the second level and outputs the separated activation signal to swing between the first level and the third level; a clock signal separating circuit that separates a clock signal by including a transistor having a threshold voltage between the second level and the third level, and outputs the separated clock signal to swing between being the first level and the third level.

4. The LED backlight of claim 2,

the data input/output control section includes:

a first switch that receives the light emission data inputted from the input/output bus or outputs the fault detection signal to the input/output bus by being connected to the input/output bus, and is turned on to transmit the light emission data when the input/output control signal is in a first state after being connected to the input/output bus; and

a second switch that is turned on when an input/output control signal is in a second state complementary to the first state after being connected to the input/output bus to connect the fault detection signal to the input/output bus.

5. The LED backlight of claim 2,

the data processing part includes an internal control signal forming part, wherein the internal control signal forming part includes:

a first SR latch to which the activation signal is input;

a first counter that counts a number of pulses included in the clock signal after being activated as an output signal of the first SR latch; and

an internal control signal forming part including a first operation part which forms and outputs a short fault passing signal and an open fault passing signal when a count result of the first counter is supplied and the count result is greater than the number of bits of light emission data, and the data input/output control part forms and outputs an input/output control signal so that the fault signal is output to the outside during a period of the short fault passing signal and the open fault passing signal, and outputs an internal control signal forming part stop signal after the short fault passing signal and the open fault passing signal are output,

wherein the internal control signal forming part stop signal is provided to the first SR latch to deactivate the first counter.

6. The LED backlight of claim 2,

the lighting data is serial (serial) data,

the data processing section includes: a luminance control signal forming section including a shift register which receives the input light emission data and outputs after forming each bit in parallel, and a register which outputs each bit of the light emission data output from the shift register in accordance with a stop signal of the internal control signal forming section,

wherein the output signal of the register is a brightness control signal.

7. The LED backlight of claim 5,

the data processing part includes a light emitting time control signal forming part, wherein the light emitting time control signal forming part includes: a second SR latch to which the internal control signal is input to form a stop signal;

a second counter that counts a number of pulses included in the clock signal after being activated as an output signal of the SR latch; and

a second operation part supplied with the counting result of the second counter and a brightness control signal, and forming and outputting a light emission time control signal of which a pulse width is changed according to a value of the brightness control signal, and forming and outputting a stop signal of the light emission control signal forming part after outputting the light emission time control signal,

wherein the light emission control signal forming part stop signal is supplied to the second SR latch to deactivate the second counter.

8. The LED backlight of claim 7,

the second operation part forms the same pulse width as the light emission time control signal when the luminance control signal is greater than or equal to the threshold value, and forms the pulse width of the light emission time control signal in proportion to the value of the luminance control signal when the luminance control signal is less than the threshold value.

9. The LED backlight of claim 1,

the light emission control section includes: a series resistance (resistor string) connected between the upper limit voltage and the lower limit voltage, and including a plurality of resistors that provide a plurality of gray scale voltages by distributing a voltage difference between the upper limit voltage and the lower limit voltage;

a digital-to-analog converter (DAC) receiving the brightness control signal and outputting a gray scale voltage to emit light having a corresponding brightness;

a driving circuit unit which receives the grayscale voltage and drives the light emitting device with a luminance corresponding to the grayscale voltage; and

a driving time control part receiving the supplied light emitting time control signal, and the driving circuit part controlling the light emitting device to emit light for a time corresponding to the light emitting time control signal.

10. The LED backlight of claim 5,

the failure detection unit includes:

a first comparator that outputs a short-circuit fault signal corresponding to whether or not a short-circuit fault has occurred by comparing a voltage at a node to which the light emission control section and the light emitting device are connected with a short-circuit voltage;

a first latch for latching the short fault signal;

a first flip-flop that samples and outputs the latched short-circuit fault signal as the short-circuit fault pass signal; and

a switch that is turned on to output a short-circuit fault signal after the short-circuit fault passing signal,

wherein the short-circuit fault signal is provided to the data control section as the fault signal.

11. The LED backlight of claim 5,

the failure detection unit includes:

a second comparator that outputs a short-circuit fault signal corresponding to whether or not a short-circuit fault occurs by comparing a voltage at a node to which the light emission control section and the light emitting device are connected with a short-circuit voltage;

a second latch for latching the short fault signal;

a second flip-flop that samples and outputs the latched short-circuit fault signal as a short-circuit fault pass signal; and

a switch which is turned on to output a short-circuit fault signal after the fault passing signal;

wherein the short-circuit fault signal is provided to a data control section as the fault signal.

12. The LED backlight of claim 1,

the failure detection section outputs one or more of a short-circuit failure signal indicating a detected short-circuit failure of the light emitting device and a short-circuit failure signal indicating a detected short-circuit failure,

and the fault detection part outputs the short fault signal and the open fault signal according to the short fault passing signal, the open fault passing signal and the output short circuit provided by the data control part.

13. The LED backlight of claim 1,

a programming phase of inputting the light emitting data to the data control part is periodically executed;

a fault output stage for outputting fault signals by the fault detection part; and

a light emitting stage in which the light emitting device emits light.

14. The LED backlight of claim 13,

in the light-emitting phase, the clock period has a larger value than the clock periods of the program phase and the fail output phase.

15. The LED backlight of claim 1,

arranged in a plurality of rows and columns and driven by an active matrix.

16. The LED backlight of claim 15,

the same control signal is supplied to the LED backlights arranged in the plurality of rows and the same lighting data is supplied to the LED backlights arranged in the plurality of columns.

Technical Field

The present invention relates to an LED backlight unit capable of detecting a failure.

Background

Recently, in terms of realizing display outdoors and indoors in business, there is a trend that display resolution is improved while the display area is enlarged. In addition, LEDs are employed as light emitting devices in order to achieve high luminance, high contrast, and good color reproducibility.

For LED backlights (back-light) for LED displays and LCD display panels, the narrower the pitch between individual LEDs, the denser the number of pixels. The overall display resolution will also improve as the brightness of the individual LEDs increases and the image quality will also improve. In addition, better effects in terms of physical size or cost can be obtained by implementing the LEDs included in the LED backlight portion as an active matrix type. The LED backlight may obtain a high contrast ratio (contrast) by performing local dimming (local dimming) of individually driving the light emitting devices.

Disclosure of Invention

Technical problem to be solved

The large-area and/or high-density LED array is a backlight unit (BLU) configured with a large number of light emitting devices and circuit devices for driving the light emitting devices. Accordingly, if a large-area and/or high-density light emitting device array malfunctions, it is difficult to determine whether the malfunction has occurred.

The present invention aims to solve the above-mentioned problems of the prior art. That is, one of the problems to be solved by the present invention is to provide a light emitting device apparatus capable of easily identifying and specifying a failure when a failure occurs.

Technical scheme for solving problems

The LED backlight section according to the present technology includes: a light emitting device; a data control part which receives the input light emitting data, the clock signal and the control signal embedded with the activation signal in different levels, and then outputs a brightness control signal for controlling brightness and a light emitting time control signal for controlling brightness time; a light emission control part receiving the inputted luminance control signal and light emission time control signal and driving the light emitting device to emit light with luminance corresponding to the luminance control signal for a light emission time corresponding to the light emission time control signal; and a failure detection section that detects a voltage at a node connected to the light emission control section and the light emitting device and outputs a failure signal corresponding to whether the light emitting device is failed, wherein the data control section outputs the failure detected by the failure detection section as the failure detection signal.

As an example of the LED backlight unit, the data control unit includes: a signal separating unit which receives the control signal as an input, and separates and outputs a clock signal and an activation signal from the control signal; a data input/output control section. Which is controlled according to the input/output control signal and receives the supplied lighting data or outputs a fault signal to the outside; and a data processing part which provides an input/output control signal, receives the provided activation signal, clock signal and light emitting data, and forms and outputs a brightness control signal and a light emitting time control signal.

As an example of the LED backlight unit, the control signal is embedded with: an activation signal that swings (swing) between a first level and a second level that is greater than the first level; and a clock signal including a plurality of pulses swinging between a second level and a third level greater than the second level, wherein the signal separating section includes: an active signal isolation circuit which separates an active signal by including a transistor having a threshold voltage between a first level and a second level and outputs the separated active signal to swing (swing) between the first level and a third level; a clock signal separation circuit that separates the clock signal by including a transistor having a threshold voltage between the second level and the third level, and outputs the separated clock signal to swing between the first level and the third level.

As an example of the LED backlight unit, the data input/output control unit includes: a first switch which receives input lighting data from the input/output bus or outputs a fault detection signal to the input/output bus by being connected to the input/output bus, and which is turned on to transmit the lighting data when the input/output control signal is in a first state after being connected to the input/output bus; and a second switch that is turned on when the input/output control signal is in a second state complementary to the first state after being connected to the input/output bus to connect the fault detection signal to the input/output bus.

As an example of the LED backlight unit, the data processing unit includes an internal control signal forming unit, wherein the internal control signal forming unit includes: a first SR latch to which an activation signal is input; a first counter that counts a number of pulses included in the clock signal after being activated as an output signal of the first SR latch; and a control signal forming part including a first operation part inside which a short fault passing signal and an open fault passing signal are formed and output when a count result of the first counter is supplied and the count result is greater than the number of bits of the light emitting data, and during a period of the short fault passing signal and the open fault passing signal, the data input/output control part forms and outputs an input/output control signal so that the fault signal is output to the outside, and outputs an internal control signal forming part stopping signal after the short fault passing signal and the open fault passing signal are output, wherein the internal control signal forming part stopping signal is supplied to the first SR latch to deactivate the first counter.

As an example of the LED backlight unit, the light emission data is serial (serial) data, and the data processing unit includes: and a brightness control signal forming part including a shift register receiving the input light emitting data and outputting each bit (bit) after forming in parallel, and a register outputting each bit (bit) of the light emitting data outputted from the shift register according to the stop signal of the internal control signal forming part, wherein the output signal of the register is a brightness control signal.

As an example of the LED backlight unit, the data processing unit includes a light emission time control signal forming unit including: a second SR latch to which an internal control signal is input to form a stop signal; a second counter which counts the number of pulses included in the clock signal after being activated as an output signal of the SR latch; and a second operation part supplied with the counting result of the second counter and the luminance control signal, and forming and outputting a light emission time control signal changing a pulse width according to a value of the luminance control signal, and forming and outputting a stop signal of the light emission control signal forming part after outputting the light emission time control signal, wherein the light emission control signal forming part stop signal is supplied to the second SR latch to deactivate the second counter.

As an example of the LED backlight unit, the second arithmetic unit forms the same pulse width as the light emission time control signal when the luminance control signal is equal to or greater than the threshold value, and forms the pulse width of the light emission time control signal in proportion to the value of the luminance control signal when the luminance control signal is less than the threshold value.

As an example of the LED backlight unit, the light emission control unit includes: a series resistance (resistor string) connected between the upper limit voltage and the lower limit voltage, and including a plurality of resistors that distribute a voltage difference between the upper limit voltage and the lower limit voltage to provide a plurality of gray scale voltages; a digital-to-analog converter (DAC) receiving the luminance control signal and outputting a gray-scale voltage to emit light having a corresponding luminance; a driving circuit part receiving a gray scale voltage and driving a light emitting device with a luminance corresponding to the gray scale voltage; and a driving time control part receiving the supplied light emitting time control signal, and the driving circuit part controlling the light emitting device to emit light for a time corresponding to the light emitting time control signal.

As an example of the LED backlight unit, the failure detection unit includes: a first comparator which outputs a short-circuit fault signal corresponding to whether or not a short-circuit fault occurs by comparing a voltage at a node to which the light emission control section and the light emitting device are connected with a short-circuit voltage; a first latch for latching the short fault signal; a first flip-flop that samples and outputs the latched short-circuit fault signal as a short-circuit fault pass signal; and a switch which is turned on to output a short-circuit fault signal after the short-circuit fault passing signal. The short-circuit fault signal is supplied to the data control unit as a fault signal.

As an example of the LED backlight unit, the failure detection unit includes: a second comparator which outputs a short-circuit fault signal corresponding to whether or not a short-circuit fault occurs by comparing a voltage at a node to which the light emission control section and the light emitting device are connected with the short-circuit voltage; a second latch for latching the short fault signal; a second flip-flop sampling and outputting the latched short-circuit fault signal as a short-circuit fault passing signal; and a switch which is turned on to output a short-circuit fault signal after the fault passing signal. The short-circuit fault signal is supplied to the data control unit as a fault signal.

As an example of the LED backlight portion, the failure detection portion outputs one or more of a short-circuit failure signal for detecting a short-circuit failure of the light emitting device and a short-circuit failure signal for detecting a short-circuit failure, and the failure detection portion outputs the short-circuit failure signal and the open-circuit failure signal based on the short-circuit failure passing signal, the open-circuit failure passing signal, and the output short-circuit provided from the data control portion.

In one example of the LED backlight unit, the LED backlight unit periodically performs a programming stage in which light emission data is input to the data control unit, a failure output stage in which the failure detection unit outputs a failure signal, and a light emission stage in which the light emitting device emits light.

As an example of the LED backlight, in the lighting phase, the clock period has a larger value than the clock periods of the programming phase and the fail output phase.

As an example of the LED backlight section, LED pixel packages are arranged in a plurality of rows and columns and driven by an active matrix.

As an example of the LED backlight section, the same control signal is supplied to the LED pixel packages arranged in a plurality of rows, and the same light emission data is supplied to the LED pixel packages arranged in a plurality of columns.

Effects of the invention

According to the present technology, there is provided an advantage in that the LED backlight portion can detect a failure of the light emitting device while emitting light.

In addition, according to an example of the present technology, there is provided an advantage in that the LED backlight section can emit light in the form of an active matrix.

Drawings

Fig. 1 is a block diagram showing an outline of an LED backlight 1 according to the present invention.

Fig. 2 is a block diagram schematically showing the data control unit 10.

Fig. 3(a) is a schematic circuit diagram of the signal separating section 100; fig. 3B is a diagram showing an overview of the control signal (S _ SIG) and the activation signal (ON) output from the signal separation unit 110, and the pulse train (S _ OUT).

Fig. 4 is a schematic circuit diagram of the data input/output control section 110.

Fig. 5 is a diagram showing an overview of the data processing section 120, and fig. 6 is a timing chart for explaining the operation of the data processing section 120.

Fig. 7 is a diagram showing an outline of the light emission control unit 20.

Fig. 8 is a graph showing a relationship between a current ILED flowing through the light emitting device according to the luminance control signal (DO [9:0]) and the light emitting time control signal (PWM).

Fig. 9 is a diagram showing an outline of the failure detection unit 30.

Fig. 10 is a diagram showing an overview of a control signal (S _ SIG) provided to the LED backlight according to the present invention.

Fig. 11 is a diagram of an LED backlight 1 configured in an active matrix form according to the present invention.

Detailed Description

The LED backlight according to the present invention includes: a light emitting device; a data control part which receives the input light emitting data, the clock signal and the control signal embedded with the activation signal in different levels, and then outputs a brightness control signal for controlling brightness and a light emitting time control signal for controlling brightness time; a light emission control section that receives the luminance control signal and the light emission time control signal input thereto, and drives the light emitting device to emit light with a luminance corresponding to the luminance control signal for a light emission time corresponding to the light emission time control signal; and a failure detection section that detects a voltage at a node connected to the light emission control section and the light emitting device and outputs a failure signal corresponding to whether the light emitting device is failed, wherein the data control section outputs the failure detected by the failure detection section as the failure detection signal.

Hereinafter, an LED backlight according to the present invention will be described with reference to the accompanying drawings. Fig. 1 is a block diagram showing an outline of an LED backlight 1 according to the present invention. Referring to fig. 1, an LED backlight 1 according to the present technology includes: a light emitting device 40; a data control unit (10) which receives an input emission data, a control signal (S _ SIG) and an emission data (DA _ OUT) in which a clock signal (CLK) and an activation signal (ON) are embedded at different levels, and outputs a luminance control signal (DO [9:0]) for controlling luminance and a luminance time control signal (PWM) for controlling luminance time; a light emission control section 20 that receives the input luminance control signal (DO [9:0]) and the light emission time control signal (PWM), and drives the light emitting device 40 to emit light with a luminance corresponding to the luminance control signal (DO [9:0]) for a light emission time corresponding to the light emission time control signal (DO [9:0 ]); and a failure detection part 30 which detects a voltage at a node connected to the light emission control part 20 and the light emitting device 40 and outputs a failure signal (DA _ FT) corresponding to whether the light emitting device is failed, wherein the data control part 10 outputs the failure detected by the failure detection part 30 as a failure detection signal.

Fig. 2 is a block diagram schematically showing the data control unit 10. Referring to fig. 2, the data control unit 10 includes: a signal separation unit 100 that receives a control signal (S _ SIG) and separates and outputs a clock signal (CLK) and an activation signal (ON) from the control signal (S _ SIG); a DATA input/output control section which is controlled in accordance with an input/output control signal (DA _ IO) and receives input light emission DATA (DA _ OUT) from a DATA input/output bus (DATA) or outputs a fail signal (DA _ FT) to the DATA input/output bus (DATA); and a data processing part 120 which supplies an input/output control signal (DA _ IO) and forms and outputs a luminance control signal (DO [9:0]) and a light emission time control signal (PWM) after receiving the input light emission data (DA _ OUT).

Fig. 3(a) is a schematic circuit diagram of the signal separation section 100, and fig. 3(B) is a diagram showing an overview of the control signal (S _ SIG) and the activation signal (ON) and the pulse train (S _ OUT) output from the signal separation section 100;

referring to fig. 3(a) and 3(B), the control signal (S _ SIG) may swing (swing) between a first level, a second level, and a third level. As an example, the first level may be a ground voltage (GND) level, the third level may be a driving Voltage (VCC) level, and the second level is greater than a threshold voltage of an NMOS transistor included in the signal separating unit 100 but smaller than the third level, and may be a level (VIH) less than twice the threshold voltage of the NMOS transistor. As an example, as shown in fig. 3, the second level (VIH) may have a voltage level greater than 1.0V.

The control signal (S SIG) is a signal embedded with a pulse sequence comprising: an activation signal that swings between a ground voltage (GND) and a second level (VIH); and a pulse that swings between the second level (VIH) and a third level as the driving Voltage (VCC).

The signal separating section 100 includes: an activation signal separation circuit 112 for separating the activation signal (ON) from the control signal (S _ SIG); and a clock signal separation circuit 114 for separating the clock signal (CLK) from the control signal (S SIG).

The activation signal separation circuit 112 is connected to an inverter (I1) Schmitt Trigger (ST) including a resistor (Ra) and a transistor (N1) having a threshold voltage between a first level and a second level and an inverter I2 cascade. The threshold voltage of the transistor (N1) is greater than the first level but less than the second level. Accordingly, if the control signal (S _ SIG) of the first level is input to the inverter I1, the transistor N1 is blocked to output a logic high signal of the third level. However, if the transistor N1 is inputted with the second level or third level control signal (S _ SIG), it is turned on. Accordingly, the inverter I1 outputs a logic low signal of the first level.

A schmitt trigger (schmitt trigger) is a circuit that is not responsive to transient noise because the response of the output according to the magnitude and direction of the input has the characteristics of a hysteresis curve, and is characterized in that the response of the output has a relatively high threshold voltage when the input rises and a relatively low threshold voltage when the input falls.

The output of the Schmitt Trigger (ST) is a signal provided to inverter I2 and swings between a first level and a third level. The output of the inverter I2 is an activation signal (ON) that controls the activation of the subsequent light emission control section 120.

The clock signal separation circuit 114 may include inverters I3, I4 connected in cascade, and the inverter I3 of the first stage is connected to a ground voltage with a diode-connected NMOS transistor N3 connected therebetween. The NMOS transistor (N4) included in the inverter I3 is turned on with a voltage by adding the threshold voltage of the diode-connected NMOS transistor (N3) to the threshold voltage of the transistor (N4).

As described above, the voltage at which the threshold voltage (N3) and the threshold voltage N4 are added is greater than the second level. Accordingly, if the control signal (S _ SIG) having the first and second levels is supplied to the inverter (I3), the NMOS transistor (N4) is not turned on, and the inverter (I3) outputs a logic high signal of the third level. However, if the control signal (S _ SIG) having the third level is supplied to the inverter (I3), the NMOS transistor (N4) is turned on, and the inverter (I3) outputs a logic low signal of the first level. Accordingly, the pulse sequence embedded in the control signal (S _ SIG) can be separated. The inverter (I4) inverts an output signal of the inverter (I3) and outputs the clock signal (CLK) swinging between the first level and the third level.

Fig. 4 is a schematic circuit diagram of the data input/output control section 110. Referring to fig. 4, the DATA input/output control part 110 is connected to a DATA input/output bus (DATA), and includes a first switch (SW1) and a second switch (SW2) controlled by an input/output control signal (DA _ IO). The first switch (SW1) may be a semiconductor switch turned on by the input/output control signal (DA _ IO) of a logic low state, and the second switch (SW2) may be a semiconductor switch turned on by the input/output control signal (DA _ IO) of a logic high state. As another example, the first switch (SW1) may be a semiconductor switch turned on by the input/output control signal (DA _ IO) of a logic high state, and the second switch (SW2) may be a semiconductor switch turned on by the input/output control signal (DA _ IO) of a logic low state.

The first switch SW1 is turned on and supplies the light emission DATA (DA _ OUT) supplied through the DATA input/output bus (DATA) to the input buffer 113. The input buffer 113 outputs the emission data (DA _ OUT) to the data processing section 120. The output buffer 115 buffers and outputs the fail signal (DA _ FT) supplied from the fail detecting section 30, and the second switch (SW2) is turned on to output the fail signal (DA _ FT) to the DATA input/output bus (DATA).

Fig. 5 is a diagram showing an overview of the data processing section 120, and fig. 6 is a timing chart for explaining the operation of the data processing section 120. Referring to fig. 5 and 6, the data processing part 120 includes an internal control signal forming part 122, a light emission time control signal forming part 124, and a luminance control signal forming part 126.

The internal control signal forming section 122 includes a first SR latch (SRa), a first counter (122b), and a first arithmetic section (122 c). The first SR latch (SRa) outputs a logic high state after receiving an input activation signal (ON). The first counter (122b) is activated by an output signal of the first SR latch (SRa), and counts and outputs the number of pulses included in the clock signal (CLK).

The first arithmetic unit (122c) receives the input count result of the first counter (122b), and generates and outputs a short-circuit failure passing signal (SH _ EN) and an open-circuit failure passing signal (OP _ EN) when the count result is greater than the number of bits of emission data (DA _ OUT). In the illustrated embodiment, since the light emission data (DA _ OUT) is 10 bits, when the count result of the first counter 122b corresponds to 11, after the logic high state open fault passing signal (SH _ EN) is formed and output, the logic high state short fault passing signal (OP _ EN) is formed and output. As an embodiment, the short fault passing signal (SH _ EN) turns on the fifth switch SW5 short-circuited included in the short fault detection section 320 (see fig. 9), thereby outputting the short fault signal (SH _ FT) in which the short fault is detected as the fault signal (DA _ FT). In addition, the open fault passing signal (OP _ EN) turns on the sixth switch (SW6) included in the open fault detecting section 340 (see fig. 9) so that the open fault signal (OP _ FT) in which the open fault is detected is output as the fault signal (DA _ FT).

The first arithmetic part (122c) outputs the fault signal (DA _ FT) of the short-circuit fault signal (SH _ FT, see fig. 9) and the open-circuit fault signal (OP _ FT, see fig. 9) detected by the fault detection part 30 through the DATA input/output bus (DATA) to form and output the input/output control signal (DA _ IO) to the DATA input/output control part 110 during the time of outputting the short-circuit fault passing signal (SH _ EN) and the open-circuit fault passing signal (OP _ EN).

The first arithmetic unit (122c) outputs a short-circuit failure passing signal (SH _ EN) and an open-circuit failure passing signal (OP _ EN), and then forms and outputs an internal control signal forming unit stop Signal (STOPA) for deactivating the internal control signal forming unit 122. When the first counter 122b counts 13, an internal control signal stop Signal (STOPA) may be output and provided to the reset input of the first SR latch (SRa) to deactivate the first counter 122 b.

The luminance control signal forming section 126 includes a shift register, a register (126a), an and gate, and a third SR latch (SRc). And masking the clock signal (CLK) with an output signal of the gate third SR latch (SRc). If an activation signal (ON) of a logic high state is supplied to the SET input of the third SR latch (SRc), the third SR latch (SRc) outputs a logic high state, so the and gate outputs a SHIFT _ CLK signal, and the SHIFT register sequentially stores and outputs each bit (DA _ OUT) of the lighting data. Then, with the output control signal (DA _ IO) provided in a logic high state, the third SR latch (SRc) outputs a logic low state to mask the clock signal.

As shown in fig. 6, after the activation signal (ON) is supplied, the operation part (122c) included in the internal control signal forming part 122 counts pulses included in the clock by the total number of bits of the emission data (DA _ OUT) and then outputs the input/output control signal (DA _ IO), so that all bits of the emission data (DA _ OUT) are stored in the shift register.

The register 126a samples and outputs each bit output from the shift register as an internal control signal forming section stop Signal (STOPA). In the illustrated embodiment, the lighting data (DA _ OUT) is serial data of 10 bits in total, and the luminance control signal (DO [9:0]) formed and output by the luminance control signal forming section 126 is a parallel signal of 10 bits in total.

The emission time control signal forming section 124 includes a second SR latch (SRb), a second counter (124b), and a second arithmetic section (124 c). The second SR latch (SRb) outputs a logic high state by supplying the internal control signal forming part stop Signal (STOPA) to the SET input. The number of pulses included in the clock signal (CLK) is counted by the second SR latch (SRb) in which the second counter (124b) is activated to a logic high state, and is output to the second arithmetic section (124 c).

The second arithmetic unit (124c) receives the count result (CNTB [3:0]) from the second counter (124b) and the luminance control signal (DO [9:0]), and outputs a light emission time control signal (PWM) having a pulse width according to the value of the luminance control signal (DO [9:0 ]).

In one embodiment, when the value of the luminance control signal (DO [9:0]) is greater than or equal to the threshold value, the second operation part (124c) may form and output a light emitting time control signal (PWM) such that the light emitting device 40 emits light for a predetermined time. However, when the luminance control signal (DO [9:0]) is less than the threshold value, the second operation part (124c) may set the light emitting time to output the light emitting time control signal (PWM) so that the light emitting device 40 emits light in proportion to the value of the luminance control signal ([ 9:0]) DO. If the value of the supplied brightness control signal DO [9:0] is 0, the second arithmetic part (124c) outputs a light-emitting time signal (PWM) in a logic low state.

In the example shown in FIG. 6, the threshold value is 16 decimal, and the brightness control signal (DO [9:0]) is greater than or equal to the threshold value 16. The second operation part (124c) outputs a logic high state when the count result (CNTB [3:0]) of the second counter 124b is 1, and outputs a logic low state to form and output a light emitting time control signal (PWM) such that the light emitting device 40 emits light for a total of 14 clock periods when the count result (CNTB [3:0]) is 15.

In an example not shown, the example shown in fig. 6, the threshold value of which is 16 decimal, outputs a logic high state if the luminance control signal (DO 9: 0) is less than the threshold value 16 and when the count result (CNTB 3: 0) of the second counter 124b is 1, and outputs a logic low state to form and output the light emitting time control signal (PWM) when the count result (CNTB 3: 0) is a decimal value +1 of the luminance control signal (DO 9: 0). Accordingly, if the brightness control signal (DO [9:0]) is less than 16, the pulse width of the light emission time control signal (PWM) is proportional to the value of the brightness control signal (DO [9:0 ]).

If the count result (CNTB [3:0]) of the second counter (124b) reaches 15, a second arithmetic unit (124c) forms a light emission control signal forming unit stop Signal (STOPB) and outputs it to the RESET input of the second SR latch (SRb). Accordingly, the second SR latch (SRb) outputs a logic low, and the second counter (124b) is deactivated.

Fig. 7 is a diagram showing an outline of the light emission control unit 20. Referring to fig. 7, the light emission control section 20 includes a register string (210), a digital-to-analog converter 220, a driving circuit section 240, and a driving time control section 230.

The resistor string 210 includes a plurality of resistors connected in series between an upper limit Voltage (VREF) and a lower limit voltage (GND). The series-connected resistors divide and output a voltage difference between an upper limit Voltage (VREF) and a lower limit voltage (GND). A plurality of voltages (V0, V1.., V255) assigned and output by the register string 210 are supplied to the light emitting device 40 to determine a light emission level (gradation).

The digital-to-analog converter 210 receives an input luminance control signal (DO [9:0]), and outputs a gray-scale voltage (DAC _ OUT) corresponding to the luminance control signal (DO [9:0]) among a plurality of voltages (V0, V1.., V255) output from the register string. In one embodiment, the dac 210 divides and outputs a plurality of voltages (V0, V1.., V255) when a decimal value corresponding to the input brightness control signal (DO [9:0]) is 15 to 255. In contrast, when the decimal value corresponding to the brightness control signal ((DO [9:0]) is 0 to 14, V15 will be output to DAC _ OUT regardless of what value the brightness control signal (DO [9:0]) has in the corresponding range.

As shown in fig. 7, the output (DAC _ OUT) of the digital-to-analog converter 220 should be supplied to the control electrode of the light emitting device driving transistor (M1) to control conduction, which may be because the light emitting device driving transistor (M1) cannot be turned on at a voltage lower than V15. Accordingly, the lower limit voltage output from the digital-to-analog converter 220 may correspond to a voltage at which the light emitting device driving transistor (M1) included in the driving circuit part 240 is turned on.

The driving time control part 230 receives the supplied light emitting time control signal (PWM) and controls the turn-on of the third switch (SW3) and the fourth switch (SW4) for a time corresponding to the pulse width of the driving time control signal (PWM). As an embodiment, the driving time control part 230 blocks the third switch (SW3) and turns on the fourth switch (SW4) to supply the ground voltage to the control electrode of the light emitting device driving transistor (M1). Accordingly, the light emitting device driving transistor (M1) is blocked.

The driving time control part 240 turns on the third switch (SW3) and turns off the fourth switch (SW4) for a time corresponding to the pulse width of the driving time control signal PWM. As the fourth switch (SW4) is turned off and the third switch (SW3) is turned on, the output of the operational amplifier 242 is supplied to the control electrode of the light emitting device driving transistor (M1), and thus the light emitting device driving transistor (M1) is turned on.

In addition, the output signal (DAC _ OUT) of the digital-to-analog converter 220, which is provided as a non-inverting input of the operational amplifier 242, is copied as an inverting input. The replicated output signal (DAC _ OUT) is provided to one end of a current limiting resistor (R). Accordingly, an ILED ═ DAC _ OUT/R current flows through the light emitting device.

Fig. 8 is a graph showing a relationship between a current ILED flowing through the light emitting device according to the luminance control signal (DO [9:0]) and the light emitting time control signal (PWM). Referring to fig. 8, it can be confirmed that when the value corresponding to the brightness control signal (DO [9:0]) is greater than or equal to the threshold value, the current flowing through the light emitting device increases. When the light emitting device is a Light Emitting Diode (LED), the luminance of light emission is proportional to the current. Accordingly, it was confirmed that the brightness of the light emitted by the light emitting device was controlled according to the value of the brightness control signal (DO [9:0 ]).

In addition, it was confirmed that when the value of the luminance control signal (DO [9:0]) is less than the threshold value, the pulse width of the light emission time control signal (PWM) is varied according to the value of the luminance control signal (DO [9:0 ]).

Fig. 9 is a diagram showing an outline of the failure detection unit 30. The fault detection section 30 includes a short fault detection section 320 for detecting a short fault and an open fault detection section 340 for detecting an open fault.

The short-circuit fault detection section includes a comparator 322, a latch 324, a flip-flop 326, and a fifth switch (SW 5). The comparator 322 receives as one input a voltage of a node to which the light emission control unit 20 and the light emitting device 40 are connected, and receives as the other input a short-circuit Voltage (VSHORT), and the comparator 322 compares and outputs the voltage of the node to which the light emission control unit 20 and the light emitting device 40 are connected and the magnitude of the short-circuit Voltage (VSHORT). If the voltage of the node connected to the light emission control part 20 and the light emitting device 40 is greater than the short circuit Voltage (VSHORT), it may be determined that a short fault exists in the light emitting device 40.

The comparator 322 outputs a short-circuit fail signal (SH _ FT) corresponding to the comparison result to the latch 324, and the latch 324 latches and outputs the short-circuit fail signal (SH _ FT) as a light emission time control signal (PWM). The flip-flop 326 samples and outputs the short fault signal (SH _ FT) as a short fault pass signal (SH _ EN), and provides the short fault to the fifth switch (SW5) of the pass signal (SH _ EN) to output the short fault signal (SH _ FT) as a fault signal (DA _ FT).

The open fault detection section includes a comparator 342, a latch 344, a flip-flop 346, and a sixth switch (SW 6). The voltage of the node of the light emission control section 20 and the light emitting device 40 is connected as one input of the comparator 342, and the open circuit Voltage (VOPEN) is supplied as the other input. The comparator 342 compares and outputs the voltage of the node to which the light emission control unit 20 and the light emitting device 40 are connected and the magnitude of the open circuit Voltage (VOPEN). If the voltage of the node to which the light emission control part 20 and the light emitting device 40 are connected is lower than the open circuit Voltage (VOPEN), it may be determined that there is an open fault (open fault) in the light emitting device 40.

The latch 344 outputs an open fault signal (OP _ FT) corresponding to the comparison result to the latch 344, and the latch 344 latches and outputs the open fault signal (SH _ FT) as a light emitting time control signal (PWM). The flip-flop 346 samples and outputs the open fault signal (OP _ FT) as an open fault pass signal (OP _ EN), and supplies the open fault pass signal (OP _ EN) to the sixth switch (SW6) to output the open fault signal (SH _ FT) as a fault signal (DA _ FT).

The failure detection section 30 outputs a failure signal (DA _ FT) including a short-circuit failure signal (SH _ FT) and/or an open-circuit failure signal (OP _ FT). The fail signal (DA _ FT) is output to the DATA input/output bus (DATA) through the second switch (SW2, see fig. 4) of the DATA input/output control part 110 (see fig. 4) during the time when the input/output control signal (DA _ IO) is output.

Fig. 10 is a diagram showing an overview of a control signal (S _ SIG) provided to the LED backlight according to the present invention. Referring to fig. 10, a control signal (S _ SIG) is provided to the LED backlight section 1 to control the operation. In the illustrated embodiment, the LED backlight section performs a programming phase (DP) in which the emission data (DA _ OUT) is input to the data control section 10, a failure output phase (FP) in which the failure detection section 30 outputs a failure report (DA _ FT), and an Emission Phase (EP) in which the light emitting devices 40 emit light. The LED backlight may periodically repeatedly perform a programming phase (DP), a fail output phase (FP), and a light Emitting Phase (EP). In addition, the programming phase (DP) and the programming phase (DP) in which the fail output phase (FP) is quickly performed and the light Emitting Phase (EP) is performed for a long time can make the clock period in the light Emitting Phase (EP) larger than the fail output phase (FP).

Fig. 11 is a diagram of an LED backlight 1 configured in an active matrix form according to the present invention. Referring to fig. 11, a plurality of backlights 1 may be arranged in rows and columns. As an example, the same control signal (S _ SIG [1]) is supplied to the backlight units 1 arranged in the 1 st row, and the same control signal (S _ SIG [2]) is supplied to the backlight units 1 arranged in the same row as the same control signal (S _ SIG [2]) is supplied to the backlight units 1 arranged in the 2 nd row.

In addition, the first DATA signal (DATA [1]) is supplied to the backlight unit 1 arranged in the first column, and the same DATA signal is supplied to the backlight unit 1 arranged in the same column as the second DATA signal (DATA [2]) is supplied to the backlight unit 1 arranged in the second column.

With the backlight configured in this manner, after the program phase (DP) and the fail output phase (FP) of the first row end, the program phase (DP) and the fail output phase (FP) of the second row may start. That is, the program phase (DP) and the fail output phase (FP) of the next driving row after the program phase (DP) and the fail output phase (FP) of the previously driven row end may be performed.

While the invention has been described with reference to the embodiments shown in the drawings for the purpose of promoting an understanding thereof, it is to be understood that such embodiments are merely illustrative of and that various changes and equivalents may be made by those skilled in the art. Therefore, the true technical scope of the present invention should be determined by the appended claims.