阅读说明：本技术 使用光电标记对半导体器件进行裸片级唯一认证和序列化的方法 (Method for die-level unique authentication and serialization of semiconductor devices using optoelectronic tags ) 是由 H·吉姆·富尔福德 安东尼·舍皮斯 安东·德维利耶 于 2020-03-02 设计创作，主要内容包括：一种用于在裸片级标记半导体衬底以提供唯一认证和序列化的方法,该方法包括：使用基于掩模的光刻法将第一图案的光化辐射投射到该衬底上的光刻胶层上,该第一图案限定半导体器件结构；以及使用直写式投射将第二图案的光化辐射投射到该光刻胶层上,该第二图案限定具有唯一电气签名的唯一布线结构。(A method for marking a semiconductor substrate at a die level to provide unique authentication and serialization, the method comprising: projecting a first pattern of actinic radiation onto a photoresist layer on the substrate using mask-based photolithography, the first pattern defining a semiconductor device structure; and projecting a second pattern of actinic radiation onto the photoresist layer using direct write projection, the second pattern defining a unique wiring structure having a unique electrical signature.)

1. A method of marking a substrate, the method comprising:

forming a photoresist layer on a substrate;

projecting a first pattern of actinic radiation onto the photoresist layer using a mask-based lithography system, the first pattern defining a semiconductor device structure;

projecting a second pattern of actinic radiation onto the photoresist layer using a direct write projection system, the second pattern defining a unique wiring structure having a unique electrical signature;

developing the photoresist layer to generate a relief pattern; and

a unique wiring structure having the unique electrical signature is formed.

2. The method of claim 1, wherein the wiring structure is an electrical line.

3. The method of claim 1, further comprising varying the resistance of the unique routing structure between different dies by varying the shape of the unique routing structure.

4. The method of claim 1, wherein the shape of the unique routing structure is changed by changing at least one of a wire length, a wire width, a wire path, a number of wire turns, and a wire cross-sectional area.

5. The method of claim 1, wherein the routing structure is a matrix of conductive paths, wherein each conductive path has a different geometry to provide one of a plurality of resistance values.

6. The method of claim 1, wherein the electrical signature comprises a unique resistance value or capacitance value.

7. The method of claim 1, wherein the unique routing structure is located on the corresponding die at a location separate from die circuitry.

8. The method of claim 1, wherein placement of tiles on conductive paths is varied by coordinate location to define different graphical arrangements of the unique routing structures.

9. The method of claim 1, wherein the first pattern is projected after the second pattern is projected.

10. The method of claim 1, wherein the second pattern is projected after the first pattern is projected.

11. The method of claim 1, wherein the unique wiring structure represents a serial number or a date of manufacture, a chip specification, or which technology generation.

12. A method of marking a substrate, the method comprising:

forming a wiring level on a predetermined layer of an integrated circuit having a field effect transistor, the wiring level comprising a first conductive material forming an electrical connection with at least one other layer of the integrated circuit; and

forming a unique wiring structure having a unique electrical signature on a predetermined layer of the integrated circuit coplanar with the wiring level, the unique wiring structure defined by a structure of the first conductive material that is electrically separate from the wiring level, wherein the wiring level and the unique wiring structure are formed during the same metallization step.

13. The method of claim 12, wherein the routing level is patterned using a mask-based lithography system and the unique routing structure is patterned using a write-through projection system.

14. The method of claim 12, wherein the electrical signature comprises a unique resistance value or capacitance value.

15. The method of claim 12, wherein the shape of the unique routing structure is changed by changing at least one of a wire length, a wire width, a wire path, a number of wire turns, and a wire cross-sectional area.

16. A method of marking a substrate, the method comprising:

patterning a wiring level on a predetermined layer of the integrated circuit using a mask-based lithography system;

patterning a unique wiring structure having a unique electrical signature on a predetermined layer of the integrated circuit coplanar with the wiring level, the unique wiring structure patterned using a direct write projection system; and

the wiring level and the unique wiring structure are metallized simultaneously, the unique wiring structure being electrically separated from the wiring level.

17. A device with authentication, the device comprising:

a die formed from a semiconductor substrate and containing an integrated circuit, the die having a plurality of field effect transistors and a plurality of wiring levels, the plurality of wiring levels having been patterned using a mask-based lithography system;

a unique routing structure formed on a predetermined area of the die, the unique routing structure having been patterned using a direct write projection system, the unique routing structure having a unique electrical signature that identifies the die relative to other dies.

18. The device of claim 17, wherein the unique routing structure is a matrix of conductive paths, wherein each conductive path has a different geometry to provide one of a plurality of resistance values.

19. The device of claim 17, wherein the electrical signature comprises a unique resistance value or capacitance value.

Technical Field

The present application relates to semiconductor device unique tags for counterfeit control and unique electrical authentication. More particularly, the present application relates to a method for placing unique wiring structures at specific locations on a wafer of semiconductor devices using direct write lithography.

Description of the Related Art

The sale of counterfeit semiconductor devices is a global problem, with billions of dollars of losses each year to chip manufacturers. Chip manufacturers in the united states alone lose more than seven billion dollars per year. The pentagon estimated that 15% of all spare and replacement chips purchased by the pentagon were counterfeit. A disproportionate amount of problematic chips come from foreign countries and enter the supply chain without being discovered. Therefore, it is strongly desired to prevent the use of counterfeit semiconductor devices.

There are many challenges and aspects to solving the counterfeit chip problem. One of the basic capabilities to combat the sale of counterfeits is to be able to identify counterfeit devices and/or to identify genuine devices. Being able to accurately and reliably identify counterfeits is very useful for removing counterfeits from commerce. Furthermore, being able to verify a genuine device as compared to all devices on the market helps to quantify losses in the event of a violation of international trade laws. There are some conventional systems to verify the authenticity/functionality of semiconductors. For example, standards of industry associations (such as SEMI) attempt to encrypt lot numbers from trusted manufacturers. However, after the counterfeit device enters the open market, the integrity can hardly be verified.

Background

Disclosure of Invention

The techniques disclosed herein enable chip manufacturers to uniquely identify their devices at the device level to provide an authentication mechanism to combat existing counterfeit devices. The techniques disclosed herein provide systems and methods that enable unique optical sequencing at the die level for chip authentication and/or in conjunction with hardware level identification using existing or conventional semiconductor processing methods. Thus, economical and unique identification can be efficiently added to a semiconductor manufacturing process.

Further, the methods disclosed herein provide unique identifiers die-by-die at a process level across multiple wafers. Conventional serialization approaches do not provide such unique die-level labeling. More specifically, the marking herein is accomplished by using a direct write patterning system configured to provide unique processing die by die. Using conventional mask-based photolithography would be cost prohibitive, while the direct write system herein provides an economical marking solution.

In one embodiment, direct write lithography is used to place unique routing structures, such as arrays of conductive paths, at specific locations on a wafer die. In addition, a mask-based exposure is used to place the circuit pattern on the die. The exposure of the unique mark may occur before or after the mask-based exposure. The photoresist layer on the die is developed to create a relief pattern.

The shape of the wiring structure is changed by changing at least one of a line length, a line width, a line path, a number of line turns, and a line cross-sectional area, thereby providing a plurality of resistance values or capacitance values. The unique electrical value of the wiring structure along with the unique visual signature provides a dual electrical/graphical identifier.

In addition to optical serialization, the techniques described herein can also customize die-level circuit performance for unique electrical authentication. Unique die level circuit performance is achieved by using direct write patterning systems that enable unique processing on a die-by-die basis.

For clarity, the order of the different steps as described herein is presented. In general, these steps may be performed in any suitable order. In addition, although each of the various features, techniques, configurations, etc. herein may be discussed in different places of this disclosure, it is intended that each concept can be performed independently of each other or in combination with each other. Thus, the features of the present application can be implemented and viewed in many different ways.

This summary does not specify each embodiment and/or novel aspect of the application. Rather, this summary provides only a preliminary discussion of various embodiments and novel correspondences as compared to conventional techniques. Additional details and/or possible aspects of the disclosed embodiments are described in the detailed description section of the disclosure and the corresponding figures, as discussed further below.

Drawings

The present application will be better understood in view of the description, given in a non-limiting manner, in conjunction with the attached drawings, in which:

FIG. 1A is a schematic illustration of an exemplary pattern resulting from mask-based projection lithography applied to a set of wafers.

FIG. 1B is a schematic diagram of an exemplary pattern resulting from direct write lithography applied to a set of wafers.

Fig. 2A is a schematic diagram of a wiring pattern on a die.

Fig. 2B is a schematic diagram of a wiring pattern on a die.

Fig. 3 is a schematic diagram of an exemplary assignment of patterns resulting from the application of direct write lithography to a group of dies.

Fig. 4 is a schematic diagram of an exemplary cross-sectional view of a die-sized substrate segment having unique routing structures formed by a direct write identifier process and die circuitry formed by mask-based exposure.

Fig. 5 is a schematic diagram of a unique routing structure in the form of an array of conductive paths formed on a die.

Fig. 6 is a schematic diagram of a unique routing structure in the form of an array of conductive paths formed on a die.

Fig. 7 is a schematic diagram of a unique routing structure in the form of an array of conductive paths formed on a die.

Fig. 8 is a schematic diagram of a unique routing structure in the form of an array of conductive paths formed on a die.

Fig. 9 is a schematic diagram of a unique routing structure in the form of an array of conductive paths formed on a die.

Fig. 10 is a schematic diagram of a unique routing structure in the form of an array of conductive paths formed on a die.

Fig. 11 is a schematic diagram of a unique routing structure in the form of an array of conductive paths formed on a die.

Detailed Description

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the application, but does not denote that they are present in every embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present application. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

The techniques herein provide a method of uniquely identifying semiconductor chips at the die level across multiple wafers and lots using conventionally available semiconductor processing techniques. This includes the use of a direct write process that provides unique markings on a die-by-die basis.

The patterning of semiconductors typically involves the use of optical lithography systems. Such systems use, for example, Deep Ultraviolet (DUV) electromagnetic radiation to form high resolution relief image patterns in photosensitive resist materials. This relief image pattern is then used as a template for selective deposition, etching processes, and other microfabrication processes. The image realized in the photoresist is the projection of the main pattern onto the photomask. Photomasks are typically composed of chromium and quartz, which combine to form opaque and transparent regions that determine the propagation of source radiation at the mask interface. The photomask effectively defines the pattern of actinic radiation that reaches the film or layer of photosensitive material. This forms an implicit pattern within the photosensitive material by changing the solubility of the material where the light of the pattern interacts with the material. The latent pattern is developed with one or more development chemistries to produce a relief pattern on the substrate. Although mask-based photolithography is effective, one limitation of this process is that the construction of the photomask is not simple. The construction of a photomask is time consuming and relatively expensive. Furthermore, a given photomask pattern is fixed or the same for all wafers processed with the photomask. Fig. 1A shows a fixed pattern resulting from mask-based projection lithography applied to a set of wafers (e.g., wafer 1 and wafer 2).

Alternative maskless patterning techniques exist that employ direct-write techniques. Direct-write systems include electron beam lithography, plasma lithography, grating light valve lithography, and digital light projection patterning systems, among others. In operation, write-through lithography typically involves providing a design file to a write engine. The write engine directs the exposure process to define a pattern in the sensitive material based on the coordinate grid to drive the write head(s). One advantage of a direct write system is that the exposure pattern is not constrained by the physical medium (such as a photomask) but is generated digitally. Thus, each exposure may use a different design file or modification to a design file so that each individual exposure may be different from the previous and subsequent exposures. The difference may be small or large. Fig. 1B illustrates how direct write lithography can generate different exposure patterns (e.g., "a" and "B") for different wafers (e.g., wafer 1 and wafer 2). As used herein, each wafer and/or each die may contain unique information by altering the information in the digital domain prior to pattern exposure.

In one non-limiting embodiment, direct write lithography is used to place electrical identifiers at specific locations in the photoresist wafer-by-wafer or device-by-device. The placement of such unique marks can be accomplished as an implicit pattern in the photosensitive material in combination with conventional coating/developing processes. Since the wafer pattern data is stored in the digital domain, such unique write-through marks can be added without worrying about physical mask (photomask) overhead. The serialization can then be permanently transferred into the underlying layer using conventional wet or dry etch processes. In some embodiments, the underlying layer may be a conductive layer or a dielectric layer. In other embodiments, the underlying layer may be an oxide layer or a nitride layer.

The particular type of electrical identification employed in the tagging methods described herein may be selected by each user or system controller and/or may be selected according to the type of identification/authentication desired. Such unique indicia may be simple or may be informative. For example, a given unique identifier may be a simple serial number for each die. Alternatively, the unique identifier may include a date of manufacture, a chip specification, which generation technology, a source factory, a lot, etc.

The techniques described herein include a stand-alone approach that provides indicia of simple, unique circuit performance parameters that can be adjusted on a die-level basis. The tunable characteristics include resistivity and capacitance, among others. For example, a simple doped polysilicon resistor may adjust the resistance based on its length, as depicted in fig. 2A and 2B. A length of wire on the die of fig. 2A has a resistance of 15 ohms, while a length of wire on the die of fig. 2B has a resistance of 30 ohms. Alternatively, various metals may be used, so that no additional processing steps (other than direct write exposure) are required. For example, the direct-write pattern is filled as part of a dual damascene metallization process. During packaging, an electrically testable configuration may be made to easily read the resistance to determine whether the optical serialization given to a particular die matches its electrical characteristics. In another embodiment, the techniques herein are applied to security applications that require encrypted parity for encoding/decoding. In other words, simple, electrically adjustable circuit components can be used for the unique authentication.

In some embodiments, the unique indicia may include assigning or designing a particular region for the ID indicia. Fig. 3 shows a typical 2 x 2 die enumeration for reviewing the enumeration field for four dies. Note that most of this area is used for a particular circuit design. This may include placement of transistors, field effect transistors, logic, memory, wiring, etc. A smaller area within the die boundary is then designated or allocated for unique electrical routing. In this example, such area is a small box (ID001, ID 002, ID 003, ID 004) in the upper left corner of each die. The area designated for the unique identification mark may be less than one square millimeter.

The exposure of the unique wiring structure may occur before or after the mask-based exposure. For example, photolithographic exposure of a wafer is prepared in a coater-developer (track) tool by coating the wafer with a photoresist film. The wafer is then ready for transport to a scanner or stepper. The wafer may be moved to another tool or another module within the coater-developer before being transferred to the scanner to expose the unique mark by way of direct write exposure. Alternatively, a mask-based exposure is first performed, followed by a direct-write exposure (e.g., using a laser galvanometer projection device).

Fig. 4 illustrates how unique routing structures can be formed in one region of a given die by direct write lithographic exposure, while die circuitry can be formed in the remaining regions of the die. Note that the remaining circuitry may also be formed by direct write lithography, but for relatively small resolutions, mask-based lithography is typically required to ensure resolution and yield. The unique wiring structures herein need not be formed in advanced semiconductor node sizes and can have relaxed resolution within the capabilities of various laser galvanometer and other direct write projection techniques. Direct-write lithography and mask-based lithography may not be required, so long as a unique wiring structure with a unique electrical signature is formed in the die.

The unique routing structures herein may be simple or complex and may incorporate graphical design elements. In one embodiment, a set of conductive paths or a matrix of conductive paths may be used to create any combination of values to provide a unique electrical identifier. By way of non-limiting example, fig. 5 illustrates an array or matrix of conductive paths. For this example, six conductive paths are shown. Each conductive path is labeled bit 1, bit 2, bit 3, bit 4, bit 5, and bit 6. More or fewer conductive paths may be used depending on the number of different unique identifier combinations desired. These conductive paths may also be considered as numbers or values or value-character positions.

Each conductive path may have a corresponding value. The value may be a resistance/capacitance value. The possible multiple different resistance values in a given conductive path may be configured as desired. For example, the range of values may be 0 to 10, 0 to 500, or one thousand or more. As shown in fig. 6, the initial value may be zero. Note that no conductor is formed between bit 1 and ground (or other conductive target or part of the corresponding circuit). Thus, there is an infinite resistance, and the state may be a first value of a first code (e.g., code 00). Likewise, there is no metal to complete other conductive paths (e.g., bit 2 to ground). Each conductive path contact (bit 1, bit 2, …) may be connected to a multiplexer. All conductive paths are open due to the absence of poly or metal.

Referring now to FIG. 7, there is a conductive structure connecting the bit 1 contact to ground so that an electrical signal can be transmitted from the bit 1 contact to ground/target through the bit 1 conductive path. For example, relatively thin conductive lines are formed between the bit 1 contacts and ground, and the entire electrical structure is patterned by direct write lithography. With relatively thin wires, the resistance between the bit 1 contact and ground may be relatively high. The resistance value may be associated with a second value or code (e.g., code 01).

First conductive paths having different geometries may then be formed to produce different resistance values. Fig. 8 shows an example of generating different resistance values. In fig. 8, the direct-write pattern design defines a section of the conductive path to have a greater thickness. This may be represented as blocks along the wire. As the thickness of the segment increases, the resistivity decreases, resulting in a resistance value between bit 1 and ground that differs from the resistance value along the bit 1 conduction path (between bit 1 and ground) in fig. 7. The different resistance value may be a third value (e.g., code 03).

The conductive path resistance of each die or wafer can be further modified by directly writing a new geometry for each conductive path. For example, fig. 9 shows that for the length of this particular conductive path, a maximum of eight blocks may be added to the conductive path. The number of blocks may be increased by resizing the blocks and/or extending the conductive paths. By adding up to eight blocks to the conductor, the bit 1 conductive path can support ten different numbers/values/codes corresponding to different resistance values. For example, one digit indicates no conductive line, a second digit indicates only a conductive line, and third to tenth digits indicate a maximum of eight blocks. A multiplexer or other circuitry may be used to test the resistance value of each conductive path. With the addition of eight poly blocks, the resistance will be less (along the wire) than with 7 poly blocks. Also, in the case of a total of 6 blocks on the conductor, the resistance will be less than in the case of 7 blocks.

By using various geometries, the resistance of the wiring structure can be varied. For example, instead of adding blocks or segments on the wire, the width of the core wire or the core wire itself may be varied. In the example of the wiring structure of fig. 10, it is noted that the width of the wire (line) extending between the bit 1 contact and the ground is thicker than that of fig. 9. If a given design allows 10 different line widths per conductive path, and each line width can have 0 to 8 blocks (9 different resistances), then the bit 1 conductive path can support 91 different codes (including no lines). The total number of different codes (resistance values) per conductive path may have any number that is a different value from the geometric variation.

This same resistance/capacitance design process may be repeated for the next conductive path and each subsequent conductive path. Note that for capacitance measurement, the lower plate may be used. If each conductive path of fig. 10 can support 100 different values and there are six conductive paths, 1e12 unique values can result. Each conductive path/bit line may use multiplexer type circuitry to read resistance or other circuitry to read resistance (or capacitance).

In another embodiment, a unique electrical signature or unique resistance value from a unique electrical structure may be combined with an optical signature from a geometric shape. This combination may provide two-factor authentication, if desired. It will be appreciated that there are various geometries of the wiring structure, including placement of the blocks. Referring now to fig. 11 and the conductive path of bit 1, 5 of the 8 possible blocks are formed. From top to bottom, the blocks are placed at the 1 st, 3 rd, 5 th, 6 th, and 8 th positions. By placing the blocks in the 1 st to 5 th positions, the same resistance can be achieved. Although the resistances were the same, the visual placements were different. This visual difference can be used to form different optical/graphic patterns based on the wiring geometry. In the conductive path of bit 3, four blocks are placed at the 5 th to 8 th sites instead of the 1 st to 4 th sites, or even or odd sites, and so on. It will be appreciated that each conductive path may accommodate a different physical arrangement of a particular resistance value, as compared to open space, depending on the number of blocks. It is also noted that the block may be formed even when there is no wire between the contact and the target. For example, conductive path bits 2 and 5 have no wires between the contacts and the target, but still have the bump placed.

The physical arrangement of the blocks may be used as a graphical signature or pictogram through the choice of tunable block placement. The line width may also be used as part of the optically critical content. In other words, the blocks along the conductive path place pixels that can be used as images. The unique electrical value of the wiring structure can then be checked and the wiring structure can also be viewed through a microscope to identify a unique graphical signature. Thus, the wiring structure can be used as both a unique electrical identifier and a graphical/optical identifier. The optical digital pattern provides a second level of security.

The unique wiring structures or resistive structures herein may be built on any layer on a given chip. For example, the unique wiring structure may be placed on metal 01 or metal 10 or a top layer. If the unique structure is built on a lower layer, the via may extend over several layers. The unique structure may surround the active parallel plate. The unique structure may be electrically connected to the corresponding chip, or may be isolated from the chip and attached to a separate processor. The unique electrical identifier of each chip can be measured while the chips are packaged. For optical identifiers, some of the packaging may need to be removed to view the optical pattern. Multiplexers may be used to minimize the contacts/pins of the unique electrical pattern. Having a multiplexer device inside can help check each bit line independently. For example, there may be one input to the multiplexer and one output to the multiplexer. The multiplexer can then determine the clock line it reads.

In the preceding description, specific details have been set forth, such as specific geometries of the processing system and descriptions of various components and processes used therein. However, it should be understood that the techniques herein may be practiced in other embodiments that depart from these specific details, and that these details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. However, embodiments may be practiced without these specific details. Components having substantially the same functional configuration are denoted by like reference numerals, and thus any redundant description may be omitted.

Various technologies have been described as multiple independent operations to aid in understanding various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order of presentation. The operations described may be performed in a different order than the described embodiments. In additional embodiments, various additional operations may be performed and/or the operations described may be omitted.

As used herein, "substrate" or "target substrate" generally refers to an object being worked according to the present invention. The substrate may comprise any material portion or structure of a device, in particular a semiconductor or other electronic device, and may for example be a base substrate structure (such as a semiconductor wafer, a reticle), or a layer (such as a thin film) on or overlying the base substrate structure. Thus, the substrate is not limited to any particular base structure, underlying layer, or overlying layer, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may refer to a particular type of substrate, but this is for illustrative purposes only.

Those skilled in the art will also appreciate that many changes can be made in the operation of the above-described techniques while still achieving the same objectives. The scope of the present disclosure is intended to encompass such changes. Accordingly, the foregoing description of the embodiments is not intended to be limiting. Rather, any limitations to the embodiments are presented in the appended claims.