阅读说明：本技术 一种三维集成芯片 (Three-dimensional integrated chip ) 是由 任奇伟 左丰国 周骏 郭一欣 江喜平 于 2021-09-02 设计创作，主要内容包括：本发明提供一种三维集成芯片,其中三维集成芯片包括：第一可编程阵列组件,包括第一键合区域；第一存储阵列组件,包括第二键合区域；第二存储阵列组件,包括第三键合区域；其中,第一键合区域与第二键合区域键合连接,第二键合区域与第三键合区域键合连接,以将第一可编程阵列组件、第一存储阵列组件以及第二存储阵列组件键合。以此拓展第一可编程阵列组件的存储空间,并通过三维键合技术将第一可编程阵列组件、第一存储阵列组件以及第二存储阵列组件键合,降低互连距离,实现存储访问的高带宽、低功耗,解决现有技术中存在的存储墙问题。(The invention provides a three-dimensional integrated chip, wherein the three-dimensional integrated chip comprises: a first programmable array assembly including a first bonding region; a first memory array assembly including a second bonding region; a second storage array assembly including a third bonded region; the first bonding region is in bonding connection with the second bonding region, and the second bonding region is in bonding connection with the third bonding region, so that the first programmable array assembly, the first storage array assembly and the second storage array assembly are bonded. Therefore, the storage space of the first programmable array component is expanded, the first programmable array component, the first storage array component and the second storage array component are bonded through a three-dimensional bonding technology, the interconnection distance is reduced, high bandwidth and low power consumption of storage access are achieved, and the problem of a storage wall in the prior art is solved.)

1. A three-dimensional integrated chip, comprising:

a first programmable array assembly including a first bonding region;

a first memory array assembly including a second bonding region;

a second storage array assembly including a third bonded region;

wherein the first bonding region is in bonding connection with the second bonding region, and the second bonding region is in bonding connection with the third bonding region to bond the first programmable array assembly, the first memory array assembly, and the second memory array assembly.

2. The three-dimensional integrated chip of claim 1, wherein the first programmable array component comprises: an interface unit;

the first storage array assembly and/or the second storage array assembly comprises: the function unit is used for executing the function of the functional unit,

the functional unit is connected with the interface unit so as to realize the connection with an external chip through the interface unit.

3. The three-dimensional integrated chip of claim 2, wherein the first programmable array component comprises:

the selection unit is connected with the interface unit and the functional unit and selectively connects the functional unit of the first storage array assembly and/or the second storage array assembly to the interface unit in a time-sharing manner.

4. The three-dimensional integrated chip of claim 2,

the interface unit includes: a first interface unit and a second interface unit;

the first storage array assembly comprises: a first functional unit for performing a first function,

the second storage array assembly comprises: a second functional unit;

the first functional unit is connected with the first interface unit through the first bonding region and the second bonding region, and the second functional unit is connected with the second interface unit through the first bonding region, the second bonding region and the third bonding region.

5. The three-dimensional integrated chip of claim 3,

the interface unit includes: a third interface unit connected with the selection unit;

the first storage array assembly comprises: a third functional unit;

the second storage array assembly comprises: a fourth functional unit;

the third functional unit is connected with the selection unit through the first bonding region and the second bonding region, the fourth functional unit is connected with the selection unit through the first bonding region, the second bonding region and the third bonding region, and the selection unit selectively connects the third functional unit and/or the fourth functional unit with the third interface unit in a time-sharing manner.

6. The three-dimensional integrated chip according to claim 2 or 3,

the first programmable array assembly includes: the device comprises a fourth interface unit and a fifth functional unit, wherein the fifth functional unit is connected with the fourth interface unit.

7. The three-dimensional integrated chip of claim 1, wherein the first programmable array component comprises: a power supply unit;

the first programmable array component, the first storage array component and/or the second storage array component comprise functional units,

the functional unit is connected with the power supply unit so as to supply power to the functional unit through the power supply unit.

8. The three-dimensional integrated chip of claim 7, wherein the functional unit of the first programmable array module and the functional unit of the first storage array module or the functional unit of the second storage array module share the same power supply unit; or

The functional unit of the first programmable array module and the functional unit of the first storage array module or the functional unit of the second storage array module are powered by different power supply units.

9. The three-dimensional integrated chip according to claim 8, wherein the power supply unit comprises: a first power supply unit;

the first programmable array assembly includes: a first functional unit;

the first storage array assembly and/or the second storage array assembly comprises: a second functional unit;

the first functional unit is connected with the first power supply unit, the second functional unit is connected with the first power supply unit through the first bonding area and the second bonding area, or the second functional unit is connected with the first power supply unit through the first bonding area, the second bonding area and the third bonding area.

10. The three-dimensional integrated chip according to claim 8, wherein the power supply unit comprises: a second power supply unit and a third power supply unit;

the first programmable array assembly includes: a third functional unit;

the first storage array assembly and/or the second storage array assembly comprises: a fourth functional unit;

the third functional unit is connected with the second power supply unit, the fourth functional unit is connected with the third power supply unit through the first bonding area and the second bonding area, or the fourth functional unit is connected with the third power supply unit through the first bonding area, the second bonding area and the third bonding area.

11. The three-dimensional integrated chip of claim 1, further comprising:

a first functional array element located between the first programmable array element and the first memory array element and including a fourth bonding region in bonding connection with the first bonding region and the second bonding region to bond the first functional array element with the first programmable array element and the first memory array element;

wherein the first functional array component is used to repair a storage array of the first storage array component and/or the second storage array component.

12. The three-dimensional integrated chip of claim 11, wherein the first functional array component comprises: a repair unit;

the first storage array assembly and/or the second storage array assembly comprises: a storage array;

the storage array is connected with the repair unit so as to repair the storage array through the repair unit.

13. The three-dimensional integrated chip of claim 12,

the first storage array assembly comprises: a first storage array;

the second storage array assembly comprises: a second storage array;

the first storage array is connected with the repair unit through the second bonding area and the fourth bonding area; the second storage array is connected with the repair unit through the third bonding region, the second bonding region and the fourth bonding region.

14. The three-dimensional integrated chip of claim 1, further comprising:

a second functional array element comprising a fifth bonding region;

the second functional array component is positioned on one side of the first programmable array component, which is far away from the first storage array component, and the fifth bonding region is in bonding connection with the first bonding region;

the second functional array component is used to store and configure a configuration file for the first programmable array component.

15. The three-dimensional integrated chip of claim 14, further comprising:

a second programmable array assembly including a sixth bonding region;

the second programmable array component is located between the second functional array component and the first programmable array component, the sixth bonding region is in bonding connection with the first bonding region, and the sixth bonding region is in bonding connection with the fifth bonding region;

the second functional array component is used to store and configure a configuration file for the first programmable array component and/or the second programmable array component.

16. The three-dimensional integrated chip of claim 15, wherein the second functional array component comprises:

a nonvolatile memory cell;

a control unit connected to the nonvolatile memory unit;

the selection unit is connected with the control unit;

the first programmable array assembly and/or the second programmable array assembly comprises: a programmable array;

the programmable array is connected with the selection unit, and the selection unit selectively establishes a data channel between the programmable array and the control unit in a time-sharing manner.

17. The three-dimensional integrated chip of claim 16, wherein the first programmable array component comprises: a first programmable array;

the second programmable array assembly includes: a second programmable array;

the first programmable array is connected with the selection unit through the first bonding region, the sixth bonding region and the fifth bonding region; the second programmable array is connected with the selection unit through the sixth bonding region and the fifth bonding region.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a three-dimensional integrated chip.

Background

With the growing scale of data processing requirements, reconfigurable architectures based on traditional FPGAs/efgas face memory access challenges. The capacity and bandwidth of storage access of the reconfigurable unit are greatly increased, the storage capacity of a static storage array in the FPGA/eFPGA component cannot be met generally, then the storage access outside the FPGA/eFPGA component is switched, the interconnection bit width and the interconnection distance of the storage access outside the FPGA/eFPGA component are obviously inferior to those of the interconnection of the storage access inside the FPGA/eFPGA component, the storage access bandwidth is limited, and the power consumption cost is far greater than that of the storage access inside the FPGA/eFPGA component, so that a storage wall is formed.

Disclosure of Invention

The invention provides a three-dimensional integrated chip which can realize high bandwidth and low power consumption of storage access and solve the problem of a storage wall in the prior art.

In order to solve the technical problems, the invention provides a technical scheme that: there is provided a three-dimensional integrated chip comprising: a first programmable array assembly including a first bonding region; a first memory array assembly including a second bonding region; a second storage array assembly including a third bonded region; the first bonding region is in bonding connection with the second bonding region, and the second bonding region is in bonding connection with the third bonding region, so that the first programmable array assembly, the first storage array assembly and the second storage array assembly are bonded.

Wherein the first programmable array module comprises: an interface unit; the first storage array assembly and/or the second storage array assembly comprises: and the functional unit is connected with the interface unit so as to realize the connection with an external chip through the interface unit.

Wherein the first programmable array module comprises: the selection unit is connected with the interface unit and the functional unit and selectively connects the functional unit of the first storage array assembly and/or the second storage array assembly to the interface unit in a time-sharing manner.

Wherein, the interface unit includes: a first interface unit and a second interface unit; the first storage array assembly includes: a first functional unit, the second storage array assembly comprising: a second functional unit; the first functional unit is connected with the first interface unit through the first bonding area and the second bonding area, and the second functional unit is connected with the second interface unit through the first bonding area, the second bonding area and the third bonding area.

Wherein, the interface unit includes: the third interface unit is connected with the selection unit; the first storage array assembly includes: a third functional unit; the second storage array assembly includes: a fourth functional unit; the third functional unit is connected with the selection unit through the first bonding area and the second bonding area, the fourth functional unit is connected with the selection unit through the first bonding area, the second bonding area and the third bonding area, and the selection unit selectively connects the third functional unit and/or the fourth functional unit with the third interface unit in a time-sharing manner.

Wherein the first programmable array module comprises: the fourth interface unit and the fifth function unit, the fifth function unit connects the fourth interface unit.

Wherein the first programmable array module comprises: a power supply unit; the first programmable array assembly, the first storage array assembly and/or the second storage array assembly comprise a functional unit, and the functional unit is connected with the power supply unit so as to supply power to the functional unit through the power supply unit.

The functional unit of the first programmable array component and the functional unit of the first storage array component or the functional unit of the second storage array component share the same power supply unit for supplying power; or the functional unit of the first programmable array component and the functional unit of the first storage array component or the functional unit of the second storage array component are powered by different power supply units.

Wherein, the power supply unit includes: a first power supply unit; the first programmable array module includes: a first functional unit; the first storage array assembly and/or the second storage array assembly comprises: a second functional unit; the first functional unit is connected with the first power supply unit, the second functional unit is connected with the first power supply unit through the first bonding area and the second bonding area, or the second functional unit is connected with the first power supply unit through the first bonding area, the second bonding area and the third bonding area.

Wherein, the power supply unit includes: a second power supply unit and a third power supply unit; the first programmable array module includes: a third functional unit; the first storage array assembly and/or the second storage array assembly comprises: a fourth functional unit; the third functional unit is connected with the second power supply unit, the fourth functional unit is connected with the third power supply unit through the first bonding area and the second bonding area, or the fourth functional unit is connected with the third power supply unit through the first bonding area, the second bonding area and the third bonding area.

Wherein, three-dimensional integrated chip still includes: the first functional array assembly is positioned between the first programmable array assembly and the first storage array assembly and comprises a fourth bonding area, and the fourth bonding area is in bonding connection with the first bonding area and the second bonding area so as to bond the first functional array assembly with the first programmable array assembly and the first storage array assembly; the first functional array component is used for repairing the storage array of the first storage array component and/or the second storage array component.

Wherein the first functional array assembly comprises: a repair unit; the first storage array assembly and/or the second storage array assembly comprises: a storage array; the storage array is connected with the repair unit so as to repair the storage array through the repair unit.

Wherein the first storage array assembly comprises: a first storage array; the second storage array assembly includes: a second storage array; the first storage array is connected with the repair unit through the second bonding area and the fourth bonding area; the second memory array is connected with the repair unit through the third bonding area, the second bonding area and the fourth bonding area.

Wherein, three-dimensional integrated chip still includes: a second functional array element comprising a fifth bonding region; the second functional array component is positioned on one side of the first programmable array component, which is far away from the first storage array component, and the fifth bonding region is in bonding connection with the first bonding region; the second functional array component is used to store and configure the configuration file of the first programmable array component.

Wherein, three-dimensional integrated chip still includes: a second programmable array assembly including a sixth bonding region; the second programmable array component is positioned between the second functional array component and the first programmable array component, the sixth bonding region is in bonding connection with the first bonding region, and the sixth bonding region is in bonding connection with the fifth bonding region; the second functional array component is used to store and configure configuration files for the first programmable array component and/or the second programmable array component.

Wherein the second functional array assembly comprises: a nonvolatile memory cell; a control unit connected to the nonvolatile memory unit; the selection unit is connected with the control unit; the first programmable array module and/or the second programmable array module includes: a programmable array; the programmable array is connected with the selection unit, and the selection unit selectively establishes a data channel between the programmable array and the control unit in a time-sharing manner.

Wherein the first programmable array module comprises: a first programmable array; the second programmable array module includes: a second programmable array; the first programmable array is connected with the selection unit through the first bonding region, the sixth bonding region and the fifth bonding region; the second programmable array is connected with the selection unit through a sixth bonding area and a fifth bonding area.

The three-dimensional integrated chip of the invention has the beneficial effects that different from the situation of the prior art, the three-dimensional integrated chip of the invention comprises: a first programmable array assembly including a first bonding region; a first memory array assembly including a second bonding region; a second storage array assembly including a third bonded region; the first bonding region is in bonding connection with the second bonding region, and the second bonding region is in bonding connection with the third bonding region, so that the first programmable array assembly, the first storage array assembly and the second storage array assembly are bonded. Therefore, the storage space of the first programmable array component is expanded, the first programmable array component, the first storage array component and the second storage array component are bonded through a three-dimensional bonding technology, the interconnection distance is reduced, high bandwidth and low power consumption of storage access are achieved, and the problem of a storage wall in the prior art is solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIG. 1 is a schematic structural diagram of a three-dimensional integrated chip according to a first embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a three-dimensional integrated chip according to a second embodiment of the present invention;

FIGS. 3 a-3 c are schematic flow charts of the method for fabricating the three-dimensional integrated chip shown in FIG. 1;

FIG. 4 is a schematic structural diagram of a three-dimensional integrated chip according to a third embodiment of the present invention;

FIGS. 5 a-5 c are schematic flow charts of the method for fabricating the three-dimensional integrated chip shown in FIG. 4;

FIG. 6 is a diagram illustrating a first embodiment of a level shifter circuit;

FIG. 7 is a diagram illustrating a second embodiment of a level shifter circuit;

FIG. 8 is a schematic diagram of the fabrication of a connection structure at the outermost layer of a three-dimensional integrated chip;

FIG. 9 is a block diagram illustrating the cross-component transfer of functional units on a first storage array component and a second storage array component;

FIG. 10 is a block diagram of the cross-module power supply for functional units on the first storage array module and the second storage array module;

FIG. 11 is a schematic diagram of a cross-component repair of a storage array on a first storage array component and a second storage array component;

FIG. 12 is a schematic diagram of the interconnection of the programmable array cross-device on the first programmable array device with the control unit and the nonvolatile memory unit;

FIG. 13 is a schematic diagram of the interconnection of the programmable array cross-devices on the first programmable array device and the second programmable array device with the control unit and the nonvolatile memory unit.

Detailed Description

In the present application, the component may be at least one of a die (die or chip) and a wafer (wafer), but not limited thereto, and may be any alternative conceivable by those skilled in the art.

The wafer (wafer) is a silicon wafer used for manufacturing a silicon semiconductor circuit, and the chip or die (chip or die) is a silicon wafer obtained by dividing the wafer on which the semiconductor circuit is manufactured. The specific embodiments of the present application are described by taking a die as an example. For example: the programmable array component is a programmable array die.

With the growing scale of data processing requirements, reconfigurable architectures based on traditional FPGAs/efgas face memory access challenges. The capacity and bandwidth of the storage access of the reconfigurable unit are greatly increased, the storage capacity of a static storage array in an FPGA/eFPGA crystal grain can not be met generally, then the storage access outside the FPGA/eFPGA crystal grain is turned to, the interconnection bit width and the interconnection distance of the storage access outside the FPGA/eFPGA crystal grain are obviously inferior to the interconnection bit width and the interconnection distance in the FPGA/eFPGA crystal grain, the storage access bandwidth is limited, and the power consumption cost is far greater than that in the FPGA/eFPGA crystal grain, so that a storage wall is formed. In order to solve the problem, the three-dimensional integrated chip is provided, and the FPGA/eFPGA crystal grain and the storage crystal grain are connected in a bonding mode through three-dimensional heterogeneous integration bonding based on a three-dimensional heterogeneous integration technology, so that the storage access distance between the FPGA/eFPGA crystal grain and the storage crystal grain is effectively reduced, and the power consumption is reduced. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a three-dimensional integrated chip according to a first embodiment of the present invention. In this embodiment, in order to expand the memory access capability of the FPGA/effpga die, the FPGA/effpga die and the memory array die are bonded and connected. Specifically, the three-dimensional integrated chip includes: a programmable array die 1 (FPGA/effpga die) and a memory array die 2. The programmable array die 1 mainly comprises an FPGA/effpga array 11, which is reconfigured in a programmable manner into a general reconfigurable compute/process array capable of implementing various compute/process tasks.

A three-dimensional heterogeneous integrated bonding region 12 is designed within the programmable array die 1 for enabling high bandwidth interconnection with an adjacent layer die, such as the memory array die 2. The FPGA/effpga array 11 is dispersedly distributed at the vertical projection overlapping position of the physical position of the corresponding memory array die 2, and establishes high bandwidth interconnection through the three-dimensional heterogeneous integrated bonding structure 3, that is, establishes an internal high bandwidth local memory access interface (generally, each group has a bit width of several thousands to several tens of thousands, and the sum of the bit widths is several tens of thousands to several hundreds of thousands), so as to form a programmable memory array three-dimensional integrated chip with a dispersedly distributed memory access structure. The cross-region storage access between the programmable storage array three-dimensional integrated chips is realized by the dynamic resource scheduling of a reconfigurable routing network in the programmable array crystal grain 1, and an internal global storage access bus can also be assisted, and is designed on the programmable array crystal grain 1 or the storage array crystal grain 2 in a hard core IP mode.

Each FPGA/eFPGA array 11 or a plurality of FPGA/eFPGA arrays 11 are correspondingly designed with an FPGA/eFPGA configuration controller; the programming result of the FPGA/effpga array 11 is stored in a CRAM (Config RAM, configuration memory) in the programmable array die 1, and the feature that the power failure disappears needs to load an FPGA/effpga programming file from outside the device, and is handled by the FPGA/effpga configuration controller. The FPGA/eFPGA configuration controller is also responsible for the functions of boundary scanning of devices, online data observation and loading and the like. The FPGA/eFPGA configuration controller can support the function of dynamic partial reconfigurable so as to switch partial functions of the FPGA/eFPGA array 11 in the operation process of the system. For example, after a calculation/processing procedure is finished, the corresponding FPGA/effpga array 11 is dynamically reconfigured into the function of the next calculation/processing procedure, and the data of the previous calculation/processing procedure is inherited (part or all of the data is in the corresponding storage array), so as to implement the next calculation/processing procedure. The programmable array die 1 may also be designed with hardmac IP to provide higher computation/processing density, and the hardmac IP functions include, but are not limited to, multiplier-adder, multiplier, systolic processor, hash calculation unit, various encoder/decoders, various digital signal processors, and dedicated layer calculation unit for machine learning.

The memory array crystal grain 2 mainly comprises a memory array 21, and the memory array crystal grain 2 is in the category of but not limited to one or more of Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Flash memory, ferroelectric memory (FRAM), phase change memory (PRAM), magnetic memory (MRAM), and resistance change memory (RRAM). Further, the memory controller can be designed to include corresponding memory according to the memory type.

A three-dimensional heterogeneous integrated bonding area 22 is designed within the memory array die 2 for enabling high bandwidth interconnection with an adjacent layer die, such as the programmable array die 1. Specifically, the three-dimensional heterogeneous integrated bonding structure 3 connects the three-dimensional heterogeneous integrated bonding region 22 on the memory array die 2 and the three-dimensional heterogeneous integrated bonding region 12 on the programmable array die 1, so as to bond and connect the programmable array die 1 and the memory array die 2. The bonding connection is realized in a three-dimensional heterogeneous bonding connection mode, the three-dimensional heterogeneous bonding connection can realize the close connection of the programmable array crystal grains 1 and the storage array crystal grains 2, the storage access power consumption is reduced, and a storage wall is avoided. In an embodiment, the three-dimensional hetero-integrated bonded structure 3 may be a three-dimensional hetero-integrated bonding layer fabricated using a back end of line (BEOL).

Any external global memory access interface controller corresponding to the memory, such as an SRAM interface controller, a JEDEC-DRAM interface controller, a Flash interface controller, an AXI interface controller, and other custom interface protocol controllers, may be designed on the memory array die 2 for global memory access of the external device to the memory array 21. An external global memory access interface controller connects the external global access buses of all memory arrays 21 of the memory array die 2, including but not limited to NOC AXI AHB and the like, to enable external global memory access. The interconnection bit width of the external global memory access interface controller to the external global access bus of all the memory arrays 21 of the memory array die 2 need not be close to the sum of the internal local memory access bit widths of the three-dimensional heterogeneous integrated device (usually, tens of thousands to hundreds of thousands of bit widths), and can be realized by referring to the prior art bit width (tens of thousands to thousands) design, because only the input and result data of calculation/processing generally pass through the external global access bus, and the memory access amount is usually much smaller than the internal memory access amount (the internal memory access amount is the sum of the memory access amounts of several calculation/processing steps).

The cross-grain three-dimensional heterogeneous integrated connection of the storage array grain 2 does not pass through an IO circuit of the storage array grain 2 or the programmable array grain 1, and because the storage array grain 2 or the programmable array grain 1 is interconnected in a device, the distance is short, the load is small, and the driving, external level boosting (during output), external level reducing (during input), a tri-state controller, an ESD protection circuit, a surge protection circuit and the like provided by the IO circuit in the prior art are not needed. When the core voltages of the memory array crystal grain 2 and the programmable array crystal grain 1 are the same, metal interconnection of three-dimensional heterogeneous integration, namely metal layer interconnection across the crystal grains, is directly carried out.

Designing a three-dimensional heterogeneous integrated bonding region 22 on the memory array die 2, and designing a three-dimensional heterogeneous integrated bonding region 12 on the programmable array die 1, and arranging a three-dimensional heterogeneous integrated bonding structure 3 to interconnect the three-dimensional heterogeneous integrated bonding region 22 designed on the memory array die 2 and the three-dimensional heterogeneous integrated bonding region 12 designed on the programmable array die 1. Depending on design requirements, when the core voltages of the memory array die 2 and the programmable array die 1 are different, level shifting circuits and the like may also be included on the three-dimensional hetero-integrated bonding area 22 or the three-dimensional hetero-integrated bonding area 12, since no IO circuitry provides level shifting, enabling metal layer interconnection across the die. The inter-grain metal connection is directly established through three-dimensional heterogeneous integrated bonding without a physical IO circuit, physical and electrical parameters of the inter-grain metal connection follow the process characteristics of semiconductor manufacturing procedures, interconnection density and speed are close to those of intra-grain metal layer interconnection, storage access bandwidth is greatly improved, and power consumption is remarkably reduced.

Specifically, the interconnection between the crystal grains is realized through a three-dimensional heterogeneous integrated bonding mode, the distance is short, the load is small, the functions of a driving circuit, a variable IO voltage circuit, a three-state control circuit, an ESD protection circuit, a surge protection circuit and the like in the existing IO interconnection technology are not needed, and the circuits in the existing IO interconnection technology can be omitted.

In this embodiment, a programmable array die 1 and a memory array die 2 are bonded and combined into a three-dimensional integrated chip. The programmable array die 1 and the memory array die 2 can also be combined into a three-dimensional integrated chip by one-to-many, many-to-one or many-to-many bonding. In another embodiment, a plurality of programmable array dies 1 can also be combined with a plurality of memory array dies 2 in a bonding manner.

Specifically, as shown in fig. 2, a programmable array die a1, a programmable array die a2, a programmable array die A3, a memory array die B1, a memory array die B2, and a memory array die B3 are bonded. The programmable array crystal grain is symmetrical to the memory array crystal grain. Specifically, the programmable array die is bonded on one side of the line of symmetry and the memory array die is bonded on the other side of the line of symmetry.

Specifically, programmable array die a1 includes three-dimensional integrated bonding area a11, programmable array die a2 includes three-dimensional integrated bonding area a12, programmable array die A3 includes three-dimensional integrated bonding area a13, memory array die B1 includes three-dimensional integrated bonding area B11, memory array die B2 includes three-dimensional integrated bonding area B12, and memory array die B3 includes three-dimensional integrated bonding area B13. The three-dimensional integrated bonding structure C1 bonds the three-dimensional integrated bonding region A11 and the three-dimensional integrated bonding region A12, and further bonds and connects the programmable array crystal grain A1 with the programmable array crystal grain A2; the three-dimensional integrated bonding structure C2 bonds the three-dimensional integrated bonding region A12 and the three-dimensional integrated bonding region A13, and further bonds and connects the programmable array crystal grain A2 with the programmable array crystal grain A3; the three-dimensional integrated bonding structure C3 bonds the three-dimensional integrated bonding region A13 and the three-dimensional integrated bonding region B11, and further bonds and connects the programmable array crystal grain A3 with the memory array crystal grain B1; the three-dimensional integrated bonding structure C4 bonds the three-dimensional integrated bonding region B11 and the three-dimensional integrated bonding region B12, and further bonds and connects the memory array crystal grain B1 with the memory array crystal grain B2; the three-dimensional integrated bonding structure C5 bonds the three-dimensional integrated bonding region B12 and the three-dimensional integrated bonding region B13, and further bonds and connects the memory array die B2 and the memory array die B3.

And meanwhile, a plurality of layers of programmable array crystal grains are stacked to increase the density of a storage and calculation integrated system, enable more operation/processing arrays and simultaneously share and fully release the advantages of high-bandwidth interconnection of three-dimensional heterogeneous integration.

And meanwhile, a plurality of layers of programmable array crystal grains are stacked to increase the storage density of a storage and computation integrated system, enable the operation/processing array to schedule a larger storage space and release the high-bandwidth interconnection advantage of three-dimensional heterogeneous integration in a concurrent scheduling mode.

In another embodiment, multiple layers of memory array dies and multiple layers of programmable array dies can also be arranged in spaced-apart bonding. That is, at least one layer of programmable array crystal grain is arranged between every two layers of storage array crystal grains; or at least one layer of memory array crystal grains is arranged between every two layers of programmable array crystal grains to improve the interconnection density of the memory array and the programmable array and reduce the interconnection distance, and the method is not limited specifically.

The present application further provides a method for manufacturing a three-dimensional integrated chip, as shown in fig. 3a to 3c, which are schematic flow diagrams of the method for manufacturing a three-dimensional integrated chip shown in fig. 1. Specifically, as shown in fig. 3a, the programmable array die 1 may be a copper metal process chip, and the memory array die 2 may be a copper or aluminum metal process chip. The programmable array die 1 includes a substrate 13 and a top metal layer 14, and the memory array die 2 includes a substrate 23 and a top metal layer 24. Next, as shown in fig. 3b, a three-dimensional heterogeneous integrated bonding region 12 connected to the top metal layer 14 is designed and fabricated on the programmable array die 1, and specifically, the three-dimensional heterogeneous integrated bonding region 12 has bonding points. Designing and manufacturing a three-dimensional heterogeneous integrated bonding region 22 corresponding to the position of the three-dimensional heterogeneous integrated bonding region 12 and connected with the top metal layer 24 on the memory array die 2, wherein the three-dimensional heterogeneous integrated bonding region 22 is provided with bonding points. Next, as shown in fig. 3c, the programmable array die 1 is turned over, so that the three-dimensional heterogeneous integrated bonding region 12 is aligned and attached to the three-dimensional heterogeneous integrated bonding region 22, thereby realizing three-dimensional heterogeneous integrated interconnection between the programmable array die 1 and the memory array die 2.

As shown in fig. 3c, after the three-dimensional heterogeneous integration interconnection of the programmable array die 1 and the memory array die 2 is achieved, the substrate 13 of the programmable array die 1 and/or the substrate 23 of the programmable array die 1 may be further thinned. In another embodiment, external connection signals in the device can be connected to the Bump or bonding PAD (PAD) by thinning the substrate and the active Layer (also called a wafer Layer, which refers to a Layer of a growing transistor (device) in a chip) through a TSV (through silicon via) process, establishing a metal Layer inside a crystal grain and connecting the metal Layer to the metal outside the substrate, and connecting external connection signals in the device to the outermost Layer interface (bonding interface, PAD/Bump leading-out interface) in combination with a back end of line (BEOL), such as RDL (Redistribution Layer). The three-dimensional heterogeneous integrated interconnection is a metal connection directly established between crystal grains, physical and electrical parameters of the three-dimensional heterogeneous integrated interconnection follow the process characteristics of semiconductor manufacturing procedures, the three-dimensional heterogeneous integrated interconnection is very close to the interconnection of metal layers in the crystal grains, compared with the cross-crystal grain interconnection in the prior art, the interconnection density (bandwidth) is greatly improved, and the interconnection power consumption is reduced.

Fig. 4 is a schematic structural diagram of a three-dimensional integrated chip according to a third embodiment of the present invention. Specifically, the three-dimensional integrated chip shown in this embodiment includes a first programmable array die 41, a first memory array die 42, and a second memory array die 43.

Wherein the first programmable array die 41 includes a first bonding area 411, the first memory array die 42 includes a second bonding area 421, and the second memory array die 43 includes a third bonding area 431.

Wherein the first bonding area 411 is in bonding connection with the second bonding area 421, and the second bonding area 421 is in bonding connection with the third bonding area 431, so as to bond the first programmable array die 41, the first memory array die 42, and the second memory array die 43.

The invention also provides a method for preparing the three-dimensional integrated chip shown in fig. 4, which is specifically shown in fig. 5 a-5 c. Specifically, as shown in fig. 5a, where M is a structure of a first memory array die 42 and a second memory array die 43 after bonding, the bonding method is shown in fig. 3a to 3c, and is not repeated herein. The difference is that the bottom metal layer 51 is prepared on the side of the first memory array die 42 away from the second memory array die 43, and the bottom metal layer 51 is connected to the bonding structure between the first memory array die 42 and the second memory array die 43 through the connection hole 52. A first programmable array die 41 is provided that includes a top metal layer 53. As shown in fig. 5b, a second bonding region 54 is prepared, which is connected to the underlying metal layer 51. A first bonding area 55 is provided on the first programmable array die 41 and is connected to the top metal layer 53. As shown in fig. 5c, the first programmable array die 41 is flipped over so that the second bonding region 54 and the first bonding region 55 are bonded together, thereby achieving bonding connection of the first programmable array die 41, the first memory array die 42 and the second memory array die 43.

In one embodiment, the internal signals of the two chips can be directly interconnected if the memory array die and the programmable array die core are at the same voltage. Logic level shifting circuitry may be designed if the core voltages of the memory array die and the programmable array die are different. Logic level shifting circuitry may be designed on the memory array die, and may also be located on the programmable array die, typically on or near the three-dimensional heterogeneous integrated bonding area. The level conversion circuit can also be transferred to the programmable array crystal grain in a trans-crystal mode by combining a three-dimensional heterogeneous integrated bonding method.

Fig. 6 is a schematic structural diagram of a logic level shifting circuit according to a first embodiment of the present invention. Specifically, in this embodiment, the level shifter circuit is designed on the programmable array die. Specifically, the core voltage VINT _ memory _ die and the ground voltage VSS of the memory array die are connected to the programmable array die to provide a voltage reference for the level shifter 02. Signals from the programmable array die to the memory array die are interconnected through the three-dimensional heterogeneous integrated structure 6. Specifically, interconnect signals from the programmable array die to the memory array die pass through buffer 01, level shifter 01, buffer 02, level shifter 02 and buffer 03 on the programmable array die, through the three-dimensional heterogeneous integrated structure 6, across the die to connect to buffer 04 on the memory array die, and into the interconnect range of level VINT _ memory _ die of the memory array die. Wherein, the buffers can be eliminated completely to simplify the structure of the level shift circuit.

Fig. 7 is a schematic structural diagram of a logic level shifting circuit according to a second embodiment of the present invention. Specifically, in the present embodiment, the level shifter circuit is designed on the memory array die. Specifically, the core voltage VINT _ FPGA _ die and the ground voltage VSS of the programmable array die are coupled to the memory array die to provide a voltage reference for the level shifter 03. Signals interconnecting the memory array die to the programmable array die are provided through the three-dimensional heterogeneous integrated structure 7. Specifically, the interconnection signal from the memory array die to the programmable array die is sent from the programmable array die, and enters the interconnection range of the level VINT _ memory _ die of the memory array die through the buffer 05, the three-dimensional heterogeneous integrated structure 7, the buffer 06 on the memory array die, the level shifter 03, the buffer 07, the level shifter 04, and the buffer 08. Wherein, the buffers can be eliminated completely to simplify the structure of the level shift circuit.

Referring to fig. 8, which is a schematic structural diagram of a fourth embodiment of the three-dimensional integrated chip of the present invention, in the present embodiment, cross-die high-density interconnection of internal metal layers can be led out through an outermost interface to be used as a PAD, so as to form an interface for interconnection of other chips. Specifically, compared with the embodiment shown in fig. 5c, the embodiment is different in that a metal Layer 57 is disposed on the outer side of the first programmable array die 41, the metal Layer 57 is connected to the top metal Layer 55 through a connection hole 56, the substrate on the outer side of the metal Layer 57 is thinned, the TSV penetrates through the thinned substrate, the metal Layer 57 is interconnected with a connection structure 58 prepared on the surface of the metal Layer 57, the connection structure 58 is located on an outermost interface (a bonding interface, a PAD/Bump leading-out interface) of the three-dimensional integrated chip, such as RDL (Redistribution Layer), external connection signals in the device are led out to the Bump or a bonding PAD, and external connection signals in any metal Layer in the stacked die in the three-dimensional integrated chip are led out to an external pin (PAD/Bump) of the outermost interface. It should be noted that, when the external connection of the internal metal layers is established through the thinned substrate and the active layer by the TSV, the active circuits in the active layer of the first programmable array die 41 need to be avoided. The design and manufacture of the connection structure 58 leading out of the chip can realize that the storage array crystal grains in the three-dimensional heterogeneous integrated three-dimensional integrated chip are led out uniformly through the three-dimensional heterogeneous integrated bonding structure on the first programmable array crystal grain 41 and the connection structure 58 so as to realize the connection with an external functional chip.

In the three-dimensional heterogeneous integrated reconfigurable storage and computation integrated framework, the device internal interconnection among crystal grains is not needed to pass through an IO interface. The three-dimensional heterogeneous integrated device needs to lead out an external interface unit, needs to use the external interface unit, and provides functions of driving, external level boosting (during output), external level reducing (during input), a tri-state controller, an ESD protection circuit, a surge protection circuit and the like. Each layer in the three-dimensional heterogeneous integrated device may generate the need of leading out an interface unit (such as a conventional leading-out function and a dft (design For test) function, etc.), and the interface unit which needs to be led out on all the dies needs to be led out from the outermost layer interface of the top die by combining the three-dimensional heterogeneous integration technology. Different from the existing IO leading-out technology, the method combines a three-dimensional heterogeneous integration technology to transfer the IO circuit needed on the leading-out crystal grain across the crystal grains. It is also possible to time-multiplex functional units that allow time-shared operation for certain pull-out requirements, especially application requirements. For example, in the structure shown in fig. 4, an interface unit may be disposed on the first programmable array die, a functional unit may be disposed on the first storage array die and/or the second storage array die, the functional unit is connected to the interface unit, the interface unit is externally led out signals, and the signals reach the outermost interface of the first programmable array die 41 through three-dimensional heterogeneous integration and cross-die interconnection, so as to implement connection with an external chip. Specifically, the through port is arranged by using the TSV process, so that the interface unit is connected with an external chip and the like through the through port, and the functions of the three-dimensional integrated chip are expanded.

Referring specifically to fig. 9, the first programmable array die 91 includes an interface unit, which in one embodiment includes a first interface unit 911 and a second interface unit 912. The first memory array die 92 includes a first functional unit connected to a first interface unit 911 of the first programmable array die 91 through a first bonding region and a second bonding region, and further, the first interface unit 911 is connected to the through port 921. The second memory array die includes a second functional unit, the second functional unit is connected to the second interface unit 912 through the first bonding region, the second bonding region and the third bonding region, and further, the second interface unit 912 is connected to the through port 922.

In another embodiment, the first programmable array die 91 includes a select unit 914. The interface unit includes a third interface unit 913, the third interface unit 913 is connected to the selecting unit 914, and further, the third interface unit 913 is connected to the conducting port 923. In this embodiment, the first memory array die 92 includes a third functional unit; the third functional unit is connected with the selection unit 914 through the first bonding region and the second bonding region. The second memory array die 93 includes a fourth functional unit; the fourth functional unit is connected to the selection unit 914 through the first bonding region, the second bonding region and the third bonding region. Specifically, the selection unit 914 may be a multiplexer, and the selection unit 914 selectively connects the third functional unit and/or the fourth functional unit with the third interface unit 913 in a time-sharing manner. Therefore, external lead-out signals of the third functional unit and the fourth functional unit are expanded, the third functional unit and the fourth functional unit are connected to the metal layer inside the first programmable array crystal grain 91 in a cross-crystal mode, IO signal conversion is achieved through the third interface unit 913 in the first programmable array crystal grain 91 through the multiplexing design of the selection unit 914, and the conduction port 923 is multiplexed and connected to an external pin of the three-dimensional integrated chip. The functional units of the first programmable array die 91, the first memory array die 92 and the second memory array die 93 are routed to and from the outside, and independently of the specific functions of the functional units, the functional units may vary with the functional variations of the die, so the functions of the first programmable array die 91, the first memory array die 92 and the second memory array die 93 may be any combination of memory arrays and/or programmable arrays.

In another embodiment, the first programmable array die 91 includes: a fourth interface unit 915 and a fifth function unit 916, wherein the fifth function unit 916 is connected to the fourth interface unit 915, and further, the fourth interface unit 915 is connected to the conducting port 924.

In this embodiment, a fifth functional unit 916 is designed in the first programmable array die 91, such as FPGA/effpga die, and it needs to be led out from the outermost interface (bonding interface, PAD/Bump lead-out interface) of the first programmable array die 91; the outbound signal from the fifth functional unit 916 is interconnected to the fourth interface unit 915 on the first programmable array die 91 via the first programmable array die 91 internal metal layer connections. The externally led signals of the fourth interface unit 915 are interconnected to the outermost interface through the internal metal layer of the first programmable array die 91 and the TSV penetrating through the active layer and the thinned substrate of the first programmable array die 91, so as to realize the externally led signals of the fifth function unit 916 of the first programmable array die 91.

A first functional unit is designed in the first memory array die 92, which needs to be brought out from the outermost interface (bonding interface, PAD/Bump brought-out interface) of the three-dimensional heterogeneous integrated device. Specifically, the first functional unit's outgoing signal is led out from the metal layer inside the first memory array die 92, and is interconnected to the first programmable array die 91 top metal layer through TSVs that penetrate through the active layer and the thinned substrate of the first memory array die 92 and the three-dimensional heterogeneous integrated bonding structures (i.e., the first bonding region, the second bonding region) of the first programmable array die 91 and the first memory array die 92. The outgoing signal from the first functional unit is interconnected to a first interface unit 911 on the first programmable array die 91 at a top metal layer of the first programmable array die 91 through an internal metal layer of the first programmable array die 91. The externally-led signals of the first interface unit 911 are interconnected to the outermost interface through the metal layer inside the first programmable array die 91 and the TSV penetrating through the active layer and the thinned substrate of the first programmable array die 91, so as to realize the external leading of the first functional unit on the first memory array die 92.

A second functional unit is designed in the second memory array die 93, which needs to be brought out from the outermost interface (bonding interface, PAD/Bump brought-out interface) of the three-dimensional heterogeneous integrated device. Specifically, the lead-out signal of the second functional unit is connected through the internal metal layer of the second memory array die 93, and is interconnected to the top metal layer of the second memory array die 93. The outgoing signal of the second functional unit is interconnected to the top metal layer of the first memory array die 92 through the three-dimensional heterogeneous integrated bonding structures (i.e., the second bonding region and the third bonding region) of the second memory array die 93 and the first memory array die 92 at the top metal layer of the second memory array die 93. The outgoing signal of the second functional unit is connected to the top metal layer of the first memory array die 92 at the metal layer inside the first memory array die 92 through the metal layer inside the first memory array die 92. The second functional unit's outgoing signal is interconnected to the first programmable array die 91 top metal layer at the first memory array die 92 top metal layer by TSVs that extend through the first memory array die 92 active layer and the thinned substrate, and the three-dimensional heterogeneous integrated bonding structures (i.e., first bonding regions, second bonding regions) of the first programmable array die 91 and the first memory array die 92. The outgoing signal from the second functional unit is interconnected to a second interface unit 912 on the first programmable array die 91 at the top metal layer of the first programmable array die 91 through the internal metal layer of the first programmable array die 91. The externally-led signals of the second interface unit 912 are interconnected to the outermost interface through the internal metal layer of the first programmable array die 91 and the TSV penetrating through the active layer and the thinned substrate of the first programmable array die 91, so as to realize the externally-led of the second functional unit on the second memory array die 93.

A third functional unit is designed in the first memory array die 92, and a fourth functional unit is designed in the second memory array die 93, which need to be led out from the outermost layer interface (bonding interface, PAD/Bump lead-out interface) of the three-dimensional heterogeneous integrated device. In the present embodiment, the externally-extracted signals of the third functional unit of the first memory array die 92 and the fourth functional unit of the second memory array die 93 are time-sharing operation signals allowed by application requirements. A selection unit 914, such as a multiplexer, is configured on the first programmable array die 91, and the selection unit 914 may time-share and multiplex the third interface unit 913 to the third functional unit of the first memory array die 92 or the fourth functional unit of the second memory array die 93.

The third functional unit and the fourth functional unit are brought out by the method of bringing out the first functional unit and the second functional unit and connected to the selection unit 914. the selection unit 914 selects in time division the third functional unit and the fourth functional unit to be switched to the third interface unit 913 on the first programmable array die 91. Specifically, the selection output signal of the selection unit 914 is interconnected to the third interface unit 913 through the internal metal layer of the first programmable array die 91; the externally-led signals of the third interface unit 913 are interconnected to the outermost interface through the internal metal layer of the first programmable array die 91 and the TSV penetrating through the active layer and the thinned substrate of the first programmable array die 91, so as to realize the time-division multiplexing external leading-out of the third functional unit and the fourth functional unit.

In this example, the intra-die connection of the functional unit and the interface unit, and the externally-led signal of the interface unit are described, and the interface unit is an IO circuit. In the embodiment, the functional unit passes through various three-dimensional heterogeneous integrated bonding interfaces, the active layer and the substrate in various forms. The flexible combination of the methods can easily realize the external extraction and the time-sharing multiplexing external extraction of the three-dimensional heterogeneous integrated device with any number of layers, different crystal grain layers and three-dimensional heterogeneous integrated bonding interface types, and any combination and/or any number of crystal circle layers.

Fig. 10 is a schematic diagram of a power network structure of the three-dimensional integrated chip shown in fig. 4. Specifically, in this embodiment, the first programmable array die 91 includes a power supply unit; the first programmable array die 91, the first memory array die 92 and/or the second memory array die 93 include functional units, and the functional units are connected to the power supply unit to supply power to the functional units through the power supply unit. Specifically, if the power supply unit is connected to the power supply device, the power supply device may supply power to the function unit through the power supply unit.

In one embodiment, the functional units of the first programmable array die 91 and the functional units of the first memory array die 92 or the functional units of the second memory array die 93 share the same power supply unit. Specifically, if the core voltage of the functional unit of the first programmable array die 91 is the same as the core voltage of the functional unit of the first storage array die 92 or the core voltage of the functional unit of the second storage array die 93, the functional unit of the first programmable array die 91 and the functional unit of the first storage array die 92 or the functional unit of the second storage array die 93 share the same power supply unit for supplying power.

As shown particularly in fig. 10, if the core voltage of the first programmable array die 91 is the same as the core voltage of the first memory array die 92 or the second memory array die 93, the same core voltage supply network may be shared across the dies.

Specifically, the power supply unit includes: the first power supply unit 901, the first programmable array die 91 includes a first functional unit, and the first functional unit is connected to the first power supply unit 901. The first memory array die 92 and/or the second memory array die 93 include: a second functional unit. The second functional unit on the first memory array die 92 is connected to the first power supply unit 901 through the first bonding region and the second bonding region; the second functional unit on the second memory array die 93 is connected to the first power supply unit 901 through the first bonding region, the second bonding region and the third bonding region. When the first power supply unit 901 is connected to the power supply device, the power supply device supplies power to the first functional unit and the second functional unit through the first power supply unit 901.

In another embodiment, the functional units of the first programmable array die 91 and the functional units of the first memory array die 92 or the functional units of the second memory array die 93 are powered by different power supply units. Specifically, if the voltage of the functional unit of the first programmable array die 91 is different from the voltage of the functional unit of the first storage array die 92 or the voltage of the functional unit of the second storage array die 93, the functional unit of the first programmable array die 91 and the functional unit of the first storage array die 92 or the functional unit of the second storage array die 93 are powered by different power supply units.

As shown in fig. 10, if the core voltages of the first programmable array die 91 and the first memory array die 92 or the second memory array die 93 are different, two different core voltage supply networks may be established to respectively provide different core voltages to the first programmable array die 91 and the first memory array die 92 and/or the second memory array die 93.

Specifically, the power supply unit includes: a second power supply unit 902 and a third power supply unit 903. The first programmable array die 91 includes a third functional unit, which is connected to the second power unit 902.

The first memory array die 92 and/or the second memory array die 93 include a fourth functional unit, the fourth functional unit on the first memory array die 92 is connected to the third power supply unit 903 through the first bonding region and the second bonding region, and the fourth functional unit on the second memory array die 93 is connected to the third power supply unit 903 through the first bonding region, the second bonding region and the third bonding region. When the second power supply unit 902 is connected to the power supply device, the power supply device supplies power to the third functional unit through the second power supply unit 902. When the third power supply unit 903 is connected to a power supply device, the power supply device supplies power to the fourth functional unit through the third power supply unit 903.

As shown in fig. 10, in this embodiment, an IO circuit of the first storage array die 92 and an IO circuit of the second storage array die 93 may be further led out to be connected to an IO circuit (not shown) of the first programmable array die 91, a fourth power supply unit 904 is disposed on the first programmable array die 91, and when the fourth power supply unit 904 is connected to a power supply device, the power supply device supplies power to the IO circuit of the first programmable array die 91, the IO circuit of the first storage array die 92, and the IO circuit of the second storage array die 93 through the fourth power supply unit 904, so that power supply to the IO circuit of the entire three-dimensional integrated chip may be achieved. Specifically, the memory array die is not limited to two layers, and the memory array die can be expanded to three layers, four layers and the like, and is not particularly limited, and specific memory requirements of the device are taken as reference. Similarly, the programmable array die can be expanded to multiple layers to increase storage density of a storage-computation integrated system, and enable the computation/processing array to schedule larger storage space and release the advantages of high-bandwidth interconnection of three-dimensional heterogeneous integration in a concurrent scheduling manner.

Physical characteristics of the storage array on the storage array crystal grain and the programmable array on the programmable array crystal grain are regularly distributed and distributed, the redundant module can be designed, when part of array units fail due to production and manufacturing defects, the failed module is bypassed, and the nearby redundant module is replaced, so that repair is realized, and the production yield of the device is improved.

In particular, redundant modules often require the design of high density local interconnects. The principle behind designing a redundant module is to control the pitch of the local high density interconnects as short as possible, with the physical location near the repair area.

In the three-dimensional heterogeneous integrated device, besides the 'physical proximity' of the active layer in the crystal grain in the prior art, the 'physical proximity' of the overlapped region of the vertical projection position of the crystal grain is also created, because the metal connection between the crystal grains is directly established in the crystal grain three-dimensional heterogeneous integrated local structure of the same process, the physical and electrical parameters of the metal connection follow the process characteristics of the semiconductor manufacture process and are very close to the density and the process parameters of the interconnection in the crystal grain.

Combining three-dimensional heterogeneous integration, the repair circuit of the local structure of the three-dimensional heterogeneous integrated device of the multilayer storage array crystal grains and the programmable array crystal grains is transferred from 'physical proximity' areas dispersed in the crystal grains to a 'physical proximity' area of the three-dimensional heterogeneous integration on a special repair crystal grain in a cross-crystal grain concentration mode, and a repair extension framework of the three-dimensional heterogeneous integrated device is formed. The method is specially used for repairing the resources to be repaired on the crystal grains, can adapt to the yield change of the local structures of the three-dimensional heterogeneous integrated devices of the multilayer storage array crystal grains and the programmable array crystal grains, and does not need to modify the designs of the storage array crystal grains and the programmable array crystal grains due to the yield target change. And designing a cross-region global bus and a centralized test circuit by utilizing the residual resources of the special repair crystal grains and combining the cross-crystal grain high-density interconnection between the vertical projection overlapping region arrays in the three-dimensional heterogeneous integrated device local structures of the multilayer storage array crystal grains and the programmable array crystal grains. The functional density of the memory array crystal grains and the programmable array crystal grains can be increased; further reducing the physical distance between the repair circuit and the repaired array; an implementation framework with adjustable yield and auxiliary functions is provided; the advantages of the three-dimensional heterogeneous integration technology are fully released, and particularly shown in figure 11.

In this embodiment, a first functional array die 94 is added, where the first functional array die 94 is disposed between the first programmable array die 91 and the first memory array die 92. The first functional array die 94 includes a fourth bonding region that is in bonding connection with the first bonding region and the second bonding region to bond the first functional array die 94 with the first programmable array die 91 and the first memory array die 92. Wherein the first functional array die 94 is used to repair failed cells in the memory array of the first memory array die 92 and/or the second memory array die 93.

Specifically, the first functional array die includes a repair unit, and the first memory array die 92 and/or the second memory array die 93 includes a memory array, and the memory array is connected to the repair unit to repair the memory array through the repair unit. Specifically, the first memory array die 92 includes a first memory array; the second memory array die 93 includes: a second storage array; the first storage array is connected with the repair unit through the second bonding area and the fourth bonding area; the second memory array is connected with the repair unit through the third bonding area, the second bonding area and the fourth bonding area.

Specifically, as shown in fig. 11, a repair cell repairs a memory array having a portion close to a projection of the repair cell in a vertical direction. For example, the first memory array L1 and the second memory array N1 are close to the repair unit H1 in the vertical projection direction, the first memory array L1 and the second memory array N1 are respectively connected with the repair unit H1 through the metal layer inside the crystal grain and the three-dimensional heterogeneous integrated bonding structure, and the first memory array L1 and the second memory array N1 are repaired by the repair unit H1. For another example, the first memory array L2 and the second memory array N2 are close to the repair unit H2 in the vertical direction, the first memory array L2 and the second memory array N2 are respectively connected to the repair unit H2 through a metal layer inside a crystal grain and a three-dimensional heterogeneous integrated bonding structure, and the first memory array L2 and the second memory array N2 are repaired by using the repair unit H2. The design can form a high-density local interconnection structure, reduce the distance between a repair unit and a storage array, and the proportion of the first functional array crystal grains 94 to the storage array provides an implementation frame with adjustable yield and auxiliary functions, fully releases the advantages of a three-dimensional heterogeneous integration technology, and further reduces power consumption.

The programmable array crystal grain and the storage array crystal grain have similar characteristics, and the physical characteristics of the repeatability and regular distribution layout of internal units can also be realized by designing a redundancy module, and when part of array units fail due to production and manufacturing defects, the failed units are repaired by the redundancy module, so that the yield of mass production is improved. By combining a cross-grain repair method for the storage array grains, the functional array grains comprising repair units of the internal units of the programmable array grains can be designed, and a multilayer grain structure for repairing at least one programmable array grain is realized through three-dimensional heterogeneous integration. The three-dimensional integrated chip may include at least one multi-layer die repair structure of the programmable array die and/or the memory array die. The hierarchical adjacency in any multi-level grain repair structure is not limited to the hierarchy shown in fig. 11. Through three-dimensional heterogeneous integration, a multilayer crystal grain repair structure with any level of adjacent relation can be prepared; other crystal grain layers can be inserted into the multilayer crystal grain repairing structure with any level adjacent relation; for three-dimensional integrated chips comprising more than one multilayer die repair structure, the multiple multilayer die repair structures may also arbitrarily intersect the die.

For example, a three-dimensional integrated chip including a multi-layer die repair structure of a programmable array die and a multi-layer die repair structure of a memory array die may be configured to, for performance and/or cost purposes, adjacently dispose at least one functional die in the multi-layer die repair structure of the programmable array die and at least one functional die in the multi-layer die repair structure of the memory array die, and connect repair unit functional array dies in the two multi-layer die repair structures adjacently, and reuse repair-dedicated three-dimensional heterogeneous integration. And simultaneously, the grain level setting with optimal performance and the repairing grain level setting with optimal cost are achieved.

In one embodiment, the first programmable array die 91 is in normal operation, with its configuration data (configuration file) stored in the volatile static memory array and reloaded at power up. Common forms are JATG mode, active serial, passive parallel mode, SPI mode, and the like. These functions require the first programmable array die 91 configuration controller to implement. The first programmable array die 91 configuration controller is also responsible for boundary scan, embedded logic analyzer, ECC check of configuration status, and dynamic reconfiguration of the first programmable array die 91 (reconfiguring part of programmable logic of the first programmable array die 91 in the working process, widely applied to the application fields of FPGA virtualization, etc.).

In conjunction with a three-dimensional heterogeneous integrated bonding structure, cross-die transfer and multiplexing of the first programmable array die 91 can be concentrated on 1 dedicated configuration die. A dedicated configuration die is designed using a non-volatile memory process, and a non-volatile memory module is designed on the dedicated configuration die for storing a configuration file for configuring the multi-layer generic first programmable array die 91. The configuration/reconfiguration time of the first programmable array die 91 is greatly reduced, and the advantages of the three-dimensional heterogeneous integration technology are fully exerted.

Referring to fig. 12, the three-dimensional integrated chip further includes: a second functional array die 95, the second functional array die including a fifth bonding region. Specifically, the second functional array die 95 is located on a side of the first programmable array die 91 away from the first memory array die 92, and the fifth bonding region is in bonding connection with the first bonding region. The second functional array die 95 is used to store and configure the configuration file for the first programmable array die 91.

Specifically, the second functional array die 95 includes: the nonvolatile memory device includes a nonvolatile memory unit, a control unit, and a selection unit. The control unit is connected with the nonvolatile storage unit, and the selection unit is connected with the control unit. The control unit is designed for time-multiplexed configuration of the programmable arrays in the first programmable array die 91. The functions include but are not limited to JATG mode functions, active serial, passive parallel mode functions and SPI mode functions, and any combination of boundary scanning, embedded logic analyzer, configuration state ECC checking, dynamic reconfiguration and the like. The selection unit is responsible for switching the control unit to the target programmable array in a time-division multiplexing mode, and establishing a high-bandwidth configuration channel from the programmable array to the control unit to a configuration file (the configuration file is stored in the nonvolatile storage unit).

Specifically, as shown in fig. 12, the first programmable array die 91 includes a first programmable array X1 and a first programmable array X2. The first programmable array X1 and the first programmable array X2 are respectively and independently connected with a selection unit, and the selection unit selectively establishes a high-bandwidth configuration channel between the first programmable array X1 or the first programmable array X2, the control unit and the nonvolatile memory unit in a time-sharing manner according to requirements. In this embodiment, the first programmable array X1 and the first programmable array X2 are connected to the selection unit through the three-dimensional heterogeneous integrated bonding structure (the first bonding region and the fifth bonding region), so that the connection distance is reduced, high-bandwidth interconnection can be realized, and power consumption is reduced.

In another embodiment, as shown in fig. 13, the three-dimensional integrated chip further includes a second programmable array die 96, the second programmable array die 96 including a sixth bonding region. Wherein the second programmable array die 96 is located between the second functional array die 95 and the first programmable array die 91. The sixth bonding region is in bonding connection with the first bonding region, and the sixth bonding region is in bonding connection with the fifth bonding region. In this embodiment, the second functional array die 95 is used to store and configure configuration files for the first programmable array die 91 and/or the second programmable array die 96.

Specifically, as shown in fig. 13, the second functional array die 95 includes: the nonvolatile memory device includes a nonvolatile memory unit, a control unit, and a selection unit. The control unit is connected with the nonvolatile storage unit, and the selection unit is connected with the control unit. The control unit is designed for time-multiplexed configuration of the programmable arrays in the first programmable array die 91 and the second programmable array die 96. The functions include but are not limited to JATG mode functions, active serial, passive parallel mode functions and SPI mode functions, and any combination of boundary scanning, embedded logic analyzer, configuration state ECC checking, dynamic reconfiguration and the like. The selection unit is responsible for switching the control unit to the target programmable array in a time-division multiplexing mode, and establishing a high-bandwidth configuration channel from the programmable array to the control unit to a configuration file (the configuration file is stored in the nonvolatile storage unit).

Specifically, the first programmable array die 91 and/or the second programmable array die 96 include programmable arrays; the programmable array is connected with the selection unit, and the selection unit selectively establishes a data channel between the programmable array and the control unit in a time-sharing manner.

As shown in fig. 13, the first programmable array die 91 includes a first programmable array and the second programmable array die 96 includes a second programmable array. The first programmable array is connected with the selection unit through the first bonding region, the sixth bonding region and the fifth bonding region, and the second programmable array is connected with the selection unit through the sixth bonding region and the fifth bonding region.

The selection unit is interconnected to the top metal layer of the second functional array die 95 by the metal layer inside the second functional array die 95, high bandwidth; the select unit is high bandwidth interconnected to the internal metal layers of the second programmable array die 96 through the three-dimensional heterogeneous integrated bonding structures (fifth bonding region, sixth bonding region) of the second functional array die 95 with the first programmable array die 91, and TSVs that extend through the active layer of the second programmable array die 96 and the thinned substrate, to the second programmable array Y1 and the second programmable array Y2 on the second programmable array die 96.

The selection unit is interconnected to the top metal layer of the second functional array die 95 by the metal layer inside the second functional array die 95, high bandwidth; the selection unit is high bandwidth interconnected to the inner metal layer of the second programmable array die 96, and further to the top metal layer of the second programmable array die 96, through the three-dimensional heterogeneous integrated bonding structures (fifth bonding region, sixth bonding region) of the second functional array die 95 and the first programmable array die 91, and the TSVs that penetrate the active layer and thinned substrate of the second programmable array die 96. The selection unit is high bandwidth interconnected to the top metal layer of the first programmable array die 91 through the three-dimensional heterogeneous integrated bonding structures (sixth bonding region, first bonding region) of the second programmable array die 96 and the first programmable array die 91 at the top metal layer of the second programmable array die 96. The select cells are high bandwidth interconnected to the first programmable array X1 and the first programmable array X2 on the first programmable array die 91 through the inner metal layers of the first programmable array die 91 at the top metal layer of the first programmable array die 91.

The selection unit selectively establishes a high-bandwidth configuration channel between the first programmable array X1, the first programmable array X2, the second programmable array Y1 or the second programmable array Y2, the control unit and the nonvolatile memory unit in a time-sharing manner according to requirements.

The three-dimensional integrated chip of the invention realizes the stacked interconnection by utilizing the three-dimensional heterogeneous integration technology and a semiconductor metal manufacturing process. The physical and electrical parameters of the inter-die interconnect lines follow the characteristics of the semiconductor manufacturing process, greatly increasing the interconnect density and speed of the programmable array die and the memory array die. The storage access from the programmable array crystal grain to the storage array crystal grain is arranged in the three-dimensional heterogeneous integrated device, so that the storage wall in the prior art is effectively avoided.

In the three-dimensional integrated chip, the three-dimensional heterogeneous integration interconnection does not pass through the traditional IO interface, so that the interconnection distance is very short, and the storage access power consumption of the programmable array crystal grains to the storage array crystal grains is obviously reduced. Different from the existing IO leading-out technology, the method combines the three-dimensional heterogeneous integration technology to transfer the IO circuit on the crystal grain to the IO circuit of the crystal grain at the outermost layer, can control the crystal grain according to the requirement, and particularly carries out time-sharing multiplexing on the IO circuit corresponding to the IO circuit which allows time-sharing operation according to the application requirement.

Combining three-dimensional heterogeneous integration, the repair circuit of the local structure of the three-dimensional heterogeneous integrated device of the multilayer programmable array crystal grain and the storage array crystal grain is transferred from 'physical proximity' areas dispersed in the crystal grains to a 'physical proximity' area of the three-dimensional heterogeneous integration on a special repair crystal grain in a cross-crystal grain concentrated mode, and a repair extension framework of the three-dimensional heterogeneous integrated device is formed. Increasing the functional density of the programmable array die and the memory array die; further reducing the physical distance between the repair circuit and the repaired array; the method can adapt to the yield change of the local structure of the three-dimensional heterogeneous integrated device of the multilayer programmable array crystal grains and the storage array crystal grains by adjusting the repair resources on the special repair crystal grains, and does not need to modify the design of the programmable array crystal grains and the storage array crystal grains due to the yield target change. And designing a cross-region global bus and a centralized test circuit by utilizing the residual resources of the special repair crystal grains and combining cross-crystal grain high-density interconnection between vertical projection overlapping region arrays in the local structure of the three-dimensional heterogeneous integrated device of the multilayer programmable array crystal grains and the storage array crystal grains. Fully releasing the advantages of the three-dimensional heterogeneous integration technology.

By combining a three-dimensional heterogeneous integrated bonding technology, the cross-grain transfer and multiplexing of the programmable array grain configuration control unit are centralized on 1 special configuration grain, the special configuration grain is designed by using a floating gate or charge storage process, and a nonvolatile storage unit is designed on the special configuration grain and used for storing and configuring configuration files of the multilayer universal programmable array grain. The configuration/reconstruction time of the programmable array crystal grain is greatly reduced, and the advantages of the three-dimensional heterogeneous integration technology are fully exerted.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.