阅读说明：本技术 相变存储器器件及其形成方法 (Phase change memory device and forming method thereof ) 是由 彭文林 刘峻 杨海波 刘广宇 匡睿 于 2021-07-28 设计创作，主要内容包括：在某些方面,一种存储器器件包括多条位线、多条字线和多个存储器单元。多个存储器单元中的每一个存储器单元设置在多条位线中的相应一条位线与多条字线中的相应一条字线的交叉点处。多个存储器单元中的每一个存储器单元包括堆叠的相变存储器(PCM)元件和选择器。PCM元件包括顶表面和底表面。顶表面的面积小于底表面的面积。(In certain aspects, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each of the plurality of memory cells is disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a stacked Phase Change Memory (PCM) element and a selector. The PCM element includes a top surface and a bottom surface. The top surface has an area smaller than that of the bottom surface.)

1. A memory device, comprising:

a plurality of bit lines;

a plurality of word lines; and

a plurality of memory cells, each memory cell disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines,

wherein each of the plurality of memory cells includes a stacked Phase Change Memory (PCM) element and a selector, and the PCM element includes:

a top surface and a bottom surface, the top surface having an area less than the area of the bottom surface.

2. The memory device of claim 1, wherein the PCM element further comprises a slope connected to the top surface of the PCM element, and a side surface connected between the slope and the bottom surface.

3. The memory device of claim 2, wherein the bevel comprises an arcuate shape.

4. The memory device of claim 2 or 3, wherein the side surface is orthogonal to the bottom surface of the PCM element.

5. The memory device of any of claims 1-4, further comprising:

an insulating layer formed on the slope and coplanar with the top surface of the PCM element.

6. The memory device of claim 5, wherein a material of the insulating layer comprises silicon nitride (Si)₃N₄) Silicon dioxide (SiO)₂) Aluminum nitride (AlN) or aluminum oxide (Al)₂O₃) At least one of (1).

7. The memory device of claim 5 or 6, wherein the insulating layer is between 10nm and 20nm thick.

8. The memory device of any one of claims 1-7, wherein each of the plurality of memory cells further comprises:

a first electrode formed between the selector and a corresponding bit line;

a second electrode formed between the PCM element and the selector; and

a third electrode formed between a respective word line and the PCM element.

9. The memory device of any of claims 1-8, wherein the PCM element comprises a pyramid shape.

10. The memory device of any of claims 1-9, wherein the PCM element is between 30nm and 50nm thick.

11. The memory device of any of claims 1-10, wherein the PCM element comprises a chalcogenide composition comprising at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

12. A Phase Change Memory (PCM) cell comprising:

a PCM element; and

a selector, wherein the PCM element comprises:

a top surface and a bottom surface, the top surface having an area less than the area of the bottom surface.

13. A PCM cell as claimed in claim 12, wherein the PCM element further comprises a chamfer connected to the top surface of the PCM element, and a side surface connected between the chamfer and the bottom surface.

14. A PCM cell according to claim 12 or 13, wherein the ramps comprise an arcuate shape.

15. A PCM cell according to any of claims 12 to 14, wherein said side surfaces are orthogonal to said bottom surface of said PCM element.

16. A PCM cell according to any of claims 12-15, further comprising:

an insulating layer formed on the slope and coplanar with the top surface of the PCM element.

17. A PCM cell as claimed in claim 16, wherein the material of the insulating layer comprises silicon nitride (Si)₃N₄) Silicon dioxide (SiO)₂) Aluminum nitride (AlN) or aluminum oxide (A)l₂O₃) At least one of (1).

18. A PCM cell according to claim 16 or 17, wherein the insulating layer has a thickness between 10 and 20 nm.

19. A PCM cell according to any of claims 12-18, further comprising:

a first electrode formed under the selector;

a second electrode formed between the PCM element and the selector; and

a third electrode formed on the PCM element.

20. A PCM cell according to any of claims 12 to 19, wherein the PCM element comprises a pyramidal shape.

21. A PCM cell according to any of claims 12 to 20, wherein the thickness of the PCM element is between 30nm and 50 nm.

22. The PCM cell of any of claims 12-21, wherein the PCM element comprises a chalcogenide composition comprising at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In) or gallium (Ga).

23. A method for forming a memory device, comprising:

sequentially depositing a bit line, a first electrode, a selector, a second electrode, and a Phase Change Memory (PCM) element on a substrate;

depositing a mask over the PCM elements;

etching the PCM elements through openings of the mask to form recesses in the PCM elements;

removing the mask and depositing a sacrificial insulating layer over the PCM elements and the grooves;

etching the sacrificial insulating layer to form an insulating layer in the groove;

depositing a third electrode on the PCM element and the insulating layer; and

depositing a word line on the third electrode.

24. The method of claim 23, wherein the mask comprises a photoresist.

25. The method of claim 23 or 24, wherein etching the PCM element comprises wet etching.

26. The method of any one of claims 23-25, wherein the recess comprises a pyramid shape.

27. The method of any of claims 23-26, wherein etching the sacrificial insulating layer to form the insulating layer comprises etching the sacrificial insulating layer on a top surface of the PCM element.

28. The method of any one of claims 23-27, further comprising:

etching through the third electrode, the PCM element, the second electrode, the selector, the first electrode, and the bit line to form a trench and expose a top surface of the substrate; and

depositing an isolation layer on sidewalls of the trench and the top surface of the substrate.

29. The method of claim 28, wherein the etching to form the trench comprises dry etching.

30. A method for forming a Phase Change Memory (PCM) cell, comprising:

sequentially depositing a first electrode, a selector, a second electrode, and a PCM element;

depositing a mask over the PCM elements;

etching the PCM elements through openings of the mask to form recesses in the PCM elements;

removing the mask and depositing a sacrificial insulating layer over the PCM elements and the grooves;

etching the sacrificial insulating layer to form an insulating layer in the groove; and

depositing a third electrode on the PCM element and the insulating layer.

31. The method of claim 30, wherein the mask comprises a photoresist.

32. The method of claim 30 or 31, wherein etching the PCM element comprises wet etching.

33. The method of any one of claims 30-32, wherein the recess comprises a pyramid shape.

34. The method of any of claims 30-33, wherein etching the sacrificial insulating layer to form the insulating layer comprises etching the sacrificial insulating layer on a top surface of the PCM element.

Technical Field

The present disclosure relates to a Phase Change Memory (PCM) device and a method of manufacturing the same.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.

Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, PCMs may utilize the difference between the resistivities of amorphous and crystalline phases in a phase change material based on electrothermal heating and quenching of the phase change material. The PCM array cells may be vertically stacked in 3D to form a 3D PCM.

Disclosure of Invention

In one aspect, a memory device includes: a plurality of bit lines; a plurality of word lines; and a plurality of memory cells. Each memory cell is disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a stacked Phase Change Memory (PCM) element and a selector. The PCM element includes a top surface and a bottom surface. The top surface has an area smaller than an area of the bottom surface.

In another aspect, a Phase Change Memory (PCM) cell includes: a PCM element; and a selector. The PCM element includes a top surface and a bottom surface. The top surface has an area smaller than an area of the bottom surface.

In yet another aspect, a method for forming a memory device includes: sequentially depositing a bit line, a first electrode, a selector, a second electrode, and a Phase Change Memory (PCM) element on a substrate; depositing a mask over the PCM elements; etching the PCM elements through openings of the mask to form recesses in the PCM elements; removing the mask and depositing a sacrificial insulating layer over the PCM elements and the grooves; etching the sacrificial insulating layer to form an insulating layer in the groove; depositing a third electrode on the PCM element and the insulating layer; and depositing a word line on the third electrode.

In yet another aspect, a method for forming a Phase Change Memory (PCM) cell, comprising: sequentially depositing a first electrode, a selector, a second electrode, and a PCM element; depositing a mask over the PCM elements; etching the PCM elements through openings of the mask to form recesses in the PCM elements; removing the mask and depositing a sacrificial insulating layer over the PCM elements and the grooves; etching the sacrificial insulating layer to form an insulating layer in the groove; and depositing a third electrode on the PCM element and the insulating layer.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

FIG. 1 illustrates a perspective view of an example 3D cross point (XPoint) memory device, in accordance with some aspects of the present disclosure.

Fig. 2 shows a side view of a cross-section of a 3D Phase Change Memory (PCM) memory device.

Fig. 3 illustrates a side view of a cross-section of an example 3D PCM device having a PCM element with a shape of a narrow top and a wide bottom, according to some aspects of the present disclosure.

Fig. 4A illustrates a schematic diagram of current distribution in an example 3D PCM device having a PCM element with a shape of a narrow top and a wide bottom, according to some aspects of the present disclosure.

Fig. 4B illustrates a 3D schematic of an example 3D PCM device having a PCM element with a shape of a narrow top and a wide bottom according to some aspects of the present disclosure.

Fig. 5 illustrates a schematic diagram of the operation of an example 3D PCM device having a PCM element with a shape of a narrow top and a wide bottom, according to some aspects of the present disclosure.

Fig. 6A-6J illustrate an exemplary fabrication process for forming a 3D PCM device having a PCM element with a shape of a narrow top and a wide bottom according to some aspects of the present disclosure.

Fig. 7 illustrates a flow diagram of an example method for forming a 3D PCM device having a PCM element with a shape of a narrow top and a wide bottom according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

Note that references in the specification to "one embodiment," "an example embodiment," "some implementations," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other implementations whether or not explicitly described.

In general, terms may be understood at least in part according to usage in context. For example, the term "one or more" as used herein may be used in describing any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey singular usage or to convey plural usage, depending at least in part on the context. Moreover, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of additional factors not necessarily expressly described, again depending at least in part on the context.

It should be readily understood that the meaning of "on … …", "above … …" and "above … …" in this disclosure should be interpreted in the broadest manner such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "above … …" or "above … …" means not only "above something" or "above something", but also includes the meaning of "above something" or "above something" without intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms, such as "below … …," "below … …," "lower," "above … …," "upper," and the like, may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a width that is less than the width of the underlying or overlying structure. Furthermore, a layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of levels at the top and bottom surfaces or between the top and bottom surfaces of a continuous structure. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "3D memory device" refers to a semiconductor device having memory cells that may be vertically arranged on a laterally oriented substrate such that the number of memory cells may increase in a vertical direction relative to the substrate. As used herein, the term "vertical" refers to nominally orthogonal to a lateral surface of a substrate.

PCMs may utilize the difference between the resistivity of amorphous and crystalline phases in a phase change material (e.g., a chalcogenide alloy) based on electrothermal heating and quenching of the phase change material. Phase change material in a PCM cell may be located between two electrodes and a current may be applied to repeatedly switch the material (or at least part of the material's blocking current path) between the two phases to store data. The PCM cells may be vertically stacked in 3D to form a 3D PCM.

The 3D PCM includes a 3D cross-point (XPoint) memory, which stores data based on resistance (e.g., high resistance state or low resistance state) changes of bulk material properties, along with a bit-addressable, stackable cross-point data access array. For example, FIG. 1 illustrates a perspective view of an exemplary 3D XPoint memory device 100, according to some embodiments of the present disclosure. According to some embodiments, 3D XPoint memory device 100 has a transistorless crosspoint architecture that positions memory cells at the intersections of orthogonal conductors. 3D XPoint memory device 100 includes a plurality of parallel lower bitlines 102 in a same plane and a plurality of parallel upper bitlines 104 in a same plane above lower bitlines 102. 3-D XPoint memory device 100 also includes a plurality of parallel word lines 106 that lie vertically in the same plane between lower bit line 102 and upper bit line 104. As shown in fig. 1, each lower bit line 102 and each upper bit line 104 extend laterally in a bit line direction (parallel to the wafer plane) in plan view, and each word line 106 extends laterally in a word line direction in plan view. In plan view, each word line 106 intersects each lower bit line 102 and each upper bit line 104. In some embodiments, each wordline 106 is orthogonal to each lower bitline 102 and each upper bitline 104.

Note that the x and y axes are included in fig. 1 to illustrate two orthogonal directions in the plane of the wafer. The x-direction is the word line direction and the y-direction is the bit line direction. Note that the z-axis is also included in FIG. 1 to further illustrate the spatial relationship of the components in 3D XPoint memory device 100. The substrate (not shown) of the 3D XPoint memory device 100 includes two lateral surfaces extending laterally in the xy plane: a top surface on the front side of the wafer, and a bottom surface on the back side opposite the front side of the wafer. The z-axis is orthogonal to the x-axis and the y-axis. As used herein, whether a component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device (e.g., 3D XPoint memory device 100) is determined in the z-direction (the vertical direction orthogonal to the xy-plane) relative to the substrate of the semiconductor device when the substrate is located in the lowest plane of the semiconductor device in the z-direction. The same concepts used to describe the spatial relationships apply throughout this disclosure.

As shown in FIG. 1, 3D XPoint memory device 100 includes a plurality of memory cells 108, each memory cell disposed at an intersection of a lower or upper bitline 102 or 104 and a corresponding wordline 106. Each memory cell 108 has a vertical square pillar shape. Each memory cell 108 includes at least a vertically stacked PCM element 110 and a selector 112. Each memory cell 108 stores a single bit of data and can be written or read by varying the voltage applied to the corresponding selector 112, instead of requiring a transistor. Each memory cell 108 is independently accessed with current applied through top and bottom conductors, such as a respective word line 106 and lower or upper line 102 or 104, in contact with each memory cell 108. The memory cells 108 in the 3D XPoint memory device 100 are arranged in a memory array.

Fig. 2 illustrates a side view of a cross-section of an example memory device 200, in accordance with some aspects of the present disclosure. In fig. 2, a memory device 200 includes a substrate 202, a plurality of parallel bit lines 204 formed on the substrate 202, and a plurality of parallel word lines 216 formed over the bit lines 204. Substrate 202 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The bit lines 204 and word lines 216 may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each of the bit line 204 and the word line 216 includes a metal, such as tungsten.

The memory device 200 may be divided by the isolation layer 222 to form a plurality of separated pillar-shaped memory cells 201. In some embodiments, each pillar shaped memory cell 201 is disposed at an intersection of a respective one of bit lines 204 and a respective one of word lines 216. Each pillar memory cell 201 may be independently accessed with a current applied through a respective word line 216 and a respective bit line 204 that are in contact with the pillar memory cell 201. Each pillar memory cell 201 has a vertical pillar shape (e.g., similar to memory cell 108 in fig. 1), and the spacer layer 222 may extend laterally in the x-direction and the y-direction to separate the pillar memory cells 201.

Each of the pillar-shaped memory cells 201 includes a first electrode layer 206 formed on a bit line 204, a selector 208 formed on the first electrode layer 206, and a second electrode layer 210 formed on the selector 208. The pillar memory cell 201 further includes a Phase Change Memory (PCM) element 212 formed on the second electrode layer 210 and a third electrode layer 214 formed on the PCM element 212. The first electrode layer 206, the selector 208, and the second electrode layer 210 function as a selector in the pillar-shaped memory cell 201 and are usedMakingA selector. The second electricityThe pole layer 210, the PCM element 212, and the third electrode layer 214 function as and function as a storage element in the pillar-shaped memory cell 201. It is to be understood that the second electrode layer 210 serves as a common electrode in the selector and storage elements.

The first electrode layer 206 is formed on the bit line 204 and is in contact with the selector 208, so that the first electrode layer 206 serves as a current path and may be formed of a conductive material. In some embodiments, the first electrode layer 206 may be a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the first electrode layer 206 may be a titanium nitride (TiN) layer, but the disclosure is not limited thereto.

The selector 208 is formed on the first electrode layer 206, and the resistance of the selector 208 changes in response to a selection voltage applied between the first electrode layer 206 and the second electrode layer 210. In some embodiments, the selector 208 may be an Ovonic Threshold Switch (OTS) device made of at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), antimony (Sb), silicon (Si), or arsenic (As). The OTS device is formed of an OTS material that exhibits OTS characteristics. Regarding the function of the selector 208 including the OTS material, when a voltage lower than the threshold voltage Vth is applied between the first electrode layer 206 and the second electrode layer 210, the selector 208 may be in a high resistance state, preventing a current from flowing therethrough, and when a voltage higher than the threshold voltage Vth is applied between the first electrode layer 206 and the second electrode layer 210, the selector 208 may be in a low resistance state, allowing a current to flow therethrough.

The second electrode layer 210 is formed between the selector and the storage element and serves as one of the electrodes of the selector and the storage element, and thus the second electrode layer 210 should be formed of a heat insulating and electrically insulating material to reduce temperature and electrical interference from the selector and the storage element. The second electrode layer 210 may be formed of or include, for example, a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the second electrode layer 210 may be a titanium nitride (TiN) layer or any suitable conductive layer. In some embodiments, the second electrode layer 210 may be formed of amorphous carbon.

The PCM element 212 is formed on the second electrode layer 210. The PCM element 212 is a material whose phase can be reversibly switched between an amorphous state and a crystalline state according to a heating time. Generally, the PCM element 212 may exist in an amorphous phase and one or sometimes several crystalline phases and may be switched between these phases rapidly and repeatedly. In some embodiments, the PCM element 212 may include a material whose phase may be reversibly changed using joule heat, which is generated when a voltage is applied between the second electrode layer 210 and the third electrode layer 214, and the resistance of the PCM element 212 may be changed by such phase change. In some embodiments, the PCM element 212 may include a chalcogenide composition including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga). In some embodiments, the PCM element 212 may be: binary (two-element) compounds such as GaSb, InSb, InSe, SbTe or GeTe; ternary (three-element) compounds such as GeSbTe, GaSeTe, InSbTe, SnSbTe or InSbGe; or quaternary (four-element) compounds such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe), or TeGeSbS. In some embodiments, the PCM element 212 may be GeSbTe.

A third electrode layer 214 is formed on the PCM element 212. In some embodiments, the material of the third electrode layer 214 may be similar to the material of the first electrode layer 206 or the second electrode layer 210. In some embodiments, the material of the third electrode layer 214 may be similar to the material of the second electrode layer 210. Then, a word line 216 is formed over the third electrode layer 214.

It should be understood that the locations of bit lines 204 and word lines 216 corresponding to pillar memory cells 201 may be swapped according to different memory designs. In other words, the first electrode layer 206 may be formed on the word line, and the bit line may be formed on the third electrode layer 214.

Fig. 3 illustrates a side view of a cross-section of an example memory device 300, in accordance with some aspects of the present disclosure. In fig. 3, a memory device 300 includes a substrate 302, a plurality of parallel bit lines 304 formed on the substrate 302, and a plurality of parallel word lines 316 formed over the bit lines 304. Substrate 302 may include silicon (e.g., monocrystalline silicon), SiGe, GaAs, Ge, SOI, or any other suitable material. The bit lines 304 and word lines 316 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each of the bit line 304 and the word line 316 includes a metal, such as tungsten.

The memory device 300 may be divided by the isolation layer 322 to form a plurality of separated pillar-shaped memory cells 301. In some implementations, each pillar shaped memory cell 301 is disposed at an intersection of a respective one of the bit lines 304 and a respective one of the word lines 316. Each pillar memory cell 301 may be independently accessed with current applied through a corresponding word line 316 and a corresponding bit line 304 in contact with the pillar memory cell 301. Each pillar memory cell 301 has a vertical pillar shape (e.g., similar to memory cell 108 in fig. 1), and the spacer layer 322 may extend laterally in the x-direction and the y-direction to separate the pillar memory cells 301.

Each pillar-shaped memory cell 301 includes a first electrode layer 306 formed on a bit line 304, a selector 308 formed on the first electrode layer 306, and a second electrode layer 310 formed on the selector 308. The pillar memory cell 301 further includes: a PCM element 312 having a polygonal cylindrical shape with a narrow top and a wide bottom, formed on the second electrode layer 310; a third electrode layer 314 formed on the PCM element 312; and an insulating layer 309 formed between the third electrode layer 314 and the PCM element 312. Polygonal cylinders include cylinders, triangular prisms (prism), quadrangular prisms, pentagonal prisms, hexagonal prisms, cones, truncated cones, triangular pyramids (pyramids), quadrangular pyramids, pentagonal pyramids, hexagonal pyramids, triangular truncated cones (frutum), quadrangular truncated cones, pentagonal truncated cones, or hexagonal truncated cones. The first electrode layer 306, the selector 308, and the second electrode layer 310 function as a selector in the pillar-shaped memory cell 301 and function as a selector. The second electrode layer 310, the PCM element 312, and the third electrode layer 314 function as and function as a storage element in the pillar-shaped memory cell 301. It should be understood that the second electrode layer 310 serves as a common electrode in the selector and storage elements. The PCM element 312 having a shape of a narrow top width and a bottom serves to reduce a contact interface area between the PCM element 312 and the third electrode layer 314, thereby increasing a current density across the contact interface and, therefore, reducing energy consumption of the pillar shaped memory cell 301. The insulating layer 309 serves to reduce heat dissipation at the contact interface, which increases the efficiency of heating the PCM element 312 having a shape of narrow top, wide bottom, and thus reduces the energy consumption of the pillar memory cell 301. Details of the PCM element 312 and the insulating layer 309 will be discussed later.

The first electrode layer 306 is formed on the bit line 304 and is in contact with the selector 308, so that the first electrode layer 306 serves as a current path and may be formed of a conductive material. In some embodiments, the first electrode layer 306 may be a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the first electrode layer 306 may be a titanium nitride (TiN) layer, but the disclosure is not limited thereto.

The selector 308 is formed on the first electrode layer 306, and the resistance of the selector 308 changes in response to a selection voltage applied between the first electrode layer 306 and the second electrode layer 310. In some embodiments, the selector 308 may be an OTS device made of at least one of O, S, Se, Te, Ge, Sb, Si, or As. The OTS device is formed of an OTS material that exhibits OTS characteristics. Regarding the function of the selector 308 including the OTS material, when a voltage lower than the threshold voltage Vth is applied between the first electrode layer 306 and the second electrode layer 310, the selector 308 may be in a high-resistance state, preventing a current from flowing therethrough, and when a voltage higher than the threshold voltage Vth is applied between the first electrode layer 306 and the second electrode layer 310, the selector 308 may be in a low-resistance state, allowing a current to flow therethrough.

The second electrode layer 310 is formed between the selector and the storage element and serves as one of the electrodes of the selector and the storage element, and thus the second electrode layer 310 should be formed of a heat insulating and electrically insulating material to reduce temperature and electrical interference from the selector and the storage element. The second electrode layer 310 may be formed of or include, for example, a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the second electrode layer 310 may be a titanium nitride (TiN) layer or any suitable conductive layer. In some embodiments, the second electrode layer 310 may be formed of amorphous carbon.

The PCM element 312 is formed on the second electrode layer 310. The PCM element 312 comprises a material whose phase may be reversibly switched between an amorphous state and a crystalline state depending on the heating time. In general, the material of the PCM element 312 may be present in an amorphous phase and one or sometimes several crystalline phases and may be switched between these phases rapidly and repeatedly. In some embodiments, the PCM element 312 may include a material whose phase may be reversibly changed using joule heat, which is generated when a voltage is applied between the second electrode layer 310 and the third electrode layer 314, and the resistance of the PCM element 312 may be changed by such phase change. In some embodiments, the PCM element 312 may include a chalcogenide composition including at least one of Ge, Sb, Te, In, or Ga. In some embodiments, the PCM element 312 may be: binary (two-element) compounds such as GaSb, InSb, InSe, SbTe or GeTe; ternary (three-element) compounds such as GeSbTe, GaSeTe, InSbTe, SnSbTe or InSbGe; or quaternary (four-element) compounds such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe), or TeGeSbS. In some embodiments, the PCM element 312 may be GeSbTe. The PCM element 312 includes a shape of a narrow top and a wide bottom in a cross-sectional view in the x-z plane or the y-z plane. In some embodiments, the PCM element 312 has four cross-sectional views, and each cross-sectional view of the PCM element 312 includes a shape of a narrow top and a wide bottom. In some embodiments, the PCM element 312 includes a pyramid shape having a flat top surface, a flat bottom surface, and a slope and/or side surfaces between the flat top surface and the flat bottom surface. For example, the PCM element 312 may include a pyramid shape having a flat top surface, a flat bottom surface, a slope connected to the flat top surface, and a side surface connected between the slope and the flat bottom surface. The side surface is orthogonal to the bottom surface. In some embodiments, the PCM element 312 comprises a pyramid shape with one or more steps, and each step comprises: a side surface extending vertically (z direction) and orthogonal to the bottom surface; and a top surface connected to the side surface and extending laterally (x or y direction) and parallel to the bottom surface. In some embodiments, each step includes a slope connected to the side surface and extending in an oblique direction. In some implementations, one or more slopes of the PCM element 312 include an arc shape that is formed as a result of an etching process (e.g., a wet etching process). In some embodiments, the thickness of the PCM element (which is measured from the top surface to the bottom surface) is 10 to 100nm, such as 30 to 50 nm.

The third electrode layer 314 is formed on the PCM element 312. In some embodiments, the material of the third electrode layer 314 can be similar to the material of the first electrode layer 306 or the second electrode layer 310. In some embodiments, the material of the third electrode layer 314 may be similar to the material of the second electrode layer 310. Then, a word line 316 is formed over the third electrode layer 314.

An insulating layer 309 is formed between the PCM element 312 and the third electrode layer 314. Specifically, insulating layer 309 is formed on a slope of PCM element 312 (e.g., slope 3121 in fig. 4A) and is coplanar with a top surface of PCM element 312 (e.g., top surface 3123 in fig. 4A). In some embodiments, the insulating layer 309 is embedded between the isolation layer 322, the PCM element 312 and the third electrode layer 314, as shown in fig. 3. In some embodiments, the material of insulating layer 309 comprises silicon nitride (Si)₃N₄) Silicon dioxide (SiO)₂) Aluminum nitride (AlN) or aluminum oxide (Al)₂O₃) At least one of (1). In some embodiments, the thickness of the insulating layer 309 (as measured from the top surface of the PCM element 312 to the end of the slope 3121 in fig. 4A) is 5 to 30nm, for example 10 to 20 nm.

It should be understood that the locations of the bit lines 304 and word lines 316 corresponding to the pillar shaped memory cells 301 may be swapped according to different memory designs. In other words, the first electrode layer 306 may be formed on the word line, and the bit line may be formed on the third electrode layer 314.

Fig. 4A illustrates a schematic diagram of current distribution in an example 3D PCM device having a PCM element with a shape of a narrow top and a wide bottom, according to some aspects of the present disclosure. As shown in fig. 4A, the pillar-shaped memory cell 301 includes a first electrode layer 306 formed on a bit line (e.g., 304 in fig. 3), a selector 308 formed on the first electrode layer 306, and a second electrode layer 310 formed on the selector 308. The pillar memory cell 301 further includes a PCM element 312 having a shape of a narrow top and a wide bottom formed on the second electrode layer 310, a third electrode layer (e.g., 314 of fig. 3) formed on the PCM element 312, and an insulating layer 309 formed between the third electrode layer (e.g., 314 of fig. 3) and the PCM element 312. The PCM element 312 includes a top surface 3123, a bottom surface 3127, a sloped surface 3121 connected to the top surface 3123, and a side surface 3125 connected between the sloped surface 3121 and the bottom surface 3127.

In some embodiments, the width of top surface 3123 is less than the width of bottom surface 3127 in a cross-sectional view, such that PCM element 312 has a shape of a narrow top and a wide bottom. In some embodiments, the top surface 3123 is smaller in area than the bottom surface 3127. By reducing the contact interface between the PCM element 312 and the third electrode layer 314, it increases the current density across the contact interface and thereby reduces the overall energy consumption of the pillar shaped memory cell 301. Furthermore, since the contact interface is significantly reduced, the heat dissipation from the PCM element 312 to the third electrode layer 314 is also reduced, thereby transferring the heating area from the contact interface to the center of the PCM element 312. This also increases the efficiency of heating the PCM element 312. In some embodiments, the top surface 3123 comprises a flat top surface and thus provides better electrical contact with the third electrode layer 314. In some embodiments, to prevent over-etching during processing of the PCM element 312 (which will be discussed later) to form a leakage path within the PCM element 312 or over-etch the second electrode layer 310, a side surface 3125 connected between the inclined surface 3121 and the bottom surface 3127 is required. In some embodiments, the side surface 3125 may also be a vertical side surface formed when processing to separate the pillar-shaped memory cells 301.

Insulating layer 309 is formed on inclined surface 3121 and is coplanar with top surface 3123. In some embodiments, the insulating layer 309 may also cover a portion of the top surface 3123. In some embodiments, the insulating layer 309 is embedded between the isolation layer 322, the PCM element 312 and the third electrode layer 314, as shown in fig. 3. The insulating layer 309 also serves to reduce heat dissipation at the contact interface, which increases the efficiency of heating the PCM element 312 and thus reduces the energy consumption of the pillar shaped memory cell 301.

Fig. 4B illustrates a 3D schematic of an example 3D PCM device having a PCM element with a shape of a narrow top and a wide bottom according to some aspects of the present disclosure. As described above, the inclined surface 3121 may include an arc shape. The shape of the inclined surface 3121 may be determined according to the type of etching process. For example, when a wet etch is applied over PCM element 312, the arcuate shape of slope 3121 may be formed.

Fig. 5 illustrates a schematic diagram of the operation of an exemplary array of PCM cells according to some embodiments of the present disclosure. As shown in fig. 5, an array of PCM cells 502 (e.g., corresponding to the pillar shaped memory cells 301 in fig. 3) may be formed as intersections of word lines 504 (e.g., corresponding to the word lines 316 in fig. 3) and bit lines 506 (e.g., corresponding to the bit lines 304 in fig. 3), respectively. Each PCM cell 502 may include a PCM element 508 (e.g., corresponding to PCM element 312 in fig. 3) in series with a selector (e.g., corresponding to selector 308 in fig. 3). To operate the array of PCM cells 502, a word line voltage (Vw) having a value of 0 or Vhh may be applied to each word line 504, and a bit line voltage (Vb) having a value of 0 or Vll may be applied to each bit line 506. The voltage (Va) applied to each PCM cell 502 (and its selector 510) may thus be Vhh, -Vll, 0, or Vhh-Vll. In some embodiments, Vhh and Vll are set based on the inherent threshold voltage (Vth) of selector 510, such that | Vhh-Vll | ≧ Vth > | Vhhl |, | Vll |, or 0. As shown in fig. 5, according to some embodiments, the voltage (Va) is equal to or greater than the threshold voltage (Vth) at only one intersection of a word line 504 and a bit line 506 having a non-zero voltage. Thus, only PCM cell 502 (in the dashed circle in FIG. 5) at the intersection of a word line 504 and bit line 506 pair having a non-zero voltage may be selected (i.e., applied with a voltage of Vhh-Vll, and in an on state). According to some embodiments, other PCM cells 502 are unselected and in an off state.

Fig. 6A-6J illustrate an exemplary fabrication process for forming a 3D PCM device having a PCM element with a shape of a narrow top and a wide bottom according to some aspects of the present disclosure. Fig. 7 illustrates a flow diagram of an example method 700 for forming a 3D PCM device having a PCM element with a narrow top-wide bottom shape according to some embodiments of the present disclosure. Examples of the 3D PCM device depicted in fig. 6A-6J and 7 include the memory device 300 depicted in fig. 3. Examples of the memory cell depicted in fig. 6A-6J and 7 include the pillar shaped memory cell 301 depicted in fig. 3 and 4A-4B. Examples of PCM elements having a shape with a narrow top and a wide bottom depicted in fig. 6A-6J and 7 include PCM element 312 depicted in fig. 3 and 4A-4B. Fig. 6A to 6J and 7 will be described together. It should be understood that the operations shown in method 700 are not exhaustive, and that other operations may be performed before, after, or between any of the shown operations. Further, some operations may be performed concurrently or in a different order than shown in FIG. 7.

Referring to fig. 7, the method 700 begins with operation 702, where a bitline, a first electrode layer, a selector, a second electrode layer, and a PCM element are sequentially deposited over a substrate. I.e. the bit lines are deposited on the substrate, the first electrode layer is deposited on the bit lines, the selector is deposited on the first electrode layer, the second electrode layer is deposited on the selector, and the PCM elements are deposited on the second electrode layer. In some embodiments, depositing may include using one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, any other suitable deposition process, or any combination thereof.

Referring to fig. 6A, a bit line 604 (e.g., corresponding to the bit line 304 in fig. 3) is formed on a substrate 602 (e.g., corresponding to the substrate 302 in fig. 3), a first electrode layer 606 (e.g., corresponding to the first electrode layer 306 in fig. 3) is formed on the bit line 604, a selector 608 (e.g., corresponding to the selector 308 in fig. 3) is formed on the first electrode layer 606, a second electrode layer 610 (e.g., corresponding to the second electrode layer 310 in fig. 3) is formed on the selector 608, and a PCM element 612 (e.g., corresponding to the PCM element 312 in fig. 3) is formed on the second electrode layer 610. In some embodiments, the bit line 604 may comprise W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the first electrode layer 606 may include W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the first electrode layer 606 comprises carbon, such as amorphous carbon (a-C).

The method 700 proceeds to operation 704, as shown in FIG. 7, where a mask is deposited over a portion of the PCM elements. In particular, the mask comprises a photoresist. The pattern of the mask is created by applying a photoresist to the surface of the PCM element to be etched, exposing the photoresist to form one or more openings, and then developing a pattern into the photoresist using a resist developer.

Referring to fig. 6B, a mask 621 is formed over the PCM element 612. Mask 621 includes photoresist. Photoresists are organic compositions that consist of a photosensitive polymer or polymer precursor dissolved in one or more organic solvents. The pattern of the mask 621 is created by applying photoresist to the top surface of the PCM element 612 to be etched and, after photolithography, etching to form one or more openings 6211. In some embodiments, mask 621 may also include an oxide material, e.g., SiO₂And (3) a layer.

The method 700 proceeds to operation 706, as shown in fig. 7, where the PCM element is etched through the masked openings to form recesses in the PCM element. In some embodiments, etching of the PCM element may include using one or more etching processes including, but not limited to, wet etching, dry etching, any other suitable etching process, or any combination thereof. In some embodiments, the etching process may form pyramid shaped holes (or recesses) instead of holes with rounded sidewalls. This is because PCM elements exhibit anisotropic etching in certain chemistries, rather than isotropic etching during wet etching processes.

Referring to fig. 6C, an etching process, such as a wet etching process, is applied through the one or more openings 6211 of the mask 621 (e.g., in fig. 6B) to form one or more recesses 625 in the PCM element 612. In some embodiments, the groove 625 comprises a pyramid shape extending through the PCM element 612. The depth of the etch may be 5 to 30nm, for example 10 to 20 nm.

The method 700 proceeds to operation 708 where the mask is removed and a sacrificial insulating layer is formed over the PCM elements and the recesses, as shown in fig. 7. The removal of the mask includes the use of organic or non-organic solvents that attack and remove the photoresist material. The deposition of the sacrificial insulating layer may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, plating, electroless plating, any other suitable deposition process, or any combination thereof.

Referring to fig. 6D, the mask 621 is removed by dissolving and removing the mask 621 over the PCM element 612 using an organic or non-organic solvent over the mask 621. After removal, the top surface 6123 and bevel 6121 of the PCM element 612 are exposed. The bevel 6121 is also part of the groove 625. In some embodiments, a bottom surface (not shown) of the groove 625 coupled to the bevel 6121 may also be formed.

Thereafter, referring to fig. 6E, a sacrificial insulating layer 6091 is formed on the PCM element 612 and the groove 625. In particular, the sacrificial insulating layer 6091 is formed on the bevel 6121 and the top surface 6123 of the PCM element 612. In some embodiments, the sacrificial insulating layer 6091 comprises silicon nitride (Si)₃N₄) Silicon dioxide (SiO)₂) Aluminum nitride (AlN) or aluminum oxide (Al)₂O₃) At least one of (1).

The method 700 proceeds to operation 710, as shown in fig. 7, where the sacrificial insulating layer is etched to form an insulating layer in the recess. In particular, the sacrificial insulating layer on the top surface of the PCM element is etched away, leaving and forming an insulating layer in the recess. In some embodiments, the etching process of the sacrificial insulating layer may include wet etching or dry etching.

Referring to fig. 6F, a sacrificial insulating layer (e.g., 6091 in fig. 6E) is etched to form an insulating layer 609 in the groove 625. In particular, the insulating layer 609 fills in the groove 625 and also on the bevel 6121 of the PCM element 612. In some embodiments, the insulating layer 609 may also cover a portion of the top surface 6123 of the PCM element 612, while exposing a majority of the top surface 6123 to contact the third electrode layer. In some implementations, portions of the insulating layer 609 that cover portions of the top surface 6123 of the PCM element 612 may be removed. In some embodiments, the etching of the sacrificial insulating layer may include Chemical Mechanical Planarization (CMP) to remove the insulating layer 609 covering portions of the top surface 6123 of the PCM elements 612.

The method 700 proceeds to operation 712 where a third electrode layer is formed over the PCM element and the insulating layer, as shown in fig. 7. I.e. the third electrode layer is deposited and covers the top surface of the PCM element and the insulating layer in the recess. Deposition of the third electrode layer may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, plating, electroless plating, any other suitable deposition process, or any combination thereof.

Referring to fig. 6G, a third electrode layer 614 is formed on the PCM element 612 and the insulating layer 609. In particular, the third electrode layer 614 is deposited and covers the top surface 6123 of the PCM element 612 and also the insulating layer 609 in the groove 625.

The method 700 proceeds to operation 714 where a trench is formed by an etching process to expose a top surface of the substrate, as shown in fig. 7. In particular, a trench is etched through the third electrode layer, the insulating layer, the PCM element, the second electrode layer, the selector, the first electrode layer, and the bit line to expose the top surface of the substrate. In some embodiments, the etching process of the trench may include dry etching, such as Reactive Ion Etching (RIE).

Referring to fig. 6H, one or more trenches 603 are formed by an etching process to expose a top surface 6021 of the substrate 602. In particular, the trench 603 is etched through the third electrode layer 614, the insulating layer 609, the PCM element 612, the second electrode layer 610, the selector 608, the first electrode layer 606 and the bit line 604 to expose the top surface 6021 of the substrate 602. These trenches 603 are used to divide a memory device (e.g., memory device 300 in fig. 3) to form a plurality of separate memory cells (e.g., pillar memory cells 301 in fig. 3).

The method 700 proceeds to operation 716 as shown in fig. 7, where an isolation layer is formed on the sidewalls of the trench and the top surface of the substrate. This may be achieved by depositing a sacrificial spacer over the third electrode, the sidewalls of the trench and the top surface of the substrate. Portions of the sacrificial spacer on the third electrode are then etched away, leaving a spacer on the sidewalls of the trench and the top surface of the substrate. The deposition of the isolation layer may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, plating, electroless plating, any other suitable deposition process, or any combination thereof.

Referring to fig. 6I, an isolation layer 622 (e.g., corresponding to 322 in fig. 3) is formed on the sidewalls of the trenches 603 and the top surface 6021 of the substrate 602. In some embodiments, the trench 603 may be filled with an isolation layer 622, or only the sidewalls of the trench may be covered, leaving some space therein.

The method 700 proceeds to operation 718 as shown in fig. 7, where a wordline is formed over the third electrode. Deposition of the word lines may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, plating, electroless plating, any other suitable deposition process, or any combination thereof.

Referring to fig. 6J, word lines 616 (e.g., corresponding to 316 in fig. 3) are formed on the third electrode layer 614. And a memory device (e.g., memory device 300 in fig. 3) is formed.

According to an aspect of the present disclosure, a memory device includes: a plurality of bit lines; a plurality of word lines; and a plurality of memory cells. Each memory cell is disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a stacked Phase Change Memory (PCM) element and a selector. The PCM element includes a top surface and a bottom surface. The top surface has an area smaller than an area of the bottom surface.

In some embodiments, the PCM element further comprises a slope connected to the top surface of the PCM element, and a side surface connected between the slope and the bottom surface.

In some embodiments, the ramp comprises an arcuate shape.

In some embodiments, the side surface is orthogonal to the bottom surface of the PCM element.

In some embodiments, the memory device further comprises: an insulating layer formed on the slope and coplanar with the top surface of the PCM element.

In some embodiments, the material of the insulating layer comprises silicon nitride (Si)₃N₄) Silicon dioxide (SiO)₂) Aluminum nitride (AlN) or aluminum oxide (Al)₂O₃) At least one of (1).

In some embodiments, the insulating layer is between 10nm and 20nm thick.

In some embodiments, each of the plurality of memory cells further comprises: a first electrode formed between the selector and a corresponding bit line; a second electrode formed between the PCM element and the selector; and a third electrode formed between the corresponding word line and the PCM element.

In some embodiments, the PCM element comprises a pyramid shape.

In some embodiments, the PCM element has a thickness between 30nm and 50 nm.

In some embodiments, the PCM element includes a chalcogenide composition including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

According to another aspect of the present disclosure, a Phase Change Memory (PCM) cell includes: a PCM element; and a selector. The PCM element includes a top surface and a bottom surface. The top surface has an area smaller than an area of the bottom surface.

In some embodiments, the PCM element further comprises a slope connected to the top surface of the PCM element, and a side surface connected between the slope and the bottom surface.

In some embodiments, the ramp comprises an arcuate shape.

In some embodiments, the side surface is orthogonal to the bottom surface of the PCM element.

In some embodiments, the PCM cell further comprises: an insulating layer formed on the slope and coplanar with the top surface of the PCM element.

In some embodiments, the material of the insulating layer comprises silicon nitride (Si)₃N₄) Silicon dioxide (SiO)₂) Aluminum nitride (AlN) or aluminum oxide (Al)₂O₃) At least one of (1).

In some embodiments, the insulating layer is between 10nm and 20nm thick.

In some embodiments, each of the plurality of memory cells further comprises: a first electrode formed between the selector and a corresponding bit line; a second electrode formed between the PCM element and the selector; and a third electrode formed between the corresponding word line and the PCM element.

In some embodiments, the PCM element comprises a pyramid shape.

In some embodiments, the PCM element has a thickness between 30nm and 50 nm.

In some embodiments, the PCM element includes a chalcogenide composition including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

According to yet another aspect of the present disclosure, a method for forming a memory device includes: sequentially depositing a bit line, a first electrode, a selector, a second electrode, and a Phase Change Memory (PCM) element on a substrate; depositing a mask over the PCM elements; etching the PCM elements through openings of the mask to form recesses in the PCM elements; removing the mask and depositing a sacrificial insulating layer over the PCM elements and the grooves; etching the sacrificial insulating layer to form an insulating layer in the groove; depositing a third electrode on the PCM element and the insulating layer; and depositing a word line on the third electrode.

In some embodiments, the mask comprises a photoresist.

In some embodiments, the etching of the PCM element comprises wet etching.

In some embodiments, the groove comprises a pyramid shape.

In some implementations, etching the sacrificial insulating layer to form the insulating layer includes etching the sacrificial insulating layer on a top surface of the PCM element.

In some embodiments, the method further comprises: etching through the third electrode, the PCM element, the second electrode, the selector, the first electrode, and the bit line to form a trench and expose a top surface of the substrate; and depositing an isolation layer on sidewalls of the trench and the top surface of the substrate.

In some embodiments, the etching to form the trench comprises dry etching.

According to yet another aspect of the present disclosure, a method for forming a Phase Change Memory (PCM) cell, comprises: sequentially depositing a first electrode, a selector, a second electrode, and a PCM element; depositing a mask over the PCM elements; etching the PCM elements through openings of the mask to form recesses in the PCM elements; removing the mask and depositing a sacrificial insulating layer over the PCM elements and the grooves; etching the sacrificial insulating layer to form an insulating layer in the groove; and depositing a third electrode on the PCM element and the insulating layer.

In some embodiments, the mask comprises a photoresist.

In some embodiments, the etching of the PCM element comprises wet etching.

In some embodiments, the groove comprises a pyramid shape.

In some implementations, etching the sacrificial insulating layer to form the insulating layer includes etching the sacrificial insulating layer on a top surface of the PCM element.

The foregoing description of the specific embodiments will reveal the general nature of the disclosure so that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Implementations of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specific functions and relationships thereof. Boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The summary and abstract sections may set forth one or more, but not all exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.