阅读说明：本技术 改善高速信令系统中接收器模拟前端带宽的分布式静电放电方案 (Distributed electrostatic discharge scheme for improving receiver analog front end bandwidth in high speed signaling system ) 是由 凯拉什·加里杜 苏哈斯·拉坦 帕拉维·穆克特什 于 2020-04-07 设计创作，主要内容包括：在所描述的方法和系统中：由相应的一组并联连接信号路径电路中的相应的开关元件选择性地提供从多线路总线的相应的线路至至少一个差分数据信号输出节点组中的至少一个相应数据信号输出节点的信号路径；以及生成一组放电电流,该组放电电流中的每一个放电电流通过流经相应的一组并联连接信号路径电路中的相应的电阻性元件所生成,以将所述多线路总线的相应的线路中的电压脉冲的一部分经相应的局部ESD保护电路放电至至少一个金属平面,相应的电阻性元件与相应的局部ESD保护电路连于相应的线路与相应的开关元件之间。(In the described method and system: selectively providing, by respective switching elements in a respective set of parallel-connected signal path circuits, a signal path from a respective line of a multi-line bus to at least one respective data signal output node in at least one set of differential data signal output nodes; and generating a set of discharge currents, each discharge current of the set of discharge currents being generated by flowing through a respective resistive element in a respective set of parallel connected signal path circuits to discharge a portion of the voltage pulse in a respective line of the multi-line bus to at least one metal plane through a respective local ESD protection circuit, the respective resistive element and the respective local ESD protection circuit being connected between the respective line and the respective switching element.)

1. An apparatus, comprising:

a set of line input nodes, wherein each line input node is connected to a respective line of the multi-line bus;

at least one set of differential data signal output nodes;

a plurality of sets of parallel connected signal path circuits, wherein each set of parallel connected signal path circuits is configured to selectively connect a respective line input node of the set of line input nodes to a respective data signal output node of the at least one set of differential data signal output nodes, wherein each signal path circuit of each set of parallel connected signal path circuits comprises:

a switching element for selectively providing a signal path from the respective line input node to the respective data signal output node; and

a resistive element and a local electrostatic discharge (ESD) protection circuit, wherein the resistive element and the local ESD protection circuit are connected between a given said line input node and said switching element to discharge a portion of a voltage pulse on a respective line through the local ESD protection circuit to at least one metal plane in the form of a discharge current flowing through the resistive element.

2. The apparatus of claim 1, wherein each line input node is selectively connected to a respective single data signal output node.

3. The apparatus of claim 2, wherein each set of differential data signal output nodes is to output a respective differential signal formed from a respective pair of signals received differentially over a respective pair of lines in the multi-line bus.

4. The apparatus of claim 1, wherein at least one line input node is selectively connected to a respective data signal output node of at least two different sets of differential data signal output nodes.

5. The apparatus of claim 4, at least one set of differential data signal output nodes to output a linear combination of signals received over at least three lines of the multi-line bus.

6. The apparatus of claim 1, wherein each line input node is disconnected from a corresponding at least one data signal output node in a power-down mode of operation.

7. The apparatus of claim 1, wherein each set of parallel connected signal path circuits provides an impedance between a respective said line input node and a respective said at least one data signal output node.

8. The apparatus of claim 7, wherein the impedance between the respective line input node and the respective at least one data signal output node is adjustable by selectively connecting portions of the respective set of parallel-connected signal path circuits.

9. The apparatus of claim 1, wherein each line input node is selectively connected to a respective said at least one data signal output node in response to initiation of a mission mode of operation for data reception.

10. The apparatus of claim 1, each local ESD protection circuit connected to the at least one metal plane through a transistor connected by a diode.

11. A method, comprising:

selectively providing, by respective switching elements in a respective set of parallel-connected signal path circuits, a signal path from a respective line of a multi-line bus to a respective at least one data signal output node in at least one set of differential data signal output nodes; and

generating a set of discharge currents, wherein each discharge current of the set of discharge currents is generated by flowing through a respective resistive element of a respective set of parallel-connected signal path circuits to discharge a portion of a voltage pulse in a respective line of the multi-line bus to at least one metal plane through a respective local electrostatic discharge (ESD) protection circuit, wherein the respective resistive element and the respective local ESD protection circuit are connected between the respective line and the respective switching element.

12. The method of claim 11, wherein respective ones of the lines are selectively connected with respective single data signal output nodes.

13. The method of claim 12, further comprising: outputting a differential signal formed from a pair of signals received differentially over a respective pair of lines of the multi-line bus.

14. The method of claim 11, wherein at least one line is selectively connected to a respective data signal output node of at least two different sets of differential data signal output nodes.

15. The method of claim 14, further comprising: outputting a linear combination of the respective at least three signals received via the at least three lines of the multi-line bus to the at least one set of differential data signal output nodes.

16. The method of claim 11, wherein each line of the multi-line bus is disconnected from the respective at least one data signal output node in a power-down mode of operation.

17. The method of claim 11, wherein each set of parallel connected signal path circuits respectively places an impedance between the respective line and the respective at least one data signal output node.

18. The method of claim 17, further comprising: adjusting the impedance between the respective line and the at least one data signal output node by selectively connecting some of the respective set of parallel-connected signal path circuits.

19. The method of claim 11, wherein each line is connected to the respective at least one data signal output node in response to initiation of a task mode of operation for data reception.

20. The method of claim 11, wherein the respective local ESD protection circuits are connected to the at least one metal plane through diode-connected transistors.

Background

In communication systems, one objective is to transfer information from one physical location to another. One commonly used information transmission medium is a serial communication link that may be based on a single wired circuit having a ground or other common reference as the object of comparison, or on a plurality of such circuits having a ground or other common reference as the object of comparison, or on a plurality of circuits acting as the object of comparison with one another. In a common example of the latter, differential signaling ("DS") is used. The working principle of the differential signaling is as follows: transmitting a signal on one line and transmitting an inverse of the signal on a counterpart line of the line; the signal information is represented by the difference between the two lines, rather than its absolute value relative to the ground or other fixed reference. Vector signaling is another example of this. By vector signaling, the multiple signals in the multiple lines can be viewed as a whole while maintaining the independence of each signal. In binary vector signaling, each component (or "symbol") of a vector takes one of two possible values. In non-binary vector signaling, the value of each symbol is a value selected from the group consisting of more than two possible values. Any subset of a vector signaling code represents a "subcode" of that code. Such a sub-code may itself constitute a vector signaling code.

Disclosure of Invention

The application describes a detection matrix for orthogonal differential vector signaling codes, wherein at least some of the code entries are summed by a passive resistor network prior to active detection of sub-channel results. This passive summing operation can reduce the negative effects of common mode signal fluctuations and increase the dynamic range of the corresponding detector.

By using this detection matrix, improvements to existing electrostatic discharge (ESD) protection circuits that are provided at device pins and rely on highly robust passive resistive elements as part thereof can be achieved. Furthermore, by employing an improved input switching scheme, the passive input network can be set to different operating modes, so that pins sharing a common passive MIC in other modes can achieve sufficient isolation between high-amplitude output signals and low-amplitude input signals in one of the modes.

In the described method and system: receiving a plurality of signals via a plurality of lines of a multi-line bus, the plurality of signals corresponding to code word numbers of a vector signaling code; generating a plurality of combined results of the vector signaling codeword symbols on a plurality of output nodes with an interconnection resistor network connected with a plurality of lines of the multi-line bus, the plurality of output nodes comprising a plurality of pairs of subchannel output nodes respectively associated with respective subchannels of a plurality of subchannels; and generating a plurality of sub-channel outputs with a plurality of pairs of differential transistors, each of the plurality of pairs of differential transistors connected with a respective one of the plurality of pairs of sub-channel output nodes.

Drawings

Fig. 1 is a circuit diagram of an ODVS subchannel detector including a passive multiple-input comparator (MIC) according to some embodiments.

Fig. 2 is a schematic diagram of a passive MIC internal interconnect resistor network according to some embodiments.

FIG. 3 is a circuit diagram of an adjustable resistor array for selectively enabling a number of resistive elements, according to some embodiments.

Fig. 4-6 are schematic diagrams of a subchannel-specific portion of an interconnection resistor network, according to some embodiments.

Fig. 7 is a schematic diagram of an interconnected resistor network including switching devices for operation in a multi-mode system, according to some embodiments.

FIG. 8 is a flow diagram of a method according to some embodiments.

Fig. 9 is a block diagram of a transceiver configured in a transmit or receive mode of operation according to some embodiments.

Fig. 10 is a block diagram of a transceiver operating in a full-duplex mode of operation according to some embodiments.

Fig. 11 is a circuit schematic of a switch used in an adjustable resistor array according to some embodiments.

Fig. 12 is a schematic diagram of an embodiment of a low impedance switch driver circuit providing greater isolation in a full duplex mode of operation.

FIG. 13 illustrates a body model (HBM) ESD protection circuit.

Fig. 14 illustrates one embodiment of a Charged Device Model (CDM) input protection circuit, according to some embodiments.

Fig. 15 is a flow diagram of a method 1500 of distributing electrostatic charge across multiple slicers of a multiple-input comparator, according to some embodiments.

Fig. 16 is a flow diagram of a method 1600 for providing greater isolation on an input side line of a full duplex communication multiple input comparator, according to some embodiments.

Detailed Description

According to [ Cronie ], orthogonal differential vector signaling codes (ODVS) are particularly suitable for use in high speed multi-line communication systems. In an explanatory view, ODVS is described as a codeword-oriented encoding/decoding method capable of providing higher performance and higher robustness. Wherein data codewords are encoded as ODVS codewords that are transmitted substantially in parallel on multiple signal lines one codeword per unit interval, and the receiver then recovers the data by detecting and decoding the ODVS codewords. In another aspect, each ODVS codeword can be interpreted as a weighted summation of a plurality of independent (e.g., orthogonal) subchannel vectors modulated in a one-to-one correspondence via respective data signals of an overall data codeword comprised of a plurality of data signals being transmitted.

In some embodiments, the ODVS code is described and defined by a matrix. Each row of the matrix can be understood as a sub-channel vector of elements that can be weighted by the corresponding signal symbols, while each column represents one line of a multi-line communication channel. As such, each individual line signal may contribute to multiple sub-channels in various combinations with other line signals.

The H4 code, also known as the enhanced non-return to zero (ENRZ) code, of [ Cronie ] is used in the following examples, but this is not meant to be limiting. The ENRZ code encodes three data bits for transmission in a four-wire channel. The definition matrix of the code is:

three data bits D₀，D₁，D₂May be encoded by multiplication with row 2 through row 4 of a Hadamard matrix H4 to obtain four output values. In such embodiments, each of rows 2-4 of the matrix of equation 1 corresponds to a respective one of the plurality of subchannel vectors. Each subchannel vector modulated or weighted by a respective data bit (taking the value +1 or-1) corresponds to a modulated subchannel. All modulation subchannels are summed to produce a codeword of the vector signaling code. From the above codeword-oriented viewpoint, the three-bit data codeword D<2：0>Encoding data into a matrix of values [ A, B, C, D ] by multiplication with lines 2 through 4 of the matrix]Forming a four-value code word. To facilitate transmission over a multi-wire bus medium, each codeword value may be added with an offset. Since the 1 st row of the matrix with all element values 1 is not used, the codewords of the resulting ENRZ code are balanced codewords, i.e. the sum of all symbols of a given codeword is 0 (or constant if an offset is added) and is a vector [ +1, -1/3, -1/3, -1/3]Or [ -1, +1/3, +1/3，+1/3]The permutation and combination form of (1). Thus, the physical line signal corresponding to a series of ENRZ codewords may take four different values.

In some embodiments, the uppermost vector of the matrix is considered to correspond to common mode signaling, and is not used in this application. Thus, each of the sub-channel vectors corresponding to rows 2 to 4 of the matrix corresponds to the set of data bits D₀，D₁，D₂The corresponding data bits therein are multiplied (i.e., modulated) to produce three modulated subchannels which are summed together to produce the codeword number a, B, C, D to be transmitted in a line of the multi-line bus.

As described in [ Cronie ], the ODVS code may be decoded by multiplying the received signal by a decoding matrix. In some embodiments, the decoding matrix may correspond to an encoding matrix or an inverse of an encoding matrix. As described in [ Cronie ], the "siervioste Hadamard (Sylvester Hadamard) matrix" is a symmetric matrix identical to its inverse. Furthermore, as described in Holden, an efficient implementation of this operation is the use of a Multiple Input Comparator (MIC). Each MIC computes a linear combination of weighted input signals, where the weight of a given MIC is determined by the corresponding subchannel vector in the detection matrix, and the output of each MIC corresponds to the antipodal subchannel output representing the transmitter input data. Thus, when encoded in the ENRZ channel, the binary data may produce antipodal MIC outputs (i.e., a single open eye in an eye diagram) that may be sampled by conventional binary signal detection methods. A set of MICs for detecting multiple ENRZ subchannels may be described by equations 2 through 4 below:

Sub₀(W1+ W3) - (W0+ W2) (formula 2)

Sub₁(W0+ W3) - (W1+ W2) (formula 3)

Sub₂(W2+ W3) - (W0+ W1) (formula 4)

The line signals W0, W1, W2, and W3 indicate the respective columns. As further described in Holden, the above equation can be effectively implemented in analog logic as three instances of a four-input differential amplifier, the implementation having multiple transistor inputs that produce two inverting and non-inverting terms with the same weight, such inverting and non-inverting terms forming the desired result by active summation.

MIC implementations that rely on active input elements may have problems with signal dynamic range and/or common mode rejection. For ODVS codes such as ENRZ codes, the latter may be a significant problem because modulation of one subchannel may produce varying common mode offsets in other subchannels.

Passive MIC implementations can address such issues. Such embodiments do not buffer and isolate the input signal by active circuit devices prior to analog computation, but rather combine the codeword symbols on pairs of sub-channel output nodes with a passive interconnection resistor network upstream of a conventional differential signal receiver or amplifier. In at least one embodiment, the interconnected resistor network may comprise three identical resistor network instances, each driven by a respective input signal permutation combination to provide a differential output on a respective pair of sub-channel output nodes provided to a respective signal receiver/differential amplifier to thereby generate three sub-channel outputs. Fig. 1 is a diagram of a specific subchannel receiver for detecting a subchannel of the above example ENRZ code, in accordance with some embodiments.

Fig. 2 illustrates an interconnected resistor network according to some embodiments. As shown, the interconnection resistor network is connected to a plurality of lines of a multi-line bus carrying signals corresponding to the character numbers of the vector signaling code. In the following description, the notations W0-W3 may correspond to the lines of a multi-line bus (on which the line signals are carried), or may be used to refer to the codeword symbols of a vector signaling code. The interconnected resistor network is used for receiving line signals corresponding to the character numbers of the vector signaling code and generating various combinations of the symbols of the vector signaling code (such as the symbol Sub) on a plurality of output nodes₀ ⁺Combinations of (ii). As shown in fig. 2, the plurality of output nodes includes a plurality of pairs of subchannel output nodes associated with respective subchannels from among a plurality of subchannels. Hereinafter, Sub₀ ⁺And Sub₀ ^-Can also be calledThe reason for this is that in some modes of operation, a MIC (such as the MIC shown in fig. 4) may pass through, for example, the line input node connected to the lines W2 and W3 and the differential data signal output node Sub₀ ⁺And Sub₀ ^-Off and operate in a non-return to zero (NRZ) mode of operation. Similar configurations may be applied to the differential data signal output nodes Sub of fig. 5 and 6, respectively₁ ⁺/Sub₁ ^-And Sub₂ ⁺/Sub₂ ^-. Differential data signal output node Sub according to above formula 2 to formula 4₀ ⁺And Sub₀ ^-Corresponding to Sub-channel Sub₀And the other two pairs of output nodes Sub₁ ⁺/Sub₁ ^-And Sub₂ ⁺/Sub₂ ^-Respectively corresponding to Sub-channels Sub₁And Sub₂. The interconnected resistor network is coupled to a plurality of pairs of differential transistors (such as the corresponding example of differential amplifier 131 of fig. 1), each of the plurality of pairs of differential transistors coupled to a corresponding one of the plurality of pairs of subchannel output nodes and configured to generate a corresponding one of a plurality of subchannel outputs.

FIG. 1 is a block diagram for detecting Sub-channel Sub according to some embodiments₀A block diagram of a subchannel receiver. In fig. 1, the line signals denoted W0, W1, W2, W3 are in this example identical to the Sub-channel Sub defined by equation 2₀The code character numbers A, B, C and D correspond to each other. In at least one embodiment, the line signal is received without further amplification or signal processing. In other embodiments, the line signal may be an output signal of an existing Variable Gain Amplifier (VGA), a Continuous Time Linear Equalizer (CTLE), or other active processing element.

As a Sub-channel Sub with the circuit of fig. 1₀In the first example of performing ENRZ detection, switches S1, S2, S3, S4 in series with resistors R1, R2, R3, R4 are all assumed to be in a closed state. In some embodiments, resistors R1-R4 are equal value resistors. In some embodiments, the resistance values of resistors R1-R4 may be adjustable, as shown in FIG. 3This will be described in further detail below. Fig. 14 illustrates a specific multi-slicer embodiment that provides adjustable resistance with multiple parallel slicers 1400, which will be described in further detail below. As shown in fig. 14, the sixteen 1400 instances may, for example, correspond to the sixteen 110 instances connected with the line W0 of fig. 1. The input signals in the lines W1 and W3 are passively summed by resistors R1 and R3 to sum with the Sub-channel Sub₀Generating a symbol Sub on a first output node of an associated pair of subchannel output nodes₀ ⁺The combined result of (1). The input signals in the lines W0 and W2 are passively summed by resistors R2 and R4 to sum with the Sub-channel Sub₀Generating a symbol Sub on a second output node of an associated pair of subchannel output nodes₀ ^-The combined result of (1). Symbol Sub₀ ⁺The combined result of (a) can be sent to the positive input (non-inverting input) of the differential amplifier 131 via the filter circuit 120, and the sign Sub₀ ^-The combined result of (a) is sent to the negative input terminal (inverting input terminal) of the differential amplifier 131 via the filter circuit 121. In the case where the values of each of the resistors R1, R2, R3, R4 are all equal, the signals are added with equal weights. In the case of using matrices with various weight sizes, using unequal values may require summing with unequal weight values. Some such matrices, such as parawing (Glasswing) matrices, are disclosed in Hormati I with various weight sizes.

As shown, according to some embodiments, the filtering circuits 120 and 121 are the same circuit made up of elements Rs and Cs connected to a termination resistor Rt for providing frequency dependent filtering and signal termination functions. In one exemplary embodiment, input series impedance (e.g., R1 in parallel with R3, etc.), a combination of Rs and Cs provides high frequency peaking, and Rt provides termination impedance for the input signal. Such filtering functions may aid in clock and data recovery or CTLE when it is desired to generate the phase error signal required for Voltage Controlled Oscillator (VCO) updating with rounded (e.g., by low pass filtering) transition sample values. Furthermore, such a filtering function may help to achieve a more rounded eye diagram with the CDR of the DFE disclosed in Hormati II when the speculative DFE sample values are taken as phase error information. In some embodiments, the adjustment of the cut-off frequency of the low pass filter may be achieved by adjusting the impedance of resistors R1-R4, which will be described in further detail below in conjunction with FIG. 3.

In one embodiment, 131 represents a differential linear amplifier implementing the subtraction of equation 2, and accordingly, the Sub-channel output Sub₀Is an analog signal representing the corresponding data signal provided to the transmitter. In another embodiment, 131 is representative of a differential comparator for performing the subtraction operation after generating the analog antipodal values by performing an amplitude slicing operation to obtain binary digital subchannel outputs corresponding to the binary data values used for subchannel modulation. In other embodiments, 131 can further contain clocked or dynamic sampling elements to acquire the state of the analog or digital result at a desired time.

The circuit of fig. 1 functions as a multi-mode subchannel receiver capable of operating in various modes in addition to the ODVS mode described above. For example, in a second ("legacy") mode, the circuit of fig. 1 may be used to operate as a data detector (also referred to as NRZ) of a conventional differential receiver. Such an embodiment may be provided by closing switches S1 and S2 (by control signals c and a, respectively) and opening switches S3 and S4 (by control signals d and b, respectively). Thus, the differential data signal output node Sub₀ ⁺And Sub₀ ^-The signals on reflect only the condition of the line signals W0 and W1 used as a conventional differential signal pair.

In some embodiments, the circuit may operate in a third mode, in which switches S1, S2, S3, S4 are all open to isolate lines W0, W1, W2, W3 from the load effects of the sub-channel receivers. Such a configuration may be used, for example, in a transmit (Tx) mode of operation where other system elements drive the lines in opposite directions. In such embodiments, each sub-channel receiver may be completely disconnected from the lines of the multi-line bus. Alternatively, a single subchannel receiver may be disconnected from the multi-line bus, while the other two subchannel receivers each act on a respective differential signal in the manner described above.

The switches S1, S2, S3, S4 are typically implemented by MOS transistors controlled by digital mode control signals (e.g., a, b, c, d) in a manner well known in the art. Fig. 4-6 are schematic illustrations of such embodiments. In some circumstances, it may be preferable to replace the MOS transistors with multi-transistor pass logic gates in order to increase signal margin or reduce distortion. Although the subchannel receiver in fig. 1 and the resistor networks in fig. 4-6 include switches for supporting multiple modes of operation, in some embodiments, these switches may be omitted by shorting terminals connected to such switches, as in the interconnected resistor network of fig. 2.

Sub-channel Sub-in addition to the connection sequence of the line signal to the input resistor₁And Sub₂May be identical to fig. 1. As shown in fig. 5, Sub₁Intermediate signal Sub is generated by combining line signals corresponding to symbols in the lines W0 and W3₁ ⁺And generates an intermediate signal Sub by combining the line signals corresponding to the symbols in the lines W1 and W2₁ ^-. Similarly, as shown in fig. 6, the line signals corresponding to the symbols in the lines W2 and W3 are combined to generate Sub₂ ⁺The line signals corresponding to the symbols in the lines W0 and W1 are combined to generate Sub₂ ^-。

Sub-channels Sub shown in fig. 4 to 6, respectively_0～2And a switching network. As shown, each resistor network receives a mode control signal for controlling a respective switch. In the following example, all three Sub-channel receivers can operate either in ODVS mode, which combines the line signals on each pair of Sub-channel output nodes, or in "legacy" mode, in which the Sub-channel receivers Sub0 and Sub1 receive the respective differential pair signals and turn off the Sub-channel receiver Sub2 (e.g., disconnected from the bus). Such modes of operation are shown in table I below. In the first mode, all switches are enabled and each pair of subchannel output nodes generates a subchannel output corresponding to the detected ODVS subchannel according to equations 2 through 4 described aboveAnd (6) discharging. In the second mode, the switches controlled by the mode control signals a and c are enabled, while all other switches are disabled. In such embodiments, a differential output between the line signals on lines W1 and W0 is generated on a pair of Sub-channel output nodes associated with Sub-channel Sub0, and a differential output between the line signals on lines W3 and W2 is generated on a pair of Sub-channel output nodes associated with Sub-channel Sub 1. Fig. 7 shows the interconnected resistor network of fig. 2 further including a mode select switch for enabling the multi-mode operation. In the third mode (transmit mode), the entire interconnect resistor network is disconnected to isolate the receive circuits, while transmit drivers are connected to the lines. In a fourth mode (full duplex mode), the interconnection resistor network is connected with two lines of the multi-line bus to obtain a differential signal, while the remaining two lines may be connected with the transmit driver to transmit a differential signal. Such other modes are shown in table I below and fig. 9 to 10.

TABLE I

In some embodiments, the interconnected resistor network is part of a transceiver that includes a plurality of drivers for driving symbols into lines of a multi-line bus, as described above. In such embodiments, the driver and interconnect resistor network may be selectively connected with the multi-wire bus in a transmit mode or one of the receive modes described above (e.g., ODVS and differential signaling modes, or "legacy" mode). Fig. 9 is a block diagram of a transceiver 900 according to some embodiments. As shown, the transceiver 900 includes a plurality of transmit drivers 905 and an interconnected resistor network 915 as described above. In some embodiments, transceiver 900 may further include an encoder (not shown) for receiving a set of input data and encoding the set of input dataResponsively providing control signals to the driver to generate codeword symbols of a vector signaling code in the multi-wire bus. The transceiver further includes a mode controller 920 operable to provide the multi-bit mode control signal according to a selected mode. In the transceiver 900 of fig. 9, the multi-bit mode control signal is made up of 8 signals a-h, m, n for controlling the switches within the interconnected resistor network 915 as described above and shown in fig. 7, and four additional signals i, j, k, l for providing to a set of driver switches 910. In some embodiments, each signal i-l may be provided to a respective driver switch for connecting or disconnecting a respective driver to a respective line of the multi-line bus. Specifically, signal i may be provided to the driver associated with line W0, signal j may be provided to the driver associated with line W1, signal k may be provided to the driver associated with line W2, and signal l may be provided to the driver associated with line W3. Table I includes two additional modes employing such driver mode control signals. In a full transmit mode, the interconnection resistor network 915 may be fully disconnected from the multi-wire bus, each driver connected to a respective wire, and wire signals driven into the multi-wire bus. In some embodiments, a full duplex mode may be set in which differential input signals received via lines W0 and W1 are compared and output signals are transmitted via respective transmit drivers within lines W2 and W3. Such an implementation may require the use of additional mode control signals, since the configuration shown in fig. 7 should not be able to reuse control signals a and c. In such embodiments, lines W2 and W3 are connected to Sub-channel output nodes Sub, respectively₁ ^-And Sub₁ ⁺May receive control signals m and n. In the configuration shown in FIG. 10, to achieve this full-duplex mode of operation, driver switch 910 uses 4 mode control signals i-l and interconnection resistor network 1015 uses 10 mode control signals a-h, m, n. As shown, the interconnected resistor network 1015 includes line input nodes 1020, 1025, 1030, 1035 connected to lines W0, W1, W2, W3, respectively, of a multi-line bus. In some embodiments, selection may be based on a variety of factorsAnd a differential line pair for transceiving. In some embodiments, the differential line pairs may be selected according to relative proximity. For example, two lines of a differential line pair used for transceiving may preferably be adjacent to each other and/or extend along similar trace traces. Another factor that may have an impact on the selection may be the orientation of the cable/connector interface (e.g., using a "two-way plug-in" type cable).

In some embodiments, a plurality of mutually orthogonal sub-channels are detected by a transceiver operating in a half-duplex mode of operation with a plurality of MICs as described above. Such transceivers may also be used to transmit and receive differential signals over different pairs of differential lines for operation in the full-duplex mode described above. The transceiver may be used for medium to high loss communication channels where the amplitude of the received input signal may be tens of decibels lower than the amplitude of the transmitted signal in a full duplex mode of operation, and a simple MOS switch may not provide a sufficiently high signal isolation when a pair of lines used to transmit the output signal in a configuration of such a mode is open. Taking the fig. 1 input system as an example, the full-duplex operating mode may be initiated by closing switches S1 and S2 and opening switches S3 and S4 in fig. 1 to use a pair of differential lines W0 and W1 for receiving differential input signals and releasing W2 and W3 for use as transmit lines carrying differential output signals propagating in opposite directions, but this is not meant to be limiting. In this case, the signal isolation (in some cases, at least 30dB) provided by switches S3 and S4 in their "off" state may prevent degradation of the quality of the received differential input signal due to the transmitted differential output signal feedthrough. In contrast, parasitic coupling effects within and around the simple MOS transistor switch may dominate over the isolation.

In such an environment, a high isolation input switch as shown in the embodiment of fig. 12 may be used. Instead of a single MOS device, each switch includes two series MOS transistors 1210 and 1220 commonly driven by an enable signal en, the interconnection node 1215 of which is configured to be driven by complementary enable signalsSwitching to ground by MOS transistor 1230 forms a shunt path that greatly reduces the coupling of the drain-source parasitic capacitance of transistor 1210 to the signal and similarly reduces the coupling of the parasitic capacitance of the receiver input through transistor 1220 to the signal in the active state. However, there are still similar signal potential paths as follows: starting at the input pin, the drain-gate capacitance is traversed 1210, followed by a path 1220 to the receiver input. To minimize signal conduction in this path, low impedance switch driver 1250 includes a high frequency low impedance enable signal path output for shunting cross-coupled interference signals from the pair of transmit lines, which means that two larger output drive transistors MSW1 and MSW2 are used simultaneously. In one embodiment, the expected improvement in the off-isolation in the full-duplex mode of operation is achieved by increasing the size of the low impedance switch driver output transistors MSW1 and MSW2 to ten to sixteen times the size of the switch transistors 1210, 1220, 1230. In an alternative embodiment, only one of the transistors of the low impedance switch driver is increased in this manner, for example, the drive transistor used to achieve the output state that brings transistors 1210 and 1220 into the off state (e.g., NMOS output transistor MSW2 that drives signal en low when transistors 1210 and 1220 are NMOS enhancement mode devices) is increased because this device is the device that provides the low impedance enable signal path to ground as shown in fig. 12.

In one embodiment, the apparatus includes a multi-line data bus having at least four lines and a plurality of pairs of subchannel output nodes, each pair for detecting a subchannel vector with a corresponding set of subchannel receivers (e.g., samplers, amplifiers, or so-called slicers). Each line of the multi-line bus is selectively connected to each pair of sub-channel output nodes in a line branching circuit having at least one respective resistor and a respective T-switch (previously called a resistor switch slicer) controlled by a low impedance switch driver circuit. The apparatus also includes a mode controller for selectively enabling (i) a half-duplex communication mode by connecting each line to the pair of sub-channel output nodes after enabling the T-switch with the at least four lines of the overall receiver, or (ii) a full-duplex communication mode using the at least two lines for a differential transmit channel by disabling the T-switch to the at least two lines to subsequently disconnect the at least two lines from the set of node pairs, wherein the low impedance switch driver circuit shunts parasitic path signal energy leaked from the differential transmit channel.

Fig. 16 is a flow diagram of a method 1600 according to some embodiments. As shown, method 1600 includes: in a half-duplex mode of operation with multiple-input comparators (MICs) to detect multiple mutually orthogonal sub-channels, a set of at least four input signals is received 1602 by a MIC among the multiple MICs. Each input signal is received over a respective line of the multi-line bus. In some embodiments, each line is connected to the MIC by a respective plurality of resistor switch slicers. Each respective set of multiple resistor switch slicers may include up to sixteen resistor switch slicers. However, this embodiment should not be considered limiting, and more or fewer resistor switch slicers may be used.

Each MIC of the plurality of MICs thereupon generates 1604 a respective linear combination of the set of at least four input signals to detect an orthogonal subchannel among the plurality of mutually orthogonal subchannels. The method further comprises the following steps: a full-duplex mode of operation is initiated 1606 by selectively disconnecting a pair of lines of the multi-line bus from the MIC with a T-switch within the MIC in response to a respective enable signal being provided via a low impedance enable signal path within a respective low impedance switch driver. The enable signal may be provided to a portion of respective resistor switch slicers for a given line among the plurality of resistor switch slicers. In some implementations, at least one of the plurality of respective resistor switch slicers has an impedance element that is twice as large as at least one other of the plurality of respective resistor switch slicers.

The selected pair of lines may then transmit a differential output signal in full duplex mode. In some embodiments, the selectively opened pair of lines of the multi-line bus corresponds to lines on opposite sides of an associated differential subchannel output node of the MIC. For example, generating differential subchannel output nodes Sub as shown in fig. 4₀ ⁺/Sub₀ ^-Lines W0 and W2 are on opposite sides of the differential subchannel outputs of lines W1 and W3 in the MIC of (1). Thus, in one such embodiment, one of the lines W0 and W2 and one of the lines W1 and W3 may be open simultaneously. In some cases, the pair of lines that are disconnected from the MIC is selected according to the proximity of the lines. For example, two lines of a differential line pair used for transceiving may preferably be adjacent to each other and/or extend along similar trace traces. Another factor that may have an impact on the selection may be the orientation of the cable/connector interface (e.g., using a "two-way plug-in" type cable).

In a full duplex mode of operation, cross-coupled jammer signals from the pair of lines are shunted 1608 through a low impedance enable signal path within the low impedance switch driver. The cross-coupled interference signal may be shunted through a transistor in the low impedance switch driver, where the transistor in the low impedance switch driver is at least 10 times larger in size than a transistor in the T-switch.

The method further comprises the following steps: in a full-duplex mode of operation, generating 1610 a differential output by comparing input signals received by at least two remaining lines of the multi-line bus connected to the MIC in the full-duplex mode of operation.

In embodiments where the input switches are rarely reset (i.e., as an initialization option rather than a dynamic half-duplex transceive function), the ac impedance to ground of the common gate path can be reduced by adding the bypass capacitor 1270, at the cost of significantly slowing the switching speed and increasing the transient current consumption of the driver. If conduction of such a potential leakage path is found to cause problems only at very high frequencies, by deliberately increasing the drive path inductance as shown at 1280, the path impedance can be increased sufficiently by means of the common gate connection, thereby reducing conduction of signals. In other embodiments, the resistance between the MOS gates need only be increased, or the bypass capacitance may be increased at the same time.

In other embodiments, some or all of the switching transistors shown in fig. 12 may be replaced with CMOS pass logic gates composed of multiple MOS transistors to increase input range and/or linearity.

In some embodiments as shown in fig. 14, an enable signal may be provided by a single low impedance driver switch 1250 to a plurality of resistor switch slicers (also referred to herein as signal path circuits) 1400 of a line branch, such that the plurality of resistor switch slicers of the line branch share the low impedance enable signal path. As shown in fig. 14, the W0 line branch for a given passive MIC has a set of sixteen resistor switch slicers 1400 as described above. As shown, binary inputA set of five low impedance switch drivers 1250 are provided that provide enable signals to the set of sixteen resistor switch slicers 1400 that branch to the W0 line. The number of low impedance switch drivers 1250 and resistor switch slicers 1400 shown in fig. 14 should not be considered limiting. Binary inputEach bit is provided to a corresponding low impedance switch driver 1250. Each low impedance switch driver 1250 provides a respective enable signal en to a respective set of resistor switch slicers 1400 of the W0 line branch<4:0>. As shown, to achieve binary control of the MIC's effective impedance, a low impedance switch driver provides an enable signal (e.g., en) to a set of eight resistor switch slices<4>) Another low impedance switch driver provides for a set of four resistor switch slicersEnable signal (e.g. en)<3>) And so on. Complementary enable signalsSupplied to and enable signal en<4:0>The corresponding resistor switch slicer, that is,and en<4>The same eight resistor switch slicers are provided,and en<3>The same four resistor switch slicers are provided, and so on. In some embodiments, the R1 value for one of the sixteen resistor switch slices may be twice as large as the R1 values for the remaining 15 resistor switch slices to achieve greater resolution, as will be described below in conjunction with fig. 3. Such a dual-resistance resistor switch slicer may have a response, for example, toOperates and generates an enable signal en<0>A dedicated low impedance switch driver.

In one non-limiting embodiment, each line branch of a given MIC may include five low impedance switch drivers for controlling a set of sixteen resistor switch slicers 1400. Each MIC includes four line branches and therefore a total of twenty low impedance switch drivers. The three sub-channels MIC comprise sixty low impedance switch drivers in total.

In some embodiments, the amount of high frequency peaking achieved by circuit 121 may be varied by varying the effective input series impedance of the line signal. In another embodiment, each resistor/switch combination 110 (e.g., R1 and S1) of FIG. 1 is implemented as a plurality of sets of series resistors and switches as shown in FIG. 3 connected in parallel. As a non-limiting example, each resistor R21-R28 has a value of 8R 1, and each switch S21-S28 is a controllable MOS transistor switch. In this embodiment, eight different effective series resistances may be generated across the combination 110 by activating one to eight of the switches S21-S28, thereby generating eight different high frequency peaking characteristics for the combined ENRZ sub-channel detector. As described above, one of the resistance values (e.g., R28) may be twice the remaining resistance values, thereby achieving greater resolution when adjusting the high frequency peaking characteristics and/or bandwidth limit settings of the received input signal. In a practical implementation, each instance of 110 in fig. 1 is replaced by the instance of fig. 3 containing sixteen parallel resistors, while the number of closed switches for a given instance in fig. 3 may be 0 (to open the input in the second or third mode of operation, as described below) or a preset value to achieve the desired frequency characteristic associated with the determined impedance value. Attenuation of high frequency signals by adjusting resistor resistance can facilitate baud rate Clock Data Recovery (CDR) applications and reduce bandwidth with lower channel loss. Since the receiver and the transmitter have a common front end, the passive MIC may completely isolate the receiver from the transmitter by opening all switches, and thus may increase the frequency response. In some embodiments, the secondary protection device consisting of a diode and a resistor (often called CDM diode and resistor) and used to prevent CDM failure of the system may be replaced by a single CDM (charged device model) diode. In this manner, the frequency response may be increased.

In an alternative embodiment, by placing series input resistors such as R1, R2, R3, R4, etc. shown in fig. 1 between the physical input pins and the active device circuit, opportunities for optimization of other device elements may also be created. For example, each external device connection needs to be protected from electrostatic discharge (ESD) to prevent excessive static discharge through the sensitive electronics of the device. An example of such ESD protection is given in [ ghanibousi ], from which fig. 13 is also taken. As described therein, the peak discharge current can be controlled by inserting a small inductive element in series with the input signal, so that a set of distributed protection diodes can direct the remaining fault current out of the main discharge path.

In contrast, embodiments such as that shown in FIG. 1 may employ ESD protection as shown in FIG. 14. Line input node 1405 may be, for example, an external bond pad, and is isolated from input switches 1410, 1420, 1430 and downstream active circuitry (e.g., MIC or CTLE receiver front end) by a series resistor 1440, which is R1 in fig. 1. In one embodiment, a set of signal path circuits 1400 is implemented as a parallel circuit. As such, the resistance of any one signal path circuit 1400 in the set of parallel signal path circuits increases proportionally, and thus the fault current discharged via any one instance becomes proportionally smaller. This scheme does not provide protection with junction diodes or schottky diodes, but rather CDM protection with very small diode-connected MOS transistors 1480 and 1490. In the circuit of fig. 14, in the power down mode, all of the parallel signal path circuits 1400 of each line are used to discharge a portion of the voltage pulse on that line. However, in a data receive mode of operation, a portion of all signal path circuits may be enabled at a particular point in time to set the effective impedance at a channel bandwidth control setting, e.g., according to the number of parallel signal path circuits enabled. The less parallel signal path circuitry enabled, the less the total output capacitance. When a larger ESD protection device is placed between the MIC and the sets of differential data signal output nodes of CTLE 1460, a relatively large constant capacitance will be formed at the input of CTLE 1460. By distributing the ESD protection circuits with the set of parallel signal path circuits, in contrast, the advantage of reducing the total capacitance obtained by the ESD protection device in the data reception mode of operation may be further realized.

As shown in fig. 14, a set of parallel connected signal path circuits 1400 selectively connects the line input node W0 to respective data signal output nodes of at least one set of differential data signal output nodes. The set of parallel connected signal path circuits 1400 may be one of a plurality of sets of parallel connected signal path circuits, wherein each set of parallel connected signal path circuits selectively connects a respective line input node to a respective data signal output node of the at least one set of differential data signal output nodes. In fig. 10, signal path circuit 1040 may correspond to a set of sixteen parallel-connected signal path circuits 1400 shown in fig. 14. In fig. 14, each of the set of parallel connected signal path circuits 1400 includes a switching element, e.g., an isolation switch comprised of transistors 1410, 1420, 1430, for selectively providing a signal path from a given line W0 to a corresponding data signal output node within a MIC connected to a Linear Tail Equalizer (LTE) 1450. In addition, each signal path circuit 1400 includes a resistive element 1440 and a local ESD protection circuit, shown in fig. 14 as diode-connected transistors 1480 and 1490. The local ESD protection circuit is connected between line W0 and the switching element to discharge a portion of the voltage pulse on the given line through the local ESD protection circuit to one or more metal planes as a discharge current through the resistive element. One specific implementation of R-2R based LTE that can be used as LTE 1450 is described in [ ranttan I ], but as an alternative, known LTE can also be used.

In some embodiments, each given line input node is selectively connected to a single respective data signal output node within the MIC, each data signal output node being connected to an input of LTE 1450. In such embodiments, each set of differential data signal output nodes is for outputting a respective differential signal formed from a respective pair of signals received differentially via a respective pair of lines of the multi-line bus. Alternatively, at least one line input node may be selectively connectable to a respective data signal output node of at least two different sets of differential data signal output nodes. Such embodiments may be used to output a linear combination of signals received over at least three lines of the multi-line bus. In such embodiments, since the signal received via the line W0 may be used in various linear combinations for detecting a plurality of mutually orthogonal sub-channels, the line input node connected to the line W0 may be simultaneously connected to the data signal output nodes of a plurality of MICs.

In some embodiments, in the power-down mode of operation, each line input node of the set of line input nodes is disconnected from at least one respective data signal output node. In the power-down mode of operation, the voltage pulse may be discharged through the local ESD protection circuit to the metal plane to provide CDM protection. In some embodiments, a respective set of signal path circuits sets an impedance between the given line and at least one respective data signal output node. In such embodiments, the impedance between the given line and at least one respective data signal output node may be adjusted by selectively connecting portions of the signal path circuits of a respective set of signal path circuits. In some embodiments, each given line is connected to at least one respective data signal output node upon initiation of a mission mode of operation in response to data reception.

FIG. 15 is a flow diagram of a method 1500 according to some embodiments. As shown, the method 1500 includes: for each line in the multi-line bus, a signal path is selectively provided 1502 from the line to at least one respective data signal output node in the at least one set of differential data signal output nodes, respectively, with a respective switching element in a respective set of parallel-connected signal path circuits. For each line, respectively 1504 a set of discharge currents is generated, each discharge current of the respective set of discharge currents generated for the respective line flowing through a respective resistive element of the respective set of signal path circuits to discharge a portion of a voltage pulse in the respective line of the multi-line bus through a respective local ESD protection circuit to one or more metal planes, the respective resistive element and the respective local ESD protection circuit being connected between the respective line and the respective switching element.

In some embodiments, the mode of operation may be set by controlling the switch circuit S2 within the resistor circuit 110 with a single mode control bit a, as shown in fig. 1. The resistor circuit 110 may further include an adjustable impedance element including a plurality of switched resistor circuits connected in parallel as shown in fig. 3, wherein the multi-bit impedance control signal sets the impedance value of R2 by controlling the switches S21 to S28, and the mode switch controlled by the mode control signal a sets the operation mode. In some embodiments, the control signals provided to S21-S28 and the mode control signal a may be logically ANDed such that the impedance value connects only line W0 to the output node depending on the mode set by the mode control signal a.

Fig. 11 is a circuit schematic of a switch (e.g., switch S21) according to some embodiments. As shown in fig. 11, the switch is composed of an NMOS transistor embedded in a P-well and further using a deep N-well (DNW). Such embodiments may isolate the parasitic capacitance of the switches within the resistor network from the matching network to reduce transmission losses. In other embodiments, the elements shown in FIG. 11 may be further combined with the elements described above in connection with FIG. 12.

In other embodiments, the sets of digitally controlled resistors and/or capacitors used to adjust the frequency characteristics of 120 and 121 may be used either alone or in combination with the embodiments described above.

In embodiments where the effective input series impedance is varied by the circuit of fig. 3, this is in addition to the Sub-channel in the "conventional" mode of operation described above₂As with the case where the associated pair of subchannel output nodes is completely open, the number of closed switches per example of fig. 3 may remain constant between all examples and all subchannel receivers, except for the example where all switches are open.

As described in Holden, detection of other ODVS codes can be achieved by adjusting the input resistor resistance values to produce other input weighting ratios. In a system environment where both original and complementary versions of the input signal are available (e.g., from an active CTLE processing stage with differential output), both in-phase and anti-phase signal values may be resistively summed prior to active detection.

Fig. 8 is a flow diagram of a method 800 according to some embodiments. As shown, the method 800 includes: receiving 802 a plurality of signals via a plurality of lines of a multi-line bus, the plurality of signals corresponding to code word numbers of a vector signaling code; generating 804 multiple combinations of codeword symbols of the vector signaling code generated on multiple output nodes in an interconnected resistor network connected to multiple lines of the multi-line bus, wherein the multiple output nodes include multiple pairs of sub-channel output nodes respectively associated with respective ones of multiple sub-channels; and generating 806 a plurality of sub-channel outputs with a plurality of pairs of differential transistors, each pair of differential transistors among the plurality of pairs of differential transistors connected with a respective pair of sub-channel output nodes among the plurality of pairs of sub-channel output nodes.

In some embodiments, the plurality of combinations of code word symbols are generated by adding two or more signals corresponding to the code word symbols. In some embodiments, the plurality of combinations of codeword symbols is generated by forming an average signal of two or more signals corresponding to the codeword symbol.

In some embodiments, as shown in fig. 2, each output node of the plurality of output nodes is connected to two or more lines of the plurality of lines of the multi-line bus through a respective resistor of a plurality of resistors. In some embodiments, the plurality of resistors have equal resistance values. In some embodiments, as shown in fig. 3, each resistor of the plurality of resistors has an adjustable impedance. In the parallel resistor network of fig. 3, the method further includes selectively enabling one or more resistors in the parallel resistor network to set the adjustable impedance. Some such embodiments include: receiving, by the parallel resistor network, a multi-bit impedance control signal, wherein the multi-bit impedance control signal represents an impedance value of the adjustable impedance. In some embodiments, the degree of high frequency peaking of the plurality of sub-channel outputs is adjusted by adjusting the adjustable impedance. This may be useful for CDR and CTLE applications.

In some embodiments, the method further comprises: the operation mode is selected with a plurality of mode selection transistors that selectively connect/disconnect one or more lines with/from one or more output nodes among the plurality of output nodes. Some such embodiments may include: connecting a respective one of a plurality of lines of the multi-line bus with a respective one of the plurality of output nodes. In such embodiments, each subchannel output among the plurality of subchannel outputs corresponds to a differential output across two lines among a plurality of lines of the multi-line bus, as described above in the "legacy" mode of operation.

In some embodiments, the plurality of subchannels corresponds to a plurality of subchannel vectors modulated by respective input data signals among a plurality of input data signals. In some such embodiments, the plurality of subchannel vectors correspond to mutually orthogonal rows within an orthogonal matrix.