阅读说明：本技术 面向Wimax协议的QC-LDPC译码器译码方法及系统 (Wimax protocol-oriented QC-LDPC decoder decoding method and system ) 是由 李丽 蒋林 傅玉祥 武瑞琪 徐瑾 陈辉 何书专 李伟 陈铠 何国强 于 2021-06-30 设计创作，主要内容包括：本发明提出了一种面向Wimax协议的QC-LDPC译码器译码方法及系统,基于提出的面向Wimax协议的QC-LDPC译码器,利用存储的QC-LDPC校验矩阵信息,简化了译码器的译码计算复杂度,同时节省了硬件计算资源。其中,译码过程采用基于Offset Min-sum的行分层译码算法作为译码方法,使得硬件兼容性更广、且具备易于实现的优点。通过流水化设计,对校验矩阵信息读取、映射,实现了高效流水LDPC译码；最终可支持IEEE 802.16e通信协议下,1/2码率19种码长的LDPC译码运算；因此本发明具有硬件复杂度低,存储资源利用率高的特点,以及可实现高吞吐率LDPC译码运算。(The invention provides a Wimax protocol-oriented QC-LDPC decoder decoding method and system, which utilize stored QC-LDPC check matrix information to simplify decoding calculation complexity of a decoder and save hardware calculation resources at the same time based on the proposed Wimax protocol-oriented QC-LDPC decoder. In the decoding process, an Offset Min-sum-based line layered decoding algorithm is used as a decoding method, so that the hardware compatibility is wider and the method has the advantage of easy implementation. Through stream design, the check matrix information is read and mapped, and high-efficiency stream LDPC decoding is realized; finally, the LDPC decoding operation with 1/2 code rates and 19 code lengths can be supported under the IEEE802.16e communication protocol; therefore, the invention has the characteristics of low hardware complexity and high utilization rate of storage resources, and can realize high-throughput LDPC decoding operation.)

1. A QC-LDPC decoder oriented to Wimax protocol, comprising: the decoding controller, the storage unit and the arithmetic unit module; the decoding controller is used as a framework for connecting the storage unit and the operation unit module and is used for realizing data interaction between the storage unit and the operation unit module;

the decoding controller is arranged to read, distribute, operate and store the calculation result of the data required by decoding operation;

the storage unit is configured to store variable node information, check node information and check matrix information;

the operation module is configured to update the variable node information and the check node information.

2. The Wimax protocol oriented QC-LDPC decoder according to claim 1,

the decoding controller further comprises an operation control module, an address generation module and a distribution module;

the operation module further comprises a node updating unit; the updating unit updates the variable node information while updating the check node information by adopting a flow design in the decoding process;

the node update unit includes: the device comprises a fixed point adder, a fixed point comparator, an exclusive or calculation module and an absolute value calculation module;

the storage unit is divided into three groups of data storage blocks according to requirements, and the first group of data storage blocks are used for storing the variable node information; the second group of data storage blocks are used for storing check node information; and the third group of data storage blocks is used for storing check matrix information.

3. The Wimax protocol oriented QC-LDPC decoder according to claim 2,

the fixed point comparator is used for a minimum value and secondary minimum value calculation module, the calculation module needs to find out the minimum value and the secondary minimum value from absolute values of variable nodes, the calculation module is composed of structures COM2 and COM4, comprises a comparator and a selector, calculates time division 3-level flow to find the minimum value and the secondary minimum value, and presets the number of input numerical values according to requirements.

4. A Wimax protocol oriented QC-LDPC decoding method using a decoder comprising any one of claims 1 to 3, characterized by comprising the steps of:

step one, presetting iteration times, initializing check node information and variable node information, and setting the current iteration times to be 1;

receiving data sequence information to be decoded, and storing the data sequence information to a storage unit according to a divided data storage block region;

reading check matrix information in the storage unit by the decoding controller, and updating check node information and variable node posterior probability information in a layering manner by combining an operation module;

step four, after the iteration times are added by 1, judging whether the current iteration value is larger than a preset value, and if so, jumping to step five; otherwise, jumping to the third step;

stopping decoding, outputting decoded code word information, and calculating and acquiring a sign bit of the variable node posterior probability by adopting fixed point data;

and sixthly, carrying the sign bit of the posterior probability of the ratio variable node to a storage unit to be used as a final result code word, and finishing the decoding process.

5. The method for QC-LDPC decoding oriented to the Wimax protocol according to claim 4,

the expression for calculating the variable node update by adopting the input end of the node update unit is as follows:

the expression of the posterior probability information of the node update and variable nodes updated by the output end of the node update unit is as follows:

the updating expression of the check node message is as follows:

in the formula, t represents the number of iterations; k represents the current update to the k layer; (t, k) represents the kth layer operation in the tth iteration;when the kth layer in the t iteration is represented, the variable nodes in the mth row and the lth column in each layer of matrix are transmitted to the check nodes;representing the posterior probability of the variable node l when the operation reaches the kth layer in the t iteration;representing the message transmitted to the variable node by the check node of the mth row and the lth column in each layer of matrix in the t iteration; l (m) \\ l represents a set of variable nodes adjacent to the check node m, and an exit node l; β represents an offset factor.

6. The method for QC-LDPC decoding oriented to the Wimax protocol according to claim 4,

when the check node information and the variable node posterior probability information are updated hierarchically, the updating steps of the information nodes corresponding to the ith iteration and the jth layer of check matrix information are as follows:

the decoding controller controls the check matrix information address generation module to take out the data information of the j-th layer of check matrix from the check matrix information storage area;

a check node information address generating module and a variable node information address generating module find the check nodes and the variable nodes which need to be updated in the current layer according to the check matrix data information and take out data;

the check node information distribution module and the variable node information distribution module send the taken data to the operation unit;

after the operation of the operation unit is completed, the updated check node and variable node values are sent to a check node information distribution module and a variable node information distribution module;

and the check node information address generating module and the variable node information address generating module store the check nodes and the variable nodes in situ according to the check matrix data information and complete the information node updating corresponding to the ith iteration jth layer check matrix information.

7. The method for QC-LDPC decoding oriented to the Wimax protocol according to claim 4,

the check matrix information is a sparse matrix, the position of the variable node needing to be updated each time is positioned according to the sparse check matrix information in the decoding process, and the calculation process of the updated position of the variable node is converted into a data mapping relation.

8. The method for QC-LDPC decoding oriented to the Wimax protocol according to claim 4,

when a decoding process is executed, the posterior probability initialization is hidden in the data storage process, namely the decoded source data storage process is used as the posterior probability initialization; and initializing and hiding the check node message in the first iterative computation, namely fixing the check node message to the data 0 when the check node message is obtained in the first iterative computation.

9. The method of claim 7, wherein the QC-LDPC decoding method for Wimax protocol,

expressing the position information of '1' in each row of the check matrix by using a preset bit value;

further dividing three groups according to a preset size, wherein the first group is used for representing the data storage block in which the '1' in each row of the check matrix is; the second group is used to represent the location of a "1" in each data storage block; the third group is used to represent the storage location of the location information of "1" in the data storage block in the second group.

10. A Wimax protocol-oriented QC-LDPC decoding system for implementing the decoding method of any one of claims 4 to 9, comprising:

an initialization module configured to initialize the corresponding parameter; the corresponding parameters comprise a preset iteration total coefficient, check node information and variable node information, and the current number of times of initialization iteration is 1;

a data receiving module configured to receive a data sequence to be decoded;

the decoder is arranged for receiving the data sequence acquired by the data receiving module and decoding the data sequence, and further comprises a decoding controller, a storage unit and an operation unit;

and the data output module is set to output the final decoding result of the decoder.

Technical Field

The invention relates to a Wimax protocol-oriented decoding method and system for a QC-LDPC decoder, in particular to the technical field of QC-LDPC decoding.

Background

The LDPC Code is called a Low Density Parity Check Code (Low Density Parity Check Code) and is a linear block Code having a sparse Check matrix. The main characteristic is the sparsity of the check matrix, i.e. the density of '1' in the check matrix is very low, and the longer the code length is, the lower the density is. The LDPC code has good error code performance which can approach to the Shannon limit, and in recent years, various related technologies of the LDPC code are rapidly developed and widely used in the field of communication, so that the LDPC decoder with high research performance and simple hardware implementation is very important.

Compared with the LDPC coding implemented by software, the LDPC coding implemented by hardware is extremely complex, so that the early LDPC coding implementation is basically in a software level and is difficult to map to a hardware level. In recent years, with the breakthrough of researchers to the study of LDPC decoding related algorithms, LDPC decoding algorithms suitable for hardware are continuously appearing, and from an initial probability-based LDPC iterative decoding algorithm, a logarithm-based LDPC iterative decoding algorithm to a subsequent min-sum algorithm, it becomes easier for hardware to implement an LDPC decoder.

However, the traditional LDPC decoder too much pays attention to the mapping implementation of the algorithm in the hardware implementation, and does not consider many characteristics of the LDPC code itself, and not only uses a large amount of hardware storage resources but also occupies many computing resources in the specific implementation, which puts higher demands on the wiring and timing in the hardware implementation process.

Disclosure of Invention

The purpose of the invention is as follows: a method and a system for decoding a QC-LDPC decoder oriented to a Wimax protocol are provided to solve the problems in the prior art. Through the stored QC-LDPC check matrix information, the decoding calculation complexity of the decoder is simplified, thereby saving hardware calculation resources and overcoming the defects of the prior art.

The technical scheme is as follows: in a first aspect, a Wimax protocol-oriented QC-LDPC decoder is provided, where the decoder specifically includes: the device comprises a decoding controller, a storage unit and an arithmetic unit module. The decoding controller is used as a framework for connecting the storage unit and the arithmetic unit module and is used for realizing data interaction between the storage unit and the arithmetic unit module. By using the check matrix information stored in the storage unit, the decoding calculation complexity of the decoder can be simplified, and hardware calculation resources can be saved.

In an implementation form of the first aspect, the decoding controller is configured to implement reading, distribution, operation of data required for decoding operation, and storage of calculation result, for controlling a work flow of the decoder. Further comprising: the device comprises an operation control module, an address generation module and a distribution module.

A storage unit configured to store variable node information, check node information, and check matrix information; the unit is divided into three groups of data storage blocks according to requirements, wherein the first group of data storage blocks is used for storing the variable node information; the second group of data storage blocks are used for storing check node information; and the third group of data storage blocks is used for storing check matrix information.

The operation module is arranged for updating the variable node information and the check node information, and further comprises a node updating unit, wherein the node updating unit adopts a flow design to update the check node information and the variable node information in the decoding process.

Wherein, the node updating unit includes: the device comprises a fixed point adder, a fixed point comparator, an exclusive OR calculation module and an absolute value calculation module. In a further embodiment, since the check matrix of the QC-LDPC code in the 802.16 standard has row weight of 6 to 2/3 and row weight of 7 to 1/3, the number of input and output information of the node operation unit is at most 14 and at least 12. The fixed point comparator is used for a minimum value and secondary minimum value calculation module, the module needs to find out the minimum value and the secondary minimum value from absolute values of 7 or 6 input variable nodes, the module is composed of basic structures COM2 and COM4, the basic structures COM2 and COM4 comprise 13 comparators and 20 selectors in total, the minimum value and the secondary minimum value are found in 3-level flow of calculation time division, and the calculation unit is set to be 8 input for convenient calculation.

In a second aspect, a Wimax protocol-oriented QC-LDPC decoding method is provided, which specifically includes the following steps:

step one, presetting iteration times, initializing check node information and variable node information, and setting the current iteration times to be 1;

receiving data sequence information to be decoded, and storing the data sequence information to a storage unit according to a divided data storage block region;

reading check matrix information in the storage unit by the decoding controller, and updating check node information and variable node posterior probability information in a layering manner by combining an operation module;

step four, after the iteration times are added by 1, judging whether the current iteration value is larger than a preset value, and if so, jumping to step five; otherwise, jumping to the third step;

stopping decoding, outputting decoded code word information, and calculating and acquiring a sign bit of the variable node posterior probability by adopting fixed point data;

and sixthly, carrying the sign bit of the posterior probability of the ratio variable node to a storage unit to be used as a final result code word, and finishing the decoding process.

In an implementation manner of the third aspect, the decoding process using row-level coding is as follows:

the data sequence information to be decoded received by the decoder is y ═ y (y)₀,y₁,...,y_n-1) The check matrix is divided into K layers, and the column weight of each layer of submatrix is at most 1. t represents iteration times, k represents that the message is updated to the kth layer, and both t and k are 0 during initialization; (t, k) denotes the kth layer operation in the t-th iteration.Representing the posterior probability of the variable node l when the operation reaches the kth layer in the t iteration;representing the message transmitted to the variable node by the check node of the mth row and the lth column in each layer of matrix in the t iteration;and when the k layer in the t iteration is represented, the variable node of the mth row and the lth column in each layer of matrix is transmitted to the check node. In a further embodiment, the decoding process includes the following initialization, iteration, and bit decision processes:

initialization includes a posteriori probability initialization and check node message initialization, i.e.

The iteration process is realized by a layered updating mode, and the updating content comprises the following steps: variable node message update, check node message update and posterior probability message update. Wherein, the variable node message updating expression is as follows:

the check node message is more expressed as:

in the formula, l (m) \\ l represents a set of variable nodes adjacent to the check node m and an exit node l; β represents an Offset factor in the Offset Min-sum algorithm.

The posterior probability message update expression is:

in a further embodiment, when the number of decoding iterations reaches a set maximum value, decoding is stopped and bit decision is performed. When making a decision, ifThen decision is madeOn the contrary, the method can be used for carrying out the following steps,whereinThe sign bit representing the posterior probability of the variable node.

In an implementation manner of the second aspect, when the check node information and the variable node posterior probability information are updated hierarchically, the information node updating step corresponding to the i-th iteration and the j-th layer check matrix information is as follows:

the decoding controller controls the check matrix information address generation module to take out the data information of the j-th layer of check matrix from the check matrix information storage area; the check matrix information is a sparse matrix, and in the decoding process, the positions of the variable nodes needing to be updated each time are positioned according to the sparse check matrix information, so that the calculation process of the updated positions of the variable nodes is converted into a data mapping relation.

And the check node information address generating module and the variable node information address generating module find the check nodes and the variable nodes which need to be updated at the current layer according to the check matrix data information and take out the data.

The check node information distribution module and the variable node information distribution module send the taken data to the operation unit.

And after the operation of the operation unit is completed, the updated check node and variable node values are sent to the check node information distribution module and the variable node information distribution module.

And the check node information address generating module and the variable node information address generating module store the check nodes and the variable nodes in situ according to the check matrix data information and complete the information node updating corresponding to the ith iteration jth layer check matrix information.

When a decoding process is executed, the posterior probability initialization is hidden in the data storage process, namely the decoded source data storage process is used as the posterior probability initialization; and initializing and hiding the check node message in the first iterative computation, namely fixing the check node message to the data 0 when the check node message is obtained in the first iterative computation.

In some realizations of the second aspect, further aiming at LDPC coding with 1/2 code rates under the IEEE802.16e standard, by changing the expansion factor z, the method supports decoding with 19 code lengths under 1/2 code rates, where the code length ranges from 576 to 2304 at intervals of 96, and correspondingly, z ranges from 24 to 96 at intervals of 4.

In some implementations of the second aspect, a method for sparsely storing check matrix information is provided, where the method is used for data storage of a storage unit in a decoder, and the method specifically includes: and expressing the position information of '1' in each row of the check matrix by using a preset bit value. Further dividing three groups according to a preset size, wherein the first group is used for representing the data storage block in which the '1' in each row of the check matrix is; the second group is used to represent the location of a "1" in each data storage block; a third group for representing the storage position of the position information of 1 in each data storage block in the second group

In some realizations of the second aspect, the LDPC code check information matrix with code rate 1/2 under the IEEE802.16e standard is a sparse matrix, the size of the sparse matrix is 12 × 24 blocks, the size of each block is z × z, useful information is position information of "1" of each row, and the row weight of the matrix is 7 at the highest and 6 at the lowest.

In the storage process, the position information of '1' in each row of the check matrix is represented by limited (12 xz) x 152bit, so that the storage and the utilization are convenient. The concrete form is as follows: bits 0-23 indicate in which block a "1" is in each row of the check matrix; 8 bits are used as one group of bits 24-79, and 7 groups are used in total, and represent the position of '1' in each block; when there is "1" in the block, bits 80 to 151 are grouped into 24 groups with 3 bits, and the position information indicating "1" is stored in the groups of bits 24 to 79.

In a third aspect, a Wimax protocol-oriented QC-LDPC decoding system is provided, which includes:

an initialization module configured to initialize the corresponding parameter; the corresponding parameters comprise a preset iteration total coefficient, check node information and variable node information, and the current number of times of initialization iteration is 1;

a data receiving module configured to receive a data sequence to be decoded;

the decoder is arranged to receive the data sequence acquired by the data receiving module and decode the data sequence; further comprises a decoding controller, a storage unit and an arithmetic unit, the decoder

And the data output module is set to output the final decoding result of the decoder.

Has the advantages that: the invention provides a Wimax protocol-oriented QC-LDPC decoder decoding method and system, which have the following beneficial effects: 1. the decoding calculation of 1/2 code rates and 19 code lengths is supported under an IEEE802.16e communication protocol, the compatibility is good, the supported 19 code lengths range is 576-2304, the interval is 96, the code belongs to a medium-short code, and the QC-LDPC code has better error code performance in the range. 2. And the stored QC-LDPC check matrix information is utilized to simplify the decoding calculation complexity of the decoder, thereby saving hardware calculation resources. 3. The line layered decoding mode is adopted as the decoding method, and the method has the advantages of being friendly in hardware and easy to implement. 4. By adopting the flow design, the throughput rate is still higher under the condition of small usage amount of computing resources.

In conclusion, the invention can improve the utilization rate of storage resources and reduce the computation complexity and the use of computation resources while ensuring the LDPC decoding performance.

Drawings

FIG. 1 is a hardware configuration diagram of a QC-LDPC decoder according to the present invention.

FIG. 2 is a schematic diagram of a node update unit of the QC-LDPC decoder of the present invention.

Fig. 3 is a structural diagram of a node update unit adder in the present invention.

FIG. 4 is a diagram of a minimum value searching unit of a node updating unit according to the present invention.

FIG. 5 is a decoding flow chart of the QC-LDPC decoder of the present invention

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

Example one

In the process of hardware implementation, the traditional LDPC decoder pays attention to the mapping implementation of the algorithm, does not consider various characteristics of the LDPC code, occupies a large amount of storage resources, wastes more computing resources, and improves the wiring and time sequence requirements in hardware implementation. The embodiment provides a Wimax protocol-oriented decoding system of a QC-LDPC decoder, which utilizes stored QC-LDPC check matrix information to simplify the decoding computation complexity of the decoder, thereby saving hardware computation resources. Specifically, as shown in fig. 1, the QC-LDPC decoder in the system includes:

the LDPC decoder comprises a decoding controller, a storage unit and an operation unit, wherein the LDPC decoding controller is used for controlling the working flow of the decoder; the storage unit is used for storing check matrix information, check node information and variable node information; the operation unit is used for updating the information of the variable nodes and the check nodes.

The decoding controller receives data sequence information to be decoded and stores the data sequence information to the storage unit according to the divided data storage block areas; the decoding controller reads check matrix information in the storage unit and updates check node information and variable node posterior probability information in a layering manner by combining the operation module; after the iteration times are added by 1, judging whether the current iteration value is larger than a preset value, if so, stopping decoding, outputting decoded code word information, and calculating and obtaining a sign bit of the variable node posterior probability by adopting fixed point data; otherwise, the decoding controller reads the check matrix information in the storage unit again, updates the check node information and the variable node posterior probability information in a layering manner by combining the operation module, and judges whether the iteration value is larger than the preset value again; and finally, carrying the sign bit of the posterior probability of the ratio variable node to a storage unit to be used as a final result code word to finish the decoding process.

Example two

On the basis of the first embodiment, the decoding controller further comprises an operation control module, an address generation module and a distribution module.

A storage unit configured to store variable node information, check node information, and check matrix information; the unit is divided into three groups of data storage blocks according to requirements, wherein the first group of data storage blocks is used for storing the variable node information; the second group of data storage blocks are used for storing check node information; and the third group of data storage blocks is used for storing check matrix information. In a further embodiment, the memory cell comprises 40 BANKs, wherein the BANKs 0-23 are used for storing 24 blocks of variable node information, the BANKs 24-30 are used for storing check node information, and the BANKs 32-40 are used for storing check matrix information.

The operation module is arranged for updating the variable node information and the check node information, and further comprises a node updating unit, wherein the node updating unit adopts a flow design to update the check node information and the variable node information in the decoding process.

As shown in fig. 2, the node updating unit includes: the device comprises a fixed point adder, a fixed point comparator, an exclusive OR calculation module and an absolute value calculation module. In a further embodiment, since the check matrix of the QC-LDPC code in the 802.16 standard has row weight of 6 to 2/3 and row weight of 7 to 1/3, the number of input and output information of the node operation unit is at most 14 and at least 12, that is, half of check node information and half of variable node information.

The fixed point comparator is used for a minimum value and secondary minimum value calculation module, the module needs to find out the minimum value and the secondary minimum value from absolute values of 7 or 6 input variable nodes, the module is composed of basic structures COM2 and COM4, the basic structures COM2 and COM4 comprise 13 comparators and 20 selectors in total, the minimum value and the secondary minimum value are found in 3-level flow of calculation time division, and the calculation unit is set to be 8 input for convenient calculation.

In the case of the row with the update row weight of 7, the adder structure needs 7 fixed point adders in total, and the node update unit needs 14 fixed point adders in total, as shown in fig. 3.

The check node message updating expression shows that when the check node is updated, the minimum value and the second minimum value need to be found out from the absolute values of 7 or 6 input variable nodes, and the calculation process is completed by using the fixed point comparator. The basic structure of the minimum and next-to-minimum searching calculation unit is shown in fig. 4. It can be seen that the computing unit is composed of basic structures COM2 and COM4, and comprises 13 comparators and 20 selectors in total, and the computing time is divided into 3-level pipelines to find the minimum value and the second minimum value. For ease of calculation, the calculation unit is set to 8 inputs.

And the stored QC-LDPC check matrix information is utilized to simplify the decoding calculation complexity of the decoder, thereby saving hardware calculation resources.

EXAMPLE III

A QC-LDPC decoding method facing Wimax protocol is provided, which comprises the following steps:

step one, presetting iteration times, initializing check node information and variable node information, and setting the current iteration times to be 1;

receiving data sequence information to be decoded, and storing the data sequence information to a storage unit according to a divided data storage block region;

reading check matrix information in the storage unit by the decoding controller, and updating check node information and variable node posterior probability information in a layering manner by combining an operation module;

step four, after the iteration times are added by 1, judging whether the current iteration value is larger than a preset value, and if so, jumping to step five; otherwise, jumping to the third step;

stopping decoding, outputting decoded code word information, and calculating and acquiring a sign bit of the variable node posterior probability by adopting fixed point data;

and sixthly, carrying the sign bit of the posterior probability of the ratio variable node to a storage unit to be used as a final result code word, and finishing the decoding process.

In a further embodiment, a QC-LDPC decoder is adopted to carry out hardware design based on Verilog HDL language, and VCS and FPGA are used to complete basic test verification. For example, the number of iterations is set to 5 with z being 96, code length 2304. Specifically, the implementation process comprises the following steps:

step 1, initializing a check node and a variable node, wherein the iteration number is set to 1;

step 2, according to the formula Andupdating check node information and variable node posterior probability information in a layered manner; in the formula, t represents the number of iterations; k represents the current update to the k layer; (t, k) represents the kth layer operation in the tth iteration;when the kth layer in the t iteration is represented, the variable nodes in the mth row and the lth column in each layer of matrix are transmitted to the check nodes;representing changes in time of operation to the kth layer in the t-th iterationMeasure the posterior probability of node l;representing the message transmitted to the variable node by the check node of the mth row and the lth column in each layer of matrix in the t iteration; l (m) \\ l represents a set of variable nodes adjacent to the check node m, and an exit node l; β represents an Offset factor in the Offset Min-sum algorithm.

Step 3, adding 1 to the iteration times, and if the iteration times are not more than the set maximum iteration times 5, returning to the step 2;

step 4, outputting decoded code word information;

and 5, finishing decoding operation.

In a further embodiment, check matrix information is first carried from the DDR into BANK32-BANK40, variable node information to be decoded is initialized into BANK0-BANK 23; after the source data is in place, starting decoding operation, executing the flow and finishing the decoding operation; and finally carrying the sign bit of the variable node posterior probability from the BANK0-BANK23 to the DDR to be used as a final result code word.

The method adopts a line-based layered decoding algorithm as a decoding method, and has the advantages of hardware friendliness and easiness in implementation. Meanwhile, the node updating unit can update the check node information and the variable node information simultaneously in a pipelining manner, and the pipelining design is adopted, so that the throughput rate is still higher under the condition of small use amount of computing resources.

Example four

On the basis of the third embodiment, the information node updating process corresponding to the ith iteration jth layer check matrix information is as follows:

the controller controls the check matrix information address generation module to take out 152bit information of the j layer from the check matrix information storage area;

the check node information address generating module and the variable node information address generating module find the check node and the variable node which need to be updated at the current layer according to the 152bit information and take out data;

the check node information distribution module and the variable node information distribution module send the type 2 data to the NUU operation unit;

NUU, after the operation of the operation unit is completed, the updated check node and variable node values are sent to a check node information distribution module and variable node information distribution;

and the check node information address generating module and the variable node information address generating module store the check nodes and the variable nodes in situ according to the previous 152-bit information, and complete the information node updating corresponding to the ith iteration jth layer check matrix information.

In this embodiment, 6761 cycles are required for the decoder to complete decoding, and the throughput rate is 170.4Mbps when the decoder operates at 1 GHz. The invention considers reducing the computing resource and the storage resource while ensuring the performance, and does not set the decoding mode as the line-layered parallel decoding. If storage resources and computing resources are further increased, the throughput rate of the decoder can be greatly improved, for example, 12-path parallel computing is adopted, and the throughput rate of the decoder can reach 2Gbps when the working frequency of the decoder is 1 GHz.

EXAMPLE five

A QC-LDPC decoding system facing Wimax protocol is provided, which comprises:

an initialization module configured to initialize the corresponding parameter; the corresponding parameters comprise a preset iteration total coefficient, check node information and variable node information, and the current number of times of initialization iteration is 1;

a data receiving module configured to receive a data sequence to be decoded;

the decoder comprises a decoding controller, a storage unit and an operation unit, and is arranged to receive the data sequence acquired by the data receiving module and decode the data sequence;

and the data output module is set to output the final decoding result of the decoder.

By integrating the above embodiments, the invention supports the decoding calculation of 1/2 code rates and 19 code lengths under the IEEE802.16e standard communication protocol of the Wimax protocol, and has good compatibility; the stored QC-LDPC check matrix information is utilized to simplify the decoding calculation complexity of the decoder, thereby saving hardware calculation resources; an Offset Min-sum-based line layered decoding algorithm is adopted as a decoding method, so that the method has the advantages of being friendly in hardware and easy to implement; by adopting the flow design, the decoding operation with higher throughput rate is still realized under the condition of small usage amount of computing resources.

As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.